CLI and NCP Application
Data Structures | Macros
Device_Peripheral_Registers_DA14680BA
Dialog » DA14680BA

Data Structures

struct  AES_HASH_Type
 AES_HASH registers (AES_HASH) More...
 
struct  ANAMISC_Type
 ANAMISC registers (ANAMISC) More...
 
struct  APU_Type
 APU registers (APU) More...
 
struct  BLE_Type
 BLE registers (BLE) More...
 
struct  CACHE_Type
 CACHE registers (CACHE) More...
 
struct  CHIP_VERSION_Type
 CHIP_VERSION registers (CHIP_VERSION) More...
 
struct  COEX_Type
 COEX registers (COEX) More...
 
struct  CRG_PER_Type
 CRG_PER registers (CRG_PER) More...
 
struct  CRG_TOP_Type
 CRG_TOP registers (CRG_TOP) More...
 
struct  DCDC_Type
 DCDC registers (DCDC) More...
 
struct  DEM_Type
 DEM registers (DEM) More...
 
struct  DMA_Type
 DMA registers (DMA) More...
 
struct  ECC_Type
 ECC registers (ECC) More...
 
struct  FTDF_Type
 FTDF registers (FTDF) More...
 
struct  GP_TIMERS_Type
 GP_TIMERS registers (GP_TIMERS) More...
 
struct  GPADC_Type
 GPADC registers (GPADC) More...
 
struct  GPIO_Type
 GPIO registers (GPIO) More...
 
struct  GPREG_Type
 GPREG registers (GPREG) More...
 
struct  I2C_Type
 I2C registers (I2C) More...
 
struct  I2C2_Type
 I2C2 registers (I2C2) More...
 
struct  IR_Type
 IR registers (IR) More...
 
struct  KBSCAN_Type
 KBSCAN registers (KBSCAN) More...
 
struct  OTPC_Type
 OTPC registers (OTPC) More...
 
struct  PATCH_Type
 PATCH registers (PATCH) More...
 
struct  PLLDIG_Type
 PLLDIG registers (PLLDIG) More...
 
struct  QSPIC_Type
 QSPIC registers (QSPIC) More...
 
struct  QUAD_Type
 QUAD registers (QUAD) More...
 
struct  RFCU_Type
 RFCU registers (RFCU) More...
 
struct  RFCU_POWER_Type
 RFCU_POWER registers (RFCU_POWER) More...
 
struct  RFPT_Type
 RFPT registers (RFPT) More...
 
struct  SPI_Type
 SPI registers (SPI) More...
 
struct  SPI2_Type
 SPI2 registers (SPI2) More...
 
struct  TIMER1_Type
 TIMER1 registers (TIMER1) More...
 
struct  TRNG_Type
 TRNG registers (TRNG) More...
 
struct  UART_Type
 UART registers (UART) More...
 
struct  UART2_Type
 UART2 registers (UART2) More...
 
struct  USB_Type
 USB registers (USB) More...
 
struct  WAKEUP_Type
 WAKEUP registers (WAKEUP) More...
 
struct  WDOG_Type
 WDOG registers (WDOG) More...
 

Macros

#define NVIC_ISER_BLE_WAKEUP_LP_IRQn_Pos   (0UL)
 
#define NVIC_ISER_BLE_WAKEUP_LP_IRQn_Msk   (0x1UL)
 
#define NVIC_ISER_BLE_GEN_IRQn_Pos   (1UL)
 
#define NVIC_ISER_BLE_GEN_IRQn_Msk   (0x2UL)
 
#define NVIC_ISER_FTDF_WAKEUP_IRQn_Pos   (2UL)
 
#define NVIC_ISER_FTDF_WAKEUP_IRQn_Msk   (0x4UL)
 
#define NVIC_ISER_FTDF_GEN_IRQn_Pos   (3UL)
 
#define NVIC_ISER_FTDF_GEN_IRQn_Msk   (0x8UL)
 
#define NVIC_ISER_RFCAL_IRQn_Pos   (4UL)
 
#define NVIC_ISER_RFCAL_IRQn_Msk   (0x10UL)
 
#define NVIC_ISER_COEX_IRQn_Pos   (5UL)
 
#define NVIC_ISER_COEX_IRQn_Msk   (0x20UL)
 
#define NVIC_ISER_CRYPTO_IRQn_Pos   (6UL)
 
#define NVIC_ISER_CRYPTO_IRQn_Msk   (0x40UL)
 
#define NVIC_ISER_MRM_IRQn_Pos   (7UL)
 
#define NVIC_ISER_MRM_IRQn_Msk   (0x80UL)
 
#define NVIC_ISER_UART_IRQn_Pos   (8UL)
 
#define NVIC_ISER_UART_IRQn_Msk   (0x100UL)
 
#define NVIC_ISER_UART2_IRQn_Pos   (9UL)
 
#define NVIC_ISER_UART2_IRQn_Msk   (0x200UL)
 
#define NVIC_ISER_I2C_IRQn_Pos   (10UL)
 
#define NVIC_ISER_I2C_IRQn_Msk   (0x400UL)
 
#define NVIC_ISER_I2C2_IRQn_Pos   (11UL)
 
#define NVIC_ISER_I2C2_IRQn_Msk   (0x800UL)
 
#define NVIC_ISER_SPI_IRQn_Pos   (12UL)
 
#define NVIC_ISER_SPI_IRQn_Msk   (0x1000UL)
 
#define NVIC_ISER_SPI2_IRQn_Pos   (13UL)
 
#define NVIC_ISER_SPI2_IRQn_Msk   (0x2000UL)
 
#define NVIC_ISER_ADC_IRQn_Pos   (14UL)
 
#define NVIC_ISER_ADC_IRQn_Msk   (0x4000UL)
 
#define NVIC_ISER_KEYBRD_IRQn_Pos   (15UL)
 
#define NVIC_ISER_KEYBRD_IRQn_Msk   (0x8000UL)
 
#define NVIC_ISER_IRGEN_IRQn_Pos   (16UL)
 
#define NVIC_ISER_IRGEN_IRQn_Msk   (0x10000UL)
 
#define NVIC_ISER_WKUP_GPIO_IRQn_Pos   (17UL)
 
#define NVIC_ISER_WKUP_GPIO_IRQn_Msk   (0x20000UL)
 
#define NVIC_ISER_SWTIM0_IRQn_Pos   (18UL)
 
#define NVIC_ISER_SWTIM0_IRQn_Msk   (0x40000UL)
 
#define NVIC_ISER_SWTIM1_IRQn_Pos   (19UL)
 
#define NVIC_ISER_SWTIM1_IRQn_Msk   (0x80000UL)
 
#define NVIC_ISER_QUADEC_IRQn_Pos   (20UL)
 
#define NVIC_ISER_QUADEC_IRQn_Msk   (0x100000UL)
 
#define NVIC_ISER_USB_IRQn_Pos   (21UL)
 
#define NVIC_ISER_USB_IRQn_Msk   (0x200000UL)
 
#define NVIC_ISER_PCM_IRQn_Pos   (22UL)
 
#define NVIC_ISER_PCM_IRQn_Msk   (0x400000UL)
 
#define NVIC_ISER_SRC_IN_IRQn_Pos   (23UL)
 
#define NVIC_ISER_SRC_IN_IRQn_Msk   (0x800000UL)
 
#define NVIC_ISER_SRC_OUT_IRQn_Pos   (24UL)
 
#define NVIC_ISER_SRC_OUT_IRQn_Msk   (0x1000000UL)
 
#define NVIC_ISER_VBUS_IRQn_Pos   (25UL)
 
#define NVIC_ISER_VBUS_IRQn_Msk   (0x2000000UL)
 
#define NVIC_ISER_DMA_IRQn_Pos   (26UL)
 
#define NVIC_ISER_DMA_IRQn_Msk   (0x4000000UL)
 
#define NVIC_ISER_RF_DIAG_IRQn_Pos   (27UL)
 
#define NVIC_ISER_RF_DIAG_IRQn_Msk   (0x8000000UL)
 
#define NVIC_ISER_TRNG_IRQn_Pos   (28UL)
 
#define NVIC_ISER_TRNG_IRQn_Msk   (0x10000000UL)
 
#define NVIC_ISER_DCDC_IRQn_Pos   (29UL)
 
#define NVIC_ISER_DCDC_IRQn_Msk   (0x20000000UL)
 
#define NVIC_ISER_XTAL16RDY_IRQn_Pos   (30UL)
 
#define NVIC_ISER_XTAL16RDY_IRQn_Msk   (0x40000000UL)
 
#define NVIC_ISER_Rsvd__irq__n_Pos   (31UL)
 
#define NVIC_ISER_Rsvd__irq__n_Msk   (0x80000000UL)
 
#define NVIC_ICER_BLE_WAKEUP_LP_IRQn_Pos   (0UL)
 
#define NVIC_ICER_BLE_WAKEUP_LP_IRQn_Msk   (0x1UL)
 
#define NVIC_ICER_BLE_GEN_IRQn_Pos   (1UL)
 
#define NVIC_ICER_BLE_GEN_IRQn_Msk   (0x2UL)
 
#define NVIC_ICER_FTDF_WAKEUP_IRQn_Pos   (2UL)
 
#define NVIC_ICER_FTDF_WAKEUP_IRQn_Msk   (0x4UL)
 
#define NVIC_ICER_FTDF_GEN_IRQn_Pos   (3UL)
 
#define NVIC_ICER_FTDF_GEN_IRQn_Msk   (0x8UL)
 
#define NVIC_ICER_RFCAL_IRQn_Pos   (4UL)
 
#define NVIC_ICER_RFCAL_IRQn_Msk   (0x10UL)
 
#define NVIC_ICER_COEX_IRQn_Pos   (5UL)
 
#define NVIC_ICER_COEX_IRQn_Msk   (0x20UL)
 
#define NVIC_ICER_CRYPTO_IRQn_Pos   (6UL)
 
#define NVIC_ICER_CRYPTO_IRQn_Msk   (0x40UL)
 
#define NVIC_ICER_MRM_IRQn_Pos   (7UL)
 
#define NVIC_ICER_MRM_IRQn_Msk   (0x80UL)
 
#define NVIC_ICER_UART_IRQn_Pos   (8UL)
 
#define NVIC_ICER_UART_IRQn_Msk   (0x100UL)
 
#define NVIC_ICER_UART2_IRQn_Pos   (9UL)
 
#define NVIC_ICER_UART2_IRQn_Msk   (0x200UL)
 
#define NVIC_ICER_I2C_IRQn_Pos   (10UL)
 
#define NVIC_ICER_I2C_IRQn_Msk   (0x400UL)
 
#define NVIC_ICER_I2C2_IRQn_Pos   (11UL)
 
#define NVIC_ICER_I2C2_IRQn_Msk   (0x800UL)
 
#define NVIC_ICER_SPI_IRQn_Pos   (12UL)
 
#define NVIC_ICER_SPI_IRQn_Msk   (0x1000UL)
 
#define NVIC_ICER_SPI2_IRQn_Pos   (13UL)
 
#define NVIC_ICER_SPI2_IRQn_Msk   (0x2000UL)
 
#define NVIC_ICER_ADC_IRQn_Pos   (14UL)
 
#define NVIC_ICER_ADC_IRQn_Msk   (0x4000UL)
 
#define NVIC_ICER_KEYBRD_IRQn_Pos   (15UL)
 
#define NVIC_ICER_KEYBRD_IRQn_Msk   (0x8000UL)
 
#define NVIC_ICER_IRGEN_IRQn_Pos   (16UL)
 
#define NVIC_ICER_IRGEN_IRQn_Msk   (0x10000UL)
 
#define NVIC_ICER_WKUP_GPIO_IRQn_Pos   (17UL)
 
#define NVIC_ICER_WKUP_GPIO_IRQn_Msk   (0x20000UL)
 
#define NVIC_ICER_SWTIM0_IRQn_Pos   (18UL)
 
#define NVIC_ICER_SWTIM0_IRQn_Msk   (0x40000UL)
 
#define NVIC_ICER_SWTIM1_IRQn_Pos   (19UL)
 
#define NVIC_ICER_SWTIM1_IRQn_Msk   (0x80000UL)
 
#define NVIC_ICER_QUADEC_IRQn_Pos   (20UL)
 
#define NVIC_ICER_QUADEC_IRQn_Msk   (0x100000UL)
 
#define NVIC_ICER_USB_IRQn_Pos   (21UL)
 
#define NVIC_ICER_USB_IRQn_Msk   (0x200000UL)
 
#define NVIC_ICER_PCM_IRQn_Pos   (22UL)
 
#define NVIC_ICER_PCM_IRQn_Msk   (0x400000UL)
 
#define NVIC_ICER_SRC_IN_IRQn_Pos   (23UL)
 
#define NVIC_ICER_SRC_IN_IRQn_Msk   (0x800000UL)
 
#define NVIC_ICER_SRC_OUT_IRQn_Pos   (24UL)
 
#define NVIC_ICER_SRC_OUT_IRQn_Msk   (0x1000000UL)
 
#define NVIC_ICER_VBUS_IRQn_Pos   (25UL)
 
#define NVIC_ICER_VBUS_IRQn_Msk   (0x2000000UL)
 
#define NVIC_ICER_DMA_IRQn_Pos   (26UL)
 
#define NVIC_ICER_DMA_IRQn_Msk   (0x4000000UL)
 
#define NVIC_ICER_RF_DIAG_IRQn_Pos   (27UL)
 
#define NVIC_ICER_RF_DIAG_IRQn_Msk   (0x8000000UL)
 
#define NVIC_ICER_TRNG_IRQn_Pos   (28UL)
 
#define NVIC_ICER_TRNG_IRQn_Msk   (0x10000000UL)
 
#define NVIC_ICER_DCDC_IRQn_Pos   (29UL)
 
#define NVIC_ICER_DCDC_IRQn_Msk   (0x20000000UL)
 
#define NVIC_ICER_XTAL16RDY_IRQn_Pos   (30UL)
 
#define NVIC_ICER_XTAL16RDY_IRQn_Msk   (0x40000000UL)
 
#define NVIC_ICER_Rsvd__irq__n_Pos   (31UL)
 
#define NVIC_ICER_Rsvd__irq__n_Msk   (0x80000000UL)
 
#define NVIC_ISPR_BLE_WAKEUP_LP_IRQn_Pos   (0UL)
 
#define NVIC_ISPR_BLE_WAKEUP_LP_IRQn_Msk   (0x1UL)
 
#define NVIC_ISPR_BLE_GEN_IRQn_Pos   (1UL)
 
#define NVIC_ISPR_BLE_GEN_IRQn_Msk   (0x2UL)
 
#define NVIC_ISPR_FTDF_WAKEUP_IRQn_Pos   (2UL)
 
#define NVIC_ISPR_FTDF_WAKEUP_IRQn_Msk   (0x4UL)
 
#define NVIC_ISPR_FTDF_GEN_IRQn_Pos   (3UL)
 
#define NVIC_ISPR_FTDF_GEN_IRQn_Msk   (0x8UL)
 
#define NVIC_ISPR_RFCAL_IRQn_Pos   (4UL)
 
#define NVIC_ISPR_RFCAL_IRQn_Msk   (0x10UL)
 
#define NVIC_ISPR_COEX_IRQn_Pos   (5UL)
 
#define NVIC_ISPR_COEX_IRQn_Msk   (0x20UL)
 
#define NVIC_ISPR_CRYPTO_IRQn_Pos   (6UL)
 
#define NVIC_ISPR_CRYPTO_IRQn_Msk   (0x40UL)
 
#define NVIC_ISPR_MRM_IRQn_Pos   (7UL)
 
#define NVIC_ISPR_MRM_IRQn_Msk   (0x80UL)
 
#define NVIC_ISPR_UART_IRQn_Pos   (8UL)
 
#define NVIC_ISPR_UART_IRQn_Msk   (0x100UL)
 
#define NVIC_ISPR_UART2_IRQn_Pos   (9UL)
 
#define NVIC_ISPR_UART2_IRQn_Msk   (0x200UL)
 
#define NVIC_ISPR_I2C_IRQn_Pos   (10UL)
 
#define NVIC_ISPR_I2C_IRQn_Msk   (0x400UL)
 
#define NVIC_ISPR_I2C2_IRQn_Pos   (11UL)
 
#define NVIC_ISPR_I2C2_IRQn_Msk   (0x800UL)
 
#define NVIC_ISPR_SPI_IRQn_Pos   (12UL)
 
#define NVIC_ISPR_SPI_IRQn_Msk   (0x1000UL)
 
#define NVIC_ISPR_SPI2_IRQn_Pos   (13UL)
 
#define NVIC_ISPR_SPI2_IRQn_Msk   (0x2000UL)
 
#define NVIC_ISPR_ADC_IRQn_Pos   (14UL)
 
#define NVIC_ISPR_ADC_IRQn_Msk   (0x4000UL)
 
#define NVIC_ISPR_KEYBRD_IRQn_Pos   (15UL)
 
#define NVIC_ISPR_KEYBRD_IRQn_Msk   (0x8000UL)
 
#define NVIC_ISPR_IRGEN_IRQn_Pos   (16UL)
 
#define NVIC_ISPR_IRGEN_IRQn_Msk   (0x10000UL)
 
#define NVIC_ISPR_WKUP_GPIO_IRQn_Pos   (17UL)
 
#define NVIC_ISPR_WKUP_GPIO_IRQn_Msk   (0x20000UL)
 
#define NVIC_ISPR_SWTIM0_IRQn_Pos   (18UL)
 
#define NVIC_ISPR_SWTIM0_IRQn_Msk   (0x40000UL)
 
#define NVIC_ISPR_SWTIM1_IRQn_Pos   (19UL)
 
#define NVIC_ISPR_SWTIM1_IRQn_Msk   (0x80000UL)
 
#define NVIC_ISPR_QUADEC_IRQn_Pos   (20UL)
 
#define NVIC_ISPR_QUADEC_IRQn_Msk   (0x100000UL)
 
#define NVIC_ISPR_USB_IRQn_Pos   (21UL)
 
#define NVIC_ISPR_USB_IRQn_Msk   (0x200000UL)
 
#define NVIC_ISPR_PCM_IRQn_Pos   (22UL)
 
#define NVIC_ISPR_PCM_IRQn_Msk   (0x400000UL)
 
#define NVIC_ISPR_SRC_IN_IRQn_Pos   (23UL)
 
#define NVIC_ISPR_SRC_IN_IRQn_Msk   (0x800000UL)
 
#define NVIC_ISPR_SRC_OUT_IRQn_Pos   (24UL)
 
#define NVIC_ISPR_SRC_OUT_IRQn_Msk   (0x1000000UL)
 
#define NVIC_ISPR_VBUS_IRQn_Pos   (25UL)
 
#define NVIC_ISPR_VBUS_IRQn_Msk   (0x2000000UL)
 
#define NVIC_ISPR_DMA_IRQn_Pos   (26UL)
 
#define NVIC_ISPR_DMA_IRQn_Msk   (0x4000000UL)
 
#define NVIC_ISPR_RF_DIAG_IRQn_Pos   (27UL)
 
#define NVIC_ISPR_RF_DIAG_IRQn_Msk   (0x8000000UL)
 
#define NVIC_ISPR_TRNG_IRQn_Pos   (28UL)
 
#define NVIC_ISPR_TRNG_IRQn_Msk   (0x10000000UL)
 
#define NVIC_ISPR_DCDC_IRQn_Pos   (29UL)
 
#define NVIC_ISPR_DCDC_IRQn_Msk   (0x20000000UL)
 
#define NVIC_ISPR_XTAL16RDY_IRQn_Pos   (30UL)
 
#define NVIC_ISPR_XTAL16RDY_IRQn_Msk   (0x40000000UL)
 
#define NVIC_ISPR_Rsvd__irq__n_Pos   (31UL)
 
#define NVIC_ISPR_Rsvd__irq__n_Msk   (0x80000000UL)
 
#define NVIC_ICPR_BLE_WAKEUP_LP_IRQn_Pos   (0UL)
 
#define NVIC_ICPR_BLE_WAKEUP_LP_IRQn_Msk   (0x1UL)
 
#define NVIC_ICPR_BLE_GEN_IRQn_Pos   (1UL)
 
#define NVIC_ICPR_BLE_GEN_IRQn_Msk   (0x2UL)
 
#define NVIC_ICPR_FTDF_WAKEUP_IRQn_Pos   (2UL)
 
#define NVIC_ICPR_FTDF_WAKEUP_IRQn_Msk   (0x4UL)
 
#define NVIC_ICPR_FTDF_GEN_IRQn_Pos   (3UL)
 
#define NVIC_ICPR_FTDF_GEN_IRQn_Msk   (0x8UL)
 
#define NVIC_ICPR_RFCAL_IRQn_Pos   (4UL)
 
#define NVIC_ICPR_RFCAL_IRQn_Msk   (0x10UL)
 
#define NVIC_ICPR_COEX_IRQn_Pos   (5UL)
 
#define NVIC_ICPR_COEX_IRQn_Msk   (0x20UL)
 
#define NVIC_ICPR_CRYPTO_IRQn_Pos   (6UL)
 
#define NVIC_ICPR_CRYPTO_IRQn_Msk   (0x40UL)
 
#define NVIC_ICPR_MRM_IRQn_Pos   (7UL)
 
#define NVIC_ICPR_MRM_IRQn_Msk   (0x80UL)
 
#define NVIC_ICPR_UART_IRQn_Pos   (8UL)
 
#define NVIC_ICPR_UART_IRQn_Msk   (0x100UL)
 
#define NVIC_ICPR_UART2_IRQn_Pos   (9UL)
 
#define NVIC_ICPR_UART2_IRQn_Msk   (0x200UL)
 
#define NVIC_ICPR_I2C_IRQn_Pos   (10UL)
 
#define NVIC_ICPR_I2C_IRQn_Msk   (0x400UL)
 
#define NVIC_ICPR_I2C2_IRQn_Pos   (11UL)
 
#define NVIC_ICPR_I2C2_IRQn_Msk   (0x800UL)
 
#define NVIC_ICPR_SPI_IRQn_Pos   (12UL)
 
#define NVIC_ICPR_SPI_IRQn_Msk   (0x1000UL)
 
#define NVIC_ICPR_SPI2_IRQn_Pos   (13UL)
 
#define NVIC_ICPR_SPI2_IRQn_Msk   (0x2000UL)
 
#define NVIC_ICPR_ADC_IRQn_Pos   (14UL)
 
#define NVIC_ICPR_ADC_IRQn_Msk   (0x4000UL)
 
#define NVIC_ICPR_KEYBRD_IRQn_Pos   (15UL)
 
#define NVIC_ICPR_KEYBRD_IRQn_Msk   (0x8000UL)
 
#define NVIC_ICPR_IRGEN_IRQn_Pos   (16UL)
 
#define NVIC_ICPR_IRGEN_IRQn_Msk   (0x10000UL)
 
#define NVIC_ICPR_WKUP_GPIO_IRQn_Pos   (17UL)
 
#define NVIC_ICPR_WKUP_GPIO_IRQn_Msk   (0x20000UL)
 
#define NVIC_ICPR_SWTIM0_IRQn_Pos   (18UL)
 
#define NVIC_ICPR_SWTIM0_IRQn_Msk   (0x40000UL)
 
#define NVIC_ICPR_SWTIM1_IRQn_Pos   (19UL)
 
#define NVIC_ICPR_SWTIM1_IRQn_Msk   (0x80000UL)
 
#define NVIC_ICPR_QUADEC_IRQn_Pos   (20UL)
 
#define NVIC_ICPR_QUADEC_IRQn_Msk   (0x100000UL)
 
#define NVIC_ICPR_USB_IRQn_Pos   (21UL)
 
#define NVIC_ICPR_USB_IRQn_Msk   (0x200000UL)
 
#define NVIC_ICPR_PCM_IRQn_Pos   (22UL)
 
#define NVIC_ICPR_PCM_IRQn_Msk   (0x400000UL)
 
#define NVIC_ICPR_SRC_IN_IRQn_Pos   (23UL)
 
#define NVIC_ICPR_SRC_IN_IRQn_Msk   (0x800000UL)
 
#define NVIC_ICPR_SRC_OUT_IRQn_Pos   (24UL)
 
#define NVIC_ICPR_SRC_OUT_IRQn_Msk   (0x1000000UL)
 
#define NVIC_ICPR_VBUS_IRQn_Pos   (25UL)
 
#define NVIC_ICPR_VBUS_IRQn_Msk   (0x2000000UL)
 
#define NVIC_ICPR_DMA_IRQn_Pos   (26UL)
 
#define NVIC_ICPR_DMA_IRQn_Msk   (0x4000000UL)
 
#define NVIC_ICPR_RF_DIAG_IRQn_Pos   (27UL)
 
#define NVIC_ICPR_RF_DIAG_IRQn_Msk   (0x8000000UL)
 
#define NVIC_ICPR_TRNG_IRQn_Pos   (28UL)
 
#define NVIC_ICPR_TRNG_IRQn_Msk   (0x10000000UL)
 
#define NVIC_ICPR_DCDC_IRQn_Pos   (29UL)
 
#define NVIC_ICPR_DCDC_IRQn_Msk   (0x20000000UL)
 
#define NVIC_ICPR_XTAL16RDY_IRQn_Pos   (30UL)
 
#define NVIC_ICPR_XTAL16RDY_IRQn_Msk   (0x40000000UL)
 
#define NVIC_ICPR_Rsvd__irq__n_Pos   (31UL)
 
#define NVIC_ICPR_Rsvd__irq__n_Msk   (0x80000000UL)
 
#define NVIC_IPR0_BLE_WAKEUP_LP_IRQn_prio_Pos   (0UL)
 
#define NVIC_IPR0_BLE_WAKEUP_LP_IRQn_prio_Msk   (0xffUL)
 
#define NVIC_IPR0_BLE_GEN_IRQn_prio_Pos   (8UL)
 
#define NVIC_IPR0_BLE_GEN_IRQn_prio_Msk   (0xff00UL)
 
#define NVIC_IPR0_FTDF_WAKEUP_IRQn_prio_Pos   (16UL)
 
#define NVIC_IPR0_FTDF_WAKEUP_IRQn_prio_Msk   (0xff0000UL)
 
#define NVIC_IPR0_FTDF_GEN_IRQn_prio_Pos   (24UL)
 
#define NVIC_IPR0_FTDF_GEN_IRQn_prio_Msk   (0xff000000UL)
 
#define NVIC_IPR1_RFCAL_IRQn_prio_Pos   (0UL)
 
#define NVIC_IPR1_RFCAL_IRQn_prio_Msk   (0xffUL)
 
#define NVIC_IPR1_COEX_IRQn_prio_Pos   (8UL)
 
#define NVIC_IPR1_COEX_IRQn_prio_Msk   (0xff00UL)
 
#define NVIC_IPR1_CRYPTO_IRQn_prio_Pos   (16UL)
 
#define NVIC_IPR1_CRYPTO_IRQn_prio_Msk   (0xff0000UL)
 
#define NVIC_IPR1_MRM_IRQn_prio_Pos   (24UL)
 
#define NVIC_IPR1_MRM_IRQn_prio_Msk   (0xff000000UL)
 
#define NVIC_IPR2_UART_IRQn_prio_Pos   (0UL)
 
#define NVIC_IPR2_UART_IRQn_prio_Msk   (0xffUL)
 
#define NVIC_IPR2_UART2_IRQn_prio_Pos   (8UL)
 
#define NVIC_IPR2_UART2_IRQn_prio_Msk   (0xff00UL)
 
#define NVIC_IPR2_I2C_IRQn_prio_Pos   (16UL)
 
#define NVIC_IPR2_I2C_IRQn_prio_Msk   (0xff0000UL)
 
#define NVIC_IPR2_I2C2_IRQn_prio_Pos   (24UL)
 
#define NVIC_IPR2_I2C2_IRQn_prio_Msk   (0xff000000UL)
 
#define NVIC_IPR3_SPI_IRQn_prio_Pos   (0UL)
 
#define NVIC_IPR3_SPI_IRQn_prio_Msk   (0xffUL)
 
#define NVIC_IPR3_SPI2_IRQn_prio_Pos   (8UL)
 
#define NVIC_IPR3_SPI2_IRQn_prio_Msk   (0xff00UL)
 
#define NVIC_IPR3_ADC_IRQn_prio_Pos   (16UL)
 
#define NVIC_IPR3_ADC_IRQn_prio_Msk   (0xff0000UL)
 
#define NVIC_IPR3_KEYBRD_IRQn_prio_Pos   (24UL)
 
#define NVIC_IPR3_KEYBRD_IRQn_prio_Msk   (0xff000000UL)
 
#define NVIC_IPR4_IRGEN_IRQn_prio_Pos   (0UL)
 
#define NVIC_IPR4_IRGEN_IRQn_prio_Msk   (0xffUL)
 
#define NVIC_IPR4_WKUP_GPIO_IRQn_prio_Pos   (8UL)
 
#define NVIC_IPR4_WKUP_GPIO_IRQn_prio_Msk   (0xff00UL)
 
#define NVIC_IPR4_SWTIM0_IRQn_prio_Pos   (16UL)
 
#define NVIC_IPR4_SWTIM0_IRQn_prio_Msk   (0xff0000UL)
 
#define NVIC_IPR4_SWTIM1_IRQn_prio_Pos   (24UL)
 
#define NVIC_IPR4_SWTIM1_IRQn_prio_Msk   (0xff000000UL)
 
#define NVIC_IPR5_QUADEC_IRQn_prio_Pos   (0UL)
 
#define NVIC_IPR5_QUADEC_IRQn_prio_Msk   (0xffUL)
 
#define NVIC_IPR5_USB_IRQn_prio_Pos   (8UL)
 
#define NVIC_IPR5_USB_IRQn_prio_Msk   (0xff00UL)
 
#define NVIC_IPR5_PCM_IRQn_prio_Pos   (16UL)
 
#define NVIC_IPR5_PCM_IRQn_prio_Msk   (0xff0000UL)
 
#define NVIC_IPR5_SRC_IN_IRQn_prio_Pos   (24UL)
 
#define NVIC_IPR5_SRC_IN_IRQn_prio_Msk   (0xff000000UL)
 
#define NVIC_IPR6_SRC_OUT_IRQn_prio_Pos   (0UL)
 
#define NVIC_IPR6_SRC_OUT_IRQn_prio_Msk   (0xffUL)
 
#define NVIC_IPR6_VBUS_IRQn_prio_Pos   (8UL)
 
#define NVIC_IPR6_VBUS_IRQn_prio_Msk   (0xff00UL)
 
#define NVIC_IPR6_DMA_IRQn_prio_Pos   (16UL)
 
#define NVIC_IPR6_DMA_IRQn_prio_Msk   (0xff0000UL)
 
#define NVIC_IPR6_RF_DIAG_IRQn_prio_Pos   (24UL)
 
#define NVIC_IPR6_RF_DIAG_IRQn_prio_Msk   (0xff000000UL)
 
#define NVIC_IPR7_TRNG_IRQn_prio_Pos   (0UL)
 
#define NVIC_IPR7_TRNG_IRQn_prio_Msk   (0xffUL)
 
#define NVIC_IPR7_DCDC_IRQn_prio_Pos   (8UL)
 
#define NVIC_IPR7_DCDC_IRQn_prio_Msk   (0xff00UL)
 
#define NVIC_IPR7_XTAL16RDY_IRQn_prio_Pos   (16UL)
 
#define NVIC_IPR7_XTAL16RDY_IRQn_prio_Msk   (0xff0000UL)
 
#define NVIC_IPR7_RESERVED31_IRQn_DONT_USE_Pos   (24UL)
 
#define NVIC_IPR7_RESERVED31_IRQn_DONT_USE_Msk   (0xff000000UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos   (0UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Msk   (0x3UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos   (2UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk   (0xcUL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Pos   (4UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk   (0x10UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos   (5UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk   (0x60UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Pos   (7UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Msk   (0x80UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Pos   (8UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Msk   (0x100UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Pos   (9UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk   (0x200UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Pos   (10UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Msk   (0xfc00UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Pos   (16UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk   (0x10000UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Pos   (17UL)
 
#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk   (0x20000UL)
 
#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Pos   (0UL)
 
#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Msk   (0x1UL)
 
#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Pos   (0UL)
 
#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Msk   (0xffffffffUL)
 
#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Pos   (0UL)
 
#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Msk   (0xffffffUL)
 
#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Pos   (0UL)
 
#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Msk   (0xffffffffUL)
 
#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Pos   (0UL)
 
#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Msk   (0x1UL)
 
#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Pos   (1UL)
 
#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Msk   (0x2UL)
 
#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Pos   (2UL)
 
#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk   (0x4UL)
 
#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Pos   (0UL)
 
#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Msk   (0x1UL)
 
#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Pos   (0UL)
 
#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Msk   (0xffffffffUL)
 
#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Pos   (0UL)
 
#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Msk   (0xffffffffUL)
 
#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Pos   (0UL)
 
#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Msk   (0xffffffffUL)
 
#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Pos   (0UL)
 
#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Msk   (0xffffffffUL)
 
#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Pos   (0UL)
 
#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Msk   (0xffffffffUL)
 
#define ANAMISC_ANA_TEST_REG_TEST_STRUCTURE_Pos   (0UL)
 
#define ANAMISC_ANA_TEST_REG_TEST_STRUCTURE_Msk   (0xfUL)
 
#define ANAMISC_ANA_TEST_REG_ACORE_TESTBUS_EN_Pos   (4UL)
 
#define ANAMISC_ANA_TEST_REG_ACORE_TESTBUS_EN_Msk   (0x10UL)
 
#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_LEVEL_Pos   (0UL)
 
#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_LEVEL_Msk   (0x1fUL)
 
#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_ON_Pos   (5UL)
 
#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_ON_Msk   (0x20UL)
 
#define ANAMISC_CHARGER_CTRL1_REG_NTC_DISABLE_Pos   (6UL)
 
#define ANAMISC_CHARGER_CTRL1_REG_NTC_DISABLE_Msk   (0x40UL)
 
#define ANAMISC_CHARGER_CTRL1_REG_NTC_LOW_DISABLE_Pos   (7UL)
 
#define ANAMISC_CHARGER_CTRL1_REG_NTC_LOW_DISABLE_Msk   (0x80UL)
 
#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_CUR_Pos   (8UL)
 
#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_CUR_Msk   (0xf00UL)
 
#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_SET_Pos   (12UL)
 
#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_SET_Msk   (0x3000UL)
 
#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_DISABLE_Pos   (14UL)
 
#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_DISABLE_Msk   (0x4000UL)
 
#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_GAIN_TRIM_Pos   (0UL)
 
#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_GAIN_TRIM_Msk   (0xfUL)
 
#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_VFLOAT_ADJ_Pos   (4UL)
 
#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_VFLOAT_ADJ_Msk   (0xf0UL)
 
#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_OFFSET_TRIM_Pos   (8UL)
 
#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_OFFSET_TRIM_Msk   (0x1f00UL)
 
#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_TEST_Pos   (13UL)
 
#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_TEST_Msk   (0xe000UL)
 
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CC_MODE_Pos   (0UL)
 
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CC_MODE_Msk   (0x1UL)
 
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CV_MODE_Pos   (1UL)
 
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CV_MODE_Msk   (0x2UL)
 
#define ANAMISC_CHARGER_STATUS_REG_END_OF_CHARGE_Pos   (2UL)
 
#define ANAMISC_CHARGER_STATUS_REG_END_OF_CHARGE_Msk   (0x4UL)
 
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_LOW_Pos   (3UL)
 
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_LOW_Msk   (0x8UL)
 
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_OK_Pos   (4UL)
 
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_OK_Msk   (0x10UL)
 
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_HIGH_Pos   (5UL)
 
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_HIGH_Msk   (0x20UL)
 
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_TMODE_PROT_Pos   (6UL)
 
#define ANAMISC_CHARGER_STATUS_REG_CHARGER_TMODE_PROT_Msk   (0x40UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_ENABLE_Pos   (0UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_ENABLE_Msk   (0x1UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_CHARGE_Pos   (1UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_CHARGE_Msk   (0x2UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_AVG_Pos   (2UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_AVG_Msk   (0x4UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_MUTE_Pos   (3UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_MUTE_Msk   (0x8UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_GPIO_Pos   (4UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_GPIO_Msk   (0x10UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_SIGN_Pos   (5UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_SIGN_Msk   (0x20UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_IDAC_Pos   (6UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_IDAC_Msk   (0xc0UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_LPF_Pos   (8UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_LPF_Msk   (0x100UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_CLK_Pos   (9UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_CLK_Msk   (0xe00UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_BIAS_Pos   (12UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_BIAS_Msk   (0x3000UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_CINT_Pos   (14UL)
 
#define ANAMISC_SOC_CTRL1_REG_SOC_CINT_Msk   (0xc000UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_RVI_Pos   (0UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_RVI_Msk   (0x3UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_SCYCLE_Pos   (2UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_SCYCLE_Msk   (0x1cUL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_DCYCLE_Pos   (5UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_DCYCLE_Msk   (0x20UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_ICM_Pos   (6UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_ICM_Msk   (0xc0UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_CHOP_Pos   (8UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_CHOP_Msk   (0x700UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_CMIREG_ENABLE_Pos   (11UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_CMIREG_ENABLE_Msk   (0x800UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_MAW_Pos   (12UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_MAW_Msk   (0x7000UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_DYNAVG_Pos   (15UL)
 
#define ANAMISC_SOC_CTRL2_REG_SOC_DYNAVG_Msk   (0x8000UL)
 
#define ANAMISC_SOC_CTRL3_REG_SOC_VSAT_Pos   (0UL)
 
#define ANAMISC_SOC_CTRL3_REG_SOC_VSAT_Msk   (0x3UL)
 
#define ANAMISC_SOC_CTRL3_REG_SOC_DYNTARG_Pos   (2UL)
 
#define ANAMISC_SOC_CTRL3_REG_SOC_DYNTARG_Msk   (0x4UL)
 
#define ANAMISC_SOC_CTRL3_REG_SOC_DYNHYS_Pos   (3UL)
 
#define ANAMISC_SOC_CTRL3_REG_SOC_DYNHYS_Msk   (0x8UL)
 
#define ANAMISC_SOC_CTRL3_REG_SOC_VCMI_Pos   (4UL)
 
#define ANAMISC_SOC_CTRL3_REG_SOC_VCMI_Msk   (0x30UL)
 
#define ANAMISC_SOC_ADD2CH_REG_SOC_ADD2CH_Pos   (0UL)
 
#define ANAMISC_SOC_ADD2CH_REG_SOC_ADD2CH_Msk   (0xffffUL)
 
#define ANAMISC_SOC_CHARGE_CNTR1_REG_CHARGE_CNT1_Pos   (0UL)
 
#define ANAMISC_SOC_CHARGE_CNTR1_REG_CHARGE_CNT1_Msk   (0xffffUL)
 
#define ANAMISC_SOC_CHARGE_CNTR2_REG_CHARGE_CNT2_Pos   (0UL)
 
#define ANAMISC_SOC_CHARGE_CNTR2_REG_CHARGE_CNT2_Msk   (0xffffUL)
 
#define ANAMISC_SOC_CHARGE_CNTR3_REG_CHARGE_CNT3_Pos   (0UL)
 
#define ANAMISC_SOC_CHARGE_CNTR3_REG_CHARGE_CNT3_Msk   (0xffUL)
 
#define ANAMISC_SOC_CHARGE_AVG_REG_CHARGE_AVG_Pos   (0UL)
 
#define ANAMISC_SOC_CHARGE_AVG_REG_CHARGE_AVG_Msk   (0xffffUL)
 
#define ANAMISC_SOC_STATUS_REG_SOC_INT_OVERLOAD_Pos   (0UL)
 
#define ANAMISC_SOC_STATUS_REG_SOC_INT_OVERLOAD_Msk   (0x1UL)
 
#define ANAMISC_SOC_STATUS_REG_SOC_INT_LOCKED_Pos   (1UL)
 
#define ANAMISC_SOC_STATUS_REG_SOC_INT_LOCKED_Msk   (0x2UL)
 
#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_VAL_Pos   (0UL)
 
#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_VAL_Msk   (0x1ffUL)
 
#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_SIGN_Pos   (9UL)
 
#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_SIGN_Msk   (0x200UL)
 
#define ANAMISC_SOC_EXT_IN_REG_SOC_RDAC_DIS_Pos   (10UL)
 
#define ANAMISC_SOC_EXT_IN_REG_SOC_RDAC_DIS_Msk   (0x400UL)
 
#define ANAMISC_SOC_EXT_IN_REG_SOC_NR_SCYCLE_Pos   (11UL)
 
#define ANAMISC_SOC_EXT_IN_REG_SOC_NR_SCYCLE_Msk   (0x3800UL)
 
#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_SCYCLE_EN_Pos   (14UL)
 
#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_SCYCLE_EN_Msk   (0x4000UL)
 
#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_IDAC_EN_Pos   (15UL)
 
#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_IDAC_EN_Msk   (0x8000UL)
 
#define ANAMISC_SOC_EXT_OUT_REG_SOC_HIGH_LIM_Pos   (0UL)
 
#define ANAMISC_SOC_EXT_OUT_REG_SOC_HIGH_LIM_Msk   (0x1UL)
 
#define ANAMISC_SOC_EXT_OUT_REG_SOC_LOWLIM_COMP_Pos   (1UL)
 
#define ANAMISC_SOC_EXT_OUT_REG_SOC_LOWLIM_COMP_Msk   (0x2UL)
 
#define ANAMISC_SOC_EXT_OUT_REG_SOC_POS_COMP_Pos   (2UL)
 
#define ANAMISC_SOC_EXT_OUT_REG_SOC_POS_COMP_Msk   (0x4UL)
 
#define ANAMISC_SOC_EXT_OUT_REG_SOC_RISING_COMP_Pos   (3UL)
 
#define ANAMISC_SOC_EXT_OUT_REG_SOC_RISING_COMP_Msk   (0x8UL)
 
#define ANAMISC_SOC_EXT_OUT_REG_SOC_STATE_Pos   (4UL)
 
#define ANAMISC_SOC_EXT_OUT_REG_SOC_STATE_Msk   (0xf0UL)
 
#define ANAMISC_SOC_EXT_OUT_REG_SOC_CTRL_EVENT_Pos   (8UL)
 
#define ANAMISC_SOC_EXT_OUT_REG_SOC_CTRL_EVENT_Msk   (0x100UL)
 
#define ANAMISC_CLK_REF_SEL_REG_REF_CLK_SEL_Pos   (0UL)
 
#define ANAMISC_CLK_REF_SEL_REG_REF_CLK_SEL_Msk   (0x3UL)
 
#define ANAMISC_CLK_REF_SEL_REG_REF_CAL_START_Pos   (2UL)
 
#define ANAMISC_CLK_REF_SEL_REG_REF_CAL_START_Msk   (0x4UL)
 
#define ANAMISC_CLK_REF_CNT_REG_REF_CNT_VAL_Pos   (0UL)
 
#define ANAMISC_CLK_REF_CNT_REG_REF_CNT_VAL_Msk   (0xffffUL)
 
#define ANAMISC_CLK_REF_VAL_L_REG_XTAL_CNT_VAL_Pos   (0UL)
 
#define ANAMISC_CLK_REF_VAL_L_REG_XTAL_CNT_VAL_Msk   (0xffffUL)
 
#define ANAMISC_CLK_REF_VAL_H_REG_XTAL_CNT_VAL_Pos   (0UL)
 
#define ANAMISC_CLK_REF_VAL_H_REG_XTAL_CNT_VAL_Msk   (0xffffUL)
 
#define APU_SRC1_CTRL_REG_SRC_EN_Pos   (0UL)
 
#define APU_SRC1_CTRL_REG_SRC_EN_Msk   (0x1UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Pos   (1UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Msk   (0x2UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Pos   (2UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Msk   (0x4UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_DS_Pos   (4UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_DS_Msk   (0x30UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_OK_Pos   (6UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_OK_Msk   (0x40UL)
 
#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Pos   (7UL)
 
#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Msk   (0x80UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Pos   (13UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Msk   (0x2000UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos   (14UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk   (0x4000UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_US_Pos   (16UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_US_Msk   (0x30000UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Pos   (18UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Msk   (0x40000UL)
 
#define APU_SRC1_CTRL_REG_SRC_RESYNC_Pos   (19UL)
 
#define APU_SRC1_CTRL_REG_SRC_RESYNC_Msk   (0x80000UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Pos   (20UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Msk   (0x100000UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Pos   (21UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Msk   (0x200000UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Pos   (22UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Msk   (0x400000UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Pos   (23UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Msk   (0x800000UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Pos   (24UL)
 
#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Msk   (0x1000000UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Pos   (25UL)
 
#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Msk   (0x2000000UL)
 
#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Pos   (26UL)
 
#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Msk   (0xc000000UL)
 
#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Pos   (28UL)
 
#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Msk   (0x30000000UL)
 
#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Pos   (30UL)
 
#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Msk   (0xc0000000UL)
 
#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Pos   (0UL)
 
#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Msk   (0xffffffUL)
 
#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Pos   (0UL)
 
#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Msk   (0xffffffUL)
 
#define APU_SRC1_IN1_REG_SRC_IN_Pos   (8UL)
 
#define APU_SRC1_IN1_REG_SRC_IN_Msk   (0xffffff00UL)
 
#define APU_SRC1_IN2_REG_SRC_IN_Pos   (8UL)
 
#define APU_SRC1_IN2_REG_SRC_IN_Msk   (0xffffff00UL)
 
#define APU_SRC1_OUT1_REG_SRC_OUT_Pos   (8UL)
 
#define APU_SRC1_OUT1_REG_SRC_OUT_Msk   (0xffffff00UL)
 
#define APU_SRC1_OUT2_REG_SRC_OUT_Pos   (8UL)
 
#define APU_SRC1_OUT2_REG_SRC_OUT_Msk   (0xffffff00UL)
 
#define APU_APU_MUX_REG_SRC1_MUX_IN_Pos   (0UL)
 
#define APU_APU_MUX_REG_SRC1_MUX_IN_Msk   (0x7UL)
 
#define APU_APU_MUX_REG_PCM1_MUX_IN_Pos   (3UL)
 
#define APU_APU_MUX_REG_PCM1_MUX_IN_Msk   (0x38UL)
 
#define APU_APU_MUX_REG_PDM1_MUX_IN_Pos   (6UL)
 
#define APU_APU_MUX_REG_PDM1_MUX_IN_Msk   (0x40UL)
 
#define APU_COEF10_SET1_REG_SRC_COEF0_Pos   (0UL)
 
#define APU_COEF10_SET1_REG_SRC_COEF0_Msk   (0xffffUL)
 
#define APU_COEF10_SET1_REG_SRC_COEF1_Pos   (16UL)
 
#define APU_COEF10_SET1_REG_SRC_COEF1_Msk   (0xffff0000UL)
 
#define APU_COEF32_SET1_REG_SRC_COEF2_Pos   (0UL)
 
#define APU_COEF32_SET1_REG_SRC_COEF2_Msk   (0xffffUL)
 
#define APU_COEF32_SET1_REG_SRC_COEF3_Pos   (16UL)
 
#define APU_COEF32_SET1_REG_SRC_COEF3_Msk   (0xffff0000UL)
 
#define APU_COEF54_SET1_REG_SRC_COEF4_Pos   (0UL)
 
#define APU_COEF54_SET1_REG_SRC_COEF4_Msk   (0xffffUL)
 
#define APU_COEF54_SET1_REG_SRC_COEF5_Pos   (16UL)
 
#define APU_COEF54_SET1_REG_SRC_COEF5_Msk   (0xffff0000UL)
 
#define APU_COEF76_SET1_REG_SRC_COEF6_Pos   (0UL)
 
#define APU_COEF76_SET1_REG_SRC_COEF6_Msk   (0xffffUL)
 
#define APU_COEF76_SET1_REG_SRC_COEF7_Pos   (16UL)
 
#define APU_COEF76_SET1_REG_SRC_COEF7_Msk   (0xffff0000UL)
 
#define APU_COEF98_SET1_REG_SRC_COEF8_Pos   (0UL)
 
#define APU_COEF98_SET1_REG_SRC_COEF8_Msk   (0xffffUL)
 
#define APU_COEF98_SET1_REG_SRC_COEF9_Pos   (16UL)
 
#define APU_COEF98_SET1_REG_SRC_COEF9_Msk   (0xffff0000UL)
 
#define APU_COEF0A_SET1_REG_SRC_COEF10_Pos   (0UL)
 
#define APU_COEF0A_SET1_REG_SRC_COEF10_Msk   (0xffffUL)
 
#define APU_PCM1_CTRL_REG_PCM_EN_Pos   (0UL)
 
#define APU_PCM1_CTRL_REG_PCM_EN_Msk   (0x1UL)
 
#define APU_PCM1_CTRL_REG_PCM_MASTER_Pos   (1UL)
 
#define APU_PCM1_CTRL_REG_PCM_MASTER_Msk   (0x2UL)
 
#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Pos   (2UL)
 
#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Msk   (0x3cUL)
 
#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Pos   (6UL)
 
#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Msk   (0x40UL)
 
#define APU_PCM1_CTRL_REG_PCM_PPOD_Pos   (7UL)
 
#define APU_PCM1_CTRL_REG_PCM_PPOD_Msk   (0x80UL)
 
#define APU_PCM1_CTRL_REG_PCM_CLKINV_Pos   (8UL)
 
#define APU_PCM1_CTRL_REG_PCM_CLKINV_Msk   (0x100UL)
 
#define APU_PCM1_CTRL_REG_PCM_FSCINV_Pos   (9UL)
 
#define APU_PCM1_CTRL_REG_PCM_FSCINV_Msk   (0x200UL)
 
#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Pos   (10UL)
 
#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Msk   (0x400UL)
 
#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Pos   (11UL)
 
#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Msk   (0xf800UL)
 
#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Pos   (16UL)
 
#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Msk   (0x10000UL)
 
#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Pos   (20UL)
 
#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Msk   (0xfff00000UL)
 
#define APU_PCM1_IN1_REG_PCM_IN_Pos   (0UL)
 
#define APU_PCM1_IN1_REG_PCM_IN_Msk   (0xffffffffUL)
 
#define APU_PCM1_IN2_REG_PCM_IN_Pos   (0UL)
 
#define APU_PCM1_IN2_REG_PCM_IN_Msk   (0xffffffffUL)
 
#define APU_PCM1_OUT1_REG_PCM_OUT_Pos   (0UL)
 
#define APU_PCM1_OUT1_REG_PCM_OUT_Msk   (0xffffffffUL)
 
#define APU_PCM1_OUT2_REG_PCM_OUT_Pos   (0UL)
 
#define APU_PCM1_OUT2_REG_PCM_OUT_Msk   (0xffffffffUL)
 
#define BLE_BLE_RWBLECNTL_REG_SYNCERR_Pos   (0UL)
 
#define BLE_BLE_RWBLECNTL_REG_SYNCERR_Msk   (0x7UL)
 
#define BLE_BLE_RWBLECNTL_REG_RXWINSZDEF_Pos   (4UL)
 
#define BLE_BLE_RWBLECNTL_REG_RXWINSZDEF_Msk   (0xf0UL)
 
#define BLE_BLE_RWBLECNTL_REG_RWBLE_EN_Pos   (8UL)
 
#define BLE_BLE_RWBLECNTL_REG_RWBLE_EN_Msk   (0x100UL)
 
#define BLE_BLE_RWBLECNTL_REG_ADVERTFILT_EN_Pos   (9UL)
 
#define BLE_BLE_RWBLECNTL_REG_ADVERTFILT_EN_Msk   (0x200UL)
 
#define BLE_BLE_RWBLECNTL_REG_CORR_MODE_Pos   (12UL)
 
#define BLE_BLE_RWBLECNTL_REG_CORR_MODE_Msk   (0x3000UL)
 
#define BLE_BLE_RWBLECNTL_REG_HOP_REMAP_DSB_Pos   (16UL)
 
#define BLE_BLE_RWBLECNTL_REG_HOP_REMAP_DSB_Msk   (0x10000UL)
 
#define BLE_BLE_RWBLECNTL_REG_CRC_DSB_Pos   (17UL)
 
#define BLE_BLE_RWBLECNTL_REG_CRC_DSB_Msk   (0x20000UL)
 
#define BLE_BLE_RWBLECNTL_REG_WHIT_DSB_Pos   (18UL)
 
#define BLE_BLE_RWBLECNTL_REG_WHIT_DSB_Msk   (0x40000UL)
 
#define BLE_BLE_RWBLECNTL_REG_CRYPT_DSB_Pos   (19UL)
 
#define BLE_BLE_RWBLECNTL_REG_CRYPT_DSB_Msk   (0x80000UL)
 
#define BLE_BLE_RWBLECNTL_REG_NESN_DSB_Pos   (20UL)
 
#define BLE_BLE_RWBLECNTL_REG_NESN_DSB_Msk   (0x100000UL)
 
#define BLE_BLE_RWBLECNTL_REG_SN_DSB_Pos   (21UL)
 
#define BLE_BLE_RWBLECNTL_REG_SN_DSB_Msk   (0x200000UL)
 
#define BLE_BLE_RWBLECNTL_REG_MD_DSB_Pos   (22UL)
 
#define BLE_BLE_RWBLECNTL_REG_MD_DSB_Msk   (0x400000UL)
 
#define BLE_BLE_RWBLECNTL_REG_SCAN_ABORT_Pos   (24UL)
 
#define BLE_BLE_RWBLECNTL_REG_SCAN_ABORT_Msk   (0x1000000UL)
 
#define BLE_BLE_RWBLECNTL_REG_ADVERT_ABORT_Pos   (25UL)
 
#define BLE_BLE_RWBLECNTL_REG_ADVERT_ABORT_Msk   (0x2000000UL)
 
#define BLE_BLE_RWBLECNTL_REG_RFTEST_ABORT_Pos   (26UL)
 
#define BLE_BLE_RWBLECNTL_REG_RFTEST_ABORT_Msk   (0x4000000UL)
 
#define BLE_BLE_RWBLECNTL_REG_SWINT_REQ_Pos   (28UL)
 
#define BLE_BLE_RWBLECNTL_REG_SWINT_REQ_Msk   (0x10000000UL)
 
#define BLE_BLE_RWBLECNTL_REG_REG_SOFT_RST_Pos   (29UL)
 
#define BLE_BLE_RWBLECNTL_REG_REG_SOFT_RST_Msk   (0x20000000UL)
 
#define BLE_BLE_RWBLECNTL_REG_MASTER_TGSOFT_RST_Pos   (30UL)
 
#define BLE_BLE_RWBLECNTL_REG_MASTER_TGSOFT_RST_Msk   (0x40000000UL)
 
#define BLE_BLE_RWBLECNTL_REG_MASTER_SOFT_RST_Pos   (31UL)
 
#define BLE_BLE_RWBLECNTL_REG_MASTER_SOFT_RST_Msk   (0x80000000UL)
 
#define BLE_BLE_VERSION_REG_BUILD_Pos   (0UL)
 
#define BLE_BLE_VERSION_REG_BUILD_Msk   (0xffUL)
 
#define BLE_BLE_VERSION_REG_UPG_Pos   (8UL)
 
#define BLE_BLE_VERSION_REG_UPG_Msk   (0xff00UL)
 
#define BLE_BLE_VERSION_REG_REL_Pos   (16UL)
 
#define BLE_BLE_VERSION_REG_REL_Msk   (0xff0000UL)
 
#define BLE_BLE_VERSION_REG_TYP_Pos   (24UL)
 
#define BLE_BLE_VERSION_REG_TYP_Msk   (0xff000000UL)
 
#define BLE_BLE_RWBLECONF_REG_BUSWIDTH_Pos   (0UL)
 
#define BLE_BLE_RWBLECONF_REG_BUSWIDTH_Msk   (0x1UL)
 
#define BLE_BLE_RWBLECONF_REG_USECRYPT_Pos   (1UL)
 
#define BLE_BLE_RWBLECONF_REG_USECRYPT_Msk   (0x2UL)
 
#define BLE_BLE_RWBLECONF_REG_USEDBG_Pos   (2UL)
 
#define BLE_BLE_RWBLECONF_REG_USEDBG_Msk   (0x4UL)
 
#define BLE_BLE_RWBLECONF_REG_COEX_Pos   (3UL)
 
#define BLE_BLE_RWBLECONF_REG_COEX_Msk   (0x8UL)
 
#define BLE_BLE_RWBLECONF_REG_INTMODE_Pos   (4UL)
 
#define BLE_BLE_RWBLECONF_REG_INTMODE_Msk   (0x10UL)
 
#define BLE_BLE_RWBLECONF_REG_DMMODE_Pos   (5UL)
 
#define BLE_BLE_RWBLECONF_REG_DMMODE_Msk   (0x20UL)
 
#define BLE_BLE_RWBLECONF_REG_DECIPHER_Pos   (6UL)
 
#define BLE_BLE_RWBLECONF_REG_DECIPHER_Msk   (0x40UL)
 
#define BLE_BLE_RWBLECONF_REG_CLK_SEL_Pos   (8UL)
 
#define BLE_BLE_RWBLECONF_REG_CLK_SEL_Msk   (0x3f00UL)
 
#define BLE_BLE_RWBLECONF_REG_RFIF_Pos   (16UL)
 
#define BLE_BLE_RWBLECONF_REG_RFIF_Msk   (0x7f0000UL)
 
#define BLE_BLE_RWBLECONF_REG_ADD_WIDTH_Pos   (24UL)
 
#define BLE_BLE_RWBLECONF_REG_ADD_WIDTH_Msk   (0x3f000000UL)
 
#define BLE_BLE_INTCNTL_REG_CSCNTINTMSK_Pos   (0UL)
 
#define BLE_BLE_INTCNTL_REG_CSCNTINTMSK_Msk   (0x1UL)
 
#define BLE_BLE_INTCNTL_REG_RXINTMSK_Pos   (1UL)
 
#define BLE_BLE_INTCNTL_REG_RXINTMSK_Msk   (0x2UL)
 
#define BLE_BLE_INTCNTL_REG_SLPINTMSK_Pos   (2UL)
 
#define BLE_BLE_INTCNTL_REG_SLPINTMSK_Msk   (0x4UL)
 
#define BLE_BLE_INTCNTL_REG_EVENTINTMSK_Pos   (3UL)
 
#define BLE_BLE_INTCNTL_REG_EVENTINTMSK_Msk   (0x8UL)
 
#define BLE_BLE_INTCNTL_REG_CRYPTINTMSK_Pos   (4UL)
 
#define BLE_BLE_INTCNTL_REG_CRYPTINTMSK_Msk   (0x10UL)
 
#define BLE_BLE_INTCNTL_REG_ERRORINTMSK_Pos   (5UL)
 
#define BLE_BLE_INTCNTL_REG_ERRORINTMSK_Msk   (0x20UL)
 
#define BLE_BLE_INTCNTL_REG_GROSSTGTIMINTMSK_Pos   (6UL)
 
#define BLE_BLE_INTCNTL_REG_GROSSTGTIMINTMSK_Msk   (0x40UL)
 
#define BLE_BLE_INTCNTL_REG_FINETGTIMINTMSK_Pos   (7UL)
 
#define BLE_BLE_INTCNTL_REG_FINETGTIMINTMSK_Msk   (0x80UL)
 
#define BLE_BLE_INTCNTL_REG_EVENTAPFAINTMSK_Pos   (8UL)
 
#define BLE_BLE_INTCNTL_REG_EVENTAPFAINTMSK_Msk   (0x100UL)
 
#define BLE_BLE_INTCNTL_REG_SWINTMSK_Pos   (9UL)
 
#define BLE_BLE_INTCNTL_REG_SWINTMSK_Msk   (0x200UL)
 
#define BLE_BLE_INTCNTL_REG_CSCNTDEVMSK_Pos   (15UL)
 
#define BLE_BLE_INTCNTL_REG_CSCNTDEVMSK_Msk   (0x8000UL)
 
#define BLE_BLE_INTSTAT_REG_CSCNTINTSTAT_Pos   (0UL)
 
#define BLE_BLE_INTSTAT_REG_CSCNTINTSTAT_Msk   (0x1UL)
 
#define BLE_BLE_INTSTAT_REG_RXINTSTAT_Pos   (1UL)
 
#define BLE_BLE_INTSTAT_REG_RXINTSTAT_Msk   (0x2UL)
 
#define BLE_BLE_INTSTAT_REG_SLPINTSTAT_Pos   (2UL)
 
#define BLE_BLE_INTSTAT_REG_SLPINTSTAT_Msk   (0x4UL)
 
#define BLE_BLE_INTSTAT_REG_EVENTINTSTAT_Pos   (3UL)
 
#define BLE_BLE_INTSTAT_REG_EVENTINTSTAT_Msk   (0x8UL)
 
#define BLE_BLE_INTSTAT_REG_CRYPTINTSTAT_Pos   (4UL)
 
#define BLE_BLE_INTSTAT_REG_CRYPTINTSTAT_Msk   (0x10UL)
 
#define BLE_BLE_INTSTAT_REG_ERRORINTSTAT_Pos   (5UL)
 
#define BLE_BLE_INTSTAT_REG_ERRORINTSTAT_Msk   (0x20UL)
 
#define BLE_BLE_INTSTAT_REG_GROSSTGTIMINTSTAT_Pos   (6UL)
 
#define BLE_BLE_INTSTAT_REG_GROSSTGTIMINTSTAT_Msk   (0x40UL)
 
#define BLE_BLE_INTSTAT_REG_FINETGTIMINTSTAT_Pos   (7UL)
 
#define BLE_BLE_INTSTAT_REG_FINETGTIMINTSTAT_Msk   (0x80UL)
 
#define BLE_BLE_INTSTAT_REG_EVENTAPFAINTSTAT_Pos   (8UL)
 
#define BLE_BLE_INTSTAT_REG_EVENTAPFAINTSTAT_Msk   (0x100UL)
 
#define BLE_BLE_INTSTAT_REG_SWINTSTAT_Pos   (9UL)
 
#define BLE_BLE_INTSTAT_REG_SWINTSTAT_Msk   (0x200UL)
 
#define BLE_BLE_INTRAWSTAT_REG_CSCNTINTRAWSTAT_Pos   (0UL)
 
#define BLE_BLE_INTRAWSTAT_REG_CSCNTINTRAWSTAT_Msk   (0x1UL)
 
#define BLE_BLE_INTRAWSTAT_REG_RXINTRAWSTAT_Pos   (1UL)
 
#define BLE_BLE_INTRAWSTAT_REG_RXINTRAWSTAT_Msk   (0x2UL)
 
#define BLE_BLE_INTRAWSTAT_REG_SLPINTRAWSTAT_Pos   (2UL)
 
#define BLE_BLE_INTRAWSTAT_REG_SLPINTRAWSTAT_Msk   (0x4UL)
 
#define BLE_BLE_INTRAWSTAT_REG_EVENTINTRAWSTAT_Pos   (3UL)
 
#define BLE_BLE_INTRAWSTAT_REG_EVENTINTRAWSTAT_Msk   (0x8UL)
 
#define BLE_BLE_INTRAWSTAT_REG_CRYPTINTRAWSTAT_Pos   (4UL)
 
#define BLE_BLE_INTRAWSTAT_REG_CRYPTINTRAWSTAT_Msk   (0x10UL)
 
#define BLE_BLE_INTRAWSTAT_REG_ERRORINTRAWSTAT_Pos   (5UL)
 
#define BLE_BLE_INTRAWSTAT_REG_ERRORINTRAWSTAT_Msk   (0x20UL)
 
#define BLE_BLE_INTRAWSTAT_REG_GROSSTGTIMINTRAWSTAT_Pos   (6UL)
 
#define BLE_BLE_INTRAWSTAT_REG_GROSSTGTIMINTRAWSTAT_Msk   (0x40UL)
 
#define BLE_BLE_INTRAWSTAT_REG_FINETGTIMINTRAWSTAT_Pos   (7UL)
 
#define BLE_BLE_INTRAWSTAT_REG_FINETGTIMINTRAWSTAT_Msk   (0x80UL)
 
#define BLE_BLE_INTRAWSTAT_REG_EVENTAPFAINTRAWSTAT_Pos   (8UL)
 
#define BLE_BLE_INTRAWSTAT_REG_EVENTAPFAINTRAWSTAT_Msk   (0x100UL)
 
#define BLE_BLE_INTRAWSTAT_REG_SWINTRAWSTAT_Pos   (9UL)
 
#define BLE_BLE_INTRAWSTAT_REG_SWINTRAWSTAT_Msk   (0x200UL)
 
#define BLE_BLE_INTACK_REG_CSCNTINTACK_Pos   (0UL)
 
#define BLE_BLE_INTACK_REG_CSCNTINTACK_Msk   (0x1UL)
 
#define BLE_BLE_INTACK_REG_RXINTACK_Pos   (1UL)
 
#define BLE_BLE_INTACK_REG_RXINTACK_Msk   (0x2UL)
 
#define BLE_BLE_INTACK_REG_SLPINTACK_Pos   (2UL)
 
#define BLE_BLE_INTACK_REG_SLPINTACK_Msk   (0x4UL)
 
#define BLE_BLE_INTACK_REG_EVENTINTACK_Pos   (3UL)
 
#define BLE_BLE_INTACK_REG_EVENTINTACK_Msk   (0x8UL)
 
#define BLE_BLE_INTACK_REG_CRYPTINTACK_Pos   (4UL)
 
#define BLE_BLE_INTACK_REG_CRYPTINTACK_Msk   (0x10UL)
 
#define BLE_BLE_INTACK_REG_ERRORINTACK_Pos   (5UL)
 
#define BLE_BLE_INTACK_REG_ERRORINTACK_Msk   (0x20UL)
 
#define BLE_BLE_INTACK_REG_GROSSTGTIMINTACK_Pos   (6UL)
 
#define BLE_BLE_INTACK_REG_GROSSTGTIMINTACK_Msk   (0x40UL)
 
#define BLE_BLE_INTACK_REG_FINETGTIMINTACK_Pos   (7UL)
 
#define BLE_BLE_INTACK_REG_FINETGTIMINTACK_Msk   (0x80UL)
 
#define BLE_BLE_INTACK_REG_EVENTAPFAINTACK_Pos   (8UL)
 
#define BLE_BLE_INTACK_REG_EVENTAPFAINTACK_Msk   (0x100UL)
 
#define BLE_BLE_INTACK_REG_SWINTACK_Pos   (9UL)
 
#define BLE_BLE_INTACK_REG_SWINTACK_Msk   (0x200UL)
 
#define BLE_BLE_BASETIMECNT_REG_BASETIMECNT_Pos   (0UL)
 
#define BLE_BLE_BASETIMECNT_REG_BASETIMECNT_Msk   (0x7ffffffUL)
 
#define BLE_BLE_FINETIMECNT_REG_FINECNT_Pos   (0UL)
 
#define BLE_BLE_FINETIMECNT_REG_FINECNT_Msk   (0x3ffUL)
 
#define BLE_BLE_BDADDRL_REG_BDADDRL_Pos   (0UL)
 
#define BLE_BLE_BDADDRL_REG_BDADDRL_Msk   (0xffffffffUL)
 
#define BLE_BLE_BDADDRU_REG_BDADDRU_Pos   (0UL)
 
#define BLE_BLE_BDADDRU_REG_BDADDRU_Msk   (0xffffUL)
 
#define BLE_BLE_BDADDRU_REG_PRIV_NPUB_Pos   (16UL)
 
#define BLE_BLE_BDADDRU_REG_PRIV_NPUB_Msk   (0x10000UL)
 
#define BLE_BLE_CURRENTRXDESCPTR_REG_CURRENTRXDESCPTR_Pos   (0UL)
 
#define BLE_BLE_CURRENTRXDESCPTR_REG_CURRENTRXDESCPTR_Msk   (0x7fffUL)
 
#define BLE_BLE_CURRENTRXDESCPTR_REG_ETPTR_Pos   (16UL)
 
#define BLE_BLE_CURRENTRXDESCPTR_REG_ETPTR_Msk   (0xffff0000UL)
 
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_IRQ_EN_Pos   (0UL)
 
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_IRQ_EN_Msk   (0x3UL)
 
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_ON_Pos   (2UL)
 
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_ON_Msk   (0x4UL)
 
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_CORR_EN_Pos   (3UL)
 
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_CORR_EN_Msk   (0x8UL)
 
#define BLE_BLE_DEEPSLCNTL_REG_SOFT_WAKEUP_REQ_Pos   (4UL)
 
#define BLE_BLE_DEEPSLCNTL_REG_SOFT_WAKEUP_REQ_Msk   (0x10UL)
 
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_STAT_Pos   (15UL)
 
#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_STAT_Msk   (0x8000UL)
 
#define BLE_BLE_DEEPSLCNTL_REG_EXTWKUPDSB_Pos   (31UL)
 
#define BLE_BLE_DEEPSLCNTL_REG_EXTWKUPDSB_Msk   (0x80000000UL)
 
#define BLE_BLE_DEEPSLWKUP_REG_DEEPSLTIME_Pos   (0UL)
 
#define BLE_BLE_DEEPSLWKUP_REG_DEEPSLTIME_Msk   (0xffffffffUL)
 
#define BLE_BLE_DEEPSLSTAT_REG_DEEPSLDUR_Pos   (0UL)
 
#define BLE_BLE_DEEPSLSTAT_REG_DEEPSLDUR_Msk   (0xffffffffUL)
 
#define BLE_BLE_ENBPRESET_REG_TWIRQ_RESET_Pos   (0UL)
 
#define BLE_BLE_ENBPRESET_REG_TWIRQ_RESET_Msk   (0x3ffUL)
 
#define BLE_BLE_ENBPRESET_REG_TWIRQ_SET_Pos   (10UL)
 
#define BLE_BLE_ENBPRESET_REG_TWIRQ_SET_Msk   (0x1ffc00UL)
 
#define BLE_BLE_ENBPRESET_REG_TWEXT_Pos   (21UL)
 
#define BLE_BLE_ENBPRESET_REG_TWEXT_Msk   (0xffe00000UL)
 
#define BLE_BLE_FINECNTCORR_REG_FINECNTCORR_Pos   (0UL)
 
#define BLE_BLE_FINECNTCORR_REG_FINECNTCORR_Msk   (0x3ffUL)
 
#define BLE_BLE_BASETIMECNTCORR_REG_BASETIMECNTCORR_Pos   (0UL)
 
#define BLE_BLE_BASETIMECNTCORR_REG_BASETIMECNTCORR_Msk   (0x7ffffffUL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG0_Pos   (0UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG0_Msk   (0x3fUL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG0_EN_Pos   (7UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG0_EN_Msk   (0x80UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG1_Pos   (8UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG1_Msk   (0x3f00UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG1_EN_Pos   (15UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG1_EN_Msk   (0x8000UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG2_Pos   (16UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG2_Msk   (0x3f0000UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG2_EN_Pos   (23UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG2_EN_Msk   (0x800000UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG3_Pos   (24UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG3_Msk   (0x3f000000UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG3_EN_Pos   (31UL)
 
#define BLE_BLE_DIAGCNTL_REG_DIAG3_EN_Msk   (0x80000000UL)
 
#define BLE_BLE_DIAGSTAT_REG_DIAG0STAT_Pos   (0UL)
 
#define BLE_BLE_DIAGSTAT_REG_DIAG0STAT_Msk   (0xffUL)
 
#define BLE_BLE_DIAGSTAT_REG_DIAG1STAT_Pos   (8UL)
 
#define BLE_BLE_DIAGSTAT_REG_DIAG1STAT_Msk   (0xff00UL)
 
#define BLE_BLE_DIAGSTAT_REG_DIAG2STAT_Pos   (16UL)
 
#define BLE_BLE_DIAGSTAT_REG_DIAG2STAT_Msk   (0xff0000UL)
 
#define BLE_BLE_DIAGSTAT_REG_DIAG3STAT_Pos   (24UL)
 
#define BLE_BLE_DIAGSTAT_REG_DIAG3STAT_Msk   (0xff000000UL)
 
#define BLE_BLE_DEBUGADDMAX_REG_EM_ADDMAX_Pos   (0UL)
 
#define BLE_BLE_DEBUGADDMAX_REG_EM_ADDMAX_Msk   (0xffffUL)
 
#define BLE_BLE_DEBUGADDMAX_REG_REG_ADDMAX_Pos   (16UL)
 
#define BLE_BLE_DEBUGADDMAX_REG_REG_ADDMAX_Msk   (0xffff0000UL)
 
#define BLE_BLE_DEBUGADDMIN_REG_EM_ADDMIN_Pos   (0UL)
 
#define BLE_BLE_DEBUGADDMIN_REG_EM_ADDMIN_Msk   (0xffffUL)
 
#define BLE_BLE_DEBUGADDMIN_REG_REG_ADDMIN_Pos   (16UL)
 
#define BLE_BLE_DEBUGADDMIN_REG_REG_ADDMIN_Msk   (0xffff0000UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_TXCRYPT_ERROR_Pos   (0UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_TXCRYPT_ERROR_Msk   (0x1UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_RXCRYPT_ERROR_Pos   (1UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_RXCRYPT_ERROR_Msk   (0x2UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_PKTCNTL_EMACC_ERROR_Pos   (2UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_PKTCNTL_EMACC_ERROR_Msk   (0x4UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_RADIO_EMACC_ERROR_Pos   (3UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_RADIO_EMACC_ERROR_Msk   (0x8UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_EMACC_ERROR_Pos   (4UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_EMACC_ERROR_Msk   (0x10UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_ENTRY_ERROR_Pos   (5UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_ENTRY_ERROR_Msk   (0x20UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_APFM_ERROR_Pos   (6UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_APFM_ERROR_Msk   (0x40UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_CNTL_APFM_ERROR_Pos   (7UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_EVT_CNTL_APFM_ERROR_Msk   (0x80UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_WHITELIST_ERROR_Pos   (8UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_WHITELIST_ERROR_Msk   (0x100UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_IFS_UNDERRUN_Pos   (9UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_IFS_UNDERRUN_Msk   (0x200UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_ADV_UNDERRUN_Pos   (10UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_ADV_UNDERRUN_Msk   (0x400UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_LLCHMAP_ERROR_Pos   (11UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_LLCHMAP_ERROR_Msk   (0x800UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_CSFORMAT_ERROR_Pos   (12UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_CSFORMAT_ERROR_Msk   (0x1000UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_TXDESC_EMPTY_ERROR_Pos   (13UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_TXDESC_EMPTY_ERROR_Msk   (0x2000UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_RXDESC_EMPTY_ERROR_Pos   (14UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_RXDESC_EMPTY_ERROR_Msk   (0x4000UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_TXDATA_PTR_ERROR_Pos   (15UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_TXDATA_PTR_ERROR_Msk   (0x8000UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_RXDATA_PTR_ERROR_Pos   (16UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_RXDATA_PTR_ERROR_Msk   (0x10000UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_CONCEVTIRQ_ERROR_Pos   (17UL)
 
#define BLE_BLE_ERRORTYPESTAT_REG_CONCEVTIRQ_ERROR_Msk   (0x20000UL)
 
#define BLE_BLE_SWPROFILING_REG_SWPROFVAL_Pos   (0UL)
 
#define BLE_BLE_SWPROFILING_REG_SWPROFVAL_Msk   (0xffffffffUL)
 
#define BLE_BLE_RADIOCNTL0_REG_field246rsv_Pos   (2UL)
 
#define BLE_BLE_RADIOCNTL0_REG_field246rsv_Msk   (0x1cUL)
 
#define BLE_BLE_RADIOCNTL1_REG_XRFSEL_Pos   (16UL)
 
#define BLE_BLE_RADIOCNTL1_REG_XRFSEL_Msk   (0x1f0000UL)
 
#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRUP_Pos   (0UL)
 
#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRUP_Msk   (0xffUL)
 
#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRDN_Pos   (8UL)
 
#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRDN_Msk   (0xf00UL)
 
#define BLE_BLE_RADIOPWRUPDN_REG_RXPWRUP_Pos   (16UL)
 
#define BLE_BLE_RADIOPWRUPDN_REG_RXPWRUP_Msk   (0xff0000UL)
 
#define BLE_BLE_RADIOPWRUPDN_REG_RTRIP_DELAY_Pos   (24UL)
 
#define BLE_BLE_RADIOPWRUPDN_REG_RTRIP_DELAY_Msk   (0x7f000000UL)
 
#define BLE_BLE_ADVCHMAP_REG_ADVCHMAP_Pos   (0UL)
 
#define BLE_BLE_ADVCHMAP_REG_ADVCHMAP_Msk   (0x7UL)
 
#define BLE_BLE_ADVTIM_REG_ADVINT_Pos   (0UL)
 
#define BLE_BLE_ADVTIM_REG_ADVINT_Msk   (0x3fffUL)
 
#define BLE_BLE_ACTSCANSTAT_REG_UPPERLIMIT_Pos   (0UL)
 
#define BLE_BLE_ACTSCANSTAT_REG_UPPERLIMIT_Msk   (0x1ffUL)
 
#define BLE_BLE_ACTSCANSTAT_REG_BACKOFF_Pos   (16UL)
 
#define BLE_BLE_ACTSCANSTAT_REG_BACKOFF_Msk   (0x1ff0000UL)
 
#define BLE_BLE_WLPUBADDPTR_REG_WLPUBADDPTR_Pos   (0UL)
 
#define BLE_BLE_WLPUBADDPTR_REG_WLPUBADDPTR_Msk   (0xffffUL)
 
#define BLE_BLE_WLPRIVADDPTR_REG_WLPRIVADDPTR_Pos   (0UL)
 
#define BLE_BLE_WLPRIVADDPTR_REG_WLPRIVADDPTR_Msk   (0xffffUL)
 
#define BLE_BLE_WLNBDEV_REG_NBPUBDEV_Pos   (0UL)
 
#define BLE_BLE_WLNBDEV_REG_NBPUBDEV_Msk   (0xffUL)
 
#define BLE_BLE_WLNBDEV_REG_NBPRIVDEV_Pos   (8UL)
 
#define BLE_BLE_WLNBDEV_REG_NBPRIVDEV_Msk   (0xff00UL)
 
#define BLE_BLE_AESCNTL_REG_AES_START_Pos   (0UL)
 
#define BLE_BLE_AESCNTL_REG_AES_START_Msk   (0x1UL)
 
#define BLE_BLE_AESCNTL_REG_AES_MODE_Pos   (1UL)
 
#define BLE_BLE_AESCNTL_REG_AES_MODE_Msk   (0x2UL)
 
#define BLE_BLE_AESKEY31_0_REG_AESKEY31_0_Pos   (0UL)
 
#define BLE_BLE_AESKEY31_0_REG_AESKEY31_0_Msk   (0xffffffffUL)
 
#define BLE_BLE_AESKEY63_32_REG_AESKEY63_32_Pos   (0UL)
 
#define BLE_BLE_AESKEY63_32_REG_AESKEY63_32_Msk   (0xffffffffUL)
 
#define BLE_BLE_AESKEY95_64_REG_AESKEY95_64_Pos   (0UL)
 
#define BLE_BLE_AESKEY95_64_REG_AESKEY95_64_Msk   (0xffffffffUL)
 
#define BLE_BLE_AESKEY127_96_REG_AESKEY127_96_Pos   (0UL)
 
#define BLE_BLE_AESKEY127_96_REG_AESKEY127_96_Msk   (0xffffffffUL)
 
#define BLE_BLE_AESPTR_REG_AESPTR_Pos   (0UL)
 
#define BLE_BLE_AESPTR_REG_AESPTR_Msk   (0xffffUL)
 
#define BLE_BLE_TXMICVAL_REG_TXMICVAL_Pos   (0UL)
 
#define BLE_BLE_TXMICVAL_REG_TXMICVAL_Msk   (0xffffffffUL)
 
#define BLE_BLE_RXMICVAL_REG_RXMICVAL_Pos   (0UL)
 
#define BLE_BLE_RXMICVAL_REG_RXMICVAL_Msk   (0xffffffffUL)
 
#define BLE_BLE_RFTESTCNTL_REG_TXLENGTH_Pos   (0UL)
 
#define BLE_BLE_RFTESTCNTL_REG_TXLENGTH_Msk   (0x1ffUL)
 
#define BLE_BLE_RFTESTCNTL_REG_TXPKTCNTEN_Pos   (11UL)
 
#define BLE_BLE_RFTESTCNTL_REG_TXPKTCNTEN_Msk   (0x800UL)
 
#define BLE_BLE_RFTESTCNTL_REG_TXPLDSRC_Pos   (12UL)
 
#define BLE_BLE_RFTESTCNTL_REG_TXPLDSRC_Msk   (0x1000UL)
 
#define BLE_BLE_RFTESTCNTL_REG_PRBSTYPE_Pos   (13UL)
 
#define BLE_BLE_RFTESTCNTL_REG_PRBSTYPE_Msk   (0x2000UL)
 
#define BLE_BLE_RFTESTCNTL_REG_TXLENGTHSRC_Pos   (14UL)
 
#define BLE_BLE_RFTESTCNTL_REG_TXLENGTHSRC_Msk   (0x4000UL)
 
#define BLE_BLE_RFTESTCNTL_REG_INFINITETX_Pos   (15UL)
 
#define BLE_BLE_RFTESTCNTL_REG_INFINITETX_Msk   (0x8000UL)
 
#define BLE_BLE_RFTESTCNTL_REG_RXPKTCNTEN_Pos   (27UL)
 
#define BLE_BLE_RFTESTCNTL_REG_RXPKTCNTEN_Msk   (0x8000000UL)
 
#define BLE_BLE_RFTESTCNTL_REG_INFINITERX_Pos   (31UL)
 
#define BLE_BLE_RFTESTCNTL_REG_INFINITERX_Msk   (0x80000000UL)
 
#define BLE_BLE_RFTESTTXSTAT_REG_TXPKTCNT_Pos   (0UL)
 
#define BLE_BLE_RFTESTTXSTAT_REG_TXPKTCNT_Msk   (0xffffffffUL)
 
#define BLE_BLE_RFTESTRXSTAT_REG_RXPKTCNT_Pos   (0UL)
 
#define BLE_BLE_RFTESTRXSTAT_REG_RXPKTCNT_Msk   (0xffffffffUL)
 
#define BLE_BLE_TIMGENCNTL_REG_PREFETCH_TIME_Pos   (0UL)
 
#define BLE_BLE_TIMGENCNTL_REG_PREFETCH_TIME_Msk   (0x1ffUL)
 
#define BLE_BLE_TIMGENCNTL_REG_PREFETCHABORT_TIME_Pos   (16UL)
 
#define BLE_BLE_TIMGENCNTL_REG_PREFETCHABORT_TIME_Msk   (0x3ff0000UL)
 
#define BLE_BLE_TIMGENCNTL_REG_APFM_EN_Pos   (31UL)
 
#define BLE_BLE_TIMGENCNTL_REG_APFM_EN_Msk   (0x80000000UL)
 
#define BLE_BLE_GROSSTIMTGT_REG_GROSSTARGET_Pos   (0UL)
 
#define BLE_BLE_GROSSTIMTGT_REG_GROSSTARGET_Msk   (0x7fffffUL)
 
#define BLE_BLE_FINETIMTGT_REG_FINETARGET_Pos   (0UL)
 
#define BLE_BLE_FINETIMTGT_REG_FINETARGET_Msk   (0x7ffffffUL)
 
#define BLE_BLE_SAMPLECLK_REG_SAMP_Pos   (0UL)
 
#define BLE_BLE_SAMPLECLK_REG_SAMP_Msk   (0x1UL)
 
#define BLE_BLE_COEXIFCNTL0_REG_COEX_EN_Pos   (0UL)
 
#define BLE_BLE_COEXIFCNTL0_REG_COEX_EN_Msk   (0x1UL)
 
#define BLE_BLE_COEXIFCNTL0_REG_SYNCGEN_EN_Pos   (1UL)
 
#define BLE_BLE_COEXIFCNTL0_REG_SYNCGEN_EN_Msk   (0x2UL)
 
#define BLE_BLE_COEXIFCNTL0_REG_WLANRXMSK_Pos   (4UL)
 
#define BLE_BLE_COEXIFCNTL0_REG_WLANRXMSK_Msk   (0x30UL)
 
#define BLE_BLE_COEXIFCNTL0_REG_WLANTXMSK_Pos   (6UL)
 
#define BLE_BLE_COEXIFCNTL0_REG_WLANTXMSK_Msk   (0xc0UL)
 
#define BLE_BLE_COEXIFCNTL0_REG_WLCTXPRIOMODE_Pos   (16UL)
 
#define BLE_BLE_COEXIFCNTL0_REG_WLCTXPRIOMODE_Msk   (0x30000UL)
 
#define BLE_BLE_COEXIFCNTL0_REG_WLCRXPRIOMODE_Pos   (20UL)
 
#define BLE_BLE_COEXIFCNTL0_REG_WLCRXPRIOMODE_Msk   (0x300000UL)
 
#define BLE_BLE_COEXIFCNTL1_REG_WLCPDELAY_Pos   (0UL)
 
#define BLE_BLE_COEXIFCNTL1_REG_WLCPDELAY_Msk   (0x7fUL)
 
#define BLE_BLE_COEXIFCNTL1_REG_WLCPDURATION_Pos   (8UL)
 
#define BLE_BLE_COEXIFCNTL1_REG_WLCPDURATION_Msk   (0x7f00UL)
 
#define BLE_BLE_COEXIFCNTL1_REG_WLCPTXTHR_Pos   (16UL)
 
#define BLE_BLE_COEXIFCNTL1_REG_WLCPTXTHR_Msk   (0x1f0000UL)
 
#define BLE_BLE_COEXIFCNTL1_REG_WLCPRXTHR_Pos   (24UL)
 
#define BLE_BLE_COEXIFCNTL1_REG_WLCPRXTHR_Msk   (0x1f000000UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM0_Pos   (0UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM0_Msk   (0xfUL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM1_Pos   (4UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM1_Msk   (0xf0UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM2_Pos   (8UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM2_Msk   (0xf00UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM3_Pos   (12UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM3_Msk   (0xf000UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM4_Pos   (16UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM4_Msk   (0xf0000UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM5_Pos   (20UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM5_Msk   (0xf00000UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM6_Pos   (24UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM6_Msk   (0xf000000UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM7_Pos   (28UL)
 
#define BLE_BLE_BLEMPRIO0_REG_BLEM7_Msk   (0xf0000000UL)
 
#define BLE_BLE_BLEMPRIO1_REG_BLEMDEFAULT_Pos   (28UL)
 
#define BLE_BLE_BLEMPRIO1_REG_BLEMDEFAULT_Msk   (0xf0000000UL)
 
#define BLE_BLE_CNTL2_REG_EMACCERRSTAT_Pos   (0UL)
 
#define BLE_BLE_CNTL2_REG_EMACCERRSTAT_Msk   (0x1UL)
 
#define BLE_BLE_CNTL2_REG_EMACCERRACK_Pos   (1UL)
 
#define BLE_BLE_CNTL2_REG_EMACCERRACK_Msk   (0x2UL)
 
#define BLE_BLE_CNTL2_REG_EMACCERRMSK_Pos   (2UL)
 
#define BLE_BLE_CNTL2_REG_EMACCERRMSK_Msk   (0x4UL)
 
#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_Pos   (3UL)
 
#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_Msk   (0x8UL)
 
#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_SEL_Pos   (4UL)
 
#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_SEL_Msk   (0x30UL)
 
#define BLE_BLE_CNTL2_REG_BLE_CLK_STAT_Pos   (6UL)
 
#define BLE_BLE_CNTL2_REG_BLE_CLK_STAT_Msk   (0x40UL)
 
#define BLE_BLE_CNTL2_REG_MON_LP_CLK_Pos   (7UL)
 
#define BLE_BLE_CNTL2_REG_MON_LP_CLK_Msk   (0x80UL)
 
#define BLE_BLE_CNTL2_REG_RADIO_PWRDN_ALLOW_Pos   (8UL)
 
#define BLE_BLE_CNTL2_REG_RADIO_PWRDN_ALLOW_Msk   (0x100UL)
 
#define BLE_BLE_CNTL2_REG_BLE_CLK_SEL_Pos   (9UL)
 
#define BLE_BLE_CNTL2_REG_BLE_CLK_SEL_Msk   (0x7e00UL)
 
#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_SRC_Pos   (15UL)
 
#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_SRC_Msk   (0x8000UL)
 
#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_MODE_Pos   (16UL)
 
#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_MODE_Msk   (0x10000UL)
 
#define BLE_BLE_CNTL2_REG_BLE_PTI_SOURCE_SEL_Pos   (17UL)
 
#define BLE_BLE_CNTL2_REG_BLE_PTI_SOURCE_SEL_Msk   (0x20000UL)
 
#define BLE_BLE_CNTL2_REG_BB_ONLY_Pos   (18UL)
 
#define BLE_BLE_CNTL2_REG_BB_ONLY_Msk   (0x40000UL)
 
#define BLE_BLE_CNTL2_REG_SW_RPL_SPI_Pos   (19UL)
 
#define BLE_BLE_CNTL2_REG_SW_RPL_SPI_Msk   (0x80000UL)
 
#define BLE_BLE_CNTL2_REG_WAKEUPLPSTAT_Pos   (20UL)
 
#define BLE_BLE_CNTL2_REG_WAKEUPLPSTAT_Msk   (0x100000UL)
 
#define BLE_BLE_CNTL2_REG_BLE_RSSI_SEL_Pos   (21UL)
 
#define BLE_BLE_CNTL2_REG_BLE_RSSI_SEL_Msk   (0x200000UL)
 
#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_START_Pos   (22UL)
 
#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_START_Msk   (0xffc00000UL)
 
#define BLE_BLE_EM_BASE_REG_BLE_EM_BASE_16_10_Pos   (10UL)
 
#define BLE_BLE_EM_BASE_REG_BLE_EM_BASE_16_10_Msk   (0x1fc00UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG4_Pos   (0UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG4_Msk   (0x3fUL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG4_EN_Pos   (7UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG4_EN_Msk   (0x80UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG5_Pos   (8UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG5_Msk   (0x3f00UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG5_EN_Pos   (15UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG5_EN_Msk   (0x8000UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG6_Pos   (16UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG6_Msk   (0x3f0000UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG6_EN_Pos   (23UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG6_EN_Msk   (0x800000UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG7_Pos   (24UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG7_Msk   (0x3f000000UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG7_EN_Pos   (31UL)
 
#define BLE_BLE_DIAGCNTL2_REG_DIAG7_EN_Msk   (0x80000000UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG0_BIT_Pos   (0UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG0_BIT_Msk   (0x7UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG0_INV_Pos   (3UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG0_INV_Msk   (0x8UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG1_BIT_Pos   (4UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG1_BIT_Msk   (0x70UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG1_INV_Pos   (7UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG1_INV_Msk   (0x80UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG2_BIT_Pos   (8UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG2_BIT_Msk   (0x700UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG2_INV_Pos   (11UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG2_INV_Msk   (0x800UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG3_BIT_Pos   (12UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG3_BIT_Msk   (0x7000UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG3_INV_Pos   (15UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG3_INV_Msk   (0x8000UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG4_BIT_Pos   (16UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG4_BIT_Msk   (0x70000UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG4_INV_Pos   (19UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG4_INV_Msk   (0x80000UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG5_BIT_Pos   (20UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG5_BIT_Msk   (0x700000UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG5_INV_Pos   (23UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG5_INV_Msk   (0x800000UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG6_BIT_Pos   (24UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG6_BIT_Msk   (0x7000000UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG6_INV_Pos   (27UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG6_INV_Msk   (0x8000000UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG7_BIT_Pos   (28UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG7_BIT_Msk   (0x70000000UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG7_INV_Pos   (31UL)
 
#define BLE_BLE_DIAGCNTL3_REG_DIAG7_INV_Msk   (0x80000000UL)
 
#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Pos   (0UL)
 
#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Msk   (0x1UL)
 
#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Pos   (1UL)
 
#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Msk   (0x2UL)
 
#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Pos   (0UL)
 
#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Msk   (0x3UL)
 
#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Pos   (0UL)
 
#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Msk   (0x3UL)
 
#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos   (0UL)
 
#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk   (0x1ffUL)
 
#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Pos   (9UL)
 
#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Msk   (0x200UL)
 
#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos   (10UL)
 
#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk   (0x400UL)
 
#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_OTP_CACHED_Pos   (11UL)
 
#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_OTP_CACHED_Msk   (0x800UL)
 
#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_QSPIFLASH_CACHED_Pos   (12UL)
 
#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_QSPIFLASH_CACHED_Msk   (0x1000UL)
 
#define CACHE_CACHE_CTRL3_REG_CACHE_ASSOCIATIVITY_RESET_VALUE_Pos   (0UL)
 
#define CACHE_CACHE_CTRL3_REG_CACHE_ASSOCIATIVITY_RESET_VALUE_Msk   (0x3UL)
 
#define CACHE_CACHE_CTRL3_REG_CACHE_LINE_SIZE_RESET_VALUE_Pos   (2UL)
 
#define CACHE_CACHE_CTRL3_REG_CACHE_LINE_SIZE_RESET_VALUE_Msk   (0xcUL)
 
#define CACHE_CACHE_CTRL3_REG_CACHE_RAM_SIZE_RESET_VALUE_Pos   (4UL)
 
#define CACHE_CACHE_CTRL3_REG_CACHE_RAM_SIZE_RESET_VALUE_Msk   (0x70UL)
 
#define CACHE_CACHE_CTRL3_REG_CACHE_CONTROLLER_RESET_Pos   (7UL)
 
#define CACHE_CACHE_CTRL3_REG_CACHE_CONTROLLER_RESET_Msk   (0x80UL)
 
#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Pos   (0UL)
 
#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Msk   (0x7ffffUL)
 
#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos   (0UL)
 
#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk   (0x3ffffUL)
 
#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Pos   (0UL)
 
#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Msk   (0x1UL)
 
#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos   (1UL)
 
#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk   (0x2UL)
 
#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos   (2UL)
 
#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk   (0x4UL)
 
#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_THRES_STATUS_Pos   (3UL)
 
#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_THRES_STATUS_Msk   (0x8UL)
 
#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Pos   (0UL)
 
#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk   (0x3ffffUL)
 
#define CACHE_CACHE_MRM_THRES_REG_MRM_THRES_Pos   (0UL)
 
#define CACHE_CACHE_MRM_THRES_REG_MRM_THRES_Msk   (0x3ffffUL)
 
#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Pos   (0UL)
 
#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Msk   (0x1UL)
 
#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Pos   (0UL)
 
#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk   (0xffUL)
 
#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Pos   (0UL)
 
#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk   (0xffUL)
 
#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Pos   (0UL)
 
#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk   (0xffUL)
 
#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Pos   (0UL)
 
#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Msk   (0xfUL)
 
#define CHIP_VERSION_CHIP_REVISION_REG_REVISION_ID_Pos   (0UL)
 
#define CHIP_VERSION_CHIP_REVISION_REG_REVISION_ID_Msk   (0xffUL)
 
#define CHIP_VERSION_CHIP_CONFIG1_REG_CHIP_CONFIG1_Pos   (0UL)
 
#define CHIP_VERSION_CHIP_CONFIG1_REG_CHIP_CONFIG1_Msk   (0xffUL)
 
#define CHIP_VERSION_CHIP_CONFIG2_REG_CHIP_CONFIG2_Pos   (0UL)
 
#define CHIP_VERSION_CHIP_CONFIG2_REG_CHIP_CONFIG2_Msk   (0xffUL)
 
#define CHIP_VERSION_CHIP_CONFIG3_REG_CHIP_CONFIG3_Pos   (0UL)
 
#define CHIP_VERSION_CHIP_CONFIG3_REG_CHIP_CONFIG3_Msk   (0xffUL)
 
#define COEX_COEX_CTRL_REG_PRGING_ARBITER_Pos   (0UL)
 
#define COEX_COEX_CTRL_REG_PRGING_ARBITER_Msk   (0x1UL)
 
#define COEX_COEX_CTRL_REG_DECISION_SW_ALL_Pos   (1UL)
 
#define COEX_COEX_CTRL_REG_DECISION_SW_ALL_Msk   (0x2UL)
 
#define COEX_COEX_CTRL_REG_TXRX_MON_FTDF_ALL_Pos   (2UL)
 
#define COEX_COEX_CTRL_REG_TXRX_MON_FTDF_ALL_Msk   (0x4UL)
 
#define COEX_COEX_CTRL_REG_TXRX_MON_BLE_ALL_Pos   (3UL)
 
#define COEX_COEX_CTRL_REG_TXRX_MON_BLE_ALL_Msk   (0x8UL)
 
#define COEX_COEX_CTRL_REG_SMART_ACT_IMPL_Pos   (4UL)
 
#define COEX_COEX_CTRL_REG_SMART_ACT_IMPL_Msk   (0x10UL)
 
#define COEX_COEX_CTRL_REG_SEL_COEX_DIAG_Pos   (5UL)
 
#define COEX_COEX_CTRL_REG_SEL_COEX_DIAG_Msk   (0x60UL)
 
#define COEX_COEX_CTRL_REG_SEL_FTDF_CCA_Pos   (7UL)
 
#define COEX_COEX_CTRL_REG_SEL_FTDF_CCA_Msk   (0x80UL)
 
#define COEX_COEX_CTRL_REG_SEL_FTDF_PTI_Pos   (8UL)
 
#define COEX_COEX_CTRL_REG_SEL_FTDF_PTI_Msk   (0x100UL)
 
#define COEX_COEX_CTRL_REG_SEL_BLE_PTI_Pos   (9UL)
 
#define COEX_COEX_CTRL_REG_SEL_BLE_PTI_Msk   (0x200UL)
 
#define COEX_COEX_CTRL_REG_SEL_BLE_WLAN_TX_RX_Pos   (10UL)
 
#define COEX_COEX_CTRL_REG_SEL_BLE_WLAN_TX_RX_Msk   (0x400UL)
 
#define COEX_COEX_CTRL_REG_SEL_BLE_RADIO_BUSY_Pos   (11UL)
 
#define COEX_COEX_CTRL_REG_SEL_BLE_RADIO_BUSY_Msk   (0x1800UL)
 
#define COEX_COEX_CTRL_REG_IGNORE_EXT_Pos   (13UL)
 
#define COEX_COEX_CTRL_REG_IGNORE_EXT_Msk   (0x2000UL)
 
#define COEX_COEX_CTRL_REG_IGNORE_FTDF_Pos   (14UL)
 
#define COEX_COEX_CTRL_REG_IGNORE_FTDF_Msk   (0x4000UL)
 
#define COEX_COEX_CTRL_REG_IGNORE_BLE_Pos   (15UL)
 
#define COEX_COEX_CTRL_REG_IGNORE_BLE_Msk   (0x8000UL)
 
#define COEX_COEX_STAT_REG_COEX_DECISION_PTR_Pos   (0UL)
 
#define COEX_COEX_STAT_REG_COEX_DECISION_PTR_Msk   (0xfUL)
 
#define COEX_COEX_STAT_REG_COEX_DECISION_Pos   (5UL)
 
#define COEX_COEX_STAT_REG_COEX_DECISION_Msk   (0x60UL)
 
#define COEX_COEX_STAT_REG_COEX_CLOSING_Pos   (7UL)
 
#define COEX_COEX_STAT_REG_COEX_CLOSING_Msk   (0x80UL)
 
#define COEX_COEX_STAT_REG_SMART_ACT_Pos   (8UL)
 
#define COEX_COEX_STAT_REG_SMART_ACT_Msk   (0x100UL)
 
#define COEX_COEX_STAT_REG_SMART_PRI_Pos   (9UL)
 
#define COEX_COEX_STAT_REG_SMART_PRI_Msk   (0x200UL)
 
#define COEX_COEX_STAT_REG_EXT_ACT0_Pos   (10UL)
 
#define COEX_COEX_STAT_REG_EXT_ACT0_Msk   (0x400UL)
 
#define COEX_COEX_STAT_REG_EXT_ACT1_Pos   (11UL)
 
#define COEX_COEX_STAT_REG_EXT_ACT1_Msk   (0x800UL)
 
#define COEX_COEX_STAT_REG_COEX_RADIO_BUSY_Pos   (12UL)
 
#define COEX_COEX_STAT_REG_COEX_RADIO_BUSY_Msk   (0x1000UL)
 
#define COEX_COEX_STAT_REG_IGNORE_EXT_STAT_Pos   (13UL)
 
#define COEX_COEX_STAT_REG_IGNORE_EXT_STAT_Msk   (0x2000UL)
 
#define COEX_COEX_STAT_REG_IGNORE_FTDF_STAT_Pos   (14UL)
 
#define COEX_COEX_STAT_REG_IGNORE_FTDF_STAT_Msk   (0x4000UL)
 
#define COEX_COEX_STAT_REG_IGNORE_BLE_STAT_Pos   (15UL)
 
#define COEX_COEX_STAT_REG_IGNORE_BLE_STAT_Msk   (0x8000UL)
 
#define COEX_COEX_STAT2_REG_COEX_DECISION_WITH_CLOSING_Pos   (0UL)
 
#define COEX_COEX_STAT2_REG_COEX_DECISION_WITH_CLOSING_Msk   (0x7UL)
 
#define COEX_COEX_STAT2_REG_COEX_FTDF_ACTIVE_Pos   (3UL)
 
#define COEX_COEX_STAT2_REG_COEX_FTDF_ACTIVE_Msk   (0x8UL)
 
#define COEX_COEX_STAT2_REG_COEX_FTDF_RX_EN_Pos   (4UL)
 
#define COEX_COEX_STAT2_REG_COEX_FTDF_RX_EN_Msk   (0x10UL)
 
#define COEX_COEX_STAT2_REG_COEX_FTDF_TX_EN_Pos   (5UL)
 
#define COEX_COEX_STAT2_REG_COEX_FTDF_TX_EN_Msk   (0x20UL)
 
#define COEX_COEX_STAT2_REG_COEX_FTDF_PTI_INT_Pos   (6UL)
 
#define COEX_COEX_STAT2_REG_COEX_FTDF_PTI_INT_Msk   (0x1c0UL)
 
#define COEX_COEX_STAT2_REG_COEX_BLE_ACTIVE_Pos   (9UL)
 
#define COEX_COEX_STAT2_REG_COEX_BLE_ACTIVE_Msk   (0x200UL)
 
#define COEX_COEX_STAT2_REG_COEX_BLE_RX_EN_Pos   (10UL)
 
#define COEX_COEX_STAT2_REG_COEX_BLE_RX_EN_Msk   (0x400UL)
 
#define COEX_COEX_STAT2_REG_COEX_BLE_TX_EN_Pos   (11UL)
 
#define COEX_COEX_STAT2_REG_COEX_BLE_TX_EN_Msk   (0x800UL)
 
#define COEX_COEX_STAT2_REG_COEX_BLE_PTI_INT_Pos   (12UL)
 
#define COEX_COEX_STAT2_REG_COEX_BLE_PTI_INT_Msk   (0x7000UL)
 
#define COEX_COEX_STAT2_REG_COEX_EXT_ACT_Pos   (15UL)
 
#define COEX_COEX_STAT2_REG_COEX_EXT_ACT_Msk   (0x8000UL)
 
#define COEX_COEX_INT_MASK_REG_IRQ_TXRX_MON_Pos   (8UL)
 
#define COEX_COEX_INT_MASK_REG_IRQ_TXRX_MON_Msk   (0x100UL)
 
#define COEX_COEX_INT_MASK_REG_IRQ_DECISION_SW_Pos   (9UL)
 
#define COEX_COEX_INT_MASK_REG_IRQ_DECISION_SW_Msk   (0x200UL)
 
#define COEX_COEX_INT_STAT_REG_TXRX_MON_PTR_Pos   (0UL)
 
#define COEX_COEX_INT_STAT_REG_TXRX_MON_PTR_Msk   (0xfUL)
 
#define COEX_COEX_INT_STAT_REG_TXRX_MON_TX_Pos   (5UL)
 
#define COEX_COEX_INT_STAT_REG_TXRX_MON_TX_Msk   (0x20UL)
 
#define COEX_COEX_INT_STAT_REG_TXRX_MON_PASSED_Pos   (6UL)
 
#define COEX_COEX_INT_STAT_REG_TXRX_MON_PASSED_Msk   (0x40UL)
 
#define COEX_COEX_INT_STAT_REG_TXRX_MON_OVWR_Pos   (7UL)
 
#define COEX_COEX_INT_STAT_REG_TXRX_MON_OVWR_Msk   (0x80UL)
 
#define COEX_COEX_INT_STAT_REG_IRQ_TXRX_MON_Pos   (8UL)
 
#define COEX_COEX_INT_STAT_REG_IRQ_TXRX_MON_Msk   (0x100UL)
 
#define COEX_COEX_INT_STAT_REG_IRQ_DECISION_SW_Pos   (9UL)
 
#define COEX_COEX_INT_STAT_REG_IRQ_DECISION_SW_Msk   (0x200UL)
 
#define COEX_COEX_BLE_PTI_REG_COEX_BLE_PTI_Pos   (0UL)
 
#define COEX_COEX_BLE_PTI_REG_COEX_BLE_PTI_Msk   (0x7UL)
 
#define COEX_COEX_FTDF_PTI_REG_COEX_FTDF_PTI_Pos   (0UL)
 
#define COEX_COEX_FTDF_PTI_REG_COEX_FTDF_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI1_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI1_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI1_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI1_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI2_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI2_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI2_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI2_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI3_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI3_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI3_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI3_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI4_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI4_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI4_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI4_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI5_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI5_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI5_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI5_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI6_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI6_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI6_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI6_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI7_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI7_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI7_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI7_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI8_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI8_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI8_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI8_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI9_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI9_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI9_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI9_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI10_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI10_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI10_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI10_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI11_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI11_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI11_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI11_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI12_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI12_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI12_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI12_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI13_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI13_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI13_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI13_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI14_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI14_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI14_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI14_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define COEX_COEX_PRI15_REG_COEX_PRI_PTI_Pos   (0UL)
 
#define COEX_COEX_PRI15_REG_COEX_PRI_PTI_Msk   (0x7UL)
 
#define COEX_COEX_PRI15_REG_COEX_PRI_MAC_Pos   (3UL)
 
#define COEX_COEX_PRI15_REG_COEX_PRI_MAC_Msk   (0x18UL)
 
#define CRG_PER_CLK_PER_REG_UART_ENABLE_Pos   (0UL)
 
#define CRG_PER_CLK_PER_REG_UART_ENABLE_Msk   (0x1UL)
 
#define CRG_PER_CLK_PER_REG_SPI_ENABLE_Pos   (1UL)
 
#define CRG_PER_CLK_PER_REG_SPI_ENABLE_Msk   (0x2UL)
 
#define CRG_PER_CLK_PER_REG_I2C_ENABLE_Pos   (2UL)
 
#define CRG_PER_CLK_PER_REG_I2C_ENABLE_Msk   (0x4UL)
 
#define CRG_PER_CLK_PER_REG_QUAD_ENABLE_Pos   (3UL)
 
#define CRG_PER_CLK_PER_REG_QUAD_ENABLE_Msk   (0x8UL)
 
#define CRG_PER_CLK_PER_REG_IR_CLK_ENABLE_Pos   (4UL)
 
#define CRG_PER_CLK_PER_REG_IR_CLK_ENABLE_Msk   (0x10UL)
 
#define CRG_PER_CLK_PER_REG_KBSCAN_ENABLE_Pos   (5UL)
 
#define CRG_PER_CLK_PER_REG_KBSCAN_ENABLE_Msk   (0x20UL)
 
#define CRG_PER_CLK_PER_REG_SPI_CLK_SEL_Pos   (8UL)
 
#define CRG_PER_CLK_PER_REG_SPI_CLK_SEL_Msk   (0x100UL)
 
#define CRG_PER_CLK_PER_REG_I2C_CLK_SEL_Pos   (9UL)
 
#define CRG_PER_CLK_PER_REG_I2C_CLK_SEL_Msk   (0x200UL)
 
#define CRG_PER_CLK_PER_REG_KBSCAN_CLK_SEL_Pos   (10UL)
 
#define CRG_PER_CLK_PER_REG_KBSCAN_CLK_SEL_Msk   (0x400UL)
 
#define CRG_PER_CLK_PER_REG_ADC_CLK_SEL_Pos   (11UL)
 
#define CRG_PER_CLK_PER_REG_ADC_CLK_SEL_Msk   (0x800UL)
 
#define CRG_PER_PCM_DIV_REG_PCM_DIV_Pos   (0UL)
 
#define CRG_PER_PCM_DIV_REG_PCM_DIV_Msk   (0xfffUL)
 
#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Pos   (12UL)
 
#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Msk   (0x1000UL)
 
#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Pos   (13UL)
 
#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Msk   (0x2000UL)
 
#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Pos   (0UL)
 
#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Msk   (0xffffUL)
 
#define CRG_PER_PDM_DIV_REG_PDM_DIV_Pos   (0UL)
 
#define CRG_PER_PDM_DIV_REG_PDM_DIV_Msk   (0xffUL)
 
#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Pos   (8UL)
 
#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Msk   (0x100UL)
 
#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Pos   (9UL)
 
#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Msk   (0x200UL)
 
#define CRG_PER_SRC_DIV_REG_SRC_DIV_Pos   (0UL)
 
#define CRG_PER_SRC_DIV_REG_SRC_DIV_Msk   (0xffUL)
 
#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Pos   (8UL)
 
#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Msk   (0x100UL)
 
#define CRG_PER_EH_REG_EH_EN_Pos   (0UL)
 
#define CRG_PER_EH_REG_EH_EN_Msk   (0x1UL)
 
#define CRG_PER_USBPAD_REG_USBPAD_EN_Pos   (0UL)
 
#define CRG_PER_USBPAD_REG_USBPAD_EN_Msk   (0x1UL)
 
#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Pos   (1UL)
 
#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Msk   (0x2UL)
 
#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW2_ON_Pos   (2UL)
 
#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW2_ON_Msk   (0x4UL)
 
#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Pos   (0UL)
 
#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk   (0x7UL)
 
#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Pos   (4UL)
 
#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk   (0x30UL)
 
#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Pos   (6UL)
 
#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk   (0x40UL)
 
#define CRG_TOP_CLK_AMBA_REG_ECC_CLK_ENABLE_Pos   (7UL)
 
#define CRG_TOP_CLK_AMBA_REG_ECC_CLK_ENABLE_Msk   (0x80UL)
 
#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Pos   (8UL)
 
#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Msk   (0x100UL)
 
#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Pos   (9UL)
 
#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk   (0x200UL)
 
#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Pos   (10UL)
 
#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Msk   (0xc00UL)
 
#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Pos   (12UL)
 
#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Msk   (0x1000UL)
 
#define CRG_TOP_CLK_FREQ_TRIM_REG_FINE_ADJ_Pos   (0UL)
 
#define CRG_TOP_CLK_FREQ_TRIM_REG_FINE_ADJ_Msk   (0xffUL)
 
#define CRG_TOP_CLK_FREQ_TRIM_REG_COARSE_ADJ_Pos   (8UL)
 
#define CRG_TOP_CLK_FREQ_TRIM_REG_COARSE_ADJ_Msk   (0x700UL)
 
#define CRG_TOP_CLK_RADIO_REG_RFCU_DIV_Pos   (0UL)
 
#define CRG_TOP_CLK_RADIO_REG_RFCU_DIV_Msk   (0x3UL)
 
#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos   (3UL)
 
#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Msk   (0x8UL)
 
#define CRG_TOP_CLK_RADIO_REG_BLE_DIV_Pos   (4UL)
 
#define CRG_TOP_CLK_RADIO_REG_BLE_DIV_Msk   (0x30UL)
 
#define CRG_TOP_CLK_RADIO_REG_BLE_LP_RESET_Pos   (6UL)
 
#define CRG_TOP_CLK_RADIO_REG_BLE_LP_RESET_Msk   (0x40UL)
 
#define CRG_TOP_CLK_RADIO_REG_BLE_ENABLE_Pos   (7UL)
 
#define CRG_TOP_CLK_RADIO_REG_BLE_ENABLE_Msk   (0x80UL)
 
#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_DIV_Pos   (8UL)
 
#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_DIV_Msk   (0x300UL)
 
#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_ENABLE_Pos   (11UL)
 
#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_ENABLE_Msk   (0x800UL)
 
#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos   (0UL)
 
#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk   (0x3UL)
 
#define CRG_TOP_CLK_CTRL_REG_XTAL16M_DISABLE_Pos   (2UL)
 
#define CRG_TOP_CLK_CTRL_REG_XTAL16M_DISABLE_Msk   (0x4UL)
 
#define CRG_TOP_CLK_CTRL_REG_XTAL32M_MODE_Pos   (3UL)
 
#define CRG_TOP_CLK_CTRL_REG_XTAL32M_MODE_Msk   (0x8UL)
 
#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Pos   (4UL)
 
#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk   (0x10UL)
 
#define CRG_TOP_CLK_CTRL_REG_PLL_DIV2_Pos   (5UL)
 
#define CRG_TOP_CLK_CTRL_REG_PLL_DIV2_Msk   (0x20UL)
 
#define CRG_TOP_CLK_CTRL_REG_DIVN_XTAL32M_MODE_Pos   (6UL)
 
#define CRG_TOP_CLK_CTRL_REG_DIVN_XTAL32M_MODE_Msk   (0x40UL)
 
#define CRG_TOP_CLK_CTRL_REG_DIVN_SYNC_LEVEL_Pos   (7UL)
 
#define CRG_TOP_CLK_CTRL_REG_DIVN_SYNC_LEVEL_Msk   (0x80UL)
 
#define CRG_TOP_CLK_CTRL_REG_CLK32K_SOURCE_Pos   (8UL)
 
#define CRG_TOP_CLK_CTRL_REG_CLK32K_SOURCE_Msk   (0x300UL)
 
#define CRG_TOP_CLK_CTRL_REG_DIVN_SHIFT_SEL_Pos   (10UL)
 
#define CRG_TOP_CLK_CTRL_REG_DIVN_SHIFT_SEL_Msk   (0x400UL)
 
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_32K_Pos   (12UL)
 
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_32K_Msk   (0x1000UL)
 
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC16M_Pos   (13UL)
 
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC16M_Msk   (0x2000UL)
 
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL16M_Pos   (14UL)
 
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL16M_Msk   (0x4000UL)
 
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Pos   (15UL)
 
#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk   (0x8000UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR0_DIV_Pos   (0UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR0_DIV_Msk   (0x3UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Pos   (2UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Msk   (0x4UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Pos   (3UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Msk   (0x8UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR1_DIV_Pos   (4UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR1_DIV_Msk   (0x30UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR1_ENABLE_Pos   (6UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR1_ENABLE_Msk   (0x40UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR1_CLK_SEL_Pos   (7UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR1_CLK_SEL_Msk   (0x80UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR2_DIV_Pos   (8UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR2_DIV_Msk   (0x300UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR2_ENABLE_Pos   (10UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR2_ENABLE_Msk   (0x400UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR2_CLK_SEL_Pos   (11UL)
 
#define CRG_TOP_CLK_TMR_REG_TMR2_CLK_SEL_Msk   (0x800UL)
 
#define CRG_TOP_CLK_TMR_REG_BREATH_ENABLE_Pos   (12UL)
 
#define CRG_TOP_CLK_TMR_REG_BREATH_ENABLE_Msk   (0x1000UL)
 
#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Pos   (13UL)
 
#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk   (0x2000UL)
 
#define CRG_TOP_CLK_TMR_REG_P06_TMR1_PWM_MODE_Pos   (14UL)
 
#define CRG_TOP_CLK_TMR_REG_P06_TMR1_PWM_MODE_Msk   (0x4000UL)
 
#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos   (0UL)
 
#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk   (0x1UL)
 
#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos   (1UL)
 
#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk   (0x2UL)
 
#define CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Pos   (2UL)
 
#define CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Msk   (0x4UL)
 
#define CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Pos   (3UL)
 
#define CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Msk   (0x8UL)
 
#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Pos   (4UL)
 
#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Msk   (0x10UL)
 
#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Pos   (5UL)
 
#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Msk   (0x20UL)
 
#define CRG_TOP_PMU_CTRL_REG_OTP_COPY_DIV_Pos   (6UL)
 
#define CRG_TOP_PMU_CTRL_REG_OTP_COPY_DIV_Msk   (0xc0UL)
 
#define CRG_TOP_PMU_CTRL_REG_RETAIN_RAM_Pos   (8UL)
 
#define CRG_TOP_PMU_CTRL_REG_RETAIN_RAM_Msk   (0x1f00UL)
 
#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Pos   (13UL)
 
#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Msk   (0x2000UL)
 
#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Pos   (14UL)
 
#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Msk   (0x4000UL)
 
#define CRG_TOP_PMU_CTRL_REG_RETAIN_ECCRAM_Pos   (15UL)
 
#define CRG_TOP_PMU_CTRL_REG_RETAIN_ECCRAM_Msk   (0x8000UL)
 
#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Pos   (0UL)
 
#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk   (0x7UL)
 
#define CRG_TOP_SYS_CTRL_REG_REMAP_RAMS_Pos   (3UL)
 
#define CRG_TOP_SYS_CTRL_REG_REMAP_RAMS_Msk   (0x18UL)
 
#define CRG_TOP_SYS_CTRL_REG_PAD_LATCH_EN_Pos   (5UL)
 
#define CRG_TOP_SYS_CTRL_REG_PAD_LATCH_EN_Msk   (0x20UL)
 
#define CRG_TOP_SYS_CTRL_REG_OTPC_RESET_REQ_Pos   (6UL)
 
#define CRG_TOP_SYS_CTRL_REG_OTPC_RESET_REQ_Msk   (0x40UL)
 
#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Pos   (7UL)
 
#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk   (0x80UL)
 
#define CRG_TOP_SYS_CTRL_REG_DRA_OFF_Pos   (8UL)
 
#define CRG_TOP_SYS_CTRL_REG_DRA_OFF_Msk   (0x100UL)
 
#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Pos   (9UL)
 
#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Msk   (0x200UL)
 
#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Pos   (10UL)
 
#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk   (0x400UL)
 
#define CRG_TOP_SYS_CTRL_REG_DEV_PHASE_Pos   (11UL)
 
#define CRG_TOP_SYS_CTRL_REG_DEV_PHASE_Msk   (0x800UL)
 
#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Pos   (12UL)
 
#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Msk   (0x1000UL)
 
#define CRG_TOP_SYS_CTRL_REG_OTP_COPY_Pos   (13UL)
 
#define CRG_TOP_SYS_CTRL_REG_OTP_COPY_Msk   (0x2000UL)
 
#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Pos   (14UL)
 
#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk   (0x4000UL)
 
#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Pos   (15UL)
 
#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk   (0x8000UL)
 
#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Pos   (0UL)
 
#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Msk   (0x1UL)
 
#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Pos   (1UL)
 
#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Msk   (0x2UL)
 
#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Pos   (2UL)
 
#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Msk   (0x4UL)
 
#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Pos   (3UL)
 
#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Msk   (0x8UL)
 
#define CRG_TOP_SYS_STAT_REG_XTAL16_SW2_Pos   (4UL)
 
#define CRG_TOP_SYS_STAT_REG_XTAL16_SW2_Msk   (0x10UL)
 
#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Pos   (5UL)
 
#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk   (0x20UL)
 
#define CRG_TOP_SYS_STAT_REG_XTAL16_TRIM_READY_Pos   (6UL)
 
#define CRG_TOP_SYS_STAT_REG_XTAL16_TRIM_READY_Msk   (0x40UL)
 
#define CRG_TOP_SYS_STAT_REG_XTAL16_SETTLE_READY_Pos   (7UL)
 
#define CRG_TOP_SYS_STAT_REG_XTAL16_SETTLE_READY_Msk   (0x80UL)
 
#define CRG_TOP_SYS_STAT_REG_BLE_IS_DOWN_Pos   (8UL)
 
#define CRG_TOP_SYS_STAT_REG_BLE_IS_DOWN_Msk   (0x100UL)
 
#define CRG_TOP_SYS_STAT_REG_BLE_IS_UP_Pos   (9UL)
 
#define CRG_TOP_SYS_STAT_REG_BLE_IS_UP_Msk   (0x200UL)
 
#define CRG_TOP_SYS_STAT_REG_FTDF_IS_DOWN_Pos   (10UL)
 
#define CRG_TOP_SYS_STAT_REG_FTDF_IS_DOWN_Msk   (0x400UL)
 
#define CRG_TOP_SYS_STAT_REG_FTDF_IS_UP_Pos   (11UL)
 
#define CRG_TOP_SYS_STAT_REG_FTDF_IS_UP_Msk   (0x800UL)
 
#define CRG_TOP_TRIM_CTRL_REG_XTAL_COUNT_N_Pos   (0UL)
 
#define CRG_TOP_TRIM_CTRL_REG_XTAL_COUNT_N_Msk   (0x3fUL)
 
#define CRG_TOP_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Pos   (6UL)
 
#define CRG_TOP_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Msk   (0xc0UL)
 
#define CRG_TOP_TRIM_CTRL_REG_XTAL_SETTLE_N_Pos   (8UL)
 
#define CRG_TOP_TRIM_CTRL_REG_XTAL_SETTLE_N_Msk   (0x3f00UL)
 
#define CRG_TOP_CLK_32K_REG_XTAL32K_ENABLE_Pos   (0UL)
 
#define CRG_TOP_CLK_32K_REG_XTAL32K_ENABLE_Msk   (0x1UL)
 
#define CRG_TOP_CLK_32K_REG_XTAL32K_RBIAS_Pos   (1UL)
 
#define CRG_TOP_CLK_32K_REG_XTAL32K_RBIAS_Msk   (0x6UL)
 
#define CRG_TOP_CLK_32K_REG_XTAL32K_CUR_Pos   (3UL)
 
#define CRG_TOP_CLK_32K_REG_XTAL32K_CUR_Msk   (0x78UL)
 
#define CRG_TOP_CLK_32K_REG_RC32K_ENABLE_Pos   (7UL)
 
#define CRG_TOP_CLK_32K_REG_RC32K_ENABLE_Msk   (0x80UL)
 
#define CRG_TOP_CLK_32K_REG_RC32K_TRIM_Pos   (8UL)
 
#define CRG_TOP_CLK_32K_REG_RC32K_TRIM_Msk   (0xf00UL)
 
#define CRG_TOP_CLK_32K_REG_XTAL32K_DISABLE_AMPREG_Pos   (12UL)
 
#define CRG_TOP_CLK_32K_REG_XTAL32K_DISABLE_AMPREG_Msk   (0x1000UL)
 
#define CRG_TOP_CLK_32K_REG_XTAL32K_XTAL1_BIAS_DISABLE_Pos   (13UL)
 
#define CRG_TOP_CLK_32K_REG_XTAL32K_XTAL1_BIAS_DISABLE_Msk   (0x2000UL)
 
#define CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Pos   (0UL)
 
#define CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Msk   (0x1UL)
 
#define CRG_TOP_CLK_16M_REG_RC16M_TRIM_Pos   (1UL)
 
#define CRG_TOP_CLK_16M_REG_RC16M_TRIM_Msk   (0x1eUL)
 
#define CRG_TOP_CLK_16M_REG_XTAL16_CUR_SET_Pos   (5UL)
 
#define CRG_TOP_CLK_16M_REG_XTAL16_CUR_SET_Msk   (0xe0UL)
 
#define CRG_TOP_CLK_16M_REG_XTAL16_MAX_CURRENT_Pos   (8UL)
 
#define CRG_TOP_CLK_16M_REG_XTAL16_MAX_CURRENT_Msk   (0x100UL)
 
#define CRG_TOP_CLK_16M_REG_XTAL16_EXT_CLK_ENABLE_Pos   (9UL)
 
#define CRG_TOP_CLK_16M_REG_XTAL16_EXT_CLK_ENABLE_Msk   (0x200UL)
 
#define CRG_TOP_CLK_16M_REG_XTAL16_AMP_TRIM_Pos   (10UL)
 
#define CRG_TOP_CLK_16M_REG_XTAL16_AMP_TRIM_Msk   (0x1c00UL)
 
#define CRG_TOP_CLK_16M_REG_XTAL16_SPIKE_FLT_BYPASS_Pos   (13UL)
 
#define CRG_TOP_CLK_16M_REG_XTAL16_SPIKE_FLT_BYPASS_Msk   (0x2000UL)
 
#define CRG_TOP_CLK_16M_REG_XTAL16_HPASS_FLT_EN_Pos   (14UL)
 
#define CRG_TOP_CLK_16M_REG_XTAL16_HPASS_FLT_EN_Msk   (0x4000UL)
 
#define CRG_TOP_CLK_16M_REG_RC16M_STARTUP_DISABLE_Pos   (15UL)
 
#define CRG_TOP_CLK_16M_REG_RC16M_STARTUP_DISABLE_Msk   (0x8000UL)
 
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_TRIM_Pos   (0UL)
 
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_TRIM_Msk   (0xfUL)
 
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_NTC_Pos   (4UL)
 
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_NTC_Msk   (0xf0UL)
 
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_BIAS_Pos   (8UL)
 
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_BIAS_Msk   (0x300UL)
 
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_LOWF_Pos   (10UL)
 
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_LOWF_Msk   (0x400UL)
 
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_ENABLE_Pos   (11UL)
 
#define CRG_TOP_CLK_RCX20K_REG_RCX20K_ENABLE_Msk   (0x800UL)
 
#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Pos   (0UL)
 
#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Msk   (0x1fUL)
 
#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Pos   (5UL)
 
#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Msk   (0x3e0UL)
 
#define CRG_TOP_BANDGAP_REG_LDO_SLEEP_TRIM_Pos   (10UL)
 
#define CRG_TOP_BANDGAP_REG_LDO_SLEEP_TRIM_Msk   (0x3c00UL)
 
#define CRG_TOP_BANDGAP_REG_LDO_SUPPLY_USE_BGREF_Pos   (14UL)
 
#define CRG_TOP_BANDGAP_REG_LDO_SUPPLY_USE_BGREF_Msk   (0x4000UL)
 
#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Pos   (0UL)
 
#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Msk   (0x1UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_OK_Pos   (1UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_OK_Msk   (0x2UL)
 
#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Pos   (2UL)
 
#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk   (0x4UL)
 
#define CRG_TOP_ANA_STATUS_REG_NEWBAT_Pos   (3UL)
 
#define CRG_TOP_ANA_STATUS_REG_NEWBAT_Msk   (0x8UL)
 
#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_VBAT_OK_Pos   (4UL)
 
#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_VBAT_OK_Msk   (0x10UL)
 
#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_USB_OK_Pos   (5UL)
 
#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_USB_OK_Msk   (0x20UL)
 
#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Pos   (6UL)
 
#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Msk   (0x40UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_HIGH_Pos   (7UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_HIGH_Msk   (0x80UL)
 
#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Pos   (8UL)
 
#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Msk   (0x100UL)
 
#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_PA_OK_Pos   (9UL)
 
#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_PA_OK_Msk   (0x200UL)
 
#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_FLASH_OK_Pos   (10UL)
 
#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_FLASH_OK_Msk   (0x400UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Pos   (11UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Msk   (0x800UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Pos   (12UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Msk   (0x1000UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_V33_HIGH_Pos   (13UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_V33_HIGH_Msk   (0x2000UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_FLASH_HIGH_Pos   (14UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_FLASH_HIGH_Msk   (0x4000UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_PA_HIGH_Pos   (15UL)
 
#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_PA_HIGH_Msk   (0x8000UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_BANDGAP_OK_Pos   (0UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_BANDGAP_OK_Msk   (0x1UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Pos   (1UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Msk   (0x2UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_SUPPLY_VBAT_OK_Pos   (2UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_SUPPLY_VBAT_OK_Msk   (0x4UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_LOD_SUPPLY_USB_OK_Pos   (3UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_LOD_SUPPLY_USB_OK_Msk   (0x8UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_CORE_OK_Pos   (4UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_CORE_OK_Msk   (0x10UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_PA_OK_Pos   (5UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_PA_OK_Msk   (0x20UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VDD_HIGH_Pos   (6UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VDD_HIGH_Msk   (0x40UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_V33_HIGH_Pos   (7UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_V33_HIGH_Msk   (0x80UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_HIGH_Pos   (8UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_HIGH_Msk   (0x100UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_LOW_Pos   (9UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_LOW_Msk   (0x200UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_PA_HIGH_Pos   (10UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_PA_HIGH_Msk   (0x400UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_FLASH_HIGH_Pos   (11UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_FLASH_HIGH_Msk   (0x800UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Pos   (12UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Msk   (0x1000UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_BOD_STATUS_Pos   (13UL)
 
#define CRG_TOP_STARTUP_STATUS_REG_SU_BOD_STATUS_Msk   (0xe000UL)
 
#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Pos   (0UL)
 
#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk   (0x1UL)
 
#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Pos   (1UL)
 
#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk   (0x2UL)
 
#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Pos   (0UL)
 
#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Msk   (0xffffUL)
 
#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_TRIM_Pos   (0UL)
 
#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_TRIM_Msk   (0x3UL)
 
#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_TRIM_Pos   (2UL)
 
#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_TRIM_Msk   (0xcUL)
 
#define CRG_TOP_BOD_CTRL_REG_BOD_1V4_TRIM_Pos   (4UL)
 
#define CRG_TOP_BOD_CTRL_REG_BOD_1V4_TRIM_Msk   (0x30UL)
 
#define CRG_TOP_BOD_CTRL_REG_BOD_V33_TRIM_Pos   (6UL)
 
#define CRG_TOP_BOD_CTRL_REG_BOD_V33_TRIM_Msk   (0xc0UL)
 
#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_LVL_Pos   (8UL)
 
#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_LVL_Msk   (0x700UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_RESET_EN_Pos   (0UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_RESET_EN_Msk   (0x1UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_VDD_EN_Pos   (1UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_VDD_EN_Msk   (0x2UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_V33_EN_Pos   (2UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_V33_EN_Msk   (0x4UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_PA_EN_Pos   (3UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_PA_EN_Msk   (0x8UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_FLASH_EN_Pos   (4UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_FLASH_EN_Msk   (0x10UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_VBAT_EN_Pos   (5UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_VBAT_EN_Msk   (0x20UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_V14_EN_Pos   (6UL)
 
#define CRG_TOP_BOD_CTRL2_REG_BOD_V14_EN_Msk   (0x40UL)
 
#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_LOW_Pos   (0UL)
 
#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_LOW_Msk   (0x1UL)
 
#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_PA_LOW_Pos   (1UL)
 
#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_PA_LOW_Msk   (0x2UL)
 
#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_FLASH_LOW_Pos   (2UL)
 
#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_FLASH_LOW_Msk   (0x4UL)
 
#define CRG_TOP_BOD_STATUS_REG_BOD_V33_LOW_Pos   (3UL)
 
#define CRG_TOP_BOD_STATUS_REG_BOD_V33_LOW_Msk   (0x8UL)
 
#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_LOW_Pos   (4UL)
 
#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_LOW_Msk   (0x10UL)
 
#define CRG_TOP_BOD_STATUS_REG_BOD_V14_LOW_Pos   (5UL)
 
#define CRG_TOP_BOD_STATUS_REG_BOD_V14_LOW_Msk   (0x20UL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_CURLIM_Pos   (0UL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_CURLIM_Msk   (0x3UL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_VBAT_RET_LEVEL_Pos   (2UL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_VBAT_RET_LEVEL_Msk   (0xcUL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_VBAT_LEVEL_Pos   (4UL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_VBAT_LEVEL_Msk   (0x30UL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_USB_LEVEL_Pos   (6UL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_USB_LEVEL_Msk   (0xc0UL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_SETVDD_Pos   (8UL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_SETVDD_Msk   (0x700UL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_SETVDD_Pos   (11UL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_SETVDD_Msk   (0x3800UL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_ENABLE_Pos   (14UL)
 
#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_ENABLE_Msk   (0x4000UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V2_ON_Pos   (0UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V2_ON_Msk   (0x1UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_3V3_ON_Pos   (1UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_3V3_ON_Msk   (0x2UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_ON_Pos   (2UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_ON_Msk   (0x4UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_ON_Pos   (3UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_ON_Msk   (0x8UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_VBAT_RET_DISABLE_Pos   (4UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_VBAT_RET_DISABLE_Msk   (0x10UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_RET_DISABLE_Pos   (5UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_RET_DISABLE_Msk   (0x20UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_RET_DISABLE_Pos   (6UL)
 
#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_RET_DISABLE_Msk   (0x40UL)
 
#define CRG_TOP_SLEEP_TIMER_REG_SLEEP_TIMER_Pos   (0UL)
 
#define CRG_TOP_SLEEP_TIMER_REG_SLEEP_TIMER_Msk   (0xffffUL)
 
#define CRG_TOP_POWER_CTRL_REG_TRIM_NEWBAT_Pos   (0UL)
 
#define CRG_TOP_POWER_CTRL_REG_TRIM_NEWBAT_Msk   (0x7UL)
 
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Pos   (0UL)
 
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Msk   (0xfUL)
 
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Pos   (4UL)
 
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Msk   (0xf0UL)
 
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Pos   (8UL)
 
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Msk   (0xf00UL)
 
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Pos   (12UL)
 
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Msk   (0x1000UL)
 
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Pos   (13UL)
 
#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Msk   (0x2000UL)
 
#define CRG_TOP_XTALRDY_CTRL_REG_XTALRDY_CNT_Pos   (0UL)
 
#define CRG_TOP_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk   (0xffUL)
 
#define CRG_TOP_XTALRDY_STAT_REG_XTALRDY_STAT_Pos   (0UL)
 
#define CRG_TOP_XTALRDY_STAT_REG_XTALRDY_STAT_Msk   (0xffUL)
 
#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_ENABLE_Pos   (0UL)
 
#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_ENABLE_Msk   (0x1UL)
 
#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_VREF_HOLD_Pos   (1UL)
 
#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_VREF_HOLD_Msk   (0x2UL)
 
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_ENABLE_Pos   (2UL)
 
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_ENABLE_Msk   (0x4UL)
 
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_VREF_HOLD_Pos   (3UL)
 
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_VREF_HOLD_Msk   (0x8UL)
 
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_ENABLE_Pos   (4UL)
 
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_ENABLE_Msk   (0x10UL)
 
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Pos   (5UL)
 
#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Msk   (0x20UL)
 
#define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Pos   (0UL)
 
#define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Msk   (0xffUL)
 
#define CRG_TOP_XTAL16M_START_REG_COARSE_ADJ_Pos   (8UL)
 
#define CRG_TOP_XTAL16M_START_REG_COARSE_ADJ_Msk   (0x700UL)
 
#define CRG_TOP_XTAL16M_RAMP_REG_FINE_ADJ_Pos   (0UL)
 
#define CRG_TOP_XTAL16M_RAMP_REG_FINE_ADJ_Msk   (0xffUL)
 
#define CRG_TOP_XTAL16M_RAMP_REG_COARSE_ADJ_Pos   (8UL)
 
#define CRG_TOP_XTAL16M_RAMP_REG_COARSE_ADJ_Msk   (0x700UL)
 
#define CRG_TOP_XTAL16M_TRSTAT_REG_XTAL16M_TRSTAT_Pos   (0UL)
 
#define CRG_TOP_XTAL16M_TRSTAT_REG_XTAL16M_TRSTAT_Msk   (0x7fffUL)
 
#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos   (0UL)
 
#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk   (0x1UL)
 
#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos   (1UL)
 
#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk   (0x2UL)
 
#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos   (2UL)
 
#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk   (0x4UL)
 
#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Pos   (3UL)
 
#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk   (0x8UL)
 
#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos   (4UL)
 
#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk   (0x10UL)
 
#define CRG_TOP_FORCE_SLEEP_REG_FORCE_FTDF_SLEEP_Pos   (0UL)
 
#define CRG_TOP_FORCE_SLEEP_REG_FORCE_FTDF_SLEEP_Msk   (0x1UL)
 
#define CRG_TOP_FORCE_SLEEP_REG_FORCE_BLE_SLEEP_Pos   (1UL)
 
#define CRG_TOP_FORCE_SLEEP_REG_FORCE_BLE_SLEEP_Msk   (0x2UL)
 
#define CRG_TOP_LDOS_DISABLE_REG_LDOS_DISABLE_Pos   (0UL)
 
#define CRG_TOP_LDOS_DISABLE_REG_LDOS_DISABLE_Msk   (0x1UL)
 
#define CRG_TOP_AON_SPARE_REG_OSC16_HOLD_AMP_REG_Pos   (0UL)
 
#define CRG_TOP_AON_SPARE_REG_OSC16_HOLD_AMP_REG_Msk   (0x1UL)
 
#define CRG_TOP_AON_SPARE_REG_OSC16_SH_DISABLE_Pos   (1UL)
 
#define CRG_TOP_AON_SPARE_REG_OSC16_SH_DISABLE_Msk   (0x2UL)
 
#define CRG_TOP_AON_SPARE_REG_EN_BATSYS_RET_Pos   (2UL)
 
#define CRG_TOP_AON_SPARE_REG_EN_BATSYS_RET_Msk   (0x4UL)
 
#define CRG_TOP_AON_SPARE_REG_EN_BUSSYS_RET_Pos   (3UL)
 
#define CRG_TOP_AON_SPARE_REG_EN_BUSSYS_RET_Msk   (0x8UL)
 
#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Pos   (0UL)
 
#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Msk   (0x1UL)
 
#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Pos   (1UL)
 
#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Msk   (0x2UL)
 
#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V14_Pos   (0UL)
 
#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V14_Msk   (0x1UL)
 
#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18_Pos   (1UL)
 
#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18_Msk   (0x2UL)
 
#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18P_Pos   (2UL)
 
#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18P_Msk   (0x4UL)
 
#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Pos   (0UL)
 
#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Msk   (0x1UL)
 
#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Pos   (1UL)
 
#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Msk   (0x2UL)
 
#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Pos   (2UL)
 
#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Msk   (0x4UL)
 
#define DCDC_DCDC_CTRL_0_REG_DCDC_MODE_Pos   (0UL)
 
#define DCDC_DCDC_CTRL_0_REG_DCDC_MODE_Msk   (0x3UL)
 
#define DCDC_DCDC_CTRL_0_REG_DCDC_FW_ENABLE_Pos   (2UL)
 
#define DCDC_DCDC_CTRL_0_REG_DCDC_FW_ENABLE_Msk   (0x4UL)
 
#define DCDC_DCDC_CTRL_0_REG_DCDC_PRIORITY_Pos   (3UL)
 
#define DCDC_DCDC_CTRL_0_REG_DCDC_PRIORITY_Msk   (0x7f8UL)
 
#define DCDC_DCDC_CTRL_0_REG_DCDC_IDLE_CLK_DIV_Pos   (11UL)
 
#define DCDC_DCDC_CTRL_0_REG_DCDC_IDLE_CLK_DIV_Msk   (0x1800UL)
 
#define DCDC_DCDC_CTRL_0_REG_DCDC_BROWNOUT_LV_MODE_Pos   (13UL)
 
#define DCDC_DCDC_CTRL_0_REG_DCDC_BROWNOUT_LV_MODE_Msk   (0x2000UL)
 
#define DCDC_DCDC_CTRL_0_REG_DCDC_FAST_STARTUP_Pos   (14UL)
 
#define DCDC_DCDC_CTRL_0_REG_DCDC_FAST_STARTUP_Msk   (0x4000UL)
 
#define DCDC_DCDC_CTRL_1_REG_DCDC_TIMEOUT_Pos   (0UL)
 
#define DCDC_DCDC_CTRL_1_REG_DCDC_TIMEOUT_Msk   (0x1fUL)
 
#define DCDC_DCDC_CTRL_1_REG_DCDC_GLOBAL_MAX_IDLE_TIME_Pos   (5UL)
 
#define DCDC_DCDC_CTRL_1_REG_DCDC_GLOBAL_MAX_IDLE_TIME_Msk   (0x7e0UL)
 
#define DCDC_DCDC_CTRL_1_REG_DCDC_STARTUP_DELAY_Pos   (11UL)
 
#define DCDC_DCDC_CTRL_1_REG_DCDC_STARTUP_DELAY_Msk   (0xf800UL)
 
#define DCDC_DCDC_CTRL_2_REG_DCDC_HSGND_TRIM_Pos   (0UL)
 
#define DCDC_DCDC_CTRL_2_REG_DCDC_HSGND_TRIM_Msk   (0x7UL)
 
#define DCDC_DCDC_CTRL_2_REG_DCDC_LSSUP_TRIM_Pos   (3UL)
 
#define DCDC_DCDC_CTRL_2_REG_DCDC_LSSUP_TRIM_Msk   (0x38UL)
 
#define DCDC_DCDC_CTRL_2_REG_DCDC_TUNE_Pos   (6UL)
 
#define DCDC_DCDC_CTRL_2_REG_DCDC_TUNE_Msk   (0xc0UL)
 
#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_RES_Pos   (8UL)
 
#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_RES_Msk   (0xf00UL)
 
#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_TRIG_Pos   (12UL)
 
#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_TRIG_Msk   (0xf000UL)
 
#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MIN_Pos   (0UL)
 
#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MIN_Msk   (0x1fUL)
 
#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MAX_HV_Pos   (5UL)
 
#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MAX_HV_Msk   (0x3e0UL)
 
#define DCDC_DCDC_V14_0_REG_DCDC_V14_VOLTAGE_Pos   (10UL)
 
#define DCDC_DCDC_V14_0_REG_DCDC_V14_VOLTAGE_Msk   (0x7c00UL)
 
#define DCDC_DCDC_V14_0_REG_DCDC_V14_FAST_RAMPING_Pos   (15UL)
 
#define DCDC_DCDC_V14_0_REG_DCDC_V14_FAST_RAMPING_Msk   (0x8000UL)
 
#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_MIN_Pos   (0UL)
 
#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_MIN_Msk   (0x1fUL)
 
#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_HYST_Pos   (5UL)
 
#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_HYST_Msk   (0x3e0UL)
 
#define DCDC_DCDC_V14_1_REG_DCDC_V14_CUR_LIM_MAX_LV_Pos   (10UL)
 
#define DCDC_DCDC_V14_1_REG_DCDC_V14_CUR_LIM_MAX_LV_Msk   (0x3c00UL)
 
#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_LV_Pos   (14UL)
 
#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_LV_Msk   (0x4000UL)
 
#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_HV_Pos   (15UL)
 
#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_HV_Msk   (0x8000UL)
 
#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MIN_Pos   (0UL)
 
#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MIN_Msk   (0x1fUL)
 
#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MAX_HV_Pos   (5UL)
 
#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MAX_HV_Msk   (0x3e0UL)
 
#define DCDC_DCDC_V18_0_REG_DCDC_V18_VOLTAGE_Pos   (10UL)
 
#define DCDC_DCDC_V18_0_REG_DCDC_V18_VOLTAGE_Msk   (0x7c00UL)
 
#define DCDC_DCDC_V18_0_REG_DCDC_V18_FAST_RAMPING_Pos   (15UL)
 
#define DCDC_DCDC_V18_0_REG_DCDC_V18_FAST_RAMPING_Msk   (0x8000UL)
 
#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_MIN_Pos   (0UL)
 
#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_MIN_Msk   (0x1fUL)
 
#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_HYST_Pos   (5UL)
 
#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_HYST_Msk   (0x3e0UL)
 
#define DCDC_DCDC_V18_1_REG_DCDC_V18_CUR_LIM_MAX_LV_Pos   (10UL)
 
#define DCDC_DCDC_V18_1_REG_DCDC_V18_CUR_LIM_MAX_LV_Msk   (0x3c00UL)
 
#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_LV_Pos   (14UL)
 
#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_LV_Msk   (0x4000UL)
 
#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_HV_Pos   (15UL)
 
#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_HV_Msk   (0x8000UL)
 
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MIN_Pos   (0UL)
 
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MIN_Msk   (0x1fUL)
 
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MAX_HV_Pos   (5UL)
 
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MAX_HV_Msk   (0x3e0UL)
 
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_VOLTAGE_Pos   (10UL)
 
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_VOLTAGE_Msk   (0x7c00UL)
 
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_FAST_RAMPING_Pos   (15UL)
 
#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_FAST_RAMPING_Msk   (0x8000UL)
 
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_MIN_Pos   (0UL)
 
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_MIN_Msk   (0x1fUL)
 
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_HYST_Pos   (5UL)
 
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_HYST_Msk   (0x3e0UL)
 
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_CUR_LIM_MAX_LV_Pos   (10UL)
 
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_CUR_LIM_MAX_LV_Msk   (0x3c00UL)
 
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_LV_Pos   (14UL)
 
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_LV_Msk   (0x4000UL)
 
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_HV_Pos   (15UL)
 
#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_HV_Msk   (0x8000UL)
 
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MIN_Pos   (0UL)
 
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MIN_Msk   (0x1fUL)
 
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MAX_HV_Pos   (5UL)
 
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MAX_HV_Msk   (0x3e0UL)
 
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_VOLTAGE_Pos   (10UL)
 
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_VOLTAGE_Msk   (0x7c00UL)
 
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_FAST_RAMPING_Pos   (15UL)
 
#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_FAST_RAMPING_Msk   (0x8000UL)
 
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_MIN_Pos   (0UL)
 
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_MIN_Msk   (0x1fUL)
 
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_HYST_Pos   (5UL)
 
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_HYST_Msk   (0x3e0UL)
 
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_CUR_LIM_MAX_LV_Pos   (10UL)
 
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_CUR_LIM_MAX_LV_Msk   (0x3c00UL)
 
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_LV_Pos   (14UL)
 
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_LV_Msk   (0x4000UL)
 
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_HV_Pos   (15UL)
 
#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_HV_Msk   (0x8000UL)
 
#define DCDC_DCDC_RET_0_REG_DCDC_VDD_CUR_LIM_RET_Pos   (0UL)
 
#define DCDC_DCDC_RET_0_REG_DCDC_VDD_CUR_LIM_RET_Msk   (0x1fUL)
 
#define DCDC_DCDC_RET_0_REG_DCDC_VDD_RET_CYCLES_Pos   (5UL)
 
#define DCDC_DCDC_RET_0_REG_DCDC_VDD_RET_CYCLES_Msk   (0xe0UL)
 
#define DCDC_DCDC_RET_0_REG_DCDC_V18P_CUR_LIM_RET_Pos   (8UL)
 
#define DCDC_DCDC_RET_0_REG_DCDC_V18P_CUR_LIM_RET_Msk   (0x1f00UL)
 
#define DCDC_DCDC_RET_0_REG_DCDC_V18P_RET_CYCLES_Pos   (13UL)
 
#define DCDC_DCDC_RET_0_REG_DCDC_V18P_RET_CYCLES_Msk   (0xe000UL)
 
#define DCDC_DCDC_RET_1_REG_DCDC_V14_CUR_LIM_RET_Pos   (0UL)
 
#define DCDC_DCDC_RET_1_REG_DCDC_V14_CUR_LIM_RET_Msk   (0x1fUL)
 
#define DCDC_DCDC_RET_1_REG_DCDC_V14_RET_CYCLES_Pos   (5UL)
 
#define DCDC_DCDC_RET_1_REG_DCDC_V14_RET_CYCLES_Msk   (0xe0UL)
 
#define DCDC_DCDC_RET_1_REG_DCDC_V18_CUR_LIM_RET_Pos   (8UL)
 
#define DCDC_DCDC_RET_1_REG_DCDC_V18_CUR_LIM_RET_Msk   (0x1f00UL)
 
#define DCDC_DCDC_RET_1_REG_DCDC_V18_RET_CYCLES_Pos   (13UL)
 
#define DCDC_DCDC_RET_1_REG_DCDC_V18_RET_CYCLES_Msk   (0xe000UL)
 
#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_TRIM_Pos   (0UL)
 
#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_TRIM_Msk   (0x3fUL)
 
#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_MAN_TRIM_Pos   (6UL)
 
#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_MAN_TRIM_Msk   (0x40UL)
 
#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_TRIM_Pos   (7UL)
 
#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_TRIM_Msk   (0x1f80UL)
 
#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_MAN_TRIM_Pos   (13UL)
 
#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_MAN_TRIM_Msk   (0x2000UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_PSW_Pos   (0UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_PSW_Msk   (0x1UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_NSW_Pos   (1UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_NSW_Msk   (0x2UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_FW_Pos   (2UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_FW_Msk   (0x4UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V14_Pos   (3UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V14_Msk   (0x8UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18_Pos   (4UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18_Msk   (0x10UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_VDD_Pos   (5UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_VDD_Msk   (0x20UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18P_Pos   (6UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18P_Msk   (0x40UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_IDLE_Pos   (7UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_IDLE_Msk   (0x80UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_ANA_TEST_Pos   (8UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_ANA_TEST_Msk   (0x700UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_OUTPUT_MONITOR_Pos   (11UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_OUTPUT_MONITOR_Msk   (0x3800UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_CURRENT_Pos   (14UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_CURRENT_Msk   (0x4000UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_COMP_CLK_Pos   (15UL)
 
#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_COMP_CLK_Msk   (0x8000UL)
 
#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_REG_Pos   (0UL)
 
#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_REG_Msk   (0xfUL)
 
#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_CURRENT_Pos   (4UL)
 
#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_CURRENT_Msk   (0x1f0UL)
 
#define DCDC_DCDC_TEST_1_REG_DCDC_COMP_CLK_Pos   (9UL)
 
#define DCDC_DCDC_TEST_1_REG_DCDC_COMP_CLK_Msk   (0x1e00UL)
 
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_0_Pos   (0UL)
 
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_0_Msk   (0x7UL)
 
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_1_Pos   (3UL)
 
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_1_Msk   (0x38UL)
 
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_2_Pos   (6UL)
 
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_2_Msk   (0x1c0UL)
 
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_3_Pos   (9UL)
 
#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_3_Msk   (0xe00UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_NOK_Pos   (0UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_NOK_Msk   (0x1UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_NOK_Pos   (1UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_NOK_Msk   (0x2UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_NOK_Pos   (2UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_NOK_Msk   (0x4UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_NOK_Pos   (3UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_NOK_Msk   (0x8UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_OK_Pos   (4UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_OK_Msk   (0x10UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_OK_Pos   (5UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_OK_Msk   (0x20UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_OK_Pos   (6UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_OK_Msk   (0x40UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_OK_Pos   (7UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_OK_Msk   (0x80UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_AVAILABLE_Pos   (8UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_AVAILABLE_Msk   (0x100UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_AVAILABLE_Pos   (9UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_AVAILABLE_Msk   (0x200UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_AVAILABLE_Pos   (10UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_AVAILABLE_Msk   (0x400UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_AVAILABLE_Pos   (11UL)
 
#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_AVAILABLE_Msk   (0x800UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_Pos   (0UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_Msk   (0x1UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_Pos   (1UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_Msk   (0x2UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_N_Pos   (2UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_N_Msk   (0x4UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_P_Pos   (3UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_P_Msk   (0x8UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_N_Pos   (4UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_N_Msk   (0x10UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_P_Pos   (5UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_P_Msk   (0x20UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_PSW_STATE_Pos   (6UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_PSW_STATE_Msk   (0x40UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_NSW_STATE_Pos   (7UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_NSW_STATE_Msk   (0x80UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_V14_SW_STATE_Pos   (8UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_V14_SW_STATE_Msk   (0x100UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_V18_SW_STATE_Pos   (9UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_V18_SW_STATE_Msk   (0x200UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_VDD_SW_STATE_Pos   (10UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_VDD_SW_STATE_Msk   (0x400UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_V18P_SW_STATE_Pos   (11UL)
 
#define DCDC_DCDC_STATUS_2_REG_DCDC_V18P_SW_STATE_Msk   (0x800UL)
 
#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_VDD_Pos   (0UL)
 
#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_VDD_Msk   (0x1fUL)
 
#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_V18P_Pos   (5UL)
 
#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_V18P_Msk   (0x3e0UL)
 
#define DCDC_DCDC_STATUS_3_REG_DCDC_LV_MODE_Pos   (10UL)
 
#define DCDC_DCDC_STATUS_3_REG_DCDC_LV_MODE_Msk   (0x400UL)
 
#define DCDC_DCDC_STATUS_3_REG_DCDC_STARTUP_COMPLETE_Pos   (11UL)
 
#define DCDC_DCDC_STATUS_3_REG_DCDC_STARTUP_COMPLETE_Msk   (0x800UL)
 
#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V14_Pos   (0UL)
 
#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V14_Msk   (0x1fUL)
 
#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V18_Pos   (5UL)
 
#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V18_Msk   (0x3e0UL)
 
#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_N_Pos   (0UL)
 
#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_N_Msk   (0x3fUL)
 
#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_P_Pos   (6UL)
 
#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_P_Msk   (0xfc0UL)
 
#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_N_Pos   (0UL)
 
#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_N_Msk   (0x3fUL)
 
#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_P_Pos   (6UL)
 
#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_P_Msk   (0xfc0UL)
 
#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_N_Pos   (0UL)
 
#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_N_Msk   (0x3fUL)
 
#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_P_Pos   (6UL)
 
#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_P_Msk   (0xfc0UL)
 
#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_N_Pos   (0UL)
 
#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_N_Msk   (0x3fUL)
 
#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_P_Pos   (6UL)
 
#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_P_Msk   (0xfc0UL)
 
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Pos   (0UL)
 
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Msk   (0x1UL)
 
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Pos   (1UL)
 
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Msk   (0x2UL)
 
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Pos   (2UL)
 
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Msk   (0x4UL)
 
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Pos   (3UL)
 
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Msk   (0x8UL)
 
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_BROWN_OUT_IRQ_STATUS_Pos   (4UL)
 
#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_BROWN_OUT_IRQ_STATUS_Msk   (0x10UL)
 
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Pos   (0UL)
 
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Msk   (0x1UL)
 
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Pos   (1UL)
 
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Msk   (0x2UL)
 
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Pos   (2UL)
 
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Msk   (0x4UL)
 
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Pos   (3UL)
 
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Msk   (0x8UL)
 
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_BROWN_OUT_IRQ_CLEAR_Pos   (4UL)
 
#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_BROWN_OUT_IRQ_CLEAR_Msk   (0x10UL)
 
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Pos   (0UL)
 
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Msk   (0x1UL)
 
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Pos   (1UL)
 
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Msk   (0x2UL)
 
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Pos   (2UL)
 
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Msk   (0x4UL)
 
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Pos   (3UL)
 
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Msk   (0x8UL)
 
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_BROWN_OUT_IRQ_MASK_Pos   (4UL)
 
#define DCDC_DCDC_IRQ_MASK_REG_DCDC_BROWN_OUT_IRQ_MASK_Msk   (0x10UL)
 
#define DEM_RF_DEM_CTRL_REG_RXDATA_INV_Pos   (0UL)
 
#define DEM_RF_DEM_CTRL_REG_RXDATA_INV_Msk   (0x1UL)
 
#define DEM_RF_DEM_CTRL_REG_DEM_HSI_POL_Pos   (1UL)
 
#define DEM_RF_DEM_CTRL_REG_DEM_HSI_POL_Msk   (0x2UL)
 
#define DEM_RF_DEM_CTRL_REG_MATCH0101_TH_Pos   (2UL)
 
#define DEM_RF_DEM_CTRL_REG_MATCH0101_TH_Msk   (0x3cUL)
 
#define DEM_RF_DEM_CTRL_REG_EQUAL_EN_Pos   (6UL)
 
#define DEM_RF_DEM_CTRL_REG_EQUAL_EN_Msk   (0x40UL)
 
#define DEM_RF_DEM_CTRL_REG_BLE_DDC_EN_Pos   (7UL)
 
#define DEM_RF_DEM_CTRL_REG_BLE_DDC_EN_Msk   (0x80UL)
 
#define DEM_RF_DEM_CTRL_REG_IQCORR_EN_Pos   (8UL)
 
#define DEM_RF_DEM_CTRL_REG_IQCORR_EN_Msk   (0x100UL)
 
#define DEM_RF_DEM_CTRL_REG_CFE_DOUBLE_EN_Pos   (9UL)
 
#define DEM_RF_DEM_CTRL_REG_CFE_DOUBLE_EN_Msk   (0x200UL)
 
#define DEM_RF_DEM_CTRL_REG_CFE_MEDIAN_EN_Pos   (10UL)
 
#define DEM_RF_DEM_CTRL_REG_CFE_MEDIAN_EN_Msk   (0x400UL)
 
#define DEM_RF_DEM_CTRL_REG_CFE_PPOLE_Pos   (11UL)
 
#define DEM_RF_DEM_CTRL_REG_CFE_PPOLE_Msk   (0x3800UL)
 
#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN0_Pos   (0UL)
 
#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN0_Msk   (0x7UL)
 
#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN0_Pos   (3UL)
 
#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN0_Msk   (0x38UL)
 
#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN0_Pos   (6UL)
 
#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN0_Msk   (0xc0UL)
 
#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN1_Pos   (8UL)
 
#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN1_Msk   (0x700UL)
 
#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN1_Pos   (11UL)
 
#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN1_Msk   (0x3800UL)
 
#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN1_Pos   (14UL)
 
#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN1_Msk   (0xc000UL)
 
#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN2_Pos   (0UL)
 
#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN2_Msk   (0x7UL)
 
#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN2_Pos   (3UL)
 
#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN2_Msk   (0x38UL)
 
#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN2_Pos   (6UL)
 
#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN2_Msk   (0xc0UL)
 
#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN3_Pos   (8UL)
 
#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN3_Msk   (0x700UL)
 
#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN3_Pos   (11UL)
 
#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN3_Msk   (0x3800UL)
 
#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN3_Pos   (14UL)
 
#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN3_Msk   (0xc000UL)
 
#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN4_Pos   (0UL)
 
#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN4_Msk   (0x7UL)
 
#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN4_Pos   (3UL)
 
#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN4_Msk   (0x38UL)
 
#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN4_Pos   (6UL)
 
#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN4_Msk   (0xc0UL)
 
#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN5_Pos   (8UL)
 
#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN5_Msk   (0x700UL)
 
#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN5_Pos   (11UL)
 
#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN5_Msk   (0x3800UL)
 
#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN5_Pos   (14UL)
 
#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN5_Msk   (0xc000UL)
 
#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN6_Pos   (0UL)
 
#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN6_Msk   (0x7UL)
 
#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN6_Pos   (3UL)
 
#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN6_Msk   (0x38UL)
 
#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN6_Pos   (6UL)
 
#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN6_Msk   (0xc0UL)
 
#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN7_Pos   (8UL)
 
#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN7_Msk   (0x700UL)
 
#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN7_Pos   (11UL)
 
#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN7_Msk   (0x3800UL)
 
#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN7_Pos   (14UL)
 
#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN7_Msk   (0xc000UL)
 
#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN8_Pos   (0UL)
 
#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN8_Msk   (0x7UL)
 
#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN8_Pos   (3UL)
 
#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN8_Msk   (0x38UL)
 
#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN8_Pos   (6UL)
 
#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN8_Msk   (0xc0UL)
 
#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN9_Pos   (8UL)
 
#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN9_Msk   (0x700UL)
 
#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN9_Pos   (11UL)
 
#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN9_Msk   (0x3800UL)
 
#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN9_Pos   (14UL)
 
#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN9_Msk   (0xc000UL)
 
#define DEM_RF_AGC_CTRL1_REG_AGC_TH_LOW_Pos   (0UL)
 
#define DEM_RF_AGC_CTRL1_REG_AGC_TH_LOW_Msk   (0x7fUL)
 
#define DEM_RF_AGC_CTRL1_REG_AGC_TH_HIGH_Pos   (7UL)
 
#define DEM_RF_AGC_CTRL1_REG_AGC_TH_HIGH_Msk   (0x3f80UL)
 
#define DEM_RF_AGC_CTRL1_REG_AGC_MODE_Pos   (14UL)
 
#define DEM_RF_AGC_CTRL1_REG_AGC_MODE_Msk   (0xc000UL)
 
#define DEM_RF_AGC_CTRL2_REG_RSSI_TH_Pos   (0UL)
 
#define DEM_RF_AGC_CTRL2_REG_RSSI_TH_Msk   (0x3fUL)
 
#define DEM_RF_AGC_CTRL2_REG_EN_FRZ_GAIN_Pos   (6UL)
 
#define DEM_RF_AGC_CTRL2_REG_EN_FRZ_GAIN_Msk   (0x40UL)
 
#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_SEL_Pos   (7UL)
 
#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_SEL_Msk   (0x80UL)
 
#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_WR_Pos   (8UL)
 
#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_WR_Msk   (0xf00UL)
 
#define DEM_RF_AGC_CTRL2_REG_SLOW_AGC_Pos   (12UL)
 
#define DEM_RF_AGC_CTRL2_REG_SLOW_AGC_Msk   (0x1000UL)
 
#define DEM_RF_AFC_CTRL_REG_AFC_MODE_Pos   (0UL)
 
#define DEM_RF_AFC_CTRL_REG_AFC_MODE_Msk   (0xfUL)
 
#define DEM_RF_AFC_CTRL_REG_POLE1_Pos   (4UL)
 
#define DEM_RF_AFC_CTRL_REG_POLE1_Msk   (0x30UL)
 
#define DEM_RF_AFC_CTRL_REG_POLE2_Pos   (6UL)
 
#define DEM_RF_AFC_CTRL_REG_POLE2_Msk   (0xc0UL)
 
#define DEM_RF_AFC_CTRL_REG_PAD_MODE_Pos   (8UL)
 
#define DEM_RF_AFC_CTRL_REG_PAD_MODE_Msk   (0x300UL)
 
#define DEM_RF_AFC_CTRL_REG_APD_MODE_Pos   (10UL)
 
#define DEM_RF_AFC_CTRL_REG_APD_MODE_Msk   (0x1c00UL)
 
#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_I_WR_Pos   (0UL)
 
#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_I_WR_Msk   (0xffUL)
 
#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_Q_WR_Pos   (8UL)
 
#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_Q_WR_Msk   (0xff00UL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCOFFSET_SEL_Pos   (0UL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCOFFSET_SEL_Msk   (0x1UL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_EN_Pos   (1UL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_EN_Msk   (0x2UL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPOLE_Pos   (2UL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPOLE_Msk   (0xcUL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNSTEP_Pos   (4UL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNSTEP_Msk   (0x70UL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNGAIN_Pos   (7UL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNGAIN_Msk   (0x180UL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_INIT_Pos   (9UL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_INIT_Msk   (0x200UL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCVGA1SCALE_EN_Pos   (10UL)
 
#define DEM_RF_DC_OFFSET_CTRL2_REG_DCVGA1SCALE_EN_Msk   (0x400UL)
 
#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_I_Pos   (0UL)
 
#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_I_Msk   (0xffUL)
 
#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_Q_Pos   (8UL)
 
#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_Q_Msk   (0xff00UL)
 
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL0_Pos   (0UL)
 
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL0_Msk   (0xfUL)
 
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL1_Pos   (4UL)
 
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL1_Msk   (0xf0UL)
 
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL2_Pos   (8UL)
 
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL2_Msk   (0xf00UL)
 
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL3_Pos   (12UL)
 
#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL3_Msk   (0xf000UL)
 
#define DEM_RF_AGC_RESULT_REG_AFC_RD_Pos   (0UL)
 
#define DEM_RF_AGC_RESULT_REG_AFC_RD_Msk   (0xffUL)
 
#define DEM_RF_AGC_RESULT_REG_AGCSETTING_RD_Pos   (8UL)
 
#define DEM_RF_AGC_RESULT_REG_AGCSETTING_RD_Msk   (0xf00UL)
 
#define DEM_RF_RSSI_RESULT_REG_RSSI_PH_RD_Pos   (0UL)
 
#define DEM_RF_RSSI_RESULT_REG_RSSI_PH_RD_Msk   (0x3fUL)
 
#define DEM_RF_RSSI_RESULT_REG_RSSI_AVG_RD_Pos   (6UL)
 
#define DEM_RF_RSSI_RESULT_REG_RSSI_AVG_RD_Msk   (0xffc0UL)
 
#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_I_RD_Pos   (0UL)
 
#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_I_RD_Msk   (0xffUL)
 
#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_Q_RD_Pos   (8UL)
 
#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_Q_RD_Msk   (0xff00UL)
 
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP01_Pos   (0UL)
 
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP01_Msk   (0xfUL)
 
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP10_Pos   (4UL)
 
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP10_Msk   (0xf0UL)
 
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP11_Pos   (8UL)
 
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP11_Msk   (0xf00UL)
 
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP00_Pos   (12UL)
 
#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP00_Msk   (0xf000UL)
 
#define DEM_RF_FTDF_CTRL1_REG_CFE_BIAS_Pos   (0UL)
 
#define DEM_RF_FTDF_CTRL1_REG_CFE_BIAS_Msk   (0x3ffUL)
 
#define DEM_RF_FTDF_CTRL1_REG_CFE_MODE_Pos   (10UL)
 
#define DEM_RF_FTDF_CTRL1_REG_CFE_MODE_Msk   (0xc00UL)
 
#define DEM_RF_FTDF_CTRL1_REG_CFE_NSTEP_Pos   (12UL)
 
#define DEM_RF_FTDF_CTRL1_REG_CFE_NSTEP_Msk   (0x3000UL)
 
#define DEM_RF_FTDF_CTRL1_REG_CHSEL_FILT_MODE2_Pos   (14UL)
 
#define DEM_RF_FTDF_CTRL1_REG_CHSEL_FILT_MODE2_Msk   (0xc000UL)
 
#define DEM_RF_FTDF_CTRL2_REG_CORRTH_Pos   (0UL)
 
#define DEM_RF_FTDF_CTRL2_REG_CORRTH_Msk   (0x3fUL)
 
#define DEM_RF_FTDF_CTRL2_REG_NORM_EN_Pos   (6UL)
 
#define DEM_RF_FTDF_CTRL2_REG_NORM_EN_Msk   (0x40UL)
 
#define DEM_RF_FTDF_CTRL2_REG_PD_MODE_Pos   (7UL)
 
#define DEM_RF_FTDF_CTRL2_REG_PD_MODE_Msk   (0x80UL)
 
#define DEM_RF_FTDF_CTRL2_REG_PD_NPEAK_Pos   (8UL)
 
#define DEM_RF_FTDF_CTRL2_REG_PD_NPEAK_Msk   (0x700UL)
 
#define DEM_RF_FTDF_CTRL2_REG_PD_NWIN_Pos   (11UL)
 
#define DEM_RF_FTDF_CTRL2_REG_PD_NWIN_Msk   (0x3800UL)
 
#define DEM_RF_FTDF_CTRL2_REG_PD_OFFSET_Pos   (14UL)
 
#define DEM_RF_FTDF_CTRL2_REG_PD_OFFSET_Msk   (0xc000UL)
 
#define DEM_RF_FTDF_CTRL3_REG_FIF_Pos   (0UL)
 
#define DEM_RF_FTDF_CTRL3_REG_FIF_Msk   (0x1ffUL)
 
#define DEM_RF_FTDF_CTRL3_REG_FTDF_DDC_EN_Pos   (9UL)
 
#define DEM_RF_FTDF_CTRL3_REG_FTDF_DDC_EN_Msk   (0x200UL)
 
#define DEM_RF_FTDF_CTRL3_REG_MATCH_FILT_EN_Pos   (10UL)
 
#define DEM_RF_FTDF_CTRL3_REG_MATCH_FILT_EN_Msk   (0x400UL)
 
#define DEM_RF_FTDF_CTRL3_REG_TIMING_CORR_EN_Pos   (11UL)
 
#define DEM_RF_FTDF_CTRL3_REG_TIMING_CORR_EN_Msk   (0x800UL)
 
#define DEM_RF_FTDF_CTRL3_REG_CHSEL_FILT_MODE1_Pos   (12UL)
 
#define DEM_RF_FTDF_CTRL3_REG_CHSEL_FILT_MODE1_Msk   (0x3000UL)
 
#define DEM_RF_FTDF_CTRL3_REG_DS_OFFSET_Pos   (14UL)
 
#define DEM_RF_FTDF_CTRL3_REG_DS_OFFSET_Msk   (0xc000UL)
 
#define DEM_RF_FTDF_CTRL4_REG_SFD0_Pos   (0UL)
 
#define DEM_RF_FTDF_CTRL4_REG_SFD0_Msk   (0xfUL)
 
#define DEM_RF_FTDF_CTRL4_REG_SFD1_Pos   (4UL)
 
#define DEM_RF_FTDF_CTRL4_REG_SFD1_Msk   (0xf0UL)
 
#define DEM_RF_FTDF_CTRL4_REG_LQI_PREAMBLE_EN_Pos   (8UL)
 
#define DEM_RF_FTDF_CTRL4_REG_LQI_PREAMBLE_EN_Msk   (0x100UL)
 
#define DEM_RF_FTDF_CTRL4_REG_LQI_SYMBOL_EN_Pos   (9UL)
 
#define DEM_RF_FTDF_CTRL4_REG_LQI_SYMBOL_EN_Msk   (0x200UL)
 
#define DEM_RF_FTDF_CTRL4_REG_LQI_CORRTH_EN_Pos   (10UL)
 
#define DEM_RF_FTDF_CTRL4_REG_LQI_CORRTH_EN_Msk   (0x400UL)
 
#define DEM_RF_FTDF_CTRL4_REG_LQI_SCALE_Pos   (11UL)
 
#define DEM_RF_FTDF_CTRL4_REG_LQI_SCALE_Msk   (0x1800UL)
 
#define DEM_RF_FTDF_CTRL4_REG_FTDF_HSI_POL_Pos   (13UL)
 
#define DEM_RF_FTDF_CTRL4_REG_FTDF_HSI_POL_Msk   (0x2000UL)
 
#define DEM_RF_FTDF_CTRL4_REG_CCA_MODE_Pos   (14UL)
 
#define DEM_RF_FTDF_CTRL4_REG_CCA_MODE_Msk   (0x4000UL)
 
#define DEM_RF_FTDF_CTRL4_REG_SO_FTDF_SEL_Pos   (15UL)
 
#define DEM_RF_FTDF_CTRL4_REG_SO_FTDF_SEL_Msk   (0x8000UL)
 
#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KP_LF_PD_Pos   (0UL)
 
#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KP_LF_PD_Msk   (0xffUL)
 
#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KI_LF_PD_Pos   (8UL)
 
#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KI_LF_PD_Msk   (0xff00UL)
 
#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KP_LF_DS_Pos   (0UL)
 
#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KP_LF_DS_Msk   (0xffUL)
 
#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KI_LF_DS_Pos   (8UL)
 
#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KI_LF_DS_Msk   (0xff00UL)
 
#define DEM_RF_FTDF_CTRL5_REG_RSSITH_Pos   (0UL)
 
#define DEM_RF_FTDF_CTRL5_REG_RSSITH_Msk   (0x1fffUL)
 
#define DEM_RF_FTDF_CTRL5_REG_FTDF_DDC_INV_Pos   (13UL)
 
#define DEM_RF_FTDF_CTRL5_REG_FTDF_DDC_INV_Msk   (0x2000UL)
 
#define DEM_RF_FTDF_CTRL5_REG_FSSS_CLEAR_Pos   (14UL)
 
#define DEM_RF_FTDF_CTRL5_REG_FSSS_CLEAR_Msk   (0x4000UL)
 
#define DEM_RF_FTDF_CTRL5_REG_DS_OFFSET_SEL_Pos   (15UL)
 
#define DEM_RF_FTDF_CTRL5_REG_DS_OFFSET_SEL_Msk   (0x8000UL)
 
#define DEM_RF_FTDF_COBI_LOW_REG_COBI_Pos   (0UL)
 
#define DEM_RF_FTDF_COBI_LOW_REG_COBI_Msk   (0xffffUL)
 
#define DEM_RF_FTDF_COBI_HIGH_REG_COBI_Pos   (0UL)
 
#define DEM_RF_FTDF_COBI_HIGH_REG_COBI_Msk   (0xffffUL)
 
#define DEM_RF_DEM_TESTMODE_REG_DEM_TESTMODE_Pos   (0UL)
 
#define DEM_RF_DEM_TESTMODE_REG_DEM_TESTMODE_Msk   (0x3ffUL)
 
#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_BETA_Pos   (0UL)
 
#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_BETA_Msk   (0xffUL)
 
#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_ALPHA_Pos   (8UL)
 
#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_ALPHA_Msk   (0xff00UL)
 
#define DEM_RF_PAD_CNT_CTRL_REG_PAD_POS_LIMIT_Pos   (0UL)
 
#define DEM_RF_PAD_CNT_CTRL_REG_PAD_POS_LIMIT_Msk   (0x7fUL)
 
#define DEM_RF_PAD_CNT_CTRL_REG_PAD_NEG_LIMIT_Pos   (7UL)
 
#define DEM_RF_PAD_CNT_CTRL_REG_PAD_NEG_LIMIT_Msk   (0x3f80UL)
 
#define DEM_RF_PAD_CNT_CTRL_REG_PAD_CLEAR_COUNT_Pos   (14UL)
 
#define DEM_RF_PAD_CNT_CTRL_REG_PAD_CLEAR_COUNT_Msk   (0x4000UL)
 
#define DEM_RF_PAD_CNT_RESULT_REG_PAD_POS_CNT_RD_Pos   (0UL)
 
#define DEM_RF_PAD_CNT_RESULT_REG_PAD_POS_CNT_RD_Msk   (0xffUL)
 
#define DEM_RF_PAD_CNT_RESULT_REG_PAD_NEG_CNT_RD_Pos   (8UL)
 
#define DEM_RF_PAD_CNT_RESULT_REG_PAD_NEG_CNT_RD_Msk   (0xff00UL)
 
#define DEM_RF_FSSS_I_RESULT_REG_FSSS_I_RD_Pos   (0UL)
 
#define DEM_RF_FSSS_I_RESULT_REG_FSSS_I_RD_Msk   (0xffffUL)
 
#define DEM_RF_FSSS_Q_RESULT_REG_FSSS_Q_RD_Pos   (0UL)
 
#define DEM_RF_FSSS_Q_RESULT_REG_FSSS_Q_RD_Msk   (0xffffUL)
 
#define DEM_RF_FSSS_MAG_RESULT_REG_FSSS_MAG_RD_Pos   (0UL)
 
#define DEM_RF_FSSS_MAG_RESULT_REG_FSSS_MAG_RD_Msk   (0xffffUL)
 
#define DEM_RF_CCA_RSSITH_REG_CCA_RSSITH_Pos   (0UL)
 
#define DEM_RF_CCA_RSSITH_REG_CCA_RSSITH_Msk   (0x1fffUL)
 
#define DEM_RF_CCA_RSSITH_REG_SIGDET_TIMEOUT_LEN_Pos   (13UL)
 
#define DEM_RF_CCA_RSSITH_REG_SIGDET_TIMEOUT_LEN_Msk   (0xe000UL)
 
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_MODE_Pos   (0UL)
 
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_MODE_Msk   (0x3UL)
 
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_THRESHOLD_Pos   (2UL)
 
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_THRESHOLD_Msk   (0xfcUL)
 
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DIFF_Pos   (8UL)
 
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DIFF_Msk   (0x100UL)
 
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR2_Pos   (9UL)
 
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR2_Msk   (0x600UL)
 
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR1_Pos   (11UL)
 
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR1_Msk   (0x1800UL)
 
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DELAY_Pos   (13UL)
 
#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DELAY_Msk   (0x6000UL)
 
#define DMA_DMA0_A_STARTL_REG_DMA0_A_STARTL_Pos   (0UL)
 
#define DMA_DMA0_A_STARTL_REG_DMA0_A_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA0_A_STARTH_REG_DMA0_A_STARTH_Pos   (0UL)
 
#define DMA_DMA0_A_STARTH_REG_DMA0_A_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA0_B_STARTL_REG_DMA0_B_STARTL_Pos   (0UL)
 
#define DMA_DMA0_B_STARTL_REG_DMA0_B_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA0_B_STARTH_REG_DMA0_B_STARTH_Pos   (0UL)
 
#define DMA_DMA0_B_STARTH_REG_DMA0_B_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA0_INT_REG_DMA0_INT_Pos   (0UL)
 
#define DMA_DMA0_INT_REG_DMA0_INT_Msk   (0xffffUL)
 
#define DMA_DMA0_LEN_REG_DMA0_LEN_Pos   (0UL)
 
#define DMA_DMA0_LEN_REG_DMA0_LEN_Msk   (0xffffUL)
 
#define DMA_DMA0_CTRL_REG_DMA_ON_Pos   (0UL)
 
#define DMA_DMA0_CTRL_REG_DMA_ON_Msk   (0x1UL)
 
#define DMA_DMA0_CTRL_REG_BW_Pos   (1UL)
 
#define DMA_DMA0_CTRL_REG_BW_Msk   (0x6UL)
 
#define DMA_DMA0_CTRL_REG_IRQ_ENABLE_Pos   (3UL)
 
#define DMA_DMA0_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)
 
#define DMA_DMA0_CTRL_REG_DREQ_MODE_Pos   (4UL)
 
#define DMA_DMA0_CTRL_REG_DREQ_MODE_Msk   (0x10UL)
 
#define DMA_DMA0_CTRL_REG_BINC_Pos   (5UL)
 
#define DMA_DMA0_CTRL_REG_BINC_Msk   (0x20UL)
 
#define DMA_DMA0_CTRL_REG_AINC_Pos   (6UL)
 
#define DMA_DMA0_CTRL_REG_AINC_Msk   (0x40UL)
 
#define DMA_DMA0_CTRL_REG_CIRCULAR_Pos   (7UL)
 
#define DMA_DMA0_CTRL_REG_CIRCULAR_Msk   (0x80UL)
 
#define DMA_DMA0_CTRL_REG_DMA_PRIO_Pos   (8UL)
 
#define DMA_DMA0_CTRL_REG_DMA_PRIO_Msk   (0x700UL)
 
#define DMA_DMA0_CTRL_REG_DMA_IDLE_Pos   (11UL)
 
#define DMA_DMA0_CTRL_REG_DMA_IDLE_Msk   (0x800UL)
 
#define DMA_DMA0_CTRL_REG_DMA_INIT_Pos   (12UL)
 
#define DMA_DMA0_CTRL_REG_DMA_INIT_Msk   (0x1000UL)
 
#define DMA_DMA0_CTRL_REG_REQ_SENSE_Pos   (13UL)
 
#define DMA_DMA0_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)
 
#define DMA_DMA0_IDX_REG_DMA0_IDX_Pos   (0UL)
 
#define DMA_DMA0_IDX_REG_DMA0_IDX_Msk   (0xffffUL)
 
#define DMA_DMA1_A_STARTL_REG_DMA1_A_STARTL_Pos   (0UL)
 
#define DMA_DMA1_A_STARTL_REG_DMA1_A_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA1_A_STARTH_REG_DMA1_A_STARTH_Pos   (0UL)
 
#define DMA_DMA1_A_STARTH_REG_DMA1_A_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA1_B_STARTL_REG_DMA1_B_STARTL_Pos   (0UL)
 
#define DMA_DMA1_B_STARTL_REG_DMA1_B_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA1_B_STARTH_REG_DMA1_B_STARTH_Pos   (0UL)
 
#define DMA_DMA1_B_STARTH_REG_DMA1_B_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA1_INT_REG_DMA1_INT_Pos   (0UL)
 
#define DMA_DMA1_INT_REG_DMA1_INT_Msk   (0xffffUL)
 
#define DMA_DMA1_LEN_REG_DMA1_LEN_Pos   (0UL)
 
#define DMA_DMA1_LEN_REG_DMA1_LEN_Msk   (0xffffUL)
 
#define DMA_DMA1_CTRL_REG_DMA_ON_Pos   (0UL)
 
#define DMA_DMA1_CTRL_REG_DMA_ON_Msk   (0x1UL)
 
#define DMA_DMA1_CTRL_REG_BW_Pos   (1UL)
 
#define DMA_DMA1_CTRL_REG_BW_Msk   (0x6UL)
 
#define DMA_DMA1_CTRL_REG_IRQ_ENABLE_Pos   (3UL)
 
#define DMA_DMA1_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)
 
#define DMA_DMA1_CTRL_REG_DREQ_MODE_Pos   (4UL)
 
#define DMA_DMA1_CTRL_REG_DREQ_MODE_Msk   (0x10UL)
 
#define DMA_DMA1_CTRL_REG_BINC_Pos   (5UL)
 
#define DMA_DMA1_CTRL_REG_BINC_Msk   (0x20UL)
 
#define DMA_DMA1_CTRL_REG_AINC_Pos   (6UL)
 
#define DMA_DMA1_CTRL_REG_AINC_Msk   (0x40UL)
 
#define DMA_DMA1_CTRL_REG_CIRCULAR_Pos   (7UL)
 
#define DMA_DMA1_CTRL_REG_CIRCULAR_Msk   (0x80UL)
 
#define DMA_DMA1_CTRL_REG_DMA_PRIO_Pos   (8UL)
 
#define DMA_DMA1_CTRL_REG_DMA_PRIO_Msk   (0x700UL)
 
#define DMA_DMA1_CTRL_REG_DMA_IDLE_Pos   (11UL)
 
#define DMA_DMA1_CTRL_REG_DMA_IDLE_Msk   (0x800UL)
 
#define DMA_DMA1_CTRL_REG_DMA_INIT_Pos   (12UL)
 
#define DMA_DMA1_CTRL_REG_DMA_INIT_Msk   (0x1000UL)
 
#define DMA_DMA1_CTRL_REG_REQ_SENSE_Pos   (13UL)
 
#define DMA_DMA1_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)
 
#define DMA_DMA1_IDX_REG_DMA1_IDX_Pos   (0UL)
 
#define DMA_DMA1_IDX_REG_DMA1_IDX_Msk   (0xffffUL)
 
#define DMA_DMA2_A_STARTL_REG_DMA2_A_STARTL_Pos   (0UL)
 
#define DMA_DMA2_A_STARTL_REG_DMA2_A_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA2_A_STARTH_REG_DMA2_A_STARTH_Pos   (0UL)
 
#define DMA_DMA2_A_STARTH_REG_DMA2_A_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA2_B_STARTL_REG_DMA2_B_STARTL_Pos   (0UL)
 
#define DMA_DMA2_B_STARTL_REG_DMA2_B_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA2_B_STARTH_REG_DMA2_B_STARTH_Pos   (0UL)
 
#define DMA_DMA2_B_STARTH_REG_DMA2_B_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA2_INT_REG_DMA2_INT_Pos   (0UL)
 
#define DMA_DMA2_INT_REG_DMA2_INT_Msk   (0xffffUL)
 
#define DMA_DMA2_LEN_REG_DMA2_LEN_Pos   (0UL)
 
#define DMA_DMA2_LEN_REG_DMA2_LEN_Msk   (0xffffUL)
 
#define DMA_DMA2_CTRL_REG_DMA_ON_Pos   (0UL)
 
#define DMA_DMA2_CTRL_REG_DMA_ON_Msk   (0x1UL)
 
#define DMA_DMA2_CTRL_REG_BW_Pos   (1UL)
 
#define DMA_DMA2_CTRL_REG_BW_Msk   (0x6UL)
 
#define DMA_DMA2_CTRL_REG_IRQ_ENABLE_Pos   (3UL)
 
#define DMA_DMA2_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)
 
#define DMA_DMA2_CTRL_REG_DREQ_MODE_Pos   (4UL)
 
#define DMA_DMA2_CTRL_REG_DREQ_MODE_Msk   (0x10UL)
 
#define DMA_DMA2_CTRL_REG_BINC_Pos   (5UL)
 
#define DMA_DMA2_CTRL_REG_BINC_Msk   (0x20UL)
 
#define DMA_DMA2_CTRL_REG_AINC_Pos   (6UL)
 
#define DMA_DMA2_CTRL_REG_AINC_Msk   (0x40UL)
 
#define DMA_DMA2_CTRL_REG_CIRCULAR_Pos   (7UL)
 
#define DMA_DMA2_CTRL_REG_CIRCULAR_Msk   (0x80UL)
 
#define DMA_DMA2_CTRL_REG_DMA_PRIO_Pos   (8UL)
 
#define DMA_DMA2_CTRL_REG_DMA_PRIO_Msk   (0x700UL)
 
#define DMA_DMA2_CTRL_REG_DMA_IDLE_Pos   (11UL)
 
#define DMA_DMA2_CTRL_REG_DMA_IDLE_Msk   (0x800UL)
 
#define DMA_DMA2_CTRL_REG_DMA_INIT_Pos   (12UL)
 
#define DMA_DMA2_CTRL_REG_DMA_INIT_Msk   (0x1000UL)
 
#define DMA_DMA2_CTRL_REG_REQ_SENSE_Pos   (13UL)
 
#define DMA_DMA2_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)
 
#define DMA_DMA2_IDX_REG_DMA2_IDX_Pos   (0UL)
 
#define DMA_DMA2_IDX_REG_DMA2_IDX_Msk   (0xffffUL)
 
#define DMA_DMA3_A_STARTL_REG_DMA3_A_STARTL_Pos   (0UL)
 
#define DMA_DMA3_A_STARTL_REG_DMA3_A_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA3_A_STARTH_REG_DMA3_A_STARTH_Pos   (0UL)
 
#define DMA_DMA3_A_STARTH_REG_DMA3_A_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA3_B_STARTL_REG_DMA3_B_STARTL_Pos   (0UL)
 
#define DMA_DMA3_B_STARTL_REG_DMA3_B_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA3_B_STARTH_REG_DMA3_B_STARTH_Pos   (0UL)
 
#define DMA_DMA3_B_STARTH_REG_DMA3_B_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA3_INT_REG_DMA3_INT_Pos   (0UL)
 
#define DMA_DMA3_INT_REG_DMA3_INT_Msk   (0xffffUL)
 
#define DMA_DMA3_LEN_REG_DMA3_LEN_Pos   (0UL)
 
#define DMA_DMA3_LEN_REG_DMA3_LEN_Msk   (0xffffUL)
 
#define DMA_DMA3_CTRL_REG_DMA_ON_Pos   (0UL)
 
#define DMA_DMA3_CTRL_REG_DMA_ON_Msk   (0x1UL)
 
#define DMA_DMA3_CTRL_REG_BW_Pos   (1UL)
 
#define DMA_DMA3_CTRL_REG_BW_Msk   (0x6UL)
 
#define DMA_DMA3_CTRL_REG_IRQ_ENABLE_Pos   (3UL)
 
#define DMA_DMA3_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)
 
#define DMA_DMA3_CTRL_REG_DREQ_MODE_Pos   (4UL)
 
#define DMA_DMA3_CTRL_REG_DREQ_MODE_Msk   (0x10UL)
 
#define DMA_DMA3_CTRL_REG_BINC_Pos   (5UL)
 
#define DMA_DMA3_CTRL_REG_BINC_Msk   (0x20UL)
 
#define DMA_DMA3_CTRL_REG_AINC_Pos   (6UL)
 
#define DMA_DMA3_CTRL_REG_AINC_Msk   (0x40UL)
 
#define DMA_DMA3_CTRL_REG_CIRCULAR_Pos   (7UL)
 
#define DMA_DMA3_CTRL_REG_CIRCULAR_Msk   (0x80UL)
 
#define DMA_DMA3_CTRL_REG_DMA_PRIO_Pos   (8UL)
 
#define DMA_DMA3_CTRL_REG_DMA_PRIO_Msk   (0x700UL)
 
#define DMA_DMA3_CTRL_REG_DMA_IDLE_Pos   (11UL)
 
#define DMA_DMA3_CTRL_REG_DMA_IDLE_Msk   (0x800UL)
 
#define DMA_DMA3_CTRL_REG_DMA_INIT_Pos   (12UL)
 
#define DMA_DMA3_CTRL_REG_DMA_INIT_Msk   (0x1000UL)
 
#define DMA_DMA3_CTRL_REG_REQ_SENSE_Pos   (13UL)
 
#define DMA_DMA3_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)
 
#define DMA_DMA3_IDX_REG_DMA3_IDX_Pos   (0UL)
 
#define DMA_DMA3_IDX_REG_DMA3_IDX_Msk   (0xffffUL)
 
#define DMA_DMA4_A_STARTL_REG_DMA4_A_STARTL_Pos   (0UL)
 
#define DMA_DMA4_A_STARTL_REG_DMA4_A_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA4_A_STARTH_REG_DMA4_A_STARTH_Pos   (0UL)
 
#define DMA_DMA4_A_STARTH_REG_DMA4_A_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA4_B_STARTL_REG_DMA4_B_STARTL_Pos   (0UL)
 
#define DMA_DMA4_B_STARTL_REG_DMA4_B_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA4_B_STARTH_REG_DMA4_B_STARTH_Pos   (0UL)
 
#define DMA_DMA4_B_STARTH_REG_DMA4_B_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA4_INT_REG_DMA4_INT_Pos   (0UL)
 
#define DMA_DMA4_INT_REG_DMA4_INT_Msk   (0xffffUL)
 
#define DMA_DMA4_LEN_REG_DMA4_LEN_Pos   (0UL)
 
#define DMA_DMA4_LEN_REG_DMA4_LEN_Msk   (0xffffUL)
 
#define DMA_DMA4_CTRL_REG_DMA_ON_Pos   (0UL)
 
#define DMA_DMA4_CTRL_REG_DMA_ON_Msk   (0x1UL)
 
#define DMA_DMA4_CTRL_REG_BW_Pos   (1UL)
 
#define DMA_DMA4_CTRL_REG_BW_Msk   (0x6UL)
 
#define DMA_DMA4_CTRL_REG_IRQ_ENABLE_Pos   (3UL)
 
#define DMA_DMA4_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)
 
#define DMA_DMA4_CTRL_REG_DREQ_MODE_Pos   (4UL)
 
#define DMA_DMA4_CTRL_REG_DREQ_MODE_Msk   (0x10UL)
 
#define DMA_DMA4_CTRL_REG_BINC_Pos   (5UL)
 
#define DMA_DMA4_CTRL_REG_BINC_Msk   (0x20UL)
 
#define DMA_DMA4_CTRL_REG_AINC_Pos   (6UL)
 
#define DMA_DMA4_CTRL_REG_AINC_Msk   (0x40UL)
 
#define DMA_DMA4_CTRL_REG_CIRCULAR_Pos   (7UL)
 
#define DMA_DMA4_CTRL_REG_CIRCULAR_Msk   (0x80UL)
 
#define DMA_DMA4_CTRL_REG_DMA_PRIO_Pos   (8UL)
 
#define DMA_DMA4_CTRL_REG_DMA_PRIO_Msk   (0x700UL)
 
#define DMA_DMA4_CTRL_REG_DMA_IDLE_Pos   (11UL)
 
#define DMA_DMA4_CTRL_REG_DMA_IDLE_Msk   (0x800UL)
 
#define DMA_DMA4_CTRL_REG_DMA_INIT_Pos   (12UL)
 
#define DMA_DMA4_CTRL_REG_DMA_INIT_Msk   (0x1000UL)
 
#define DMA_DMA4_CTRL_REG_REQ_SENSE_Pos   (13UL)
 
#define DMA_DMA4_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)
 
#define DMA_DMA4_IDX_REG_DMA4_IDX_Pos   (0UL)
 
#define DMA_DMA4_IDX_REG_DMA4_IDX_Msk   (0xffffUL)
 
#define DMA_DMA5_A_STARTL_REG_DMA5_A_STARTL_Pos   (0UL)
 
#define DMA_DMA5_A_STARTL_REG_DMA5_A_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA5_A_STARTH_REG_DMA5_A_STARTH_Pos   (0UL)
 
#define DMA_DMA5_A_STARTH_REG_DMA5_A_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA5_B_STARTL_REG_DMA5_B_STARTL_Pos   (0UL)
 
#define DMA_DMA5_B_STARTL_REG_DMA5_B_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA5_B_STARTH_REG_DMA5_B_STARTH_Pos   (0UL)
 
#define DMA_DMA5_B_STARTH_REG_DMA5_B_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA5_INT_REG_DMA5_INT_Pos   (0UL)
 
#define DMA_DMA5_INT_REG_DMA5_INT_Msk   (0xffffUL)
 
#define DMA_DMA5_LEN_REG_DMA5_LEN_Pos   (0UL)
 
#define DMA_DMA5_LEN_REG_DMA5_LEN_Msk   (0xffffUL)
 
#define DMA_DMA5_CTRL_REG_DMA_ON_Pos   (0UL)
 
#define DMA_DMA5_CTRL_REG_DMA_ON_Msk   (0x1UL)
 
#define DMA_DMA5_CTRL_REG_BW_Pos   (1UL)
 
#define DMA_DMA5_CTRL_REG_BW_Msk   (0x6UL)
 
#define DMA_DMA5_CTRL_REG_IRQ_ENABLE_Pos   (3UL)
 
#define DMA_DMA5_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)
 
#define DMA_DMA5_CTRL_REG_DREQ_MODE_Pos   (4UL)
 
#define DMA_DMA5_CTRL_REG_DREQ_MODE_Msk   (0x10UL)
 
#define DMA_DMA5_CTRL_REG_BINC_Pos   (5UL)
 
#define DMA_DMA5_CTRL_REG_BINC_Msk   (0x20UL)
 
#define DMA_DMA5_CTRL_REG_AINC_Pos   (6UL)
 
#define DMA_DMA5_CTRL_REG_AINC_Msk   (0x40UL)
 
#define DMA_DMA5_CTRL_REG_CIRCULAR_Pos   (7UL)
 
#define DMA_DMA5_CTRL_REG_CIRCULAR_Msk   (0x80UL)
 
#define DMA_DMA5_CTRL_REG_DMA_PRIO_Pos   (8UL)
 
#define DMA_DMA5_CTRL_REG_DMA_PRIO_Msk   (0x700UL)
 
#define DMA_DMA5_CTRL_REG_DMA_IDLE_Pos   (11UL)
 
#define DMA_DMA5_CTRL_REG_DMA_IDLE_Msk   (0x800UL)
 
#define DMA_DMA5_CTRL_REG_DMA_INIT_Pos   (12UL)
 
#define DMA_DMA5_CTRL_REG_DMA_INIT_Msk   (0x1000UL)
 
#define DMA_DMA5_CTRL_REG_REQ_SENSE_Pos   (13UL)
 
#define DMA_DMA5_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)
 
#define DMA_DMA5_IDX_REG_DMA5_IDX_Pos   (0UL)
 
#define DMA_DMA5_IDX_REG_DMA5_IDX_Msk   (0xffffUL)
 
#define DMA_DMA6_A_STARTL_REG_DMA6_A_STARTL_Pos   (0UL)
 
#define DMA_DMA6_A_STARTL_REG_DMA6_A_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA6_A_STARTH_REG_DMA6_A_STARTH_Pos   (0UL)
 
#define DMA_DMA6_A_STARTH_REG_DMA6_A_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA6_B_STARTL_REG_DMA6_B_STARTL_Pos   (0UL)
 
#define DMA_DMA6_B_STARTL_REG_DMA6_B_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA6_B_STARTH_REG_DMA6_B_STARTH_Pos   (0UL)
 
#define DMA_DMA6_B_STARTH_REG_DMA6_B_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA6_INT_REG_DMA6_INT_Pos   (0UL)
 
#define DMA_DMA6_INT_REG_DMA6_INT_Msk   (0xffffUL)
 
#define DMA_DMA6_LEN_REG_DMA6_LEN_Pos   (0UL)
 
#define DMA_DMA6_LEN_REG_DMA6_LEN_Msk   (0xffffUL)
 
#define DMA_DMA6_CTRL_REG_DMA_ON_Pos   (0UL)
 
#define DMA_DMA6_CTRL_REG_DMA_ON_Msk   (0x1UL)
 
#define DMA_DMA6_CTRL_REG_BW_Pos   (1UL)
 
#define DMA_DMA6_CTRL_REG_BW_Msk   (0x6UL)
 
#define DMA_DMA6_CTRL_REG_IRQ_ENABLE_Pos   (3UL)
 
#define DMA_DMA6_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)
 
#define DMA_DMA6_CTRL_REG_DREQ_MODE_Pos   (4UL)
 
#define DMA_DMA6_CTRL_REG_DREQ_MODE_Msk   (0x10UL)
 
#define DMA_DMA6_CTRL_REG_BINC_Pos   (5UL)
 
#define DMA_DMA6_CTRL_REG_BINC_Msk   (0x20UL)
 
#define DMA_DMA6_CTRL_REG_AINC_Pos   (6UL)
 
#define DMA_DMA6_CTRL_REG_AINC_Msk   (0x40UL)
 
#define DMA_DMA6_CTRL_REG_CIRCULAR_Pos   (7UL)
 
#define DMA_DMA6_CTRL_REG_CIRCULAR_Msk   (0x80UL)
 
#define DMA_DMA6_CTRL_REG_DMA_PRIO_Pos   (8UL)
 
#define DMA_DMA6_CTRL_REG_DMA_PRIO_Msk   (0x700UL)
 
#define DMA_DMA6_CTRL_REG_DMA_IDLE_Pos   (11UL)
 
#define DMA_DMA6_CTRL_REG_DMA_IDLE_Msk   (0x800UL)
 
#define DMA_DMA6_CTRL_REG_DMA_INIT_Pos   (12UL)
 
#define DMA_DMA6_CTRL_REG_DMA_INIT_Msk   (0x1000UL)
 
#define DMA_DMA6_CTRL_REG_REQ_SENSE_Pos   (13UL)
 
#define DMA_DMA6_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)
 
#define DMA_DMA6_IDX_REG_DMA6_IDX_Pos   (0UL)
 
#define DMA_DMA6_IDX_REG_DMA6_IDX_Msk   (0xffffUL)
 
#define DMA_DMA7_A_STARTL_REG_DMA7_A_STARTL_Pos   (0UL)
 
#define DMA_DMA7_A_STARTL_REG_DMA7_A_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA7_A_STARTH_REG_DMA7_A_STARTH_Pos   (0UL)
 
#define DMA_DMA7_A_STARTH_REG_DMA7_A_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA7_B_STARTL_REG_DMA7_B_STARTL_Pos   (0UL)
 
#define DMA_DMA7_B_STARTL_REG_DMA7_B_STARTL_Msk   (0xffffUL)
 
#define DMA_DMA7_B_STARTH_REG_DMA7_B_STARTH_Pos   (0UL)
 
#define DMA_DMA7_B_STARTH_REG_DMA7_B_STARTH_Msk   (0xffffUL)
 
#define DMA_DMA7_INT_REG_DMA7_INT_Pos   (0UL)
 
#define DMA_DMA7_INT_REG_DMA7_INT_Msk   (0xffffUL)
 
#define DMA_DMA7_LEN_REG_DMA7_LEN_Pos   (0UL)
 
#define DMA_DMA7_LEN_REG_DMA7_LEN_Msk   (0xffffUL)
 
#define DMA_DMA7_CTRL_REG_DMA_ON_Pos   (0UL)
 
#define DMA_DMA7_CTRL_REG_DMA_ON_Msk   (0x1UL)
 
#define DMA_DMA7_CTRL_REG_BW_Pos   (1UL)
 
#define DMA_DMA7_CTRL_REG_BW_Msk   (0x6UL)
 
#define DMA_DMA7_CTRL_REG_IRQ_ENABLE_Pos   (3UL)
 
#define DMA_DMA7_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)
 
#define DMA_DMA7_CTRL_REG_DREQ_MODE_Pos   (4UL)
 
#define DMA_DMA7_CTRL_REG_DREQ_MODE_Msk   (0x10UL)
 
#define DMA_DMA7_CTRL_REG_BINC_Pos   (5UL)
 
#define DMA_DMA7_CTRL_REG_BINC_Msk   (0x20UL)
 
#define DMA_DMA7_CTRL_REG_AINC_Pos   (6UL)
 
#define DMA_DMA7_CTRL_REG_AINC_Msk   (0x40UL)
 
#define DMA_DMA7_CTRL_REG_CIRCULAR_Pos   (7UL)
 
#define DMA_DMA7_CTRL_REG_CIRCULAR_Msk   (0x80UL)
 
#define DMA_DMA7_CTRL_REG_DMA_PRIO_Pos   (8UL)
 
#define DMA_DMA7_CTRL_REG_DMA_PRIO_Msk   (0x700UL)
 
#define DMA_DMA7_CTRL_REG_DMA_IDLE_Pos   (11UL)
 
#define DMA_DMA7_CTRL_REG_DMA_IDLE_Msk   (0x800UL)
 
#define DMA_DMA7_CTRL_REG_DMA_INIT_Pos   (12UL)
 
#define DMA_DMA7_CTRL_REG_DMA_INIT_Msk   (0x1000UL)
 
#define DMA_DMA7_CTRL_REG_REQ_SENSE_Pos   (13UL)
 
#define DMA_DMA7_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)
 
#define DMA_DMA7_IDX_REG_DMA7_IDX_Pos   (0UL)
 
#define DMA_DMA7_IDX_REG_DMA7_IDX_Msk   (0xffffUL)
 
#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Pos   (0UL)
 
#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Msk   (0xfUL)
 
#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Pos   (4UL)
 
#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Msk   (0xf0UL)
 
#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Pos   (8UL)
 
#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Msk   (0xf00UL)
 
#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Pos   (12UL)
 
#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Msk   (0xf000UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Pos   (0UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Msk   (0x1UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Pos   (1UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Msk   (0x2UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Pos   (2UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Msk   (0x4UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Pos   (3UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Msk   (0x8UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Pos   (4UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Msk   (0x10UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Pos   (5UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Msk   (0x20UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Pos   (6UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Msk   (0x40UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Pos   (7UL)
 
#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Msk   (0x80UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Pos   (0UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Msk   (0x1UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Pos   (1UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Msk   (0x2UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Pos   (2UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Msk   (0x4UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Pos   (3UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Msk   (0x8UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Pos   (4UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Msk   (0x10UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Pos   (5UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Msk   (0x20UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Pos   (6UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Msk   (0x40UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Pos   (7UL)
 
#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Msk   (0x80UL)
 
#define ECC_ECC_CONFIG_REG_ECC_OpPtrA_Pos   (0UL)
 
#define ECC_ECC_CONFIG_REG_ECC_OpPtrA_Msk   (0x1fUL)
 
#define ECC_ECC_CONFIG_REG_ECC_OpPtrB_Pos   (8UL)
 
#define ECC_ECC_CONFIG_REG_ECC_OpPtrB_Msk   (0x1f00UL)
 
#define ECC_ECC_CONFIG_REG_ECC_OpPtrC_Pos   (16UL)
 
#define ECC_ECC_CONFIG_REG_ECC_OpPtrC_Msk   (0x1f0000UL)
 
#define ECC_ECC_COMMAND_REG_ECC_TypeOperation_Pos   (0UL)
 
#define ECC_ECC_COMMAND_REG_ECC_TypeOperation_Msk   (0x7fUL)
 
#define ECC_ECC_COMMAND_REG_ECC_Field_Pos   (7UL)
 
#define ECC_ECC_COMMAND_REG_ECC_Field_Msk   (0x80UL)
 
#define ECC_ECC_COMMAND_REG_ECC_SizeOfOperands_Pos   (8UL)
 
#define ECC_ECC_COMMAND_REG_ECC_SizeOfOperands_Msk   (0xff00UL)
 
#define ECC_ECC_COMMAND_REG_ECC_SignA_Pos   (29UL)
 
#define ECC_ECC_COMMAND_REG_ECC_SignA_Msk   (0x20000000UL)
 
#define ECC_ECC_COMMAND_REG_ECC_SignB_Pos   (30UL)
 
#define ECC_ECC_COMMAND_REG_ECC_SignB_Msk   (0x40000000UL)
 
#define ECC_ECC_COMMAND_REG_ECC_CalcR2_Pos   (31UL)
 
#define ECC_ECC_COMMAND_REG_ECC_CalcR2_Msk   (0x80000000UL)
 
#define ECC_ECC_CONTROL_REG_ECC_Start_Pos   (0UL)
 
#define ECC_ECC_CONTROL_REG_ECC_Start_Msk   (0x1UL)
 
#define ECC_ECC_STATUS_REG_ECC_Fail_Address_Pos   (0UL)
 
#define ECC_ECC_STATUS_REG_ECC_Fail_Address_Msk   (0xfUL)
 
#define ECC_ECC_STATUS_REG_ECC_Point_Px_NotOnCurve_Pos   (4UL)
 
#define ECC_ECC_STATUS_REG_ECC_Point_Px_NotOnCurve_Msk   (0x10UL)
 
#define ECC_ECC_STATUS_REG_ECC_Point_Px_AtInfinity_Pos   (5UL)
 
#define ECC_ECC_STATUS_REG_ECC_Point_Px_AtInfinity_Msk   (0x20UL)
 
#define ECC_ECC_STATUS_REG_ECC_Couple_NotValid_Pos   (6UL)
 
#define ECC_ECC_STATUS_REG_ECC_Couple_NotValid_Msk   (0x40UL)
 
#define ECC_ECC_STATUS_REG_ECC_Param_n_NotValid_Pos   (7UL)
 
#define ECC_ECC_STATUS_REG_ECC_Param_n_NotValid_Msk   (0x80UL)
 
#define ECC_ECC_STATUS_REG_ECC_Signature_NotValid_Pos   (9UL)
 
#define ECC_ECC_STATUS_REG_ECC_Signature_NotValid_Msk   (0x200UL)
 
#define ECC_ECC_STATUS_REG_ECC_Param_AB_NotValid_Pos   (10UL)
 
#define ECC_ECC_STATUS_REG_ECC_Param_AB_NotValid_Msk   (0x400UL)
 
#define ECC_ECC_STATUS_REG_ECC_NotInvertible_Pos   (11UL)
 
#define ECC_ECC_STATUS_REG_ECC_NotInvertible_Msk   (0x800UL)
 
#define ECC_ECC_STATUS_REG_ECC_PrimalityTestResult_Pos   (12UL)
 
#define ECC_ECC_STATUS_REG_ECC_PrimalityTestResult_Msk   (0x1000UL)
 
#define ECC_ECC_STATUS_REG_ECC_Busy_Pos   (16UL)
 
#define ECC_ECC_STATUS_REG_ECC_Busy_Msk   (0x10000UL)
 
#define ECC_ECC_VERSION_REG_ECC_SVN_Pos   (0UL)
 
#define ECC_ECC_VERSION_REG_ECC_SVN_Msk   (0xffUL)
 
#define ECC_ECC_VERSION_REG_ECC_HVN_Pos   (8UL)
 
#define ECC_ECC_VERSION_REG_ECC_HVN_Msk   (0xff00UL)
 
#define FTDF_FTDF_TX_FIFO_0_0_REG_TX_FIFO_Pos   (0UL)
 
#define FTDF_FTDF_TX_FIFO_0_0_REG_TX_FIFO_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_TX_FIFO_1_0_REG_TX_FIFO_Pos   (0UL)
 
#define FTDF_FTDF_TX_FIFO_1_0_REG_TX_FIFO_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_TX_FIFO_2_0_REG_TX_FIFO_Pos   (0UL)
 
#define FTDF_FTDF_TX_FIFO_2_0_REG_TX_FIFO_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_TX_FIFO_3_0_REG_TX_FIFO_Pos   (0UL)
 
#define FTDF_FTDF_TX_FIFO_3_0_REG_TX_FIFO_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAME_LENGTH_Pos   (0UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAME_LENGTH_Msk   (0x7fUL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_DEM_PTI_Pos   (7UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_DEM_PTI_Msk   (0x780UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CN_Pos   (11UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CN_Msk   (0x7800UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CALCAP_Pos   (15UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CALCAP_Msk   (0x78000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_RF_GPIO_PINS_Pos   (19UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_RF_GPIO_PINS_Msk   (0x380000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_HSI_Pos   (22UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_HSI_Msk   (0x400000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAMETYPE_Pos   (23UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAMETYPE_Msk   (0x3800000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_CSMACA_ENA_Pos   (26UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_CSMACA_ENA_Msk   (0x4000000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_ACKREQUEST_Pos   (28UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_ACKREQUEST_Msk   (0x10000000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_CRC16_ENA_Pos   (30UL)
 
#define FTDF_FTDF_TX_META_DATA_0_0_REG_CRC16_ENA_Msk   (0x40000000UL)
 
#define FTDF_FTDF_TX_META_DATA_1_0_REG_MACSN_Pos   (0UL)
 
#define FTDF_FTDF_TX_META_DATA_1_0_REG_MACSN_Msk   (0xffUL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAME_LENGTH_Pos   (0UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAME_LENGTH_Msk   (0x7fUL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_DEM_PTI_Pos   (7UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_DEM_PTI_Msk   (0x780UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CN_Pos   (11UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CN_Msk   (0x7800UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CALCAP_Pos   (15UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CALCAP_Msk   (0x78000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_RF_GPIO_PINS_Pos   (19UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_RF_GPIO_PINS_Msk   (0x380000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_HSI_Pos   (22UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_HSI_Msk   (0x400000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAMETYPE_Pos   (23UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAMETYPE_Msk   (0x3800000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_CSMACA_ENA_Pos   (26UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_CSMACA_ENA_Msk   (0x4000000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_ACKREQUEST_Pos   (28UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_ACKREQUEST_Msk   (0x10000000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_CRC16_ENA_Pos   (30UL)
 
#define FTDF_FTDF_TX_META_DATA_0_1_REG_CRC16_ENA_Msk   (0x40000000UL)
 
#define FTDF_FTDF_TX_META_DATA_1_1_REG_MACSN_Pos   (0UL)
 
#define FTDF_FTDF_TX_META_DATA_1_1_REG_MACSN_Msk   (0xffUL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAME_LENGTH_Pos   (0UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAME_LENGTH_Msk   (0x7fUL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_DEM_PTI_Pos   (7UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_DEM_PTI_Msk   (0x780UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CN_Pos   (11UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CN_Msk   (0x7800UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CALCAP_Pos   (15UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CALCAP_Msk   (0x78000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_RF_GPIO_PINS_Pos   (19UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_RF_GPIO_PINS_Msk   (0x380000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_HSI_Pos   (22UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_HSI_Msk   (0x400000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAMETYPE_Pos   (23UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAMETYPE_Msk   (0x3800000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_CSMACA_ENA_Pos   (26UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_CSMACA_ENA_Msk   (0x4000000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_ACKREQUEST_Pos   (28UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_ACKREQUEST_Msk   (0x10000000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_CRC16_ENA_Pos   (30UL)
 
#define FTDF_FTDF_TX_META_DATA_0_2_REG_CRC16_ENA_Msk   (0x40000000UL)
 
#define FTDF_FTDF_TX_META_DATA_1_2_REG_MACSN_Pos   (0UL)
 
#define FTDF_FTDF_TX_META_DATA_1_2_REG_MACSN_Msk   (0xffUL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAME_LENGTH_Pos   (0UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAME_LENGTH_Msk   (0x7fUL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_DEM_PTI_Pos   (7UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_DEM_PTI_Msk   (0x780UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CN_Pos   (11UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CN_Msk   (0x7800UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CALCAP_Pos   (15UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CALCAP_Msk   (0x78000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_RF_GPIO_PINS_Pos   (19UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_RF_GPIO_PINS_Msk   (0x380000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_HSI_Pos   (22UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_HSI_Msk   (0x400000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAMETYPE_Pos   (23UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAMETYPE_Msk   (0x3800000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_CSMACA_ENA_Pos   (26UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_CSMACA_ENA_Msk   (0x4000000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_ACKREQUEST_Pos   (28UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_ACKREQUEST_Msk   (0x10000000UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_CRC16_ENA_Pos   (30UL)
 
#define FTDF_FTDF_TX_META_DATA_0_3_REG_CRC16_ENA_Msk   (0x40000000UL)
 
#define FTDF_FTDF_TX_META_DATA_1_3_REG_MACSN_Pos   (0UL)
 
#define FTDF_FTDF_TX_META_DATA_1_3_REG_MACSN_Msk   (0xffUL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_0_0_REG_TXTIMESTAMP_Pos   (0UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_0_0_REG_TXTIMESTAMP_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_ACKFAIL_Pos   (0UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_ACKFAIL_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACAFAIL_Pos   (1UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACAFAIL_Msk   (0x2UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACANRRETRIES_Pos   (2UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACANRRETRIES_Msk   (0x1cUL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_0_1_REG_TXTIMESTAMP_Pos   (0UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_0_1_REG_TXTIMESTAMP_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_ACKFAIL_Pos   (0UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_ACKFAIL_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACAFAIL_Pos   (1UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACAFAIL_Msk   (0x2UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACANRRETRIES_Pos   (2UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACANRRETRIES_Msk   (0x1cUL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_0_2_REG_TXTIMESTAMP_Pos   (0UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_0_2_REG_TXTIMESTAMP_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_ACKFAIL_Pos   (0UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_ACKFAIL_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACAFAIL_Pos   (1UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACAFAIL_Msk   (0x2UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACANRRETRIES_Pos   (2UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACANRRETRIES_Msk   (0x1cUL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_0_3_REG_TXTIMESTAMP_Pos   (0UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_0_3_REG_TXTIMESTAMP_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_ACKFAIL_Pos   (0UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_ACKFAIL_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACAFAIL_Pos   (1UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACAFAIL_Msk   (0x2UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACANRRETRIES_Pos   (2UL)
 
#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACANRRETRIES_Msk   (0x1cUL)
 
#define FTDF_FTDF_RX_META_0_0_REG_RX_TIMESTAMP_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_0_0_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_META_1_0_REG_CRC16_ERROR_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_CRC16_ERROR_Msk   (0x1UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_DPANID_ERROR_Pos   (4UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_DPANID_ERROR_Msk   (0x10UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_DADDR_ERROR_Pos   (5UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_DADDR_ERROR_Msk   (0x20UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_SPANID_ERROR_Pos   (6UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_SPANID_ERROR_Msk   (0x40UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_ISPANID_COORD_ERROR_Pos   (7UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_QUALITY_INDICATOR_Pos   (8UL)
 
#define FTDF_FTDF_RX_META_1_0_REG_QUALITY_INDICATOR_Msk   (0xff00UL)
 
#define FTDF_FTDF_RX_META_0_1_REG_RX_TIMESTAMP_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_0_1_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_META_1_1_REG_CRC16_ERROR_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_CRC16_ERROR_Msk   (0x1UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_DPANID_ERROR_Pos   (4UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_DPANID_ERROR_Msk   (0x10UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_DADDR_ERROR_Pos   (5UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_DADDR_ERROR_Msk   (0x20UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_SPANID_ERROR_Pos   (6UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_SPANID_ERROR_Msk   (0x40UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_ISPANID_COORD_ERROR_Pos   (7UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_QUALITY_INDICATOR_Pos   (8UL)
 
#define FTDF_FTDF_RX_META_1_1_REG_QUALITY_INDICATOR_Msk   (0xff00UL)
 
#define FTDF_FTDF_RX_META_0_2_REG_RX_TIMESTAMP_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_0_2_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_META_1_2_REG_CRC16_ERROR_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_CRC16_ERROR_Msk   (0x1UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_DPANID_ERROR_Pos   (4UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_DPANID_ERROR_Msk   (0x10UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_DADDR_ERROR_Pos   (5UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_DADDR_ERROR_Msk   (0x20UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_SPANID_ERROR_Pos   (6UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_SPANID_ERROR_Msk   (0x40UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_ISPANID_COORD_ERROR_Pos   (7UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_QUALITY_INDICATOR_Pos   (8UL)
 
#define FTDF_FTDF_RX_META_1_2_REG_QUALITY_INDICATOR_Msk   (0xff00UL)
 
#define FTDF_FTDF_RX_META_0_3_REG_RX_TIMESTAMP_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_0_3_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_META_1_3_REG_CRC16_ERROR_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_CRC16_ERROR_Msk   (0x1UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_DPANID_ERROR_Pos   (4UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_DPANID_ERROR_Msk   (0x10UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_DADDR_ERROR_Pos   (5UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_DADDR_ERROR_Msk   (0x20UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_SPANID_ERROR_Pos   (6UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_SPANID_ERROR_Msk   (0x40UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_ISPANID_COORD_ERROR_Pos   (7UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_QUALITY_INDICATOR_Pos   (8UL)
 
#define FTDF_FTDF_RX_META_1_3_REG_QUALITY_INDICATOR_Msk   (0xff00UL)
 
#define FTDF_FTDF_RX_META_0_4_REG_RX_TIMESTAMP_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_0_4_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_META_1_4_REG_CRC16_ERROR_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_CRC16_ERROR_Msk   (0x1UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_DPANID_ERROR_Pos   (4UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_DPANID_ERROR_Msk   (0x10UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_DADDR_ERROR_Pos   (5UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_DADDR_ERROR_Msk   (0x20UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_SPANID_ERROR_Pos   (6UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_SPANID_ERROR_Msk   (0x40UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_ISPANID_COORD_ERROR_Pos   (7UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_QUALITY_INDICATOR_Pos   (8UL)
 
#define FTDF_FTDF_RX_META_1_4_REG_QUALITY_INDICATOR_Msk   (0xff00UL)
 
#define FTDF_FTDF_RX_META_0_5_REG_RX_TIMESTAMP_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_0_5_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_META_1_5_REG_CRC16_ERROR_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_CRC16_ERROR_Msk   (0x1UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_DPANID_ERROR_Pos   (4UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_DPANID_ERROR_Msk   (0x10UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_DADDR_ERROR_Pos   (5UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_DADDR_ERROR_Msk   (0x20UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_SPANID_ERROR_Pos   (6UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_SPANID_ERROR_Msk   (0x40UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_ISPANID_COORD_ERROR_Pos   (7UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_QUALITY_INDICATOR_Pos   (8UL)
 
#define FTDF_FTDF_RX_META_1_5_REG_QUALITY_INDICATOR_Msk   (0xff00UL)
 
#define FTDF_FTDF_RX_META_0_6_REG_RX_TIMESTAMP_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_0_6_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_META_1_6_REG_CRC16_ERROR_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_CRC16_ERROR_Msk   (0x1UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_DPANID_ERROR_Pos   (4UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_DPANID_ERROR_Msk   (0x10UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_DADDR_ERROR_Pos   (5UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_DADDR_ERROR_Msk   (0x20UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_SPANID_ERROR_Pos   (6UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_SPANID_ERROR_Msk   (0x40UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_ISPANID_COORD_ERROR_Pos   (7UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_QUALITY_INDICATOR_Pos   (8UL)
 
#define FTDF_FTDF_RX_META_1_6_REG_QUALITY_INDICATOR_Msk   (0xff00UL)
 
#define FTDF_FTDF_RX_META_0_7_REG_RX_TIMESTAMP_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_0_7_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_META_1_7_REG_CRC16_ERROR_Pos   (0UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_CRC16_ERROR_Msk   (0x1UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_DPANID_ERROR_Pos   (4UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_DPANID_ERROR_Msk   (0x10UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_DADDR_ERROR_Pos   (5UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_DADDR_ERROR_Msk   (0x20UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_SPANID_ERROR_Pos   (6UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_SPANID_ERROR_Msk   (0x40UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_ISPANID_COORD_ERROR_Pos   (7UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_QUALITY_INDICATOR_Pos   (8UL)
 
#define FTDF_FTDF_RX_META_1_7_REG_QUALITY_INDICATOR_Msk   (0xff00UL)
 
#define FTDF_FTDF_RX_FIFO_0_0_REG_RX_FIFO_Pos   (0UL)
 
#define FTDF_FTDF_RX_FIFO_0_0_REG_RX_FIFO_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_FIFO_1_0_REG_RX_FIFO_Pos   (0UL)
 
#define FTDF_FTDF_RX_FIFO_1_0_REG_RX_FIFO_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_FIFO_2_0_REG_RX_FIFO_Pos   (0UL)
 
#define FTDF_FTDF_RX_FIFO_2_0_REG_RX_FIFO_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_FIFO_3_0_REG_RX_FIFO_Pos   (0UL)
 
#define FTDF_FTDF_RX_FIFO_3_0_REG_RX_FIFO_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_FIFO_4_0_REG_RX_FIFO_Pos   (0UL)
 
#define FTDF_FTDF_RX_FIFO_4_0_REG_RX_FIFO_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_FIFO_5_0_REG_RX_FIFO_Pos   (0UL)
 
#define FTDF_FTDF_RX_FIFO_5_0_REG_RX_FIFO_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_FIFO_6_0_REG_RX_FIFO_Pos   (0UL)
 
#define FTDF_FTDF_RX_FIFO_6_0_REG_RX_FIFO_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_FIFO_7_0_REG_RX_FIFO_Pos   (0UL)
 
#define FTDF_FTDF_RX_FIFO_7_0_REG_RX_FIFO_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_REL_NAME_0_REG_REL_NAME_Pos   (0UL)
 
#define FTDF_FTDF_REL_NAME_0_REG_REL_NAME_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_REL_NAME_1_REG_REL_NAME_Pos   (0UL)
 
#define FTDF_FTDF_REL_NAME_1_REG_REL_NAME_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_REL_NAME_2_REG_REL_NAME_Pos   (0UL)
 
#define FTDF_FTDF_REL_NAME_2_REG_REL_NAME_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_REL_NAME_3_REG_REL_NAME_Pos   (0UL)
 
#define FTDF_FTDF_REL_NAME_3_REG_REL_NAME_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_BUILDTIME_0_REG_BUILDTIME_Pos   (0UL)
 
#define FTDF_FTDF_BUILDTIME_0_REG_BUILDTIME_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_BUILDTIME_1_REG_BUILDTIME_Pos   (0UL)
 
#define FTDF_FTDF_BUILDTIME_1_REG_BUILDTIME_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_BUILDTIME_2_REG_BUILDTIME_Pos   (0UL)
 
#define FTDF_FTDF_BUILDTIME_2_REG_BUILDTIME_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_BUILDTIME_3_REG_BUILDTIME_Pos   (0UL)
 
#define FTDF_FTDF_BUILDTIME_3_REG_BUILDTIME_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_GLOB_CONTROL_0_REG_ISPANCOORDINATOR_Pos   (1UL)
 
#define FTDF_FTDF_GLOB_CONTROL_0_REG_ISPANCOORDINATOR_Msk   (0x2UL)
 
#define FTDF_FTDF_GLOB_CONTROL_0_REG_RX_DMA_REQ_Pos   (2UL)
 
#define FTDF_FTDF_GLOB_CONTROL_0_REG_RX_DMA_REQ_Msk   (0x4UL)
 
#define FTDF_FTDF_GLOB_CONTROL_0_REG_TX_DMA_REQ_Pos   (3UL)
 
#define FTDF_FTDF_GLOB_CONTROL_0_REG_TX_DMA_REQ_Msk   (0x8UL)
 
#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACSIMPLEADDRESS_Pos   (8UL)
 
#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACSIMPLEADDRESS_Msk   (0xff00UL)
 
#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACLEENABLED_Pos   (17UL)
 
#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACLEENABLED_Msk   (0x20000UL)
 
#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACTSCHENABLED_Pos   (18UL)
 
#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACTSCHENABLED_Msk   (0x40000UL)
 
#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACPANID_Pos   (0UL)
 
#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACPANID_Msk   (0xffffUL)
 
#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACSHORTADDRESS_Pos   (16UL)
 
#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACSHORTADDRESS_Msk   (0xffff0000UL)
 
#define FTDF_FTDF_GLOB_CONTROL_2_REG_AEXTENDEDADDRESS_L_Pos   (0UL)
 
#define FTDF_FTDF_GLOB_CONTROL_2_REG_AEXTENDEDADDRESS_L_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_GLOB_CONTROL_3_REG_AEXTENDEDADDRESS_H_Pos   (0UL)
 
#define FTDF_FTDF_GLOB_CONTROL_3_REG_AEXTENDEDADDRESS_H_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXONDURATION_Pos   (1UL)
 
#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXONDURATION_Msk   (0x1fffffeUL)
 
#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXALWAYSON_Pos   (25UL)
 
#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXALWAYSON_Msk   (0x2000000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_RX_Pos   (27UL)
 
#define FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_RX_Msk   (0x78000000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_0_REG_KEEP_PHY_EN_Pos   (31UL)
 
#define FTDF_FTDF_LMAC_CONTROL_0_REG_KEEP_PHY_EN_Msk   (0x80000000UL)
 
#define FTDF_FTDF_TXPIPEPROPDELAY_REG_TXPIPEPROPDELAY_Pos   (0UL)
 
#define FTDF_FTDF_TXPIPEPROPDELAY_REG_TXPIPEPROPDELAY_Msk   (0xffUL)
 
#define FTDF_FTDF_MACACKWAITDURATION_REG_MACACKWAITDURATION_Pos   (0UL)
 
#define FTDF_FTDF_MACACKWAITDURATION_REG_MACACKWAITDURATION_Msk   (0xffUL)
 
#define FTDF_FTDF_MACENHACKWAITDURATION_REG_MACENHACKWAITDURATION_Pos   (0UL)
 
#define FTDF_FTDF_MACENHACKWAITDURATION_REG_MACENHACKWAITDURATION_Msk   (0xffffUL)
 
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_DEM_PTI_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_DEM_PTI_Msk   (0xfUL)
 
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CN_Pos   (4UL)
 
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CN_Msk   (0xf0UL)
 
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CALCAP_Pos   (8UL)
 
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CALCAP_Msk   (0xf00UL)
 
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_RF_GPIO_PINS_Pos   (12UL)
 
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_RF_GPIO_PINS_Msk   (0x7000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_HSI_Pos   (15UL)
 
#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_HSI_Msk   (0x8000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANENABLE_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANENABLE_Msk   (0x1UL)
 
#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANDURATION_Pos   (8UL)
 
#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANDURATION_Msk   (0xffffff00UL)
 
#define FTDF_FTDF_LMAC_CONTROL_3_REG_MACMAXFRAMETOTALWAITTIME_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_CONTROL_3_REG_MACMAXFRAMETOTALWAITTIME_Msk   (0xffffUL)
 
#define FTDF_FTDF_LMAC_CONTROL_3_REG_CCAIDLEWAIT_Pos   (16UL)
 
#define FTDF_FTDF_LMAC_CONTROL_3_REG_CCAIDLEWAIT_Msk   (0xff0000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_3_REG_ADDR_TAB_MATCH_FP_VALUE_Pos   (24UL)
 
#define FTDF_FTDF_LMAC_CONTROL_3_REG_ADDR_TAB_MATCH_FP_VALUE_Msk   (0x1000000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_OVERRIDE_Pos   (25UL)
 
#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_OVERRIDE_Msk   (0x2000000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_FORCE_VALUE_Pos   (26UL)
 
#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_FORCE_VALUE_Msk   (0x4000000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_3_REG_FTDF_LPDP_ENABLE_Pos   (27UL)
 
#define FTDF_FTDF_LMAC_CONTROL_3_REG_FTDF_LPDP_ENABLE_Msk   (0x8000000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_GETGENERATORVAL_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_GETGENERATORVAL_Msk   (0x1UL)
 
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_RXENABLE_Pos   (1UL)
 
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_RXENABLE_Msk   (0x2UL)
 
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_SINGLECCA_Pos   (2UL)
 
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_SINGLECCA_Msk   (0x4UL)
 
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_SET_Pos   (3UL)
 
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_SET_Msk   (0x8UL)
 
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_CLEAR_Pos   (4UL)
 
#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_CLEAR_Msk   (0x10UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_LMACREADY4SLEEP_Pos   (1UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_LMACREADY4SLEEP_Msk   (0x2UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CCASTAT_Pos   (2UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CCASTAT_Msk   (0x4UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_WAKEUPTIMERENABLESTATUS_Pos   (6UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_WAKEUPTIMERENABLESTATUS_Msk   (0x40UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_EDSCANVALUE_Pos   (8UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_EDSCANVALUE_Msk   (0xff00UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_NB_STAT_Pos   (16UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_NB_STAT_Msk   (0x70000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_RESUME_STAT_Pos   (19UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_RESUME_STAT_Msk   (0x80000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_BO_STAT_Pos   (24UL)
 
#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_BO_STAT_Msk   (0xff000000UL)
 
#define FTDF_FTDF_EVENTCURRVAL_REG_EVENTCURRVAL_Pos   (0UL)
 
#define FTDF_FTDF_EVENTCURRVAL_REG_EVENTCURRVAL_Msk   (0x1ffffffUL)
 
#define FTDF_FTDF_TIMESTAMPCURRVAL_REG_TIMESTAMPCURRVAL_Pos   (0UL)
 
#define FTDF_FTDF_TIMESTAMPCURRVAL_REG_TIMESTAMPCURRVAL_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYSLEEPWAIT_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYSLEEPWAIT_Msk   (0xffUL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_RXPIPEPROPDELAY_Pos   (8UL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_RXPIPEPROPDELAY_Msk   (0xff00UL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_DEM_PTI_Pos   (16UL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_DEM_PTI_Msk   (0xf0000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CN_Pos   (20UL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CN_Msk   (0xf00000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CALCAP_Pos   (24UL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CALCAP_Msk   (0xf000000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_RF_GPIO_PINS_Pos   (28UL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_RF_GPIO_PINS_Msk   (0x70000000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_HSI_Pos   (31UL)
 
#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_HSI_Msk   (0x80000000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_ACK_RESPONSE_DELAY_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_ACK_RESPONSE_DELAY_Msk   (0xffUL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_CCASTATWAIT_Pos   (8UL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_CCASTATWAIT_Msk   (0xf00UL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_DEM_PTI_Pos   (16UL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_DEM_PTI_Msk   (0xf0000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CN_Pos   (20UL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CN_Msk   (0xf00000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CALCAP_Pos   (24UL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CALCAP_Msk   (0xf000000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_RF_GPIO_PINS_Pos   (28UL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_RF_GPIO_PINS_Msk   (0x70000000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_HSI_Pos   (31UL)
 
#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_HSI_Msk   (0x80000000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_6_REG_LIFSPERIOD_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_CONTROL_6_REG_LIFSPERIOD_Msk   (0xffUL)
 
#define FTDF_FTDF_LMAC_CONTROL_6_REG_SIFSPERIOD_Pos   (8UL)
 
#define FTDF_FTDF_LMAC_CONTROL_6_REG_SIFSPERIOD_Msk   (0xff00UL)
 
#define FTDF_FTDF_LMAC_CONTROL_6_REG_WUIFSPERIOD_Pos   (16UL)
 
#define FTDF_FTDF_LMAC_CONTROL_6_REG_WUIFSPERIOD_Msk   (0xff0000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACRXTOTALCYCLETIME_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACRXTOTALCYCLETIME_Msk   (0xffffUL)
 
#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACDISCARXOFFTORZ_Pos   (16UL)
 
#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACDISCARXOFFTORZ_Msk   (0x10000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_NB_VAL_Pos   (17UL)
 
#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_NB_VAL_Msk   (0xe0000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_BO_THRESHOLD_Pos   (24UL)
 
#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_BO_THRESHOLD_Msk   (0xff000000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_LMACREADY4SLEEP_D_Pos   (1UL)
 
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_LMACREADY4SLEEP_D_Msk   (0x2UL)
 
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYNCTIMESTAMP_E_Pos   (2UL)
 
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYNCTIMESTAMP_E_Msk   (0x4UL)
 
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIMETHR_E_Pos   (3UL)
 
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIMETHR_E_Msk   (0x8UL)
 
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIME2THR_E_Pos   (4UL)
 
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIME2THR_E_Msk   (0x10UL)
 
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_GETGENERATORVAL_E_Pos   (5UL)
 
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_GETGENERATORVAL_E_Msk   (0x20UL)
 
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_WAKEUPTIMERENABLESTATUS_D_Pos   (6UL)
 
#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_WAKEUPTIMERENABLESTATUS_D_Msk   (0x40UL)
 
#define FTDF_FTDF_TIMESTAMPCURRPHASEVAL_REG_TIMESTAMPCURRPHASEVAL_Pos   (0UL)
 
#define FTDF_FTDF_TIMESTAMPCURRPHASEVAL_REG_TIMESTAMPCURRPHASEVAL_Msk   (0xffUL)
 
#define FTDF_FTDF_MACTSTXACKDELAYVAL_REG_MACTSTXACKDELAYVAL_Pos   (0UL)
 
#define FTDF_FTDF_MACTSTXACKDELAYVAL_REG_MACTSTXACKDELAYVAL_Msk   (0xffffUL)
 
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_LMACREADY4SLEEP_M_Pos   (1UL)
 
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_LMACREADY4SLEEP_M_Msk   (0x2UL)
 
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYNCTIMESTAMP_M_Pos   (2UL)
 
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYNCTIMESTAMP_M_Msk   (0x4UL)
 
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIMETHR_M_Pos   (3UL)
 
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIMETHR_M_Msk   (0x8UL)
 
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIME2THR_M_Pos   (4UL)
 
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIME2THR_M_Msk   (0x10UL)
 
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_GETGENERATORVAL_M_Pos   (5UL)
 
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_GETGENERATORVAL_M_Msk   (0x20UL)
 
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_WAKEUPTIMERENABLESTATUS_M_Pos   (6UL)
 
#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_WAKEUPTIMERENABLESTATUS_M_Msk   (0x40UL)
 
#define FTDF_FTDF_LMAC_EVENT_REG_EDSCANREADY_E_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_EVENT_REG_EDSCANREADY_E_Msk   (0x1UL)
 
#define FTDF_FTDF_LMAC_EVENT_REG_CCASTAT_E_Pos   (1UL)
 
#define FTDF_FTDF_LMAC_EVENT_REG_CCASTAT_E_Msk   (0x2UL)
 
#define FTDF_FTDF_LMAC_EVENT_REG_RXTIMEREXPIRED_E_Pos   (2UL)
 
#define FTDF_FTDF_LMAC_EVENT_REG_RXTIMEREXPIRED_E_Msk   (0x4UL)
 
#define FTDF_FTDF_LMAC_EVENT_REG_CSMA_CA_BO_THR_E_Pos   (3UL)
 
#define FTDF_FTDF_LMAC_EVENT_REG_CSMA_CA_BO_THR_E_Msk   (0x8UL)
 
#define FTDF_FTDF_LMAC_MASK_REG_EDSCANREADY_M_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_MASK_REG_EDSCANREADY_M_Msk   (0x1UL)
 
#define FTDF_FTDF_LMAC_MASK_REG_CCASTAT_M_Pos   (1UL)
 
#define FTDF_FTDF_LMAC_MASK_REG_CCASTAT_M_Msk   (0x2UL)
 
#define FTDF_FTDF_LMAC_MASK_REG_RXTIMEREXPIRED_M_Pos   (2UL)
 
#define FTDF_FTDF_LMAC_MASK_REG_RXTIMEREXPIRED_M_Msk   (0x4UL)
 
#define FTDF_FTDF_LMAC_MASK_REG_CSMA_CA_BO_THR_M_Pos   (3UL)
 
#define FTDF_FTDF_LMAC_MASK_REG_CSMA_CA_BO_THR_M_Msk   (0x8UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_MODE_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_MODE_Msk   (0x1UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_EN_Pos   (1UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_EN_Msk   (0x2UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_EN_Pos   (2UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_EN_Msk   (0x4UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_EN_Pos   (3UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_EN_Msk   (0x8UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_PIPE_EN_Pos   (4UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_PIPE_EN_Msk   (0x10UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_ED_REQUEST_Pos   (5UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_ED_REQUEST_Msk   (0x20UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_FRM_NR_Pos   (6UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_FRM_NR_Msk   (0xc0UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PTI_Pos   (8UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PTI_Msk   (0xf00UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_DEM_PTI_Pos   (16UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_DEM_PTI_Msk   (0xf0000UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CN_Pos   (20UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CN_Msk   (0xf00000UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CALCAP_Pos   (24UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CALCAP_Msk   (0xf000000UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS_Pos   (28UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS_Msk   (0x70000000UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_HSI_Pos   (31UL)
 
#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_HSI_Msk   (0x80000000UL)
 
#define FTDF_FTDF_LMAC_MANUAL_OS_REG_LMAC_MANUAL_TX_START_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_MANUAL_OS_REG_LMAC_MANUAL_TX_START_Msk   (0x1UL)
 
#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_CCA_STAT_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_CCA_STAT_Msk   (0x1UL)
 
#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_ED_STAT_Pos   (8UL)
 
#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_ED_STAT_Msk   (0xff00UL)
 
#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACWUPERIOD_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACWUPERIOD_Msk   (0xffffUL)
 
#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACCSLSAMPLEPERIOD_Pos   (16UL)
 
#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACCSLSAMPLEPERIOD_Msk   (0xffff0000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_8_REG_MACCSLSTARTSAMPLETIME_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_CONTROL_8_REG_MACCSLSTARTSAMPLETIME_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLDATAPERIOD_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLDATAPERIOD_Msk   (0xffffUL)
 
#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLFRAMEPENDINGWAITT_Pos   (16UL)
 
#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLFRAMEPENDINGWAITT_Msk   (0xffff0000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACWURZCORRECTION_Pos   (0UL)
 
#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACWURZCORRECTION_Msk   (0xffUL)
 
#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACCSLMARGINRZ_Pos   (16UL)
 
#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACCSLMARGINRZ_Msk   (0xf0000UL)
 
#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACRZZEROVAL_Pos   (28UL)
 
#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACRZZEROVAL_Msk   (0xf0000000UL)
 
#define FTDF_FTDF_SECURITY_0_REG_SECTXRXN_Pos   (1UL)
 
#define FTDF_FTDF_SECURITY_0_REG_SECTXRXN_Msk   (0x2UL)
 
#define FTDF_FTDF_SECURITY_0_REG_SECENTRY_Pos   (8UL)
 
#define FTDF_FTDF_SECURITY_0_REG_SECENTRY_Msk   (0xf00UL)
 
#define FTDF_FTDF_SECURITY_0_REG_SECALENGTH_Pos   (16UL)
 
#define FTDF_FTDF_SECURITY_0_REG_SECALENGTH_Msk   (0x7f0000UL)
 
#define FTDF_FTDF_SECURITY_0_REG_SECMLENGTH_Pos   (24UL)
 
#define FTDF_FTDF_SECURITY_0_REG_SECMLENGTH_Msk   (0x7f000000UL)
 
#define FTDF_FTDF_SECURITY_0_REG_SECENCDECN_Pos   (31UL)
 
#define FTDF_FTDF_SECURITY_0_REG_SECENCDECN_Msk   (0x80000000UL)
 
#define FTDF_FTDF_SECURITY_1_REG_SECAUTHFLAGS_Pos   (0UL)
 
#define FTDF_FTDF_SECURITY_1_REG_SECAUTHFLAGS_Msk   (0xffUL)
 
#define FTDF_FTDF_SECURITY_1_REG_SECENCRFLAGS_Pos   (8UL)
 
#define FTDF_FTDF_SECURITY_1_REG_SECENCRFLAGS_Msk   (0xff00UL)
 
#define FTDF_FTDF_SECKEY_0_REG_SECKEY_0_Pos   (0UL)
 
#define FTDF_FTDF_SECKEY_0_REG_SECKEY_0_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_SECKEY_1_REG_SECKEY_1_Pos   (0UL)
 
#define FTDF_FTDF_SECKEY_1_REG_SECKEY_1_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_SECKEY_2_REG_SECKEY_2_Pos   (0UL)
 
#define FTDF_FTDF_SECKEY_2_REG_SECKEY_2_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_SECKEY_3_REG_SECKEY_3_Pos   (0UL)
 
#define FTDF_FTDF_SECKEY_3_REG_SECKEY_3_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_SECNONCE_0_REG_SECNONCE_0_Pos   (0UL)
 
#define FTDF_FTDF_SECNONCE_0_REG_SECNONCE_0_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_SECNONCE_1_REG_SECNONCE_1_Pos   (0UL)
 
#define FTDF_FTDF_SECNONCE_1_REG_SECNONCE_1_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_SECNONCE_2_REG_SECNONCE_2_Pos   (0UL)
 
#define FTDF_FTDF_SECNONCE_2_REG_SECNONCE_2_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_SECNONCE_3_REG_SECNONCE_3_Pos   (0UL)
 
#define FTDF_FTDF_SECNONCE_3_REG_SECNONCE_3_Msk   (0xffUL)
 
#define FTDF_FTDF_SECURITY_OS_REG_SECABORT_Pos   (0UL)
 
#define FTDF_FTDF_SECURITY_OS_REG_SECABORT_Msk   (0x1UL)
 
#define FTDF_FTDF_SECURITY_OS_REG_SECSTART_Pos   (1UL)
 
#define FTDF_FTDF_SECURITY_OS_REG_SECSTART_Msk   (0x2UL)
 
#define FTDF_FTDF_SECURITY_STATUS_REG_SECBUSY_Pos   (0UL)
 
#define FTDF_FTDF_SECURITY_STATUS_REG_SECBUSY_Msk   (0x1UL)
 
#define FTDF_FTDF_SECURITY_STATUS_REG_SECAUTHFAIL_Pos   (1UL)
 
#define FTDF_FTDF_SECURITY_STATUS_REG_SECAUTHFAIL_Msk   (0x2UL)
 
#define FTDF_FTDF_SECURITY_EVENT_REG_SECREADY_E_Pos   (0UL)
 
#define FTDF_FTDF_SECURITY_EVENT_REG_SECREADY_E_Msk   (0x1UL)
 
#define FTDF_FTDF_SECURITY_EVENTMASK_REG_SECREADY_M_Pos   (0UL)
 
#define FTDF_FTDF_SECURITY_EVENTMASK_REG_SECREADY_M_Msk   (0x1UL)
 
#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSTXACKDELAY_Pos   (0UL)
 
#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSTXACKDELAY_Msk   (0xffffUL)
 
#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSRXWAIT_Pos   (16UL)
 
#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSRXWAIT_Msk   (0xffff0000UL)
 
#define FTDF_FTDF_TSCH_CONTROL_1_REG_MACTSRXTX_Pos   (0UL)
 
#define FTDF_FTDF_TSCH_CONTROL_1_REG_MACTSRXTX_Msk   (0xffffUL)
 
#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSRXACKDELAY_Pos   (0UL)
 
#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSRXACKDELAY_Msk   (0xffffUL)
 
#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSACKWAIT_Pos   (16UL)
 
#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSACKWAIT_Msk   (0xffff0000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_0_Pos   (0UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_0_Msk   (0x7UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_1_Pos   (4UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_1_Msk   (0x70UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_2_Pos   (8UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_2_Msk   (0x700UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_3_Pos   (12UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_3_Msk   (0x7000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_4_Pos   (16UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_4_Msk   (0x70000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_5_Pos   (20UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_5_Msk   (0x700000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_6_Pos   (24UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_6_Msk   (0x7000000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_7_Pos   (28UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_7_Msk   (0x70000000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_0_Pos   (0UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_0_Msk   (0x7UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_1_Pos   (4UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_1_Msk   (0x70UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_2_Pos   (8UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_2_Msk   (0x700UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_3_Pos   (12UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_3_Msk   (0x7000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_4_Pos   (16UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_4_Msk   (0x70000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_5_Pos   (20UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_5_Msk   (0x700000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_6_Pos   (24UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_6_Msk   (0x7000000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_7_Pos   (28UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_7_Msk   (0x70000000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXSTARTUP_Pos   (0UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXSTARTUP_Msk   (0xffUL)
 
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXLATENCY_Pos   (8UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXLATENCY_Msk   (0xff00UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXFINISH_Pos   (16UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXFINISH_Msk   (0xff0000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTRXWAIT_Pos   (24UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTRXWAIT_Msk   (0xff000000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXSTARTUP_Pos   (0UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXSTARTUP_Msk   (0xffUL)
 
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXLATENCY_Pos   (8UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXLATENCY_Msk   (0xff00UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYENABLE_Pos   (16UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYENABLE_Msk   (0xff0000UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_USE_LEGACY_PHY_EN_Pos   (24UL)
 
#define FTDF_FTDF_PHY_PARAMETERS_3_REG_USE_LEGACY_PHY_EN_Msk   (0x1000000UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_DBGRXTRANSPARENTMODE_Pos   (0UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_DBGRXTRANSPARENTMODE_Msk   (0x1UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_RXBEACONONLY_Pos   (1UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_RXBEACONONLY_Msk   (0x2UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_RXCOORDREALIGNONLY_Pos   (2UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_RXCOORDREALIGNONLY_Msk   (0x4UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_RX_READ_BUF_PTR_Pos   (3UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_RX_READ_BUF_PTR_Msk   (0x78UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXFRMPENDINGCA_Pos   (7UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXFRMPENDINGCA_Msk   (0x80UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKREQUESTCA_Pos   (8UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKREQUESTCA_Msk   (0x100UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSCRCERROR_Pos   (9UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSCRCERROR_Msk   (0x200UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_DISDATAREQUESTCA_Pos   (10UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_DISDATAREQUESTCA_Msk   (0x400UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSRESFRAMEVERSION_Pos   (11UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSRESFRAMEVERSION_Msk   (0x800UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDPANID_Pos   (12UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDPANID_Msk   (0x1000UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDADDR_Pos   (13UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDADDR_Msk   (0x2000UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSBEACONWRONGPANID_Pos   (14UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSBEACONWRONGPANID_Msk   (0x4000UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSTOPANCOORDINATOR_Pos   (15UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSTOPANCOORDINATOR_Msk   (0x8000UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSFRMTYPE_Pos   (16UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSFRMTYPE_Msk   (0xff0000UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWAKEUP_Pos   (24UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWAKEUP_Msk   (0x1000000UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACPASSWAKEUP_Pos   (25UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACPASSWAKEUP_Msk   (0x2000000UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACIMPLICITBROADCAST_Pos   (26UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_MACIMPLICITBROADCAST_Msk   (0x4000000UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKRECEIVEDCA_Pos   (27UL)
 
#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKRECEIVEDCA_Msk   (0x8000000UL)
 
#define FTDF_FTDF_RX_EVENT_REG_RXSOF_E_Pos   (0UL)
 
#define FTDF_FTDF_RX_EVENT_REG_RXSOF_E_Msk   (0x1UL)
 
#define FTDF_FTDF_RX_EVENT_REG_RX_OVERFLOW_E_Pos   (1UL)
 
#define FTDF_FTDF_RX_EVENT_REG_RX_OVERFLOW_E_Msk   (0x2UL)
 
#define FTDF_FTDF_RX_EVENT_REG_RX_BUF_AVAIL_E_Pos   (2UL)
 
#define FTDF_FTDF_RX_EVENT_REG_RX_BUF_AVAIL_E_Msk   (0x4UL)
 
#define FTDF_FTDF_RX_EVENT_REG_RXBYTE_E_Pos   (3UL)
 
#define FTDF_FTDF_RX_EVENT_REG_RXBYTE_E_Msk   (0x8UL)
 
#define FTDF_FTDF_RX_MASK_REG_RXSOF_M_Pos   (0UL)
 
#define FTDF_FTDF_RX_MASK_REG_RXSOF_M_Msk   (0x1UL)
 
#define FTDF_FTDF_RX_MASK_REG_RX_OVERFLOW_M_Pos   (1UL)
 
#define FTDF_FTDF_RX_MASK_REG_RX_OVERFLOW_M_Msk   (0x2UL)
 
#define FTDF_FTDF_RX_MASK_REG_RX_BUF_AVAIL_M_Pos   (2UL)
 
#define FTDF_FTDF_RX_MASK_REG_RX_BUF_AVAIL_M_Msk   (0x4UL)
 
#define FTDF_FTDF_RX_MASK_REG_RXBYTE_M_Pos   (3UL)
 
#define FTDF_FTDF_RX_MASK_REG_RXBYTE_M_Msk   (0x8UL)
 
#define FTDF_FTDF_RX_STATUS_REG_RX_BUFF_IS_FULL_Pos   (0UL)
 
#define FTDF_FTDF_RX_STATUS_REG_RX_BUFF_IS_FULL_Msk   (0x1UL)
 
#define FTDF_FTDF_RX_STATUS_REG_RX_WRITE_BUF_PTR_Pos   (1UL)
 
#define FTDF_FTDF_RX_STATUS_REG_RX_WRITE_BUF_PTR_Msk   (0x1eUL)
 
#define FTDF_FTDF_SYMBOLTIMESNAPSHOTVAL_REG_SYMBOLTIMESNAPSHOTVAL_Pos   (0UL)
 
#define FTDF_FTDF_SYMBOLTIMESNAPSHOTVAL_REG_SYMBOLTIMESNAPSHOTVAL_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_RX_STATUS_DELTA_REG_RX_BUFF_IS_FULL_D_Pos   (0UL)
 
#define FTDF_FTDF_RX_STATUS_DELTA_REG_RX_BUFF_IS_FULL_D_Msk   (0x1UL)
 
#define FTDF_FTDF_RX_STATUS_MASK_REG_RX_BUFF_IS_FULL_M_Pos   (0UL)
 
#define FTDF_FTDF_RX_STATUS_MASK_REG_RX_BUFF_IS_FULL_M_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_CONTROL_0_REG_DBGTXTRANSPARENTMODE_Pos   (0UL)
 
#define FTDF_FTDF_TX_CONTROL_0_REG_DBGTXTRANSPARENTMODE_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXBE_Pos   (4UL)
 
#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXBE_Msk   (0xf0UL)
 
#define FTDF_FTDF_TX_CONTROL_0_REG_MACMINBE_Pos   (8UL)
 
#define FTDF_FTDF_TX_CONTROL_0_REG_MACMINBE_Msk   (0xf00UL)
 
#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXCSMABACKOFFS_Pos   (12UL)
 
#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXCSMABACKOFFS_Msk   (0x7000UL)
 
#define FTDF_FTDF_FTDF_CE_REG_FTDF_CE_Pos   (0UL)
 
#define FTDF_FTDF_FTDF_CE_REG_FTDF_CE_Msk   (0x3fUL)
 
#define FTDF_FTDF_FTDF_CM_REG_FTDF_CM_Pos   (0UL)
 
#define FTDF_FTDF_FTDF_CM_REG_FTDF_CM_Msk   (0x3fUL)
 
#define FTDF_FTDF_SYNCTIMESTAMPTHR_REG_SYNCTIMESTAMPTHR_Pos   (0UL)
 
#define FTDF_FTDF_SYNCTIMESTAMPTHR_REG_SYNCTIMESTAMPTHR_Msk   (0x1ffffffUL)
 
#define FTDF_FTDF_SYNCTIMESTAMPVAL_REG_SYNCTIMESTAMPVAL_Pos   (0UL)
 
#define FTDF_FTDF_SYNCTIMESTAMPVAL_REG_SYNCTIMESTAMPVAL_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_TIMER_CONTROL_1_REG_SYNCTIMESTAMPENA_Pos   (1UL)
 
#define FTDF_FTDF_TIMER_CONTROL_1_REG_SYNCTIMESTAMPENA_Msk   (0x2UL)
 
#define FTDF_FTDF_MACTXSTDACKFRMCNT_REG_MACTXSTDACKFRMCNT_Pos   (0UL)
 
#define FTDF_FTDF_MACTXSTDACKFRMCNT_REG_MACTXSTDACKFRMCNT_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_MACRXSTDACKFRMOKCNT_REG_MACRXSTDACKFRMOKCNT_Pos   (0UL)
 
#define FTDF_FTDF_MACRXSTDACKFRMOKCNT_REG_MACRXSTDACKFRMOKCNT_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_MACRXADDRFAILFRMCNT_REG_MACRXADDRFAILFRMCNT_Pos   (0UL)
 
#define FTDF_FTDF_MACRXADDRFAILFRMCNT_REG_MACRXADDRFAILFRMCNT_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_MACRXUNSUPFRMCNT_REG_MACRXUNSUPFRMCNT_Pos   (0UL)
 
#define FTDF_FTDF_MACRXUNSUPFRMCNT_REG_MACRXUNSUPFRMCNT_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_SYNCTIMESTAMPPHASEVAL_REG_SYNCTIMESTAMPPHASEVAL_Pos   (0UL)
 
#define FTDF_FTDF_SYNCTIMESTAMPPHASEVAL_REG_SYNCTIMESTAMPPHASEVAL_Msk   (0xffUL)
 
#define FTDF_FTDF_MACFCSERRORCOUNT_REG_MACFCSERRORCOUNT_Pos   (0UL)
 
#define FTDF_FTDF_MACFCSERRORCOUNT_REG_MACFCSERRORCOUNT_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_CONTROL_Pos   (0UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_CONTROL_Msk   (0x1UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_RX_Pos   (1UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_RX_Msk   (0x2UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TX_Pos   (2UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TX_Msk   (0x4UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_AHB_Pos   (3UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_AHB_Msk   (0x8UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_OREG_Pos   (4UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_OREG_Msk   (0x10UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TSTIM_Pos   (6UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TSTIM_Msk   (0x40UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_SEC_Pos   (7UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_SEC_Msk   (0x80UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_COUNT_Pos   (9UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_COUNT_Msk   (0x200UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TIMCTRL_Pos   (10UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TIMCTRL_Msk   (0x400UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACGLOBRESET_COUNT_Pos   (16UL)
 
#define FTDF_FTDF_LMACRESET_REG_LMACGLOBRESET_COUNT_Msk   (0x10000UL)
 
#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_SET_Pos   (0UL)
 
#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_SET_Msk   (0x1UL)
 
#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_CLEAR_Pos   (1UL)
 
#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_CLEAR_Msk   (0x2UL)
 
#define FTDF_FTDF_SYMBOLTIMETHR_REG_SYMBOLTIMETHR_Pos   (0UL)
 
#define FTDF_FTDF_SYMBOLTIMETHR_REG_SYMBOLTIMETHR_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_SYMBOLTIME2THR_REG_SYMBOLTIME2THR_Pos   (0UL)
 
#define FTDF_FTDF_SYMBOLTIME2THR_REG_SYMBOLTIME2THR_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_DEBUGCONTROL_REG_DBG_RX_INPUT_Pos   (8UL)
 
#define FTDF_FTDF_DEBUGCONTROL_REG_DBG_RX_INPUT_Msk   (0x100UL)
 
#define FTDF_FTDF_TXBYTE_E_REG_TXBYTE_E_Pos   (0UL)
 
#define FTDF_FTDF_TXBYTE_E_REG_TXBYTE_E_Msk   (0x1UL)
 
#define FTDF_FTDF_TXBYTE_E_REG_TX_LAST_SYMBOL_E_Pos   (1UL)
 
#define FTDF_FTDF_TXBYTE_E_REG_TX_LAST_SYMBOL_E_Msk   (0x2UL)
 
#define FTDF_FTDF_TXBYTE_M_REG_TXBYTE_M_Pos   (0UL)
 
#define FTDF_FTDF_TXBYTE_M_REG_TXBYTE_M_Msk   (0x1UL)
 
#define FTDF_FTDF_TXBYTE_M_REG_TX_LAST_SYMBOL_M_Pos   (1UL)
 
#define FTDF_FTDF_TXBYTE_M_REG_TX_LAST_SYMBOL_M_Msk   (0x2UL)
 
#define FTDF_FTDF_TX_FLAG_S_0_REG_TX_FLAG_STAT_Pos   (0UL)
 
#define FTDF_FTDF_TX_FLAG_S_0_REG_TX_FLAG_STAT_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_E_0_REG_TX_FLAG_CLEAR_E_Pos   (0UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_E_0_REG_TX_FLAG_CLEAR_E_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_M_0_REG_TX_FLAG_CLEAR_M_Pos   (0UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_M_0_REG_TX_FLAG_CLEAR_M_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_PRIORITY_0_REG_TX_PRIORITY_Pos   (0UL)
 
#define FTDF_FTDF_TX_PRIORITY_0_REG_TX_PRIORITY_Msk   (0xfUL)
 
#define FTDF_FTDF_TX_PRIORITY_0_REG_ISWAKEUP_Pos   (4UL)
 
#define FTDF_FTDF_TX_PRIORITY_0_REG_ISWAKEUP_Msk   (0x10UL)
 
#define FTDF_FTDF_TX_PRIORITY_0_REG_PTI_TX_Pos   (8UL)
 
#define FTDF_FTDF_TX_PRIORITY_0_REG_PTI_TX_Msk   (0xf00UL)
 
#define FTDF_FTDF_TX_FLAG_S_1_REG_TX_FLAG_STAT_Pos   (0UL)
 
#define FTDF_FTDF_TX_FLAG_S_1_REG_TX_FLAG_STAT_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_E_1_REG_TX_FLAG_CLEAR_E_Pos   (0UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_E_1_REG_TX_FLAG_CLEAR_E_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_M_1_REG_TX_FLAG_CLEAR_M_Pos   (0UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_M_1_REG_TX_FLAG_CLEAR_M_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_PRIORITY_1_REG_TX_PRIORITY_Pos   (0UL)
 
#define FTDF_FTDF_TX_PRIORITY_1_REG_TX_PRIORITY_Msk   (0xfUL)
 
#define FTDF_FTDF_TX_PRIORITY_1_REG_ISWAKEUP_Pos   (4UL)
 
#define FTDF_FTDF_TX_PRIORITY_1_REG_ISWAKEUP_Msk   (0x10UL)
 
#define FTDF_FTDF_TX_PRIORITY_1_REG_PTI_TX_Pos   (8UL)
 
#define FTDF_FTDF_TX_PRIORITY_1_REG_PTI_TX_Msk   (0xf00UL)
 
#define FTDF_FTDF_TX_FLAG_S_2_REG_TX_FLAG_STAT_Pos   (0UL)
 
#define FTDF_FTDF_TX_FLAG_S_2_REG_TX_FLAG_STAT_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_E_2_REG_TX_FLAG_CLEAR_E_Pos   (0UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_E_2_REG_TX_FLAG_CLEAR_E_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_M_2_REG_TX_FLAG_CLEAR_M_Pos   (0UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_M_2_REG_TX_FLAG_CLEAR_M_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_PRIORITY_2_REG_TX_PRIORITY_Pos   (0UL)
 
#define FTDF_FTDF_TX_PRIORITY_2_REG_TX_PRIORITY_Msk   (0xfUL)
 
#define FTDF_FTDF_TX_PRIORITY_2_REG_ISWAKEUP_Pos   (4UL)
 
#define FTDF_FTDF_TX_PRIORITY_2_REG_ISWAKEUP_Msk   (0x10UL)
 
#define FTDF_FTDF_TX_PRIORITY_2_REG_PTI_TX_Pos   (8UL)
 
#define FTDF_FTDF_TX_PRIORITY_2_REG_PTI_TX_Msk   (0xf00UL)
 
#define FTDF_FTDF_TX_FLAG_S_3_REG_TX_FLAG_STAT_Pos   (0UL)
 
#define FTDF_FTDF_TX_FLAG_S_3_REG_TX_FLAG_STAT_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_E_3_REG_TX_FLAG_CLEAR_E_Pos   (0UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_E_3_REG_TX_FLAG_CLEAR_E_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_M_3_REG_TX_FLAG_CLEAR_M_Pos   (0UL)
 
#define FTDF_FTDF_TX_FLAG_CLEAR_M_3_REG_TX_FLAG_CLEAR_M_Msk   (0x1UL)
 
#define FTDF_FTDF_TX_PRIORITY_3_REG_TX_PRIORITY_Pos   (0UL)
 
#define FTDF_FTDF_TX_PRIORITY_3_REG_TX_PRIORITY_Msk   (0xfUL)
 
#define FTDF_FTDF_TX_PRIORITY_3_REG_ISWAKEUP_Pos   (4UL)
 
#define FTDF_FTDF_TX_PRIORITY_3_REG_ISWAKEUP_Msk   (0x10UL)
 
#define FTDF_FTDF_TX_PRIORITY_3_REG_PTI_TX_Pos   (8UL)
 
#define FTDF_FTDF_TX_PRIORITY_3_REG_PTI_TX_Msk   (0xf00UL)
 
#define FTDF_FTDF_TX_SET_OS_REG_TX_FLAG_SET_Pos   (0UL)
 
#define FTDF_FTDF_TX_SET_OS_REG_TX_FLAG_SET_Msk   (0xfUL)
 
#define FTDF_FTDF_TX_CLEAR_OS_REG_TX_FLAG_CLEAR_Pos   (0UL)
 
#define FTDF_FTDF_TX_CLEAR_OS_REG_TX_FLAG_CLEAR_Msk   (0xfUL)
 
#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPINTTHR_Pos   (0UL)
 
#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPINTTHR_Msk   (0x1ffffffUL)
 
#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Pos   (29UL)
 
#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Msk   (0x20000000UL)
 
#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUP_MODE_Pos   (30UL)
 
#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUP_MODE_Msk   (0xc0000000UL)
 
#define FTDF_FTDF_LONG_ADDR_0_0_REG_EXP_SA_L_Pos   (0UL)
 
#define FTDF_FTDF_LONG_ADDR_0_0_REG_EXP_SA_L_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_LONG_ADDR_1_0_REG_EXP_SA_H_Pos   (0UL)
 
#define FTDF_FTDF_LONG_ADDR_1_0_REG_EXP_SA_H_Msk   (0xffffffffUL)
 
#define FTDF_FTDF_SIZE_AND_VAL_0_REG_VALID_SA_Pos   (0UL)
 
#define FTDF_FTDF_SIZE_AND_VAL_0_REG_VALID_SA_Msk   (0xfUL)
 
#define FTDF_FTDF_SIZE_AND_VAL_0_REG_SHORT_LONGNOT_Pos   (4UL)
 
#define FTDF_FTDF_SIZE_AND_VAL_0_REG_SHORT_LONGNOT_Msk   (0x10UL)
 
#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CTRL_Pos   (0UL)
 
#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CTRL_Msk   (0x1UL)
 
#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_SEL_Pos   (1UL)
 
#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_SEL_Msk   (0x2UL)
 
#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_DIV_Pos   (2UL)
 
#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_DIV_Msk   (0x4UL)
 
#define GP_TIMERS_TIMER0_CTRL_REG_PWM_MODE_Pos   (3UL)
 
#define GP_TIMERS_TIMER0_CTRL_REG_PWM_MODE_Msk   (0x8UL)
 
#define GP_TIMERS_TIMER0_ON_REG_TIM0_ON_Pos   (0UL)
 
#define GP_TIMERS_TIMER0_ON_REG_TIM0_ON_Msk   (0xffffUL)
 
#define GP_TIMERS_TIMER0_RELOAD_M_REG_TIM0_M_Pos   (0UL)
 
#define GP_TIMERS_TIMER0_RELOAD_M_REG_TIM0_M_Msk   (0xffffUL)
 
#define GP_TIMERS_TIMER0_RELOAD_N_REG_TIM0_N_Pos   (0UL)
 
#define GP_TIMERS_TIMER0_RELOAD_N_REG_TIM0_N_Msk   (0xffffUL)
 
#define GP_TIMERS_PWM2_START_CYCLE_START_CYCLE_Pos   (0UL)
 
#define GP_TIMERS_PWM2_START_CYCLE_START_CYCLE_Msk   (0x3fffUL)
 
#define GP_TIMERS_PWM3_START_CYCLE_START_CYCLE_Pos   (0UL)
 
#define GP_TIMERS_PWM3_START_CYCLE_START_CYCLE_Msk   (0x3fffUL)
 
#define GP_TIMERS_PWM4_START_CYCLE_START_CYCLE_Pos   (0UL)
 
#define GP_TIMERS_PWM4_START_CYCLE_START_CYCLE_Msk   (0x3fffUL)
 
#define GP_TIMERS_PWM2_END_CYCLE_END_CYCLE_Pos   (0UL)
 
#define GP_TIMERS_PWM2_END_CYCLE_END_CYCLE_Msk   (0x3fffUL)
 
#define GP_TIMERS_PWM3_END_CYCLE_END_CYCLE_Pos   (0UL)
 
#define GP_TIMERS_PWM3_END_CYCLE_END_CYCLE_Msk   (0x3fffUL)
 
#define GP_TIMERS_PWM4_END_CYCLE_END_CYCLE_Pos   (0UL)
 
#define GP_TIMERS_PWM4_END_CYCLE_END_CYCLE_Msk   (0x3fffUL)
 
#define GP_TIMERS_TRIPLE_PWM_FREQUENCY_FREQ_Pos   (0UL)
 
#define GP_TIMERS_TRIPLE_PWM_FREQUENCY_FREQ_Msk   (0x3fffUL)
 
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_ENABLE_Pos   (0UL)
 
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_ENABLE_Msk   (0x1UL)
 
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_SW_PAUSE_EN_Pos   (1UL)
 
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_SW_PAUSE_EN_Msk   (0x2UL)
 
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_HW_PAUSE_EN_Pos   (2UL)
 
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_HW_PAUSE_EN_Msk   (0x4UL)
 
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_CLK_SEL_Pos   (3UL)
 
#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_CLK_SEL_Msk   (0x8UL)
 
#define GP_TIMERS_BREATH_CFG_REG_BRTH_DIV_Pos   (0UL)
 
#define GP_TIMERS_BREATH_CFG_REG_BRTH_DIV_Msk   (0xffUL)
 
#define GP_TIMERS_BREATH_CFG_REG_BRTH_STEP_Pos   (8UL)
 
#define GP_TIMERS_BREATH_CFG_REG_BRTH_STEP_Msk   (0xff00UL)
 
#define GP_TIMERS_BREATH_DUTY_MAX_REG_BRTH_DUTY_MAX_Pos   (0UL)
 
#define GP_TIMERS_BREATH_DUTY_MAX_REG_BRTH_DUTY_MAX_Msk   (0xffUL)
 
#define GP_TIMERS_BREATH_DUTY_MIN_REG_BRTH_DUTY_MIN_Pos   (0UL)
 
#define GP_TIMERS_BREATH_DUTY_MIN_REG_BRTH_DUTY_MIN_Msk   (0xffUL)
 
#define GP_TIMERS_BREATH_CTRL_REG_BRTH_EN_Pos   (0UL)
 
#define GP_TIMERS_BREATH_CTRL_REG_BRTH_EN_Msk   (0x1UL)
 
#define GP_TIMERS_BREATH_CTRL_REG_BRTH_PWM_POL_Pos   (1UL)
 
#define GP_TIMERS_BREATH_CTRL_REG_BRTH_PWM_POL_Msk   (0x2UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Pos   (0UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Msk   (0x1UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Pos   (1UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Msk   (0x2UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Pos   (2UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Msk   (0x4UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Pos   (3UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Msk   (0x8UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Pos   (4UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Msk   (0x10UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Pos   (5UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Msk   (0x20UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Pos   (6UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Msk   (0x40UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Pos   (7UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Msk   (0x80UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Pos   (8UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Msk   (0x1f00UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Pos   (13UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Msk   (0x2000UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Pos   (14UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Msk   (0x4000UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Pos   (15UL)
 
#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Msk   (0x8000UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Pos   (0UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Msk   (0x1UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Pos   (1UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Msk   (0x2UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Pos   (2UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Msk   (0x4UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Pos   (3UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Msk   (0x8UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Pos   (5UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Msk   (0xe0UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Pos   (8UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Msk   (0xf00UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Pos   (12UL)
 
#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Msk   (0xf000UL)
 
#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Pos   (0UL)
 
#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Msk   (0xffUL)
 
#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Pos   (8UL)
 
#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Msk   (0xff00UL)
 
#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Pos   (0UL)
 
#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Msk   (0x3ffUL)
 
#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Pos   (0UL)
 
#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Msk   (0x3ffUL)
 
#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Pos   (0UL)
 
#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Msk   (0xffffUL)
 
#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Pos   (0UL)
 
#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Msk   (0xffffUL)
 
#define GPIO_P0_DATA_REG_P0_DATA_Pos   (0UL)
 
#define GPIO_P0_DATA_REG_P0_DATA_Msk   (0xffUL)
 
#define GPIO_P1_DATA_REG_P1_DATA_Pos   (0UL)
 
#define GPIO_P1_DATA_REG_P1_DATA_Msk   (0xffUL)
 
#define GPIO_P2_DATA_REG_P2_DATA_Pos   (0UL)
 
#define GPIO_P2_DATA_REG_P2_DATA_Msk   (0x1fUL)
 
#define GPIO_P3_DATA_REG_P3_DATA_Pos   (0UL)
 
#define GPIO_P3_DATA_REG_P3_DATA_Msk   (0xffUL)
 
#define GPIO_P4_DATA_REG_P4_DATA_Pos   (0UL)
 
#define GPIO_P4_DATA_REG_P4_DATA_Msk   (0xffUL)
 
#define GPIO_P0_SET_DATA_REG_P0_SET_Pos   (0UL)
 
#define GPIO_P0_SET_DATA_REG_P0_SET_Msk   (0xffUL)
 
#define GPIO_P1_SET_DATA_REG_P1_SET_Pos   (0UL)
 
#define GPIO_P1_SET_DATA_REG_P1_SET_Msk   (0xffUL)
 
#define GPIO_P2_SET_DATA_REG_P2_SET_Pos   (0UL)
 
#define GPIO_P2_SET_DATA_REG_P2_SET_Msk   (0x1fUL)
 
#define GPIO_P3_SET_DATA_REG_P3_SET_Pos   (0UL)
 
#define GPIO_P3_SET_DATA_REG_P3_SET_Msk   (0xffUL)
 
#define GPIO_P4_SET_DATA_REG_P4_SET_Pos   (0UL)
 
#define GPIO_P4_SET_DATA_REG_P4_SET_Msk   (0xffUL)
 
#define GPIO_P0_RESET_DATA_REG_P0_RESET_Pos   (0UL)
 
#define GPIO_P0_RESET_DATA_REG_P0_RESET_Msk   (0xffUL)
 
#define GPIO_P1_RESET_DATA_REG_P1_RESET_Pos   (0UL)
 
#define GPIO_P1_RESET_DATA_REG_P1_RESET_Msk   (0xffUL)
 
#define GPIO_P2_RESET_DATA_REG_P2_RESET_Pos   (0UL)
 
#define GPIO_P2_RESET_DATA_REG_P2_RESET_Msk   (0x1fUL)
 
#define GPIO_P3_RESET_DATA_REG_P3_RESET_Pos   (0UL)
 
#define GPIO_P3_RESET_DATA_REG_P3_RESET_Msk   (0xffUL)
 
#define GPIO_P4_RESET_DATA_REG_P4_RESET_Pos   (0UL)
 
#define GPIO_P4_RESET_DATA_REG_P4_RESET_Msk   (0xffUL)
 
#define GPIO_P00_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P00_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P00_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P00_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P00_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P00_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P01_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P01_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P01_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P01_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P01_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P01_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P02_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P02_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P02_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P02_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P02_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P02_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P03_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P03_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P03_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P03_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P03_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P03_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P04_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P04_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P04_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P04_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P04_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P04_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P05_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P05_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P05_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P05_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P05_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P05_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P06_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P06_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P06_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P06_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P06_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P06_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P07_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P07_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P07_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P07_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P07_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P07_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P10_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P10_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P10_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P10_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P10_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P10_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P11_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P11_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P11_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P11_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P11_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P11_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P12_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P12_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P12_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P12_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P12_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P12_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P13_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P13_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P13_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P13_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P13_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P13_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P14_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P14_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P14_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P14_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P14_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P14_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P15_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P15_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P15_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P15_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P15_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P15_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P16_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P16_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P16_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P16_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P16_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P16_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P17_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P17_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P17_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P17_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P17_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P17_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P20_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P20_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P20_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P20_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P20_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P20_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P21_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P21_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P21_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P21_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P21_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P21_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P22_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P22_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P22_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P22_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P22_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P22_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P23_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P23_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P23_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P23_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P23_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P23_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P24_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P24_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P24_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P24_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P24_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P24_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P30_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P30_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P30_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P30_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P30_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P30_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P31_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P31_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P31_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P31_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P31_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P31_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P32_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P32_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P32_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P32_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P32_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P32_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P33_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P33_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P33_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P33_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P33_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P33_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P34_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P34_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P34_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P34_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P34_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P34_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P35_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P35_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P35_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P35_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P35_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P35_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P36_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P36_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P36_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P36_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P36_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P36_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P37_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P37_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P37_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P37_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P37_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P37_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P40_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P40_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P40_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P40_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P40_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P40_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P41_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P41_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P41_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P41_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P41_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P41_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P42_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P42_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P42_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P42_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P42_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P42_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P43_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P43_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P43_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P43_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P43_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P43_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P44_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P44_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P44_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P44_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P44_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P44_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P45_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P45_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P45_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P45_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P45_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P45_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P46_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P46_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P46_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P46_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P46_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P46_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P47_MODE_REG_PID_Pos   (0UL)
 
#define GPIO_P47_MODE_REG_PID_Msk   (0x3fUL)
 
#define GPIO_P47_MODE_REG_PUPD_Pos   (8UL)
 
#define GPIO_P47_MODE_REG_PUPD_Msk   (0x300UL)
 
#define GPIO_P47_MODE_REG_PPOD_Pos   (10UL)
 
#define GPIO_P47_MODE_REG_PPOD_Msk   (0x400UL)
 
#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Pos   (6UL)
 
#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Msk   (0xc0UL)
 
#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Pos   (0UL)
 
#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Msk   (0xffUL)
 
#define GPIO_P2_PADPWR_CTRL_REG_P2_OUT_CTRL_Pos   (0UL)
 
#define GPIO_P2_PADPWR_CTRL_REG_P2_OUT_CTRL_Msk   (0x1fUL)
 
#define GPIO_P3_PADPWR_CTRL_REG_P3_OUT_CTRL_Pos   (0UL)
 
#define GPIO_P3_PADPWR_CTRL_REG_P3_OUT_CTRL_Msk   (0xffUL)
 
#define GPIO_P4_PADPWR_CTRL_REG_P4_OUT_CTRL_Pos   (0UL)
 
#define GPIO_P4_PADPWR_CTRL_REG_P4_OUT_CTRL_Msk   (0xffUL)
 
#define GPIO_GPIO_CLK_SEL_FUNC_CLOCK_SEL_Pos   (0UL)
 
#define GPIO_GPIO_CLK_SEL_FUNC_CLOCK_SEL_Msk   (0x7UL)
 
#define GPIO_BIST_CTRL_REG_RAM_BIST_CONFIG_Pos   (0UL)
 
#define GPIO_BIST_CTRL_REG_RAM_BIST_CONFIG_Msk   (0x3UL)
 
#define GPIO_BIST_CTRL_REG_RAM_BIST_PATTERN_Pos   (2UL)
 
#define GPIO_BIST_CTRL_REG_RAM_BIST_PATTERN_Msk   (0xcUL)
 
#define GPIO_BIST_CTRL_REG_ROMBIST_ENABLE_Pos   (4UL)
 
#define GPIO_BIST_CTRL_REG_ROMBIST_ENABLE_Msk   (0x10UL)
 
#define GPIO_BIST_CTRL_REG_RAMBIST_ENABLE_Pos   (5UL)
 
#define GPIO_BIST_CTRL_REG_RAMBIST_ENABLE_Msk   (0x20UL)
 
#define GPIO_BIST_CTRL_REG_SYSRAMBIST_ENABLE_Pos   (6UL)
 
#define GPIO_BIST_CTRL_REG_SYSRAMBIST_ENABLE_Msk   (0x40UL)
 
#define GPIO_BIST_CTRL_REG_SHOW_BIST_Pos   (7UL)
 
#define GPIO_BIST_CTRL_REG_SHOW_BIST_Msk   (0x80UL)
 
#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_LINE_FAIL_Pos   (0UL)
 
#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_LINE_FAIL_Msk   (0x1UL)
 
#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_FAIL_Pos   (1UL)
 
#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_FAIL_Msk   (0x2UL)
 
#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_BUSY_Pos   (2UL)
 
#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_BUSY_Msk   (0x4UL)
 
#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_LINE_FAIL_Pos   (3UL)
 
#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_LINE_FAIL_Msk   (0x8UL)
 
#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_FAIL_Pos   (4UL)
 
#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_FAIL_Msk   (0x10UL)
 
#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_BUSY_Pos   (5UL)
 
#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_BUSY_Msk   (0x20UL)
 
#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_LINE_FAIL_Pos   (6UL)
 
#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_LINE_FAIL_Msk   (0x40UL)
 
#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_FAIL_Pos   (7UL)
 
#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_FAIL_Msk   (0x80UL)
 
#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_BUSY_Pos   (8UL)
 
#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_BUSY_Msk   (0x100UL)
 
#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_LINE_FAIL_Pos   (9UL)
 
#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_LINE_FAIL_Msk   (0x200UL)
 
#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_FAIL_Pos   (10UL)
 
#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_FAIL_Msk   (0x400UL)
 
#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_BUSY_Pos   (11UL)
 
#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_BUSY_Msk   (0x800UL)
 
#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_LINE_FAIL_Pos   (12UL)
 
#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_LINE_FAIL_Msk   (0x1000UL)
 
#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_FAIL_Pos   (13UL)
 
#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_FAIL_Msk   (0x2000UL)
 
#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_BUSY_Pos   (14UL)
 
#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_BUSY_Msk   (0x4000UL)
 
#define GPIO_RAMBIST_STATUS1_REG_ROM_BIST_BUSY_Pos   (15UL)
 
#define GPIO_RAMBIST_STATUS1_REG_ROM_BIST_BUSY_Msk   (0x8000UL)
 
#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_LINE_FAIL_Pos   (0UL)
 
#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_LINE_FAIL_Msk   (0x1UL)
 
#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_FAIL_Pos   (1UL)
 
#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_FAIL_Msk   (0x2UL)
 
#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_BUSY_Pos   (2UL)
 
#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_BUSY_Msk   (0x4UL)
 
#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_LINE_FAIL_Pos   (3UL)
 
#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_LINE_FAIL_Msk   (0x8UL)
 
#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_FAIL_Pos   (4UL)
 
#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_FAIL_Msk   (0x10UL)
 
#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_BUSY_Pos   (5UL)
 
#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_BUSY_Msk   (0x20UL)
 
#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_LINE_FAIL_Pos   (6UL)
 
#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_LINE_FAIL_Msk   (0x40UL)
 
#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_FAIL_Pos   (7UL)
 
#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_FAIL_Msk   (0x80UL)
 
#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_BUSY_Pos   (8UL)
 
#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_BUSY_Msk   (0x100UL)
 
#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_LINE_FAIL_Pos   (9UL)
 
#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_LINE_FAIL_Msk   (0x200UL)
 
#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_FAIL_Pos   (10UL)
 
#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_FAIL_Msk   (0x400UL)
 
#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_BUSY_Pos   (11UL)
 
#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_BUSY_Msk   (0x800UL)
 
#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_LINE_FAIL_Pos   (12UL)
 
#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_LINE_FAIL_Msk   (0x1000UL)
 
#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_FAIL_Pos   (13UL)
 
#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_FAIL_Msk   (0x2000UL)
 
#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_BUSY_Pos   (14UL)
 
#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_BUSY_Msk   (0x4000UL)
 
#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_LINE_FAIL_Pos   (0UL)
 
#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_LINE_FAIL_Msk   (0x1UL)
 
#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_FAIL_Pos   (1UL)
 
#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_FAIL_Msk   (0x2UL)
 
#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_BUSY_Pos   (2UL)
 
#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_BUSY_Msk   (0x4UL)
 
#define GPIO_ROMBIST_RESULTL_REG_ROMBIST_RESULTL_Pos   (0UL)
 
#define GPIO_ROMBIST_RESULTL_REG_ROMBIST_RESULTL_Msk   (0xffffUL)
 
#define GPIO_ROMBIST_RESULTH_REG_ROMBIST_RESULTH_Pos   (0UL)
 
#define GPIO_ROMBIST_RESULTH_REG_ROMBIST_RESULTH_Msk   (0xffffUL)
 
#define GPIO_TEST_CTRL_REG_SHOW_CLOCKS_Pos   (0UL)
 
#define GPIO_TEST_CTRL_REG_SHOW_CLOCKS_Msk   (0x1UL)
 
#define GPIO_TEST_CTRL_REG_ENABLE_RFPT_Pos   (1UL)
 
#define GPIO_TEST_CTRL_REG_ENABLE_RFPT_Msk   (0x2UL)
 
#define GPIO_TEST_CTRL_REG_SHOW_PLL_TEST_OUT_Pos   (2UL)
 
#define GPIO_TEST_CTRL_REG_SHOW_PLL_TEST_OUT_Msk   (0x4UL)
 
#define GPIO_TEST_CTRL_REG_SHOW_DCDC_TESTBUS_Pos   (3UL)
 
#define GPIO_TEST_CTRL_REG_SHOW_DCDC_TESTBUS_Msk   (0x8UL)
 
#define GPIO_TEST_CTRL_REG_XTAL16M_CAP_TEST_EN_Pos   (4UL)
 
#define GPIO_TEST_CTRL_REG_XTAL16M_CAP_TEST_EN_Msk   (0x10UL)
 
#define GPIO_TEST_CTRL_REG_SHOW_IF_RO_Pos   (5UL)
 
#define GPIO_TEST_CTRL_REG_SHOW_IF_RO_Msk   (0x20UL)
 
#define GPIO_TEST_CTRL_REG_PLL_TST_MODE_Pos   (6UL)
 
#define GPIO_TEST_CTRL_REG_PLL_TST_MODE_Msk   (0x40UL)
 
#define GPIO_TEST_CTRL_REG_SHOW_TXDAC_MOD_Pos   (7UL)
 
#define GPIO_TEST_CTRL_REG_SHOW_TXDAC_MOD_Msk   (0x80UL)
 
#define GPIO_TEST_CTRL_REG_SHOW_PWR_TST_OUT_Pos   (8UL)
 
#define GPIO_TEST_CTRL_REG_SHOW_PWR_TST_OUT_Msk   (0x700UL)
 
#define GPIO_TEST_CTRL_REG_XTAL16M_TST_SYS_Pos   (12UL)
 
#define GPIO_TEST_CTRL_REG_XTAL16M_TST_SYS_Msk   (0x3000UL)
 
#define GPIO_TEST_CTRL_REG_XTAL16M_TRIM_TEST_EN_Pos   (14UL)
 
#define GPIO_TEST_CTRL_REG_XTAL16M_TRIM_TEST_EN_Msk   (0x4000UL)
 
#define GPIO_TEST_CTRL2_REG_ANA_TESTMUX_CTRL_Pos   (0UL)
 
#define GPIO_TEST_CTRL2_REG_ANA_TESTMUX_CTRL_Msk   (0xfUL)
 
#define GPIO_TEST_CTRL2_REG_RF_IN_TESTMUX_CTRL_Pos   (8UL)
 
#define GPIO_TEST_CTRL2_REG_RF_IN_TESTMUX_CTRL_Msk   (0x300UL)
 
#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_SEL_Pos   (0UL)
 
#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_SEL_Msk   (0x3fUL)
 
#define GPIO_TEST_CTRL3_REG_VBUS_COMPARATOR_TEST_Pos   (6UL)
 
#define GPIO_TEST_CTRL3_REG_VBUS_COMPARATOR_TEST_Msk   (0x40UL)
 
#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_PARAM_Pos   (8UL)
 
#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_PARAM_Msk   (0xff00UL)
 
#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_SEL_Pos   (0UL)
 
#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_SEL_Msk   (0x7UL)
 
#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_PARAM_Pos   (8UL)
 
#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_PARAM_Msk   (0xff00UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_BUS_TO_AVS_Pos   (0UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_BUS_TO_AVS_Msk   (0x1UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V4_Pos   (1UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V4_Msk   (0x2UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_FLASH_Pos   (2UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_FLASH_Msk   (0x4UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_LDO_CORE_Pos   (3UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_LDO_CORE_Msk   (0x8UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_PA_Pos   (4UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_PA_Msk   (0x10UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_LDO_ADC_Pos   (5UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_LDO_ADC_Msk   (0x20UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_LDO_PLL_Pos   (6UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_LDO_PLL_Msk   (0x40UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_BANDGAP_I_TEST_Pos   (7UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_BANDGAP_I_TEST_Msk   (0x80UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_SIMO_BUCK_Pos   (8UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_SIMO_BUCK_Msk   (0x100UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_OUT_Pos   (9UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_OUT_Msk   (0x200UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_IN_Pos   (10UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_IN_Msk   (0x400UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_I_DCDC_FILT_Pos   (11UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_I_DCDC_FILT_Msk   (0x800UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_VCONT_A_Pos   (12UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_VCONT_A_Msk   (0x1000UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_VREF_1V2_A_Pos   (13UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_VREF_1V2_A_Msk   (0x2000UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_POR_VBAT_NOK_AVD_Pos   (14UL)
 
#define GPIO_TEST_CTRL5_REG_TEST_POR_VBAT_NOK_AVD_Msk   (0x4000UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Pos   (0UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Msk   (0x1UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_SWTIM0_Pos   (1UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_SWTIM0_Msk   (0x2UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_BLETIM_Pos   (2UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_BLETIM_Msk   (0x4UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_WDOG_Pos   (3UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk   (0x8UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_USB_Pos   (4UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_USB_Msk   (0x10UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_DMA_Pos   (5UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_DMA_Msk   (0x20UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Pos   (6UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Msk   (0x40UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Pos   (7UL)
 
#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk   (0x80UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Pos   (0UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk   (0x1UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM0_Pos   (1UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM0_Msk   (0x2UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_BLETIM_Pos   (2UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_BLETIM_Msk   (0x4UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_WDOG_Pos   (3UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_WDOG_Msk   (0x8UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_USB_Pos   (4UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_USB_Msk   (0x10UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Pos   (5UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Msk   (0x20UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM1_Pos   (6UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM1_Msk   (0x40UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Pos   (7UL)
 
#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Msk   (0x80UL)
 
#define GPREG_DEBUG_REG_DEBUGS_FREEZE_EN_Pos   (0UL)
 
#define GPREG_DEBUG_REG_DEBUGS_FREEZE_EN_Msk   (0x1UL)
 
#define GPREG_GP_STATUS_REG_CAL_PHASE_Pos   (0UL)
 
#define GPREG_GP_STATUS_REG_CAL_PHASE_Msk   (0x1UL)
 
#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_REQ_Pos   (0UL)
 
#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_REQ_Msk   (0x1UL)
 
#define GPREG_GP_CONTROL_REG_BLE_H2H_BRIDGE_BYPASS_Pos   (1UL)
 
#define GPREG_GP_CONTROL_REG_BLE_H2H_BRIDGE_BYPASS_Msk   (0x2UL)
 
#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_LP_IRQ_Pos   (2UL)
 
#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_LP_IRQ_Msk   (0x4UL)
 
#define GPREG_ECC_BASE_ADDR_REG_ECC_BASE_ADDR_Pos   (0UL)
 
#define GPREG_ECC_BASE_ADDR_REG_ECC_BASE_ADDR_Msk   (0x7fUL)
 
#define GPREG_LED_CONTROL_REG_LED1_SRC_SEL_Pos   (0UL)
 
#define GPREG_LED_CONTROL_REG_LED1_SRC_SEL_Msk   (0x1UL)
 
#define GPREG_LED_CONTROL_REG_LED2_SRC_SEL_Pos   (1UL)
 
#define GPREG_LED_CONTROL_REG_LED2_SRC_SEL_Msk   (0x2UL)
 
#define GPREG_LED_CONTROL_REG_LED3_SRC_SEL_Pos   (2UL)
 
#define GPREG_LED_CONTROL_REG_LED3_SRC_SEL_Msk   (0x4UL)
 
#define GPREG_LED_CONTROL_REG_LED1_EN_Pos   (3UL)
 
#define GPREG_LED_CONTROL_REG_LED1_EN_Msk   (0x8UL)
 
#define GPREG_LED_CONTROL_REG_LED2_EN_Pos   (4UL)
 
#define GPREG_LED_CONTROL_REG_LED2_EN_Msk   (0x10UL)
 
#define GPREG_LED_CONTROL_REG_LED3_EN_Pos   (5UL)
 
#define GPREG_LED_CONTROL_REG_LED3_EN_Msk   (0x20UL)
 
#define GPREG_LED_CONTROL_REG_LED_TRIM_Pos   (6UL)
 
#define GPREG_LED_CONTROL_REG_LED_TRIM_Msk   (0x3c0UL)
 
#define GPREG_BLE_FINECNT_SAMP_REG_BLE_FINECNT_SAMP_Pos   (0UL)
 
#define GPREG_BLE_FINECNT_SAMP_REG_BLE_FINECNT_SAMP_Msk   (0x3ffUL)
 
#define GPREG_PLL_SYS_CTRL1_REG_PLL_EN_Pos   (0UL)
 
#define GPREG_PLL_SYS_CTRL1_REG_PLL_EN_Msk   (0x1UL)
 
#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Pos   (1UL)
 
#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Msk   (0x2UL)
 
#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Pos   (2UL)
 
#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Msk   (0x4UL)
 
#define GPREG_PLL_SYS_CTRL1_REG_PLL_R_DIV_Pos   (8UL)
 
#define GPREG_PLL_SYS_CTRL1_REG_PLL_R_DIV_Msk   (0x7f00UL)
 
#define GPREG_PLL_SYS_CTRL2_REG_PLL_N_DIV_Pos   (0UL)
 
#define GPREG_PLL_SYS_CTRL2_REG_PLL_N_DIV_Msk   (0x7fUL)
 
#define GPREG_PLL_SYS_CTRL2_REG_PLL_DEL_SEL_Pos   (12UL)
 
#define GPREG_PLL_SYS_CTRL2_REG_PLL_DEL_SEL_Msk   (0x3000UL)
 
#define GPREG_PLL_SYS_CTRL2_REG_PLL_SEL_MIN_CUR_INT_Pos   (14UL)
 
#define GPREG_PLL_SYS_CTRL2_REG_PLL_SEL_MIN_CUR_INT_Msk   (0x4000UL)
 
#define GPREG_PLL_SYS_CTRL3_REG_PLL_ICP_SEL_Pos   (0UL)
 
#define GPREG_PLL_SYS_CTRL3_REG_PLL_ICP_SEL_Msk   (0x1fUL)
 
#define GPREG_PLL_SYS_CTRL3_REG_PLL_START_DEL_Pos   (10UL)
 
#define GPREG_PLL_SYS_CTRL3_REG_PLL_START_DEL_Msk   (0x7c00UL)
 
#define GPREG_PLL_SYS_CTRL3_REG_PLL_RECALIB_Pos   (15UL)
 
#define GPREG_PLL_SYS_CTRL3_REG_PLL_RECALIB_Msk   (0x8000UL)
 
#define GPREG_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Pos   (0UL)
 
#define GPREG_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Msk   (0x1UL)
 
#define GPREG_PLL_SYS_STATUS_REG_LDO_PLL_OK_Pos   (1UL)
 
#define GPREG_PLL_SYS_STATUS_REG_LDO_PLL_OK_Msk   (0x2UL)
 
#define GPREG_PLL_SYS_STATUS_REG_PLL_PLL_BEST_MIN_CUR_Pos   (5UL)
 
#define GPREG_PLL_SYS_STATUS_REG_PLL_PLL_BEST_MIN_CUR_Msk   (0x7e0UL)
 
#define GPREG_PLL_SYS_STATUS_REG_PLL_CALIBR_END_Pos   (11UL)
 
#define GPREG_PLL_SYS_STATUS_REG_PLL_CALIBR_END_Msk   (0x800UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_DIS_LOOPFILT_Pos   (0UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_DIS_LOOPFILT_Msk   (0x1UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_MIN_CURRENT_Pos   (1UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_MIN_CURRENT_Msk   (0x7eUL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_TEST_VCTR_Pos   (7UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_TEST_VCTR_Msk   (0x80UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_OPEN_LOOP_Pos   (8UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_OPEN_LOOP_Msk   (0x100UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_CHANGE_Pos   (9UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_CHANGE_Msk   (0x200UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_N_DIV_TEST_Pos   (10UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_N_DIV_TEST_Msk   (0x400UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_R_DIV_TEST_Pos   (11UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_R_DIV_TEST_Msk   (0x800UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_LOCK_DET_RES_CNT_Pos   (13UL)
 
#define GPREG_PLL_SYS_TEST_REG_PLL_LOCK_DET_RES_CNT_Msk   (0xe000UL)
 
#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Pos   (0UL)
 
#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk   (0x1UL)
 
#define I2C_I2C_CON_REG_I2C_SPEED_Pos   (1UL)
 
#define I2C_I2C_CON_REG_I2C_SPEED_Msk   (0x6UL)
 
#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Pos   (3UL)
 
#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Msk   (0x8UL)
 
#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Pos   (4UL)
 
#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk   (0x10UL)
 
#define I2C_I2C_CON_REG_I2C_RESTART_EN_Pos   (5UL)
 
#define I2C_I2C_CON_REG_I2C_RESTART_EN_Msk   (0x20UL)
 
#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Pos   (6UL)
 
#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk   (0x40UL)
 
#define I2C_I2C_TAR_REG_IC_TAR_Pos   (0UL)
 
#define I2C_I2C_TAR_REG_IC_TAR_Msk   (0x3ffUL)
 
#define I2C_I2C_TAR_REG_GC_OR_START_Pos   (10UL)
 
#define I2C_I2C_TAR_REG_GC_OR_START_Msk   (0x400UL)
 
#define I2C_I2C_TAR_REG_SPECIAL_Pos   (11UL)
 
#define I2C_I2C_TAR_REG_SPECIAL_Msk   (0x800UL)
 
#define I2C_I2C_SAR_REG_IC_SAR_Pos   (0UL)
 
#define I2C_I2C_SAR_REG_IC_SAR_Msk   (0x3ffUL)
 
#define I2C_I2C_DATA_CMD_REG_DAT_Pos   (0UL)
 
#define I2C_I2C_DATA_CMD_REG_DAT_Msk   (0xffUL)
 
#define I2C_I2C_DATA_CMD_REG_CMD_Pos   (8UL)
 
#define I2C_I2C_DATA_CMD_REG_CMD_Msk   (0x100UL)
 
#define I2C_I2C_DATA_CMD_REG_STOP_Pos   (9UL)
 
#define I2C_I2C_DATA_CMD_REG_STOP_Msk   (0x200UL)
 
#define I2C_I2C_DATA_CMD_REG_RESTART_Pos   (10UL)
 
#define I2C_I2C_DATA_CMD_REG_RESTART_Msk   (0x400UL)
 
#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos   (0UL)
 
#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk   (0xffffUL)
 
#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos   (0UL)
 
#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk   (0xffffUL)
 
#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos   (0UL)
 
#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk   (0xffffUL)
 
#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos   (0UL)
 
#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk   (0xffffUL)
 
#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Pos   (0UL)
 
#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk   (0x1UL)
 
#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Pos   (1UL)
 
#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk   (0x2UL)
 
#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Pos   (2UL)
 
#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk   (0x4UL)
 
#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Pos   (3UL)
 
#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk   (0x8UL)
 
#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Pos   (4UL)
 
#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk   (0x10UL)
 
#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Pos   (5UL)
 
#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk   (0x20UL)
 
#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Pos   (6UL)
 
#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk   (0x40UL)
 
#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Pos   (7UL)
 
#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk   (0x80UL)
 
#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Pos   (8UL)
 
#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk   (0x100UL)
 
#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Pos   (9UL)
 
#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk   (0x200UL)
 
#define I2C_I2C_INTR_STAT_REG_R_START_DET_Pos   (10UL)
 
#define I2C_I2C_INTR_STAT_REG_R_START_DET_Msk   (0x400UL)
 
#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Pos   (11UL)
 
#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk   (0x800UL)
 
#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Pos   (0UL)
 
#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Msk   (0x1UL)
 
#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Pos   (1UL)
 
#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Msk   (0x2UL)
 
#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Pos   (2UL)
 
#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk   (0x4UL)
 
#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Pos   (3UL)
 
#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Msk   (0x8UL)
 
#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Pos   (4UL)
 
#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk   (0x10UL)
 
#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Pos   (5UL)
 
#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Msk   (0x20UL)
 
#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Pos   (6UL)
 
#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Msk   (0x40UL)
 
#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Pos   (7UL)
 
#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Msk   (0x80UL)
 
#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Pos   (8UL)
 
#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Msk   (0x100UL)
 
#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Pos   (9UL)
 
#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Msk   (0x200UL)
 
#define I2C_I2C_INTR_MASK_REG_M_START_DET_Pos   (10UL)
 
#define I2C_I2C_INTR_MASK_REG_M_START_DET_Msk   (0x400UL)
 
#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Pos   (11UL)
 
#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Msk   (0x800UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Pos   (0UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Msk   (0x1UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Pos   (1UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Msk   (0x2UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Pos   (2UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Msk   (0x4UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Pos   (3UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Msk   (0x8UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Pos   (4UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Msk   (0x10UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Pos   (5UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Msk   (0x20UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Pos   (6UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Msk   (0x40UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Pos   (7UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Msk   (0x80UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Pos   (8UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Msk   (0x100UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Pos   (9UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Msk   (0x200UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Pos   (10UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Msk   (0x400UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Pos   (11UL)
 
#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Msk   (0x800UL)
 
#define I2C_I2C_RX_TL_REG_RX_TL_Pos   (0UL)
 
#define I2C_I2C_RX_TL_REG_RX_TL_Msk   (0x1fUL)
 
#define I2C_I2C_TX_TL_REG_TX_TL_Pos   (0UL)
 
#define I2C_I2C_TX_TL_REG_TX_TL_Msk   (0x1fUL)
 
#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos   (0UL)
 
#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Msk   (0x1UL)
 
#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos   (0UL)
 
#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk   (0x1UL)
 
#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Pos   (0UL)
 
#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Msk   (0x1UL)
 
#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Pos   (0UL)
 
#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Msk   (0x1UL)
 
#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Pos   (0UL)
 
#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Msk   (0x1UL)
 
#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos   (0UL)
 
#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk   (0x1UL)
 
#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Pos   (0UL)
 
#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Msk   (0x1UL)
 
#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos   (0UL)
 
#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk   (0x1UL)
 
#define I2C_I2C_CLR_STOP_DET_REG_CLR_ACTIVITY_Pos   (0UL)
 
#define I2C_I2C_CLR_STOP_DET_REG_CLR_ACTIVITY_Msk   (0x1UL)
 
#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Pos   (0UL)
 
#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Msk   (0x1UL)
 
#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos   (0UL)
 
#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk   (0x1UL)
 
#define I2C_I2C_ENABLE_REG_CTRL_ENABLE_Pos   (0UL)
 
#define I2C_I2C_ENABLE_REG_CTRL_ENABLE_Msk   (0x1UL)
 
#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Pos   (0UL)
 
#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk   (0x1UL)
 
#define I2C_I2C_STATUS_REG_TFNF_Pos   (1UL)
 
#define I2C_I2C_STATUS_REG_TFNF_Msk   (0x2UL)
 
#define I2C_I2C_STATUS_REG_TFE_Pos   (2UL)
 
#define I2C_I2C_STATUS_REG_TFE_Msk   (0x4UL)
 
#define I2C_I2C_STATUS_REG_RFNE_Pos   (3UL)
 
#define I2C_I2C_STATUS_REG_RFNE_Msk   (0x8UL)
 
#define I2C_I2C_STATUS_REG_RFF_Pos   (4UL)
 
#define I2C_I2C_STATUS_REG_RFF_Msk   (0x10UL)
 
#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Pos   (5UL)
 
#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Msk   (0x20UL)
 
#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Pos   (6UL)
 
#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Msk   (0x40UL)
 
#define I2C_I2C_TXFLR_REG_TXFLR_Pos   (0UL)
 
#define I2C_I2C_TXFLR_REG_TXFLR_Msk   (0x3fUL)
 
#define I2C_I2C_RXFLR_REG_RXFLR_Pos   (0UL)
 
#define I2C_I2C_RXFLR_REG_RXFLR_Msk   (0x3fUL)
 
#define I2C_I2C_SDA_HOLD_REG_IC_SDA_HOLD_Pos   (0UL)
 
#define I2C_I2C_SDA_HOLD_REG_IC_SDA_HOLD_Msk   (0xffffUL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos   (0UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk   (0x1UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos   (1UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk   (0x2UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos   (2UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk   (0x4UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos   (3UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk   (0x8UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos   (4UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk   (0x10UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos   (5UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk   (0x20UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos   (6UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk   (0x40UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos   (7UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk   (0x80UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos   (8UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk   (0x100UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos   (9UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk   (0x200UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos   (10UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk   (0x400UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos   (11UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk   (0x800UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Pos   (12UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk   (0x1000UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos   (13UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk   (0x2000UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos   (14UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk   (0x4000UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos   (15UL)
 
#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk   (0x8000UL)
 
#define I2C_I2C_DMA_CR_REG_RDMAE_Pos   (0UL)
 
#define I2C_I2C_DMA_CR_REG_RDMAE_Msk   (0x1UL)
 
#define I2C_I2C_DMA_CR_REG_TDMAE_Pos   (1UL)
 
#define I2C_I2C_DMA_CR_REG_TDMAE_Msk   (0x2UL)
 
#define I2C_I2C_DMA_TDLR_REG_DMATDL_Pos   (0UL)
 
#define I2C_I2C_DMA_TDLR_REG_DMATDL_Msk   (0x1fUL)
 
#define I2C_I2C_DMA_RDLR_REG_DMARDL_Pos   (0UL)
 
#define I2C_I2C_DMA_RDLR_REG_DMARDL_Msk   (0x1fUL)
 
#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Pos   (0UL)
 
#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Msk   (0xffUL)
 
#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos   (0UL)
 
#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk   (0x1UL)
 
#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Pos   (0UL)
 
#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Msk   (0x1UL)
 
#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos   (1UL)
 
#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk   (0x2UL)
 
#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos   (2UL)
 
#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk   (0x4UL)
 
#define I2C_I2C_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Pos   (0UL)
 
#define I2C_I2C_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Msk   (0xffUL)
 
#define I2C_I2C_COMP_PARAM1_REG_IC_COMP_PARAM1_Pos   (0UL)
 
#define I2C_I2C_COMP_PARAM1_REG_IC_COMP_PARAM1_Msk   (0xffffUL)
 
#define I2C_I2C_COMP_PARAM2_REG_IC_COMP_PARAM2_Pos   (0UL)
 
#define I2C_I2C_COMP_PARAM2_REG_IC_COMP_PARAM2_Msk   (0xffffUL)
 
#define I2C_I2C_COMP_VERSION_REG_IC_COMP_VERSION_Pos   (0UL)
 
#define I2C_I2C_COMP_VERSION_REG_IC_COMP_VERSION_Msk   (0xffffUL)
 
#define I2C_I2C_COMP2_VERSION_IC_COMP2_VERSION_Pos   (0UL)
 
#define I2C_I2C_COMP2_VERSION_IC_COMP2_VERSION_Msk   (0xffffUL)
 
#define I2C_I2C_COMP_TYPE_REG_IC_COMP_TYPE_Pos   (0UL)
 
#define I2C_I2C_COMP_TYPE_REG_IC_COMP_TYPE_Msk   (0xffffUL)
 
#define I2C_I2C_COMP_TYPE2_REG_IC_COMP2_TYPE_Pos   (0UL)
 
#define I2C_I2C_COMP_TYPE2_REG_IC_COMP2_TYPE_Msk   (0xffffUL)
 
#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Pos   (0UL)
 
#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Msk   (0x1UL)
 
#define I2C2_I2C2_CON_REG_I2C_SPEED_Pos   (1UL)
 
#define I2C2_I2C2_CON_REG_I2C_SPEED_Msk   (0x6UL)
 
#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Pos   (3UL)
 
#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Msk   (0x8UL)
 
#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Pos   (4UL)
 
#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Msk   (0x10UL)
 
#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Pos   (5UL)
 
#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Msk   (0x20UL)
 
#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Pos   (6UL)
 
#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Msk   (0x40UL)
 
#define I2C2_I2C2_TAR_REG_IC_TAR_Pos   (0UL)
 
#define I2C2_I2C2_TAR_REG_IC_TAR_Msk   (0x3ffUL)
 
#define I2C2_I2C2_TAR_REG_GC_OR_START_Pos   (10UL)
 
#define I2C2_I2C2_TAR_REG_GC_OR_START_Msk   (0x400UL)
 
#define I2C2_I2C2_TAR_REG_SPECIAL_Pos   (11UL)
 
#define I2C2_I2C2_TAR_REG_SPECIAL_Msk   (0x800UL)
 
#define I2C2_I2C2_SAR_REG_IC_SAR_Pos   (0UL)
 
#define I2C2_I2C2_SAR_REG_IC_SAR_Msk   (0x3ffUL)
 
#define I2C2_I2C2_DATA_CMD_REG_DAT_Pos   (0UL)
 
#define I2C2_I2C2_DATA_CMD_REG_DAT_Msk   (0xffUL)
 
#define I2C2_I2C2_DATA_CMD_REG_CMD_Pos   (8UL)
 
#define I2C2_I2C2_DATA_CMD_REG_CMD_Msk   (0x100UL)
 
#define I2C2_I2C2_DATA_CMD_REG_STOP_Pos   (9UL)
 
#define I2C2_I2C2_DATA_CMD_REG_STOP_Msk   (0x200UL)
 
#define I2C2_I2C2_DATA_CMD_REG_RESTART_Pos   (10UL)
 
#define I2C2_I2C2_DATA_CMD_REG_RESTART_Msk   (0x400UL)
 
#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos   (0UL)
 
#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk   (0xffffUL)
 
#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos   (0UL)
 
#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk   (0xffffUL)
 
#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos   (0UL)
 
#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk   (0xffffUL)
 
#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos   (0UL)
 
#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk   (0xffffUL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Pos   (0UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Msk   (0x1UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Pos   (1UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Msk   (0x2UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Pos   (2UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Msk   (0x4UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Pos   (3UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Msk   (0x8UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Pos   (4UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Msk   (0x10UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Pos   (5UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Msk   (0x20UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Pos   (6UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Msk   (0x40UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Pos   (7UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Msk   (0x80UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Pos   (8UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Msk   (0x100UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Pos   (9UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Msk   (0x200UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Pos   (10UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Msk   (0x400UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Pos   (11UL)
 
#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Msk   (0x800UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Pos   (0UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Msk   (0x1UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Pos   (1UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Msk   (0x2UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Pos   (2UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Msk   (0x4UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Pos   (3UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Msk   (0x8UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Pos   (4UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Msk   (0x10UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Pos   (5UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Msk   (0x20UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Pos   (6UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Msk   (0x40UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Pos   (7UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Msk   (0x80UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Pos   (8UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Msk   (0x100UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Pos   (9UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Msk   (0x200UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Pos   (10UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Msk   (0x400UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Pos   (11UL)
 
#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Msk   (0x800UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Pos   (0UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Msk   (0x1UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Pos   (1UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Msk   (0x2UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Pos   (2UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Msk   (0x4UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Pos   (3UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Msk   (0x8UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Pos   (4UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Msk   (0x10UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Pos   (5UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Msk   (0x20UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Pos   (6UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Msk   (0x40UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Pos   (7UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Msk   (0x80UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Pos   (8UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Msk   (0x100UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Pos   (9UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Msk   (0x200UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Pos   (10UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Msk   (0x400UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Pos   (11UL)
 
#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Msk   (0x800UL)
 
#define I2C2_I2C2_RX_TL_REG_RX_TL_Pos   (0UL)
 
#define I2C2_I2C2_RX_TL_REG_RX_TL_Msk   (0x1fUL)
 
#define I2C2_I2C2_TX_TL_REG_TX_TL_Pos   (0UL)
 
#define I2C2_I2C2_TX_TL_REG_TX_TL_Msk   (0x1fUL)
 
#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Pos   (0UL)
 
#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Msk   (0x1UL)
 
#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos   (0UL)
 
#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk   (0x1UL)
 
#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Pos   (0UL)
 
#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Msk   (0x1UL)
 
#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Pos   (0UL)
 
#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Msk   (0x1UL)
 
#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Pos   (0UL)
 
#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Msk   (0x1UL)
 
#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos   (0UL)
 
#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk   (0x1UL)
 
#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Pos   (0UL)
 
#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Msk   (0x1UL)
 
#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos   (0UL)
 
#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk   (0x1UL)
 
#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_ACTIVITY_Pos   (0UL)
 
#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_ACTIVITY_Msk   (0x1UL)
 
#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Pos   (0UL)
 
#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Msk   (0x1UL)
 
#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos   (0UL)
 
#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk   (0x1UL)
 
#define I2C2_I2C2_ENABLE_REG_CTRL_ENABLE_Pos   (0UL)
 
#define I2C2_I2C2_ENABLE_REG_CTRL_ENABLE_Msk   (0x1UL)
 
#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Pos   (0UL)
 
#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Msk   (0x1UL)
 
#define I2C2_I2C2_STATUS_REG_TFNF_Pos   (1UL)
 
#define I2C2_I2C2_STATUS_REG_TFNF_Msk   (0x2UL)
 
#define I2C2_I2C2_STATUS_REG_TFE_Pos   (2UL)
 
#define I2C2_I2C2_STATUS_REG_TFE_Msk   (0x4UL)
 
#define I2C2_I2C2_STATUS_REG_RFNE_Pos   (3UL)
 
#define I2C2_I2C2_STATUS_REG_RFNE_Msk   (0x8UL)
 
#define I2C2_I2C2_STATUS_REG_RFF_Pos   (4UL)
 
#define I2C2_I2C2_STATUS_REG_RFF_Msk   (0x10UL)
 
#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Pos   (5UL)
 
#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Msk   (0x20UL)
 
#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Pos   (6UL)
 
#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Msk   (0x40UL)
 
#define I2C2_I2C2_TXFLR_REG_TXFLR_Pos   (0UL)
 
#define I2C2_I2C2_TXFLR_REG_TXFLR_Msk   (0x3fUL)
 
#define I2C2_I2C2_RXFLR_REG_RXFLR_Pos   (0UL)
 
#define I2C2_I2C2_RXFLR_REG_RXFLR_Msk   (0x3fUL)
 
#define I2C2_I2C2_SDA_HOLD_REG_IC_SDA_HOLD_Pos   (0UL)
 
#define I2C2_I2C2_SDA_HOLD_REG_IC_SDA_HOLD_Msk   (0xffffUL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos   (0UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk   (0x1UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos   (1UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk   (0x2UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos   (2UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk   (0x4UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos   (3UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk   (0x8UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos   (4UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk   (0x10UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos   (5UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk   (0x20UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos   (6UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk   (0x40UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos   (7UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk   (0x80UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos   (8UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk   (0x100UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos   (9UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk   (0x200UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos   (10UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk   (0x400UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos   (11UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk   (0x800UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Pos   (12UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Msk   (0x1000UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos   (13UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk   (0x2000UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos   (14UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk   (0x4000UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos   (15UL)
 
#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk   (0x8000UL)
 
#define I2C2_I2C2_DMA_CR_REG_RDMAE_Pos   (0UL)
 
#define I2C2_I2C2_DMA_CR_REG_RDMAE_Msk   (0x1UL)
 
#define I2C2_I2C2_DMA_CR_REG_TDMAE_Pos   (1UL)
 
#define I2C2_I2C2_DMA_CR_REG_TDMAE_Msk   (0x2UL)
 
#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Pos   (0UL)
 
#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Msk   (0x1fUL)
 
#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Pos   (0UL)
 
#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Msk   (0x1fUL)
 
#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Pos   (0UL)
 
#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Msk   (0xffUL)
 
#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos   (0UL)
 
#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk   (0x1UL)
 
#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Pos   (0UL)
 
#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Msk   (0x1UL)
 
#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos   (1UL)
 
#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk   (0x2UL)
 
#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos   (2UL)
 
#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk   (0x4UL)
 
#define I2C2_I2C2_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Pos   (0UL)
 
#define I2C2_I2C2_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Msk   (0xffUL)
 
#define I2C2_I2C2_COMP_PARAM1_REG_IC_COMP_PARAM1_Pos   (0UL)
 
#define I2C2_I2C2_COMP_PARAM1_REG_IC_COMP_PARAM1_Msk   (0xffffUL)
 
#define I2C2_I2C2_COMP_PARAM2_REG_IC_COMP_PARAM2_Pos   (0UL)
 
#define I2C2_I2C2_COMP_PARAM2_REG_IC_COMP_PARAM2_Msk   (0xffffUL)
 
#define I2C2_I2C2_COMP_VERSION_REG_IC_COMP_VERSION_Pos   (0UL)
 
#define I2C2_I2C2_COMP_VERSION_REG_IC_COMP_VERSION_Msk   (0xffffUL)
 
#define I2C2_I2C2_COMP2_VERSION_IC_COMP2_VERSION_Pos   (0UL)
 
#define I2C2_I2C2_COMP2_VERSION_IC_COMP2_VERSION_Msk   (0xffffUL)
 
#define I2C2_I2C2_COMP_TYPE_REG_IC_COMP_TYPE_Pos   (0UL)
 
#define I2C2_I2C2_COMP_TYPE_REG_IC_COMP_TYPE_Msk   (0xffffUL)
 
#define I2C2_I2C2_COMP_TYPE2_REG_IC_COMP2_TYPE_Pos   (0UL)
 
#define I2C2_I2C2_COMP_TYPE2_REG_IC_COMP2_TYPE_Msk   (0xffffUL)
 
#define IR_IR_FREQ_CARRIER_ON_REG_IR_FREQ_CARRIER_ON_Pos   (0UL)
 
#define IR_IR_FREQ_CARRIER_ON_REG_IR_FREQ_CARRIER_ON_Msk   (0x3ffUL)
 
#define IR_IR_FREQ_CARRIER_OFF_REG_IR_FREQ_CARRIER_OFF_Pos   (0UL)
 
#define IR_IR_FREQ_CARRIER_OFF_REG_IR_FREQ_CARRIER_OFF_Msk   (0x3ffUL)
 
#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_SPACE_Pos   (0UL)
 
#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_SPACE_Msk   (0xffUL)
 
#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_MARK_Pos   (8UL)
 
#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_MARK_Msk   (0xff00UL)
 
#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_SPACE_Pos   (0UL)
 
#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_SPACE_Msk   (0xffUL)
 
#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_MARK_Pos   (8UL)
 
#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_MARK_Msk   (0xff00UL)
 
#define IR_IR_CTRL_REG_IR_CODE_FIFO_RESET_Pos   (0UL)
 
#define IR_IR_CTRL_REG_IR_CODE_FIFO_RESET_Msk   (0x1UL)
 
#define IR_IR_CTRL_REG_IR_REP_FIFO_RESET_Pos   (1UL)
 
#define IR_IR_CTRL_REG_IR_REP_FIFO_RESET_Msk   (0x2UL)
 
#define IR_IR_CTRL_REG_IR_ENABLE_Pos   (2UL)
 
#define IR_IR_CTRL_REG_IR_ENABLE_Msk   (0x4UL)
 
#define IR_IR_CTRL_REG_IR_TX_START_Pos   (3UL)
 
#define IR_IR_CTRL_REG_IR_TX_START_Msk   (0x8UL)
 
#define IR_IR_CTRL_REG_IR_REPEAT_TYPE_Pos   (4UL)
 
#define IR_IR_CTRL_REG_IR_REPEAT_TYPE_Msk   (0x10UL)
 
#define IR_IR_CTRL_REG_IR_INVERT_OUTPUT_Pos   (5UL)
 
#define IR_IR_CTRL_REG_IR_INVERT_OUTPUT_Msk   (0x20UL)
 
#define IR_IR_CTRL_REG_IR_LOGIC_ZERO_FORMAT_Pos   (6UL)
 
#define IR_IR_CTRL_REG_IR_LOGIC_ZERO_FORMAT_Msk   (0x40UL)
 
#define IR_IR_CTRL_REG_IR_LOGIC_ONE_FORMAT_Pos   (7UL)
 
#define IR_IR_CTRL_REG_IR_LOGIC_ONE_FORMAT_Msk   (0x80UL)
 
#define IR_IR_CTRL_REG_IR_IRQ_EN_Pos   (8UL)
 
#define IR_IR_CTRL_REG_IR_IRQ_EN_Msk   (0x100UL)
 
#define IR_IR_STATUS_REG_IR_CODE_FIFO_WRDS_Pos   (0UL)
 
#define IR_IR_STATUS_REG_IR_CODE_FIFO_WRDS_Msk   (0x3fUL)
 
#define IR_IR_STATUS_REG_IR_REP_FIFO_WRDS_Pos   (6UL)
 
#define IR_IR_STATUS_REG_IR_REP_FIFO_WRDS_Msk   (0x3c0UL)
 
#define IR_IR_STATUS_REG_IR_BUSY_Pos   (10UL)
 
#define IR_IR_STATUS_REG_IR_BUSY_Msk   (0x400UL)
 
#define IR_IR_REPEAT_TIME_REG_IR_REPEAT_TIME_Pos   (0UL)
 
#define IR_IR_REPEAT_TIME_REG_IR_REPEAT_TIME_Msk   (0xffffUL)
 
#define IR_IR_MAIN_FIFO_REG_IR_CODE_FIFO_DATA_Pos   (0UL)
 
#define IR_IR_MAIN_FIFO_REG_IR_CODE_FIFO_DATA_Msk   (0xffffUL)
 
#define IR_IR_REPEAT_FIFO_REG_IR_REPEAT_FIFO_DATA_Pos   (0UL)
 
#define IR_IR_REPEAT_FIFO_REG_IR_REPEAT_FIFO_DATA_Msk   (0xffffUL)
 
#define IR_IR_IRQ_STATUS_REG_IR_IRQ_ACK_Pos   (0UL)
 
#define IR_IR_IRQ_STATUS_REG_IR_IRQ_ACK_Msk   (0x1UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_EN_Pos   (0UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_EN_Msk   (0x1UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_MESSAGE_MASK_Pos   (1UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_MESSAGE_MASK_Msk   (0x2UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_INACTIVE_MASK_Pos   (2UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_INACTIVE_MASK_Msk   (0x4UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_FIFO_MASK_Pos   (3UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_FIFO_MASK_Msk   (0x8UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_TIME_Pos   (4UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_TIME_Msk   (0x7f0UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_EN_Pos   (11UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_EN_Msk   (0x800UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_CLKDIV_Pos   (12UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_CLKDIV_Msk   (0x3000UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_RESET_FIFO_Pos   (14UL)
 
#define KBSCAN_KBSCN_CTRL_REG_KBSCN_RESET_FIFO_Msk   (0x4000UL)
 
#define KBSCAN_KBSCN_CTRL2_REG_KBSCN_ROW_ACTIVE_TIME_Pos   (0UL)
 
#define KBSCAN_KBSCN_CTRL2_REG_KBSCN_ROW_ACTIVE_TIME_Msk   (0xffffUL)
 
#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_ROW_Pos   (0UL)
 
#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_ROW_Msk   (0xfUL)
 
#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_COLUMN_Pos   (4UL)
 
#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_COLUMN_Msk   (0x1f0UL)
 
#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_RELEASE_TIME_Pos   (0UL)
 
#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_RELEASE_TIME_Msk   (0x3fUL)
 
#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_PRESS_TIME_Pos   (6UL)
 
#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_PRESS_TIME_Msk   (0xfc0UL)
 
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_MES_IRQ_STATUS_Pos   (0UL)
 
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_MES_IRQ_STATUS_Msk   (0x1UL)
 
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_INACTIVE_IRQ_STATUS_Pos   (1UL)
 
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_INACTIVE_IRQ_STATUS_Msk   (0x2UL)
 
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_NUM_MESSAGE_Pos   (2UL)
 
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_NUM_MESSAGE_Msk   (0x7cUL)
 
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_OVERFL_Pos   (7UL)
 
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_OVERFL_Msk   (0x80UL)
 
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_UNDERFL_Pos   (8UL)
 
#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_UNDERFL_Msk   (0x100UL)
 
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_ROW_Pos   (0UL)
 
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_ROW_Msk   (0xfUL)
 
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_COLUMN_Pos   (4UL)
 
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_COLUMN_Msk   (0x1f0UL)
 
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEY_STATE_Pos   (9UL)
 
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEY_STATE_Msk   (0x200UL)
 
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_LAST_ENTRY_Pos   (10UL)
 
#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_LAST_ENTRY_Msk   (0x400UL)
 
#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_MODE_Pos   (0UL)
 
#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)
 
#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_ROW_Pos   (5UL)
 
#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_ROW_Msk   (0x20UL)
 
#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)
 
#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)
 
#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Pos   (0UL)
 
#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Msk   (0x7UL)
 
#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_DMA_Pos   (4UL)
 
#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_DMA_Msk   (0x10UL)
 
#define OTPC_OTPC_MODE_REG_OTPC_MODE_FIFO_FLUSH_Pos   (5UL)
 
#define OTPC_OTPC_MODE_REG_OTPC_MODE_FIFO_FLUSH_Msk   (0x20UL)
 
#define OTPC_OTPC_MODE_REG_OTPC_MODE_ERR_RESP_DIS_Pos   (6UL)
 
#define OTPC_OTPC_MODE_REG_OTPC_MODE_ERR_RESP_DIS_Msk   (0x40UL)
 
#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_SP_ROWS_Pos   (8UL)
 
#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_SP_ROWS_Msk   (0x100UL)
 
#define OTPC_OTPC_MODE_REG_OTPC_MODE_RLD_RR_REQ_Pos   (9UL)
 
#define OTPC_OTPC_MODE_REG_OTPC_MODE_RLD_RR_REQ_Msk   (0x200UL)
 
#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_WADDR_Pos   (0UL)
 
#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_WADDR_Msk   (0x1fffUL)
 
#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PRETRY_Pos   (14UL)
 
#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PRETRY_Msk   (0x4000UL)
 
#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PSTART_Pos   (15UL)
 
#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PSTART_Msk   (0x8000UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Pos   (0UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Msk   (0x1UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_UNC_Pos   (1UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_UNC_Msk   (0x2UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_COR_Pos   (2UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_COR_Msk   (0x4UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PZERO_Pos   (3UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_PZERO_Msk   (0x8UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_TRDY_Pos   (4UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_TRDY_Msk   (0x10UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_TERROR_Pos   (5UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_TERROR_Msk   (0x20UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_ARDY_Pos   (6UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_ARDY_Msk   (0x40UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_RERROR_Pos   (7UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_RERROR_Msk   (0x80UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_FWORDS_Pos   (8UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_FWORDS_Msk   (0xf00UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_NWORDS_Pos   (16UL)
 
#define OTPC_OTPC_STAT_REG_OTPC_STAT_NWORDS_Msk   (0x3fff0000UL)
 
#define OTPC_OTPC_AHBADR_REG_OTPC_AHBADR_Pos   (2UL)
 
#define OTPC_OTPC_AHBADR_REG_OTPC_AHBADR_Msk   (0xfffffffcUL)
 
#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_Pos   (0UL)
 
#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_Msk   (0x3fffUL)
 
#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_LV_Pos   (16UL)
 
#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_LV_Msk   (0x3fff0000UL)
 
#define OTPC_OTPC_NWORDS_REG_OTPC_NWORDS_Pos   (0UL)
 
#define OTPC_OTPC_NWORDS_REG_OTPC_NWORDS_Msk   (0x3fffUL)
 
#define OTPC_OTPC_FFPRT_REG_OTPC_FFPRT_Pos   (0UL)
 
#define OTPC_OTPC_FFPRT_REG_OTPC_FFPRT_Msk   (0xffffffffUL)
 
#define OTPC_OTPC_FFRD_REG_OTPC_FFRD_Pos   (0UL)
 
#define OTPC_OTPC_FFRD_REG_OTPC_FFRD_Msk   (0xffffffffUL)
 
#define OTPC_OTPC_PWORDL_REG_OTPC_PWORDL_Pos   (0UL)
 
#define OTPC_OTPC_PWORDL_REG_OTPC_PWORDL_Msk   (0xffffffffUL)
 
#define OTPC_OTPC_PWORDH_REG_OTPC_PWORDH_Pos   (0UL)
 
#define OTPC_OTPC_PWORDH_REG_OTPC_PWORDH_Msk   (0xffffffffUL)
 
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos   (0UL)
 
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Msk   (0xffUL)
 
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos   (8UL)
 
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Msk   (0xff00UL)
 
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos   (16UL)
 
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Msk   (0x3f0000UL)
 
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos   (22UL)
 
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Msk   (0x7c00000UL)
 
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos   (27UL)
 
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Msk   (0x78000000UL)
 
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos   (31UL)
 
#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Msk   (0x80000000UL)
 
#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_STBY_THR_Pos   (0UL)
 
#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_STBY_THR_Msk   (0x3ffUL)
 
#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_T_BCHK_Pos   (16UL)
 
#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_T_BCHK_Msk   (0x7f0000UL)
 
#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_RDENL_PROT_Pos   (23UL)
 
#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_RDENL_PROT_Msk   (0x800000UL)
 
#define OTPC_OTPC_TEST_REG_OTPC_SECDED_COR_DIS_Pos   (0UL)
 
#define OTPC_OTPC_TEST_REG_OTPC_SECDED_COR_DIS_Msk   (0x1UL)
 
#define OTPC_OTPC_TEST_REG_OTPC_SECDED_RAW_ECC_Pos   (16UL)
 
#define OTPC_OTPC_TEST_REG_OTPC_SECDED_RAW_ECC_Msk   (0xff0000UL)
 
#define OTPC_OTPC_TEST_REG_OTPC_SECDED_STAT_Pos   (24UL)
 
#define OTPC_OTPC_TEST_REG_OTPC_SECDED_STAT_Msk   (0x3000000UL)
 
#define OTPC_OTPC_TEST_REG_OTPC_USED_RR_Pos   (26UL)
 
#define OTPC_OTPC_TEST_REG_OTPC_USED_RR_Msk   (0x4000000UL)
 
#define PATCH_PATCH_VALID_REG_PATCH_VALID_Pos   (0UL)
 
#define PATCH_PATCH_VALID_REG_PATCH_VALID_Msk   (0xfffffffUL)
 
#define PATCH_PATCH_VALID_SET_REG_PATCH_VALID_Pos   (0UL)
 
#define PATCH_PATCH_VALID_SET_REG_PATCH_VALID_Msk   (0xfffffffUL)
 
#define PATCH_PATCH_VALID_RESET_REG_PATCH_VALID_Pos   (0UL)
 
#define PATCH_PATCH_VALID_RESET_REG_PATCH_VALID_Msk   (0xfffffffUL)
 
#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_C_Pos   (1UL)
 
#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)
 
#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_D_Pos   (2UL)
 
#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)
 
#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_DATA20_REG_PATCH_DATA_Pos   (0UL)
 
#define PATCH_PATCH_DATA20_REG_PATCH_DATA_Msk   (0xffffffffUL)
 
#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_D_Pos   (2UL)
 
#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)
 
#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_DATA21_REG_PATCH_DATA_Pos   (0UL)
 
#define PATCH_PATCH_DATA21_REG_PATCH_DATA_Msk   (0xffffffffUL)
 
#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_D_Pos   (2UL)
 
#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)
 
#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_DATA22_REG_PATCH_DATA_Pos   (0UL)
 
#define PATCH_PATCH_DATA22_REG_PATCH_DATA_Msk   (0xffffffffUL)
 
#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_D_Pos   (2UL)
 
#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)
 
#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_DATA23_REG_PATCH_DATA_Pos   (0UL)
 
#define PATCH_PATCH_DATA23_REG_PATCH_DATA_Msk   (0xffffffffUL)
 
#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_D_Pos   (2UL)
 
#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)
 
#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_DATA24_REG_PATCH_DATA_Pos   (0UL)
 
#define PATCH_PATCH_DATA24_REG_PATCH_DATA_Msk   (0xffffffffUL)
 
#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_D_Pos   (2UL)
 
#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)
 
#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_DATA25_REG_PATCH_DATA_Pos   (0UL)
 
#define PATCH_PATCH_DATA25_REG_PATCH_DATA_Msk   (0xffffffffUL)
 
#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_D_Pos   (2UL)
 
#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)
 
#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_DATA26_REG_PATCH_DATA_Pos   (0UL)
 
#define PATCH_PATCH_DATA26_REG_PATCH_DATA_Msk   (0xffffffffUL)
 
#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_D_Pos   (2UL)
 
#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)
 
#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_19_Pos   (19UL)
 
#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_19_Msk   (0x80000UL)
 
#define PATCH_PATCH_DATA27_REG_PATCH_DATA_Pos   (0UL)
 
#define PATCH_PATCH_DATA27_REG_PATCH_DATA_Msk   (0xffffffffUL)
 
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CHANNEL_ZERO_Pos   (0UL)
 
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CHANNEL_ZERO_Msk   (0xfffUL)
 
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_SGN_Pos   (12UL)
 
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_SGN_Msk   (0x1000UL)
 
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CS_Pos   (13UL)
 
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CS_Msk   (0x2000UL)
 
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_PLL_HSI_POL_Pos   (14UL)
 
#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_PLL_HSI_POL_Msk   (0x4000UL)
 
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CHANNEL_ZERO_Pos   (0UL)
 
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CHANNEL_ZERO_Msk   (0xfffUL)
 
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_SGN_Pos   (12UL)
 
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_SGN_Msk   (0x1000UL)
 
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CS_Pos   (13UL)
 
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CS_Msk   (0x2000UL)
 
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_PLL_HSI_POL_Pos   (14UL)
 
#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_PLL_HSI_POL_Msk   (0x4000UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_RX_Pos   (0UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_RX_Msk   (0x3UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_TX_Pos   (2UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_TX_Msk   (0xcUL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_MODINDEX_Pos   (4UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_MODINDEX_Msk   (0x30UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_DELAY_Pos   (6UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_DELAY_Msk   (0xc0UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_INV_Pos   (8UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_INV_Msk   (0x100UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_86_Pos   (9UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_86_Msk   (0x200UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_TXDATA_INV_Pos   (10UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_TXDATA_INV_Msk   (0x400UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_EO_PACKET_DIS_Pos   (11UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_EO_PACKET_DIS_Msk   (0x800UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BT_SEL_Pos   (12UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BT_SEL_Msk   (0x1000UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BLE_DAC_SEL_Pos   (13UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BLE_DAC_SEL_Msk   (0x2000UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_RX_Pos   (0UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_RX_Msk   (0x3UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_TX_Pos   (2UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_TX_Msk   (0xcUL)
 
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_MODINDEX_Pos   (4UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_MODINDEX_Msk   (0x30UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDAC_DELAY_Pos   (6UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDAC_DELAY_Msk   (0x40UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_GAUSS_INV_Pos   (8UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_GAUSS_INV_Msk   (0x100UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDATA_INV_Pos   (10UL)
 
#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDATA_INV_Msk   (0x400UL)
 
#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_WR_Pos   (0UL)
 
#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_WR_Msk   (0x3fffUL)
 
#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_SEL_Pos   (14UL)
 
#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_SEL_Msk   (0x4000UL)
 
#define PLLDIG_RF_SYNTH_CTRL3_REG_ZIF_MODE_EN_Pos   (15UL)
 
#define PLLDIG_RF_SYNTH_CTRL3_REG_ZIF_MODE_EN_Msk   (0x8000UL)
 
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_WR_Pos   (0UL)
 
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_WR_Msk   (0xfUL)
 
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_SEL_Pos   (4UL)
 
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_SEL_Msk   (0x30UL)
 
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_PERIOD_Pos   (6UL)
 
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_PERIOD_Msk   (0xc0UL)
 
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_MD_STATE_DLY_SEL_Pos   (8UL)
 
#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_MD_STATE_DLY_SEL_Msk   (0x100UL)
 
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_WR_Pos   (0UL)
 
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_WR_Msk   (0xffUL)
 
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_SEL_Pos   (8UL)
 
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_SEL_Msk   (0x100UL)
 
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_BLE_TESTPAT_GEN_Pos   (9UL)
 
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_BLE_TESTPAT_GEN_Msk   (0x200UL)
 
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_CMP_INV_Pos   (10UL)
 
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_CMP_INV_Msk   (0x400UL)
 
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_AVER_Pos   (11UL)
 
#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_AVER_Msk   (0x1800UL)
 
#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_WR_Pos   (0UL)
 
#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_WR_Msk   (0x7fUL)
 
#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Pos   (7UL)
 
#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Msk   (0x80UL)
 
#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_OFFSET_Pos   (8UL)
 
#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_OFFSET_Msk   (0xff00UL)
 
#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_TRANSMIT_LENGTH_Pos   (0UL)
 
#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_TRANSMIT_LENGTH_Msk   (0x7fUL)
 
#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_MODE_SEL_Pos   (7UL)
 
#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_MODE_SEL_Msk   (0x80UL)
 
#define PLLDIG_RF_MGAIN_CTRL2_REG_MSK_GAINCAL_LONG_Pos   (8UL)
 
#define PLLDIG_RF_MGAIN_CTRL2_REG_MSK_GAINCAL_LONG_Msk   (0x100UL)
 
#define PLLDIG_RF_VCO_CALCAP_BIT14_REG_VCO_CALCAP_BIT14_Pos   (0UL)
 
#define PLLDIG_RF_VCO_CALCAP_BIT14_REG_VCO_CALCAP_BIT14_Msk   (0xffffUL)
 
#define PLLDIG_RF_VCO_CALCAP_BIT15_REG_VCO_CALCAP_BIT15_Pos   (0UL)
 
#define PLLDIG_RF_VCO_CALCAP_BIT15_REG_VCO_CALCAP_BIT15_Msk   (0xffffUL)
 
#define PLLDIG_RF_BMCW_REG_CN_WR_Pos   (0UL)
 
#define PLLDIG_RF_BMCW_REG_CN_WR_Msk   (0x3fUL)
 
#define PLLDIG_RF_BMCW_REG_HSI_WR_Pos   (6UL)
 
#define PLLDIG_RF_BMCW_REG_HSI_WR_Msk   (0x40UL)
 
#define PLLDIG_RF_BMCW_REG_CN_SEL_Pos   (7UL)
 
#define PLLDIG_RF_BMCW_REG_CN_SEL_Msk   (0x80UL)
 
#define PLLDIG_RF_BMCW_REG_HSI_SEL_Pos   (8UL)
 
#define PLLDIG_RF_BMCW_REG_HSI_SEL_Msk   (0x100UL)
 
#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_GAUSSDAC_Pos   (0UL)
 
#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_GAUSSDAC_Msk   (0x3fUL)
 
#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_TXDAC_Pos   (6UL)
 
#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_TXDAC_Msk   (0xfc0UL)
 
#define PLLDIG_RF_KMOD_ALPHA_FTDF_REG_KMOD_ALPHA_FTDF_Pos   (0UL)
 
#define PLLDIG_RF_KMOD_ALPHA_FTDF_REG_KMOD_ALPHA_FTDF_Msk   (0x3fUL)
 
#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_GAUSS_GAIN_CAL_RD_Pos   (0UL)
 
#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_GAUSS_GAIN_CAL_RD_Msk   (0xffUL)
 
#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_VCO_FREQTRIM_RD_Pos   (8UL)
 
#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_VCO_FREQTRIM_RD_Msk   (0xf00UL)
 
#define PLLDIG_RF_SYNTH_RESULT_FTDF_REG_MSK_GAIN_CAL_RD_Pos   (0UL)
 
#define PLLDIG_RF_SYNTH_RESULT_FTDF_REG_MSK_GAIN_CAL_RD_Msk   (0x7fUL)
 
#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_GAUSS_GAIN_RD_Pos   (0UL)
 
#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_GAUSS_GAIN_RD_Msk   (0xffUL)
 
#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_CN_CAL_RD_Pos   (8UL)
 
#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_CN_CAL_RD_Msk   (0x3f00UL)
 
#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_RD_Pos   (0UL)
 
#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_RD_Msk   (0xffUL)
 
#define PLLDIG_RF_SYNTH_RESULT3_FTDF_REG_CN_CAL_FTDF_RD_Pos   (0UL)
 
#define PLLDIG_RF_SYNTH_RESULT3_FTDF_REG_CN_CAL_FTDF_RD_Msk   (0x3fUL)
 
#define PLLDIG_RF_CALCAP1_REG_VCO_CALCAP_LOW_Pos   (0UL)
 
#define PLLDIG_RF_CALCAP1_REG_VCO_CALCAP_LOW_Msk   (0xffffUL)
 
#define PLLDIG_RF_CALCAP2_REG_VCO_CALCAP_HIGH_Pos   (0UL)
 
#define PLLDIG_RF_CALCAP2_REG_VCO_CALCAP_HIGH_Msk   (0x3UL)
 
#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_XTAL16M_Pos   (0UL)
 
#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_XTAL16M_Msk   (0xffUL)
 
#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_PLL96M_Pos   (8UL)
 
#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_PLL96M_Msk   (0xff00UL)
 
#define PLLDIG_RF_FTDF_PHYATTR_REG_FTDF_PHYATTR_Pos   (0UL)
 
#define PLLDIG_RF_FTDF_PHYATTR_REG_FTDF_PHYATTR_Msk   (0xffffUL)
 
#define PLLDIG_RF_CALTRIM_STEP1_REG_MDSTATE_RD_Pos   (0UL)
 
#define PLLDIG_RF_CALTRIM_STEP1_REG_MDSTATE_RD_Msk   (0xffffUL)
 
#define PLLDIG_RF_CALTRIM_STEP2_REG_MDSTATE_RD_Pos   (0UL)
 
#define PLLDIG_RF_CALTRIM_STEP2_REG_MDSTATE_RD_Msk   (0xffffUL)
 
#define PLLDIG_RF_CALTRIM_STEP3_REG_MDSTATE_RD_Pos   (0UL)
 
#define PLLDIG_RF_CALTRIM_STEP3_REG_MDSTATE_RD_Msk   (0xffffUL)
 
#define PLLDIG_RF_CALTRIM_STEP4_REG_MDSTATE_RD_Pos   (0UL)
 
#define PLLDIG_RF_CALTRIM_STEP4_REG_MDSTATE_RD_Msk   (0xffffUL)
 
#define PLLDIG_RF_MGAIN_CTRL3_REG_GFSK_GAIN_OFFSET_Pos   (0UL)
 
#define PLLDIG_RF_MGAIN_CTRL3_REG_GFSK_GAIN_OFFSET_Msk   (0xffUL)
 
#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_EN_Pos   (0UL)
 
#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_EN_Msk   (0x1UL)
 
#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_LEN_Pos   (1UL)
 
#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_LEN_Msk   (0xfeUL)
 
#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_UPPER_RD_Pos   (8UL)
 
#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_UPPER_RD_Msk   (0x700UL)
 
#define PLLDIG_RF_SYNTH_SPARE_REG_SPARE_Pos   (0UL)
 
#define PLLDIG_RF_SYNTH_SPARE_REG_SPARE_Msk   (0xffUL)
 
#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DATA_Pos   (0UL)
 
#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DATA_Msk   (0xfUL)
 
#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_VALID_Pos   (4UL)
 
#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_VALID_Msk   (0x10UL)
 
#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_TX_SEL_Pos   (5UL)
 
#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_TX_SEL_Msk   (0x20UL)
 
#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_ALW_EN_Pos   (6UL)
 
#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_ALW_EN_Msk   (0x40UL)
 
#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Pos   (7UL)
 
#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Msk   (0x80UL)
 
#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Pos   (8UL)
 
#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Msk   (0x100UL)
 
#define PLLDIG_RF_MSKMOD_CHIPL_REG_MSK_CHIPL_Pos   (0UL)
 
#define PLLDIG_RF_MSKMOD_CHIPL_REG_MSK_CHIPL_Msk   (0xffffUL)
 
#define PLLDIG_RF_MSKMOD_CHIPH_REG_MSK_CHIPH_Pos   (0UL)
 
#define PLLDIG_RF_MSKMOD_CHIPH_REG_MSK_CHIPH_Msk   (0xffffUL)
 
#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_WR_Pos   (0UL)
 
#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_WR_Msk   (0xffUL)
 
#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_SEL_Pos   (8UL)
 
#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_SEL_Msk   (0x100UL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL0_REG_MGAIN_COMP_VAL_Pos   (0UL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL0_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL1_REG_MGAIN_COMP_VAL_Pos   (0UL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL1_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL2_REG_MGAIN_COMP_VAL_Pos   (0UL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL2_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL3_REG_MGAIN_COMP_VAL_Pos   (0UL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL3_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL4_REG_MGAIN_COMP_VAL_Pos   (0UL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL4_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL5_REG_MGAIN_COMP_VAL_Pos   (0UL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL5_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL6_REG_MGAIN_COMP_VAL_Pos   (0UL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL6_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL7_REG_MGAIN_COMP_VAL_Pos   (0UL)
 
#define PLLDIG_RF_MGAIN_COMP_VAL7_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)
 
#define PLLDIG_RF_PULSE_TBL_0_REG_FTDF_PULSE_VAL_Pos   (0UL)
 
#define PLLDIG_RF_PULSE_TBL_0_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)
 
#define PLLDIG_RF_PULSE_TBL_1_REG_FTDF_PULSE_VAL_Pos   (0UL)
 
#define PLLDIG_RF_PULSE_TBL_1_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)
 
#define PLLDIG_RF_PULSE_TBL_2_REG_FTDF_PULSE_VAL_Pos   (0UL)
 
#define PLLDIG_RF_PULSE_TBL_2_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)
 
#define PLLDIG_RF_PULSE_TBL_3_REG_FTDF_PULSE_VAL_Pos   (0UL)
 
#define PLLDIG_RF_PULSE_TBL_3_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)
 
#define PLLDIG_RF_PULSE_TBL_4_REG_FTDF_PULSE_VAL_Pos   (0UL)
 
#define PLLDIG_RF_PULSE_TBL_4_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)
 
#define PLLDIG_RF_PULSE_TBL_5_REG_FTDF_PULSE_VAL_Pos   (0UL)
 
#define PLLDIG_RF_PULSE_TBL_5_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)
 
#define PLLDIG_RF_PULSE_TBL_6_REG_FTDF_PULSE_VAL_Pos   (0UL)
 
#define PLLDIG_RF_PULSE_TBL_6_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)
 
#define PLLDIG_RF_PULSE_TBL_7_REG_FTDF_PULSE_VAL_Pos   (0UL)
 
#define PLLDIG_RF_PULSE_TBL_7_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)
 
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_SEL_Pos   (0UL)
 
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_SEL_Msk   (0x1UL)
 
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GATE_Pos   (1UL)
 
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GATE_Msk   (0x6UL)
 
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_LOWPASS_EN_Pos   (3UL)
 
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_LOWPASS_EN_Msk   (0x8UL)
 
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GAIN_Pos   (4UL)
 
#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GAIN_Msk   (0xf0UL)
 
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos   (0UL)
 
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk   (0x1UL)
 
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Pos   (1UL)
 
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Msk   (0x2UL)
 
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Pos   (2UL)
 
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Msk   (0x4UL)
 
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Pos   (3UL)
 
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk   (0x8UL)
 
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Pos   (4UL)
 
#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk   (0x10UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Pos   (0UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk   (0x1UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Pos   (1UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Msk   (0x2UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Pos   (2UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk   (0x4UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Pos   (3UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Msk   (0x8UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Pos   (4UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Msk   (0x10UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Pos   (5UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Msk   (0x20UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Pos   (6UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Msk   (0x40UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Pos   (7UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Msk   (0x80UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos   (8UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk   (0x100UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos   (9UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk   (0xe00UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Pos   (12UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Msk   (0x1000UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Pos   (13UL)
 
#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Msk   (0x2000UL)
 
#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Pos   (0UL)
 
#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Msk   (0xffffffffUL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Pos   (0UL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Msk   (0xffUL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Pos   (8UL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Msk   (0xff00UL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos   (16UL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk   (0xff0000UL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos   (24UL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk   (0x3000000UL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos   (26UL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk   (0xc000000UL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos   (28UL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk   (0x30000000UL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos   (30UL)
 
#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk   (0xc0000000UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos   (0UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk   (0x3UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos   (2UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk   (0x4UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos   (3UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk   (0x8UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos   (4UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk   (0x30UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Pos   (6UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Msk   (0x40UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos   (7UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk   (0x80UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos   (8UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk   (0x300UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos   (10UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk   (0xc00UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos   (12UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk   (0x7000UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos   (15UL)
 
#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk   (0x8000UL)
 
#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Pos   (0UL)
 
#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Msk   (0x1UL)
 
#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Pos   (0UL)
 
#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Msk   (0xffffffffUL)
 
#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Pos   (0UL)
 
#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Msk   (0xffffffffUL)
 
#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos   (0UL)
 
#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk   (0xffffffffUL)
 
#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos   (4UL)
 
#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk   (0xfffff0UL)
 
#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Pos   (24UL)
 
#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Msk   (0x1000000UL)
 
#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Pos   (25UL)
 
#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Msk   (0xe000000UL)
 
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Pos   (0UL)
 
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Msk   (0xffUL)
 
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Pos   (8UL)
 
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Msk   (0xff00UL)
 
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Pos   (16UL)
 
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Msk   (0xff0000UL)
 
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Pos   (24UL)
 
#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Msk   (0xff000000UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos   (0UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk   (0x3UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos   (2UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk   (0xcUL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos   (4UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk   (0x30UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos   (6UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk   (0xc0UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos   (8UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk   (0x300UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos   (10UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk   (0x7c00UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos   (16UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk   (0xf0000UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos   (24UL)
 
#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk   (0x3f000000UL)
 
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Pos   (0UL)
 
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Msk   (0xffffUL)
 
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Pos   (16UL)
 
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Msk   (0x10000UL)
 
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Pos   (17UL)
 
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Msk   (0x20000UL)
 
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos   (18UL)
 
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk   (0xc0000UL)
 
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos   (20UL)
 
#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk   (0x100000UL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos   (0UL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk   (0xffUL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos   (8UL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk   (0x300UL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos   (10UL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk   (0xc00UL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Pos   (12UL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Msk   (0x7000UL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos   (15UL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk   (0x8000UL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos   (16UL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk   (0x3f0000UL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos   (22UL)
 
#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk   (0x400000UL)
 
#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Pos   (0UL)
 
#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Msk   (0xffffffffUL)
 
#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Pos   (1UL)
 
#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Msk   (0x6UL)
 
#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Pos   (3UL)
 
#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Msk   (0x18UL)
 
#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Pos   (0UL)
 
#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Msk   (0xffffffffUL)
 
#define QUAD_QDEC_CTRL_REG_QD_IRQ_MASK_Pos   (0UL)
 
#define QUAD_QDEC_CTRL_REG_QD_IRQ_MASK_Msk   (0x1UL)
 
#define QUAD_QDEC_CTRL_REG_QD_IRQ_CLR_Pos   (1UL)
 
#define QUAD_QDEC_CTRL_REG_QD_IRQ_CLR_Msk   (0x2UL)
 
#define QUAD_QDEC_CTRL_REG_QD_IRQ_STATUS_Pos   (2UL)
 
#define QUAD_QDEC_CTRL_REG_QD_IRQ_STATUS_Msk   (0x4UL)
 
#define QUAD_QDEC_CTRL_REG_QD_IRQ_THRES_Pos   (3UL)
 
#define QUAD_QDEC_CTRL_REG_QD_IRQ_THRES_Msk   (0x3f8UL)
 
#define QUAD_QDEC_CTRL_REG_CHX_PORT_EN_Pos   (10UL)
 
#define QUAD_QDEC_CTRL_REG_CHX_PORT_EN_Msk   (0x400UL)
 
#define QUAD_QDEC_CTRL_REG_CHY_PORT_EN_Pos   (11UL)
 
#define QUAD_QDEC_CTRL_REG_CHY_PORT_EN_Msk   (0x800UL)
 
#define QUAD_QDEC_CTRL_REG_CHZ_PORT_EN_Pos   (12UL)
 
#define QUAD_QDEC_CTRL_REG_CHZ_PORT_EN_Msk   (0x1000UL)
 
#define QUAD_QDEC_XCNT_REG_X_counter_Pos   (0UL)
 
#define QUAD_QDEC_XCNT_REG_X_counter_Msk   (0xffffUL)
 
#define QUAD_QDEC_YCNT_REG_Y_counter_Pos   (0UL)
 
#define QUAD_QDEC_YCNT_REG_Y_counter_Msk   (0xffffUL)
 
#define QUAD_QDEC_ZCNT_REG_Z_counter_Pos   (0UL)
 
#define QUAD_QDEC_ZCNT_REG_Z_counter_Msk   (0xffffUL)
 
#define QUAD_QDEC_CLOCKDIV_REG_clock_divider_Pos   (0UL)
 
#define QUAD_QDEC_CLOCKDIV_REG_clock_divider_Msk   (0x3ffUL)
 
#define RFCU_RF_OVERRULE_REG_TX_EN_OVR_Pos   (0UL)
 
#define RFCU_RF_OVERRULE_REG_TX_EN_OVR_Msk   (0x3UL)
 
#define RFCU_RF_OVERRULE_REG_RX_EN_OVR_Pos   (2UL)
 
#define RFCU_RF_OVERRULE_REG_RX_EN_OVR_Msk   (0xcUL)
 
#define RFCU_RF_OVERRULE_REG_RF_MODE_OVR_Pos   (4UL)
 
#define RFCU_RF_OVERRULE_REG_RF_MODE_OVR_Msk   (0x30UL)
 
#define RFCU_RF_OVERRULE_REG_IFF_FTDF_OVR_Pos   (6UL)
 
#define RFCU_RF_OVERRULE_REG_IFF_FTDF_OVR_Msk   (0xc0UL)
 
#define RFCU_RF_OVERRULE_REG_MIX_FTDF_OVR_Pos   (8UL)
 
#define RFCU_RF_OVERRULE_REG_MIX_FTDF_OVR_Msk   (0x300UL)
 
#define RFCU_RF_OVERRULE_REG_TXDAC_SEL_Pos   (10UL)
 
#define RFCU_RF_OVERRULE_REG_TXDAC_SEL_Msk   (0xc00UL)
 
#define RFCU_RF_OVERRULE_REG_GAUSS_DAC_SEL_Pos   (12UL)
 
#define RFCU_RF_OVERRULE_REG_GAUSS_DAC_SEL_Msk   (0x3000UL)
 
#define RFCU_RF_OVERRULE_REG_CN_FTDF_TIMES2_Pos   (14UL)
 
#define RFCU_RF_OVERRULE_REG_CN_FTDF_TIMES2_Msk   (0x4000UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_0_Pos   (0UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_0_Msk   (0x1UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_0_Pos   (1UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_0_Msk   (0x6UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_0_Pos   (3UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_0_Msk   (0x38UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_0_Pos   (6UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_0_Msk   (0x40UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_1_Pos   (8UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_1_Msk   (0x100UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_1_Pos   (9UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_1_Msk   (0x600UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_1_Pos   (11UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_1_Msk   (0x3800UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_1_Pos   (14UL)
 
#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_1_Msk   (0x4000UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_2_Pos   (0UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_2_Msk   (0x1UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_2_Pos   (1UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_2_Msk   (0x6UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_2_Pos   (3UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_2_Msk   (0x38UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_2_Pos   (6UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_2_Msk   (0x40UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_3_Pos   (8UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_3_Msk   (0x100UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_3_Pos   (9UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_3_Msk   (0x600UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_3_Pos   (11UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_3_Msk   (0x3800UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_3_Pos   (14UL)
 
#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_3_Msk   (0x4000UL)
 
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_0_Pos   (0UL)
 
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_0_Msk   (0x1UL)
 
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_1_Pos   (1UL)
 
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_1_Msk   (0x2UL)
 
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_2_Pos   (2UL)
 
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_2_Msk   (0x4UL)
 
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_3_Pos   (3UL)
 
#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_3_Msk   (0x8UL)
 
#define RFCU_RF_AGC_EXT1_LUT_REG_AGC_EXT_LUT_Pos   (0UL)
 
#define RFCU_RF_AGC_EXT1_LUT_REG_AGC_EXT_LUT_Msk   (0x3ffUL)
 
#define RFCU_RF_CALSTATE_REG_CALSTATE_Pos   (0UL)
 
#define RFCU_RF_CALSTATE_REG_CALSTATE_Msk   (0xfUL)
 
#define RFCU_RF_SCAN_FEEDBACK_REG_LF_RES_Pos   (0UL)
 
#define RFCU_RF_SCAN_FEEDBACK_REG_LF_RES_Msk   (0xfUL)
 
#define RFCU_RF_SCAN_FEEDBACK_REG_CP_CUR_Pos   (4UL)
 
#define RFCU_RF_SCAN_FEEDBACK_REG_CP_CUR_Msk   (0xf0UL)
 
#define RFCU_RF_REF_OSC_BLE_REG_CNT_RO_Pos   (0UL)
 
#define RFCU_RF_REF_OSC_BLE_REG_CNT_RO_Msk   (0x3fUL)
 
#define RFCU_RF_REF_OSC_BLE_REG_CNT_CLK_Pos   (6UL)
 
#define RFCU_RF_REF_OSC_BLE_REG_CNT_CLK_Msk   (0x7fc0UL)
 
#define RFCU_RF_REF_OSC_FTDF_REG_CNT_RO_Pos   (0UL)
 
#define RFCU_RF_REF_OSC_FTDF_REG_CNT_RO_Msk   (0x3fUL)
 
#define RFCU_RF_REF_OSC_FTDF_REG_CNT_CLK_Pos   (6UL)
 
#define RFCU_RF_REF_OSC_FTDF_REG_CNT_CLK_Msk   (0x7fc0UL)
 
#define RFCU_RF_CAL_CTRL_REG_SO_CAL_Pos   (0UL)
 
#define RFCU_RF_CAL_CTRL_REG_SO_CAL_Msk   (0x1UL)
 
#define RFCU_RF_CAL_CTRL_REG_EO_CAL_Pos   (1UL)
 
#define RFCU_RF_CAL_CTRL_REG_EO_CAL_Msk   (0x2UL)
 
#define RFCU_RF_CAL_CTRL_REG_MGAIN_CAL_DIS_Pos   (2UL)
 
#define RFCU_RF_CAL_CTRL_REG_MGAIN_CAL_DIS_Msk   (0x4UL)
 
#define RFCU_RF_CAL_CTRL_REG_IFF_CAL_DIS_Pos   (3UL)
 
#define RFCU_RF_CAL_CTRL_REG_IFF_CAL_DIS_Msk   (0x8UL)
 
#define RFCU_RF_CAL_CTRL_REG_DC_OFFSET_CAL_DIS_Pos   (4UL)
 
#define RFCU_RF_CAL_CTRL_REG_DC_OFFSET_CAL_DIS_Msk   (0x10UL)
 
#define RFCU_RF_CAL_CTRL_REG_VCO_CAL_DIS_Pos   (5UL)
 
#define RFCU_RF_CAL_CTRL_REG_VCO_CAL_DIS_Msk   (0x20UL)
 
#define RFCU_RF_IRQ_CTRL_REG_EO_CAL_CLEAR_Pos   (0UL)
 
#define RFCU_RF_IRQ_CTRL_REG_EO_CAL_CLEAR_Msk   (0x1UL)
 
#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFP_I_RD_Pos   (0UL)
 
#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFP_I_RD_Msk   (0xffUL)
 
#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFN_I_RD_Pos   (8UL)
 
#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFN_I_RD_Msk   (0xff00UL)
 
#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFP_Q_RD_Pos   (0UL)
 
#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFP_Q_RD_Msk   (0xffUL)
 
#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFN_Q_RD_Pos   (8UL)
 
#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFN_Q_RD_Msk   (0xff00UL)
 
#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_RFCLK_TEST_Pos   (0UL)
 
#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_RFCLK_TEST_Msk   (0x1UL)
 
#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_PLL_DXTAL16_TEST_Pos   (1UL)
 
#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_PLL_DXTAL16_TEST_Msk   (0x2UL)
 
#define RFCU_RF_SPARE1_BLE_REG_RF_VTUNE_TO_ADC_TEST_EN_Pos   (2UL)
 
#define RFCU_RF_SPARE1_BLE_REG_RF_VTUNE_TO_ADC_TEST_EN_Msk   (0x4UL)
 
#define RFCU_RF_SPARE1_BLE_REG_RF_TXDAC_CLK_POL_SEL_Pos   (3UL)
 
#define RFCU_RF_SPARE1_BLE_REG_RF_TXDAC_CLK_POL_SEL_Msk   (0x8UL)
 
#define RFCU_RF_SPARE1_BLE_REG_RF_GDAC_CUR_SET_Pos   (4UL)
 
#define RFCU_RF_SPARE1_BLE_REG_RF_GDAC_CUR_SET_Msk   (0x30UL)
 
#define RFCU_RF_SPARE1_BLE_REG_RF_SPARE_REG_Pos   (6UL)
 
#define RFCU_RF_SPARE1_BLE_REG_RF_SPARE_REG_Msk   (0xffc0UL)
 
#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_RFCLK_TEST_Pos   (0UL)
 
#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_RFCLK_TEST_Msk   (0x1UL)
 
#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_PLL_DXTAL16_TEST_Pos   (1UL)
 
#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_PLL_DXTAL16_TEST_Msk   (0x2UL)
 
#define RFCU_RF_SPARE1_FTDF_REG_RF_VTUNE_TO_ADC_TEST_EN_Pos   (2UL)
 
#define RFCU_RF_SPARE1_FTDF_REG_RF_VTUNE_TO_ADC_TEST_EN_Msk   (0x4UL)
 
#define RFCU_RF_SPARE1_FTDF_REG_RF_TXDAC_CLK_POL_SEL_Pos   (3UL)
 
#define RFCU_RF_SPARE1_FTDF_REG_RF_TXDAC_CLK_POL_SEL_Msk   (0x8UL)
 
#define RFCU_RF_SPARE1_FTDF_REG_RF_GDAC_CUR_SET_Pos   (4UL)
 
#define RFCU_RF_SPARE1_FTDF_REG_RF_GDAC_CUR_SET_Msk   (0x30UL)
 
#define RFCU_RF_SPARE1_FTDF_REG_RF_SPARE_REG_Pos   (6UL)
 
#define RFCU_RF_SPARE1_FTDF_REG_RF_SPARE_REG_Msk   (0xffc0UL)
 
#define RFCU_RF_BIAS_CTRL1_BLE_REG_MIX_BIAS_BLE_SET_Pos   (0UL)
 
#define RFCU_RF_BIAS_CTRL1_BLE_REG_MIX_BIAS_BLE_SET_Msk   (0xfUL)
 
#define RFCU_RF_BIAS_CTRL1_BLE_REG_CP_BIAS_BLE_SET_Pos   (4UL)
 
#define RFCU_RF_BIAS_CTRL1_BLE_REG_CP_BIAS_BLE_SET_Msk   (0xf0UL)
 
#define RFCU_RF_BIAS_CTRL1_BLE_REG_VCO_BIAS_BLE_SET_Pos   (8UL)
 
#define RFCU_RF_BIAS_CTRL1_BLE_REG_VCO_BIAS_BLE_SET_Msk   (0xf00UL)
 
#define RFCU_RF_BIAS_CTRL1_BLE_REG_IFF_BIAS_BLE_SET_Pos   (12UL)
 
#define RFCU_RF_BIAS_CTRL1_BLE_REG_IFF_BIAS_BLE_SET_Msk   (0xf000UL)
 
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_MIX_BIAS_FTDF_SET_Pos   (0UL)
 
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_MIX_BIAS_FTDF_SET_Msk   (0xfUL)
 
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_CP_BIAS_FTDF_SET_Pos   (4UL)
 
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_CP_BIAS_FTDF_SET_Msk   (0xf0UL)
 
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_VCO_BIAS_FTDF_SET_Pos   (8UL)
 
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_VCO_BIAS_FTDF_SET_Msk   (0xf00UL)
 
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_IFF_BIAS_FTDF_SET_Pos   (12UL)
 
#define RFCU_RF_BIAS_CTRL1_FTDF_REG_IFF_BIAS_FTDF_SET_Msk   (0xf000UL)
 
#define RFCU_RF_IFF_CTRL1_REG_IF_CAL_CAP_Pos   (0UL)
 
#define RFCU_RF_IFF_CTRL1_REG_IF_CAL_CAP_Msk   (0x1fUL)
 
#define RFCU_RF_IFF_CTRL1_REG_IF_MUTE_Pos   (5UL)
 
#define RFCU_RF_IFF_CTRL1_REG_IF_MUTE_Msk   (0x20UL)
 
#define RFCU_RF_IFF_CTRL1_REG_IFF_DCOC_DAC_DIS_Pos   (6UL)
 
#define RFCU_RF_IFF_CTRL1_REG_IFF_DCOC_DAC_DIS_Msk   (0x40UL)
 
#define RFCU_RF_IFF_CTRL1_REG_RO_TO_PINS_Pos   (7UL)
 
#define RFCU_RF_IFF_CTRL1_REG_RO_TO_PINS_Msk   (0x80UL)
 
#define RFCU_RF_IFF_CTRL1_REG_IF_SEL_SET2_GT_Pos   (8UL)
 
#define RFCU_RF_IFF_CTRL1_REG_IF_SEL_SET2_GT_Msk   (0xf00UL)
 
#define RFCU_RF_IFF_CTRL1_REG_IF_SELECT_FSM_Pos   (12UL)
 
#define RFCU_RF_IFF_CTRL1_REG_IF_SELECT_FSM_Msk   (0x1000UL)
 
#define RFCU_RF_IFF_CTRL1_REG_IFF_COMPLEX_DIS_Pos   (13UL)
 
#define RFCU_RF_IFF_CTRL1_REG_IFF_COMPLEX_DIS_Msk   (0x2000UL)
 
#define RFCU_RF_ADC_CTRL1_REG_ADC_DC_OFFSET_SEL_Pos   (0UL)
 
#define RFCU_RF_ADC_CTRL1_REG_ADC_DC_OFFSET_SEL_Msk   (0x1UL)
 
#define RFCU_RF_ADC_CTRL1_REG_ADC_MUTE_Pos   (13UL)
 
#define RFCU_RF_ADC_CTRL1_REG_ADC_MUTE_Msk   (0x2000UL)
 
#define RFCU_RF_ADC_CTRL1_REG_ADC_SIGN_Pos   (14UL)
 
#define RFCU_RF_ADC_CTRL1_REG_ADC_SIGN_Msk   (0x4000UL)
 
#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFP_I_WR_Pos   (0UL)
 
#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFP_I_WR_Msk   (0xffUL)
 
#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFN_I_WR_Pos   (8UL)
 
#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFN_I_WR_Msk   (0xff00UL)
 
#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFP_Q_WR_Pos   (0UL)
 
#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFP_Q_WR_Msk   (0xffUL)
 
#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFN_Q_WR_Pos   (8UL)
 
#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFN_Q_WR_Msk   (0xff00UL)
 
#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_DOWN_Pos   (5UL)
 
#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_DOWN_Msk   (0x60UL)
 
#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_UP_Pos   (7UL)
 
#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_UP_Msk   (0x180UL)
 
#define RFCU_RF_PA_CTRL_REG_PA_FAST_DISCHARGE_EN_Pos   (9UL)
 
#define RFCU_RF_PA_CTRL_REG_PA_FAST_DISCHARGE_EN_Msk   (0x200UL)
 
#define RFCU_RF_PA_CTRL_REG_LEVEL_LDO_RFPA_Pos   (11UL)
 
#define RFCU_RF_PA_CTRL_REG_LEVEL_LDO_RFPA_Msk   (0x7800UL)
 
#define RFCU_RF_MGC_CTRL_REG_MGC_GAIN_SET_Pos   (0UL)
 
#define RFCU_RF_MGC_CTRL_REG_MGC_GAIN_SET_Msk   (0x1UL)
 
#define RFCU_RF_MGC_CTRL_REG_MGC_POLE_SW_Pos   (1UL)
 
#define RFCU_RF_MGC_CTRL_REG_MGC_POLE_SW_Msk   (0x2UL)
 
#define RFCU_RF_MGC_CTRL_REG_GAUSS_DAC_CTRL_Pos   (2UL)
 
#define RFCU_RF_MGC_CTRL_REG_GAUSS_DAC_CTRL_Msk   (0xcUL)
 
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V0_Pos   (0UL)
 
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V0_Msk   (0x7UL)
 
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V1_Pos   (3UL)
 
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V1_Msk   (0x38UL)
 
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V2_Pos   (6UL)
 
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V2_Msk   (0x1c0UL)
 
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V3_Pos   (9UL)
 
#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V3_Msk   (0xe00UL)
 
#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V0_Pos   (12UL)
 
#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V0_Msk   (0x3000UL)
 
#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V1_Pos   (14UL)
 
#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V1_Msk   (0xc000UL)
 
#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_SET_Pos   (0UL)
 
#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_SET_Msk   (0x3UL)
 
#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_EN_Pos   (2UL)
 
#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_EN_Msk   (0x4UL)
 
#define RFCU_RF_PFD_CTRL_REG_PFD_POLARITY_Pos   (3UL)
 
#define RFCU_RF_PFD_CTRL_REG_PFD_POLARITY_Msk   (0x8UL)
 
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_RX_Pos   (0UL)
 
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_RX_Msk   (0xfUL)
 
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_TX_Pos   (4UL)
 
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_TX_Msk   (0xf0UL)
 
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_RX_Pos   (8UL)
 
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_RX_Msk   (0xf00UL)
 
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_TX_Pos   (12UL)
 
#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_TX_Msk   (0xf000UL)
 
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_RX_Pos   (0UL)
 
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_RX_Msk   (0xfUL)
 
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_TX_Pos   (4UL)
 
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_TX_Msk   (0xf0UL)
 
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_RX_Pos   (8UL)
 
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_RX_Msk   (0xf00UL)
 
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_TX_Pos   (12UL)
 
#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_TX_Msk   (0xf000UL)
 
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_RX_Pos   (0UL)
 
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_RX_Msk   (0xfUL)
 
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_TX_Pos   (4UL)
 
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_TX_Msk   (0xf0UL)
 
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_RX_Pos   (8UL)
 
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_RX_Msk   (0xf00UL)
 
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_TX_Pos   (12UL)
 
#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_TX_Msk   (0xf000UL)
 
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_RX_Pos   (0UL)
 
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_RX_Msk   (0xfUL)
 
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_TX_Pos   (4UL)
 
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_TX_Msk   (0xf0UL)
 
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_RX_Pos   (8UL)
 
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_RX_Msk   (0xf00UL)
 
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_TX_Pos   (12UL)
 
#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_TX_Msk   (0xf000UL)
 
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_GMBIAS_BLE_Pos   (0UL)
 
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_GMBIAS_BLE_Msk   (0xfUL)
 
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_IBIAS_BLE_Pos   (4UL)
 
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_IBIAS_BLE_Msk   (0xf0UL)
 
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_VCM_BLE_Pos   (8UL)
 
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_VCM_BLE_Msk   (0xf00UL)
 
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_SPARE_BLE_Pos   (12UL)
 
#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_SPARE_BLE_Msk   (0xf000UL)
 
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_GMBIAS_FTDF_Pos   (0UL)
 
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_GMBIAS_FTDF_Msk   (0xfUL)
 
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_IBIAS_FTDF_Pos   (4UL)
 
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_IBIAS_FTDF_Msk   (0xf0UL)
 
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_VCM_FTDF_Pos   (8UL)
 
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_VCM_FTDF_Msk   (0xf00UL)
 
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_SPARE_Pos   (12UL)
 
#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_SPARE_Msk   (0xf000UL)
 
#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_BLE_Pos   (0UL)
 
#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_BLE_Msk   (0x1fUL)
 
#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_SELECT_Pos   (5UL)
 
#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_SELECT_Msk   (0x20UL)
 
#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_FTDF_Pos   (6UL)
 
#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_FTDF_Msk   (0x7c0UL)
 
#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_BLE_Pos   (0UL)
 
#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_BLE_Msk   (0x1fUL)
 
#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_SEL_Pos   (5UL)
 
#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_SEL_Msk   (0x20UL)
 
#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_BLE_Pos   (6UL)
 
#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_BLE_Msk   (0x40UL)
 
#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_FTDF_Pos   (7UL)
 
#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_FTDF_Msk   (0x80UL)
 
#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_FTDF_Pos   (8UL)
 
#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_FTDF_Msk   (0x1f00UL)
 
#define RFCU_RF_TDC_CTRL_REG_CTRL_FAST_Pos   (0UL)
 
#define RFCU_RF_TDC_CTRL_REG_CTRL_FAST_Msk   (0xfUL)
 
#define RFCU_RF_TDC_CTRL_REG_CTRL_SLOW_Pos   (4UL)
 
#define RFCU_RF_TDC_CTRL_REG_CTRL_SLOW_Msk   (0xf0UL)
 
#define RFCU_RF_TDC_CTRL_REG_CAL_PH_1_Pos   (8UL)
 
#define RFCU_RF_TDC_CTRL_REG_CAL_PH_1_Msk   (0x100UL)
 
#define RFCU_RF_TDC_CTRL_REG_CAL_PH_2_Pos   (9UL)
 
#define RFCU_RF_TDC_CTRL_REG_CAL_PH_2_Msk   (0x200UL)
 
#define RFCU_RF_TDC_CTRL_REG_REF_CTRL_Pos   (10UL)
 
#define RFCU_RF_TDC_CTRL_REG_REF_CTRL_Msk   (0xc00UL)
 
#define RFCU_RF_TDC_CTRL_REG_TDC_CONNECT_Pos   (12UL)
 
#define RFCU_RF_TDC_CTRL_REG_TDC_CONNECT_Msk   (0x1000UL)
 
#define RFCU_RF_IO_CTRL1_REG_RFIO_TRIM1_CAP_Pos   (0UL)
 
#define RFCU_RF_IO_CTRL1_REG_RFIO_TRIM1_CAP_Msk   (0xffUL)
 
#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_LF_Pos   (0UL)
 
#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_LF_Msk   (0x3fUL)
 
#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_HF_Pos   (6UL)
 
#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_HF_Msk   (0xfc0UL)
 
#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_HI_Pos   (0UL)
 
#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_HI_Msk   (0x3fUL)
 
#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_LO_Pos   (6UL)
 
#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_LO_Msk   (0xfc0UL)
 
#define RFCU_RF_LNA_CTRL3_REG_LNA_TRIM_CGS_Pos   (0UL)
 
#define RFCU_RF_LNA_CTRL3_REG_LNA_TRIM_CGS_Msk   (0x1fUL)
 
#define RFCU_RF_VCO_AMP_CTRL1_REG_VCO_AMPL_MODE_Pos   (0UL)
 
#define RFCU_RF_VCO_AMP_CTRL1_REG_VCO_AMPL_MODE_Msk   (0x7fUL)
 
#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_TX_Pos   (0UL)
 
#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_TX_Msk   (0xffUL)
 
#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_RX_Pos   (8UL)
 
#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_RX_Msk   (0xff00UL)
 
#define RFCU_RF_TX_PWR_BLE_REG_TX_POWER_SET_Pos   (0UL)
 
#define RFCU_RF_TX_PWR_BLE_REG_TX_POWER_SET_Msk   (0x7UL)
 
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)
 
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)
 
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)
 
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)
 
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)
 
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)
 
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)
 
#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)
 
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)
 
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)
 
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)
 
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)
 
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)
 
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)
 
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)
 
#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)
 
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)
 
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)
 
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)
 
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)
 
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)
 
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)
 
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)
 
#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)
 
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)
 
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)
 
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)
 
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)
 
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)
 
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)
 
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)
 
#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)
 
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)
 
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)
 
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)
 
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)
 
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)
 
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)
 
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)
 
#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)
 
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)
 
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)
 
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)
 
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)
 
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)
 
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)
 
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)
 
#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)
 
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)
 
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)
 
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)
 
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)
 
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)
 
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)
 
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)
 
#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)
 
#define RFCU_RF_TX_PWR_FTDF_REG_TX_POWER_SET_Pos   (0UL)
 
#define RFCU_RF_TX_PWR_FTDF_REG_TX_POWER_SET_Msk   (0x7UL)
 
#define RFCU_RF_TX_PWR_LUT_RD_REG_RF_TX_PWR_LUT_RD_Pos   (0UL)
 
#define RFCU_RF_TX_PWR_LUT_RD_REG_RF_TX_PWR_LUT_RD_Msk   (0xfffUL)
 
#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFN_TRIM_RX_Pos   (0UL)
 
#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFN_TRIM_RX_Msk   (0xfUL)
 
#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFP_TRIM_RX_Pos   (4UL)
 
#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFP_TRIM_RX_Msk   (0xf0UL)
 
#define RFCU_RF_DIV_IQ_RX_REG_DIV2_IQ_TRIM_RX_SPARE_Pos   (8UL)
 
#define RFCU_RF_DIV_IQ_RX_REG_DIV2_IQ_TRIM_RX_SPARE_Msk   (0x100UL)
 
#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFN_TRIM_TX_Pos   (0UL)
 
#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFN_TRIM_TX_Msk   (0xfUL)
 
#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFP_TRIM_TX_Pos   (4UL)
 
#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFP_TRIM_TX_Msk   (0xf0UL)
 
#define RFCU_RF_DIV_IQ_TX_REG_DIV2_IQ_TRIM_TX_SPARE_Pos   (8UL)
 
#define RFCU_RF_DIV_IQ_TX_REG_DIV2_IQ_TRIM_TX_SPARE_Msk   (0x100UL)
 
#define RFCU_RF_LO_IQ_TRIM_REG_RF_LO_IQ_TRIM_Pos   (0UL)
 
#define RFCU_RF_LO_IQ_TRIM_REG_RF_LO_IQ_TRIM_Msk   (0xffffUL)
 
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_BLE_Pos   (0UL)
 
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_BLE_Msk   (0x1fUL)
 
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_SEL_Pos   (5UL)
 
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_SEL_Msk   (0x20UL)
 
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_FIXED_CAP_ON_Pos   (6UL)
 
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_FIXED_CAP_ON_Msk   (0x40UL)
 
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_FTDF_Pos   (7UL)
 
#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_FTDF_Msk   (0xf80UL)
 
#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_CAL_CAP_RD_Pos   (0UL)
 
#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_CAL_CAP_RD_Msk   (0x1fUL)
 
#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_FIXED_CAP_ON_RD_Pos   (5UL)
 
#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_FIXED_CAP_ON_RD_Msk   (0x20UL)
 
#define RFCU_RF_IFF_RESULT_REG_IF_CAL_CAP_RD_Pos   (0UL)
 
#define RFCU_RF_IFF_RESULT_REG_IF_CAL_CAP_RD_Msk   (0x1fUL)
 
#define RFCU_RF_IFF_CC_BLE_SET1_REG_IF_CAL_CAP_WR_Pos   (0UL)
 
#define RFCU_RF_IFF_CC_BLE_SET1_REG_IF_CAL_CAP_WR_Msk   (0x1fUL)
 
#define RFCU_RF_IFF_CC_BLE_SET2_REG_IF_CAL_CAP_WR_Pos   (0UL)
 
#define RFCU_RF_IFF_CC_BLE_SET2_REG_IF_CAL_CAP_WR_Msk   (0x1fUL)
 
#define RFCU_RF_IFF_CC_FTDF_SET1_REG_IF_CAL_CAP_WR_Pos   (0UL)
 
#define RFCU_RF_IFF_CC_FTDF_SET1_REG_IF_CAL_CAP_WR_Msk   (0x1fUL)
 
#define RFCU_RF_IFF_CC_FTDF_SET2_REG_IF_CAL_CAP_WR_Pos   (0UL)
 
#define RFCU_RF_IFF_CC_FTDF_SET2_REG_IF_CAL_CAP_WR_Msk   (0x1fUL)
 
#define RFCU_RF_IFF_CAL_CAP_STAT_REG_IF_CAL_CAP_RD_Pos   (0UL)
 
#define RFCU_RF_IFF_CAL_CAP_STAT_REG_IF_CAL_CAP_RD_Msk   (0x1fUL)
 
#define RFCU_RF_MIX_CAL_CAP_STAT_REG_MIX_CAL_CAP_RD_Pos   (0UL)
 
#define RFCU_RF_MIX_CAL_CAP_STAT_REG_MIX_CAL_CAP_RD_Msk   (0x1fUL)
 
#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_CAL_CAP_RD_Pos   (0UL)
 
#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_CAL_CAP_RD_Msk   (0x1fUL)
 
#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_SHORT_R4_RD_Pos   (5UL)
 
#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_SHORT_R4_RD_Msk   (0x20UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dem_dcparcal_en_ble_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dem_dcparcal_en_ble_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_spare2_en_ble_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_spare2_en_ble_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_dem_agcunfreeze_en_ble_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_dem_agcunfreeze_en_ble_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_spare3_en_ble_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_spare3_en_ble_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_dem_sigdetect_en_ble_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_dem_sigdetect_en_ble_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_spare4_en_ble_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_spare4_en_ble_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dem_dcparcal_en_ftdf_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dem_dcparcal_en_ftdf_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_spare2_en_ftdf_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_spare2_en_ftdf_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_dem_agcunfreeze_en_ftdf_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_dem_agcunfreeze_en_ftdf_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_spare3_en_ftdf_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_spare3_en_ftdf_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_dem_sigdetect_en_ftdf_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_dem_sigdetect_en_ftdf_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_spare4_en_ftdf_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_spare4_en_ftdf_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_rx_Pos   (0UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_rx_Msk   (0x1fUL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_tx_Pos   (5UL)
 
#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_tx_Msk   (0x3e0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_SET_OFFSET_Pos   (0UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_SET_OFFSET_Msk   (0xffUL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_RESET_OFFSET_Pos   (8UL)
 
#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_RESET_OFFSET_Msk   (0xff00UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_EN_Pos   (0UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_EN_Msk   (0x1UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CORE_EN_Pos   (1UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CORE_EN_Msk   (0x2UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CGM_EN_Pos   (2UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CGM_EN_Msk   (0x4UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MIX_LDO_EN_Pos   (3UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MIX_LDO_EN_Msk   (0x8UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFF_LDO_EN_Pos   (4UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFF_LDO_EN_Msk   (0x10UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFFADC_LDO_EN_Pos   (5UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFFADC_LDO_EN_Msk   (0x20UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_LDO_EN_Pos   (6UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_LDO_EN_Msk   (0x40UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MD_LDO_EN_Pos   (7UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MD_LDO_EN_Msk   (0x80UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PFD_LDO_EN_Pos   (8UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PFD_LDO_EN_Msk   (0x100UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_LDO_EN_Pos   (9UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_LDO_EN_Msk   (0x200UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_SWITCH_EN_Pos   (10UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_SWITCH_EN_Msk   (0x400UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_BIAS_EN_Pos   (11UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_BIAS_EN_Msk   (0x800UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_BIAS_EN_Pos   (12UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_BIAS_EN_Msk   (0x1000UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_ZERO_Pos   (13UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_ZERO_Msk   (0x2000UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_RAMP_EN_Pos   (14UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_RAMP_EN_Msk   (0x4000UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_EN_Pos   (15UL)
 
#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_EN_Msk   (0x8000UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_MIX_EN_Pos   (0UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_MIX_EN_Msk   (0x1UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFF_EN_Pos   (1UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFF_EN_Msk   (0x2UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_ADC_EN_Pos   (2UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_ADC_EN_Msk   (0x4UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_EN_Pos   (3UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_EN_Msk   (0x8UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_MD_EN_Pos   (4UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_MD_EN_Msk   (0x10UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_EN_Pos   (5UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_EN_Msk   (0x20UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_PDF_EN_Pos   (6UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_PDF_EN_Msk   (0x40UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_EN_Pos   (7UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_EN_Msk   (0x80UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RFIO_TXRX_Pos   (8UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RFIO_TXRX_Msk   (0x100UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_PA_EN_Pos   (9UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_PA_EN_Msk   (0x200UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RXIQ_EN_Pos   (10UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RXIQ_EN_Msk   (0x400UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_DIV2_EN_Pos   (11UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_DIV2_EN_Msk   (0x800UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_BIAS_SH_OPEN_Pos   (12UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_BIAS_SH_OPEN_Msk   (0x1000UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_BIAS_SH_OPEN_Pos   (13UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_BIAS_SH_OPEN_Msk   (0x2000UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFFMIX_BIAS_SH_OPEN_Pos   (14UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFFMIX_BIAS_SH_OPEN_Msk   (0x4000UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_BIAS_SH_Pos   (15UL)
 
#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_BIAS_SH_Msk   (0x8000UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_MIX_BIAS_SH_Pos   (0UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_MIX_BIAS_SH_Msk   (0x1UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLL_DIG_EN_Pos   (1UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLL_DIG_EN_Msk   (0x2UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLLCLOSED_EN_Pos   (2UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLLCLOSED_EN_Msk   (0x4UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_DEM_EN_Pos   (3UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_DEM_EN_Msk   (0x8UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_ZERO_EN_Pos   (4UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_ZERO_EN_Msk   (0x10UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_CAL_EN_Pos   (5UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_CAL_EN_Msk   (0x20UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TDC_EN_Pos   (6UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TDC_EN_Msk   (0x40UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RFIO_EN_Pos   (7UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RFIO_EN_Msk   (0x80UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_EN_Pos   (8UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_EN_Msk   (0x100UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_SH_Pos   (9UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_SH_Msk   (0x200UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RADIO_EN_Pos   (10UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RADIO_EN_Msk   (0x400UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_ADC_CLK_EN_Pos   (11UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_ADC_CLK_EN_Msk   (0x800UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TR_PWRM_OFF_EN_Pos   (12UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TR_PWRM_OFF_EN_Msk   (0x1000UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TXDAC_EN_Pos   (13UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TXDAC_EN_Msk   (0x2000UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE2_EN_Pos   (14UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE2_EN_Msk   (0x4000UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE3_EN_Pos   (15UL)
 
#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE3_EN_Msk   (0x8000UL)
 
#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_SPARE4_EN_Pos   (0UL)
 
#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_SPARE4_EN_Msk   (0x1UL)
 
#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_DEM_FTDF_EN_Pos   (1UL)
 
#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_DEM_FTDF_EN_Msk   (0x2UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_RX_Pos   (0UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_RX_Msk   (0x1UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_TX_Pos   (1UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_TX_Msk   (0x2UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_RX_Pos   (2UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_RX_Msk   (0x4UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_TX_Pos   (3UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_TX_Msk   (0x8UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_RX_Pos   (4UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_RX_Msk   (0x10UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_TX_Pos   (5UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_TX_Msk   (0x20UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Pos   (6UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Msk   (0x40UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Pos   (7UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Msk   (0x80UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_RX_Pos   (8UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_RX_Msk   (0x100UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_TX_Pos   (9UL)
 
#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_TX_Msk   (0x200UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_RX_Pos   (0UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_RX_Msk   (0x1UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_TX_Pos   (1UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_TX_Msk   (0x2UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_RX_Pos   (2UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_RX_Msk   (0x4UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_TX_Pos   (3UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_TX_Msk   (0x8UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_RX_Pos   (4UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_RX_Msk   (0x10UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_TX_Pos   (5UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_TX_Msk   (0x20UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Pos   (6UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Msk   (0x40UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Pos   (7UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Msk   (0x80UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_RX_Pos   (8UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_RX_Msk   (0x100UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_TX_Pos   (9UL)
 
#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_TX_Msk   (0x200UL)
 
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT0_POL_Pos   (0UL)
 
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT0_POL_Msk   (0x1UL)
 
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT1_POL_Pos   (1UL)
 
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT1_POL_Msk   (0x2UL)
 
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT2_POL_Pos   (2UL)
 
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT2_POL_Msk   (0x4UL)
 
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT3_POL_Pos   (3UL)
 
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT3_POL_Msk   (0x8UL)
 
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT4_POL_Pos   (4UL)
 
#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT4_POL_Msk   (0x10UL)
 
#define RFPT_RFPT_CTRL_REG_RFPT_PACK_EN_Pos   (0UL)
 
#define RFPT_RFPT_CTRL_REG_RFPT_PACK_EN_Msk   (0x1UL)
 
#define RFPT_RFPT_CTRL_REG_RFPT_PACK_SEL_Pos   (1UL)
 
#define RFPT_RFPT_CTRL_REG_RFPT_PACK_SEL_Msk   (0x6UL)
 
#define RFPT_RFPT_CTRL_REG_RFPT_PACK_ADC_TYPE_Pos   (3UL)
 
#define RFPT_RFPT_CTRL_REG_RFPT_PACK_ADC_TYPE_Msk   (0x8UL)
 
#define RFPT_RFPT_CTRL_REG_RFPT_CIRC_EN_Pos   (4UL)
 
#define RFPT_RFPT_CTRL_REG_RFPT_CIRC_EN_Msk   (0x10UL)
 
#define RFPT_RFPT_CTRL_REG_RFPT_BREQ_FORCE_Pos   (5UL)
 
#define RFPT_RFPT_CTRL_REG_RFPT_BREQ_FORCE_Msk   (0x20UL)
 
#define RFPT_RFPT_ADDRL_REG_RFPT_ADDRL_Pos   (2UL)
 
#define RFPT_RFPT_ADDRL_REG_RFPT_ADDRL_Msk   (0xfffcUL)
 
#define RFPT_RFPT_ADDRH_REG_RFPT_ADDRH_Pos   (0UL)
 
#define RFPT_RFPT_ADDRH_REG_RFPT_ADDRH_Msk   (0x3UL)
 
#define RFPT_RFPT_LEN_REG_RFPT_LEN_Pos   (0UL)
 
#define RFPT_RFPT_LEN_REG_RFPT_LEN_Msk   (0x7fffUL)
 
#define RFPT_RFPT_STAT_REG_RFPT_ACTIVE_Pos   (0UL)
 
#define RFPT_RFPT_STAT_REG_RFPT_ACTIVE_Msk   (0x1UL)
 
#define RFPT_RFPT_STAT_REG_RFPT_OFLOW_STK_Pos   (1UL)
 
#define RFPT_RFPT_STAT_REG_RFPT_OFLOW_STK_Msk   (0x2UL)
 
#define RFPT_RFPT_CRV_ADDRL_REG_RFPT_CRV_ADDRL_Pos   (2UL)
 
#define RFPT_RFPT_CRV_ADDRL_REG_RFPT_CRV_ADDRL_Msk   (0xfffcUL)
 
#define RFPT_RFPT_CRV_ADDRH_REG_RFPT_CRV_ADDRH_Pos   (0UL)
 
#define RFPT_RFPT_CRV_ADDRH_REG_RFPT_CRV_ADDRH_Msk   (0x3UL)
 
#define RFPT_RFPT_CRV_LEN_REG_RFPT_CRV_LEN_Pos   (0UL)
 
#define RFPT_RFPT_CRV_LEN_REG_RFPT_CRV_LEN_Msk   (0x7fffUL)
 
#define SPI_SPI_CTRL_REG_SPI_ON_Pos   (0UL)
 
#define SPI_SPI_CTRL_REG_SPI_ON_Msk   (0x1UL)
 
#define SPI_SPI_CTRL_REG_SPI_PHA_Pos   (1UL)
 
#define SPI_SPI_CTRL_REG_SPI_PHA_Msk   (0x2UL)
 
#define SPI_SPI_CTRL_REG_SPI_POL_Pos   (2UL)
 
#define SPI_SPI_CTRL_REG_SPI_POL_Msk   (0x4UL)
 
#define SPI_SPI_CTRL_REG_SPI_CLK_Pos   (3UL)
 
#define SPI_SPI_CTRL_REG_SPI_CLK_Msk   (0x18UL)
 
#define SPI_SPI_CTRL_REG_SPI_DO_Pos   (5UL)
 
#define SPI_SPI_CTRL_REG_SPI_DO_Msk   (0x20UL)
 
#define SPI_SPI_CTRL_REG_SPI_SMN_Pos   (6UL)
 
#define SPI_SPI_CTRL_REG_SPI_SMN_Msk   (0x40UL)
 
#define SPI_SPI_CTRL_REG_SPI_WORD_Pos   (7UL)
 
#define SPI_SPI_CTRL_REG_SPI_WORD_Msk   (0x180UL)
 
#define SPI_SPI_CTRL_REG_SPI_RST_Pos   (9UL)
 
#define SPI_SPI_CTRL_REG_SPI_RST_Msk   (0x200UL)
 
#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Pos   (10UL)
 
#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Msk   (0x400UL)
 
#define SPI_SPI_CTRL_REG_SPI_TXH_Pos   (11UL)
 
#define SPI_SPI_CTRL_REG_SPI_TXH_Msk   (0x800UL)
 
#define SPI_SPI_CTRL_REG_SPI_DI_Pos   (12UL)
 
#define SPI_SPI_CTRL_REG_SPI_DI_Msk   (0x1000UL)
 
#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Pos   (13UL)
 
#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Msk   (0x2000UL)
 
#define SPI_SPI_CTRL_REG_SPI_MINT_Pos   (14UL)
 
#define SPI_SPI_CTRL_REG_SPI_MINT_Msk   (0x4000UL)
 
#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Pos   (15UL)
 
#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Msk   (0x8000UL)
 
#define SPI_SPI_RX_TX_REG0_SPI_DATA0_Pos   (0UL)
 
#define SPI_SPI_RX_TX_REG0_SPI_DATA0_Msk   (0xffffUL)
 
#define SPI_SPI_RX_TX_REG1_SPI_DATA1_Pos   (0UL)
 
#define SPI_SPI_RX_TX_REG1_SPI_DATA1_Msk   (0xffffUL)
 
#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Pos   (0UL)
 
#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Msk   (0xffffUL)
 
#define SPI_SPI_CTRL_REG1_SPI_FIFO_MODE_Pos   (0UL)
 
#define SPI_SPI_CTRL_REG1_SPI_FIFO_MODE_Msk   (0x3UL)
 
#define SPI_SPI_CTRL_REG1_SPI_PRIORITY_Pos   (2UL)
 
#define SPI_SPI_CTRL_REG1_SPI_PRIORITY_Msk   (0x4UL)
 
#define SPI_SPI_CTRL_REG1_SPI_BUSY_Pos   (3UL)
 
#define SPI_SPI_CTRL_REG1_SPI_BUSY_Msk   (0x8UL)
 
#define SPI_SPI_CTRL_REG1_SPI_9BIT_VAL_Pos   (4UL)
 
#define SPI_SPI_CTRL_REG1_SPI_9BIT_VAL_Msk   (0x10UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_ON_Pos   (0UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_ON_Msk   (0x1UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_PHA_Pos   (1UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_PHA_Msk   (0x2UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_POL_Pos   (2UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_POL_Msk   (0x4UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_CLK_Pos   (3UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_CLK_Msk   (0x18UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_DO_Pos   (5UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_DO_Msk   (0x20UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_SMN_Pos   (6UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_SMN_Msk   (0x40UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_WORD_Pos   (7UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_WORD_Msk   (0x180UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_RST_Pos   (9UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_RST_Msk   (0x200UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Pos   (10UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Msk   (0x400UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_TXH_Pos   (11UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_TXH_Msk   (0x800UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_DI_Pos   (12UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_DI_Msk   (0x1000UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Pos   (13UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Msk   (0x2000UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_MINT_Pos   (14UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_MINT_Msk   (0x4000UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Pos   (15UL)
 
#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Msk   (0x8000UL)
 
#define SPI2_SPI2_RX_TX_REG0_SPI_DATA0_Pos   (0UL)
 
#define SPI2_SPI2_RX_TX_REG0_SPI_DATA0_Msk   (0xffffUL)
 
#define SPI2_SPI2_RX_TX_REG1_SPI_DATA1_Pos   (0UL)
 
#define SPI2_SPI2_RX_TX_REG1_SPI_DATA1_Msk   (0xffffUL)
 
#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Pos   (0UL)
 
#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Msk   (0xffffUL)
 
#define SPI2_SPI2_CTRL_REG1_SPI_FIFO_MODE_Pos   (0UL)
 
#define SPI2_SPI2_CTRL_REG1_SPI_FIFO_MODE_Msk   (0x3UL)
 
#define SPI2_SPI2_CTRL_REG1_SPI_PRIORITY_Pos   (2UL)
 
#define SPI2_SPI2_CTRL_REG1_SPI_PRIORITY_Msk   (0x4UL)
 
#define SPI2_SPI2_CTRL_REG1_SPI_BUSY_Pos   (3UL)
 
#define SPI2_SPI2_CTRL_REG1_SPI_BUSY_Msk   (0x8UL)
 
#define SPI2_SPI2_CTRL_REG1_SPI_9BIT_VAL_Pos   (4UL)
 
#define SPI2_SPI2_CTRL_REG1_SPI_9BIT_VAL_Msk   (0x10UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_EN_Pos   (0UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_EN_Msk   (0x1UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_ONESHOT_MODE_EN_Pos   (1UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_ONESHOT_MODE_EN_Msk   (0x2UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_COUNT_DOWN_EN_Pos   (2UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_COUNT_DOWN_EN_Msk   (0x4UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN1_EVENT_FALL_EN_Pos   (3UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN1_EVENT_FALL_EN_Msk   (0x8UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN2_EVENT_FALL_EN_Pos   (4UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN2_EVENT_FALL_EN_Msk   (0x10UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Pos   (5UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Msk   (0x20UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_FREE_RUN_MODE_EN_Pos   (6UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_FREE_RUN_MODE_EN_Msk   (0x40UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_SYS_CLK_EN_Pos   (7UL)
 
#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_SYS_CLK_EN_Msk   (0x80UL)
 
#define TIMER1_CAPTIM_TIMER_VAL_REG_CAPTIM_TIMER_VALUE_Pos   (0UL)
 
#define TIMER1_CAPTIM_TIMER_VAL_REG_CAPTIM_TIMER_VALUE_Msk   (0xffffUL)
 
#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN1_STATE_Pos   (0UL)
 
#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN1_STATE_Msk   (0x1UL)
 
#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN2_STATE_Pos   (1UL)
 
#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN2_STATE_Msk   (0x2UL)
 
#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_ONESHOT_PHASE_Pos   (2UL)
 
#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_ONESHOT_PHASE_Msk   (0xcUL)
 
#define TIMER1_CAPTIM_GPIO1_CONF_REG_CAPTIM_GPIO1_CONF_Pos   (0UL)
 
#define TIMER1_CAPTIM_GPIO1_CONF_REG_CAPTIM_GPIO1_CONF_Msk   (0x3fUL)
 
#define TIMER1_CAPTIM_GPIO2_CONF_REG_CAPTIM_GPIO2_CONF_Pos   (0UL)
 
#define TIMER1_CAPTIM_GPIO2_CONF_REG_CAPTIM_GPIO2_CONF_Msk   (0x3fUL)
 
#define TIMER1_CAPTIM_RELOAD_REG_CAPTIM_RELOAD_Pos   (0UL)
 
#define TIMER1_CAPTIM_RELOAD_REG_CAPTIM_RELOAD_Msk   (0xffffUL)
 
#define TIMER1_CAPTIM_SHOTWIDTH_REG_CAPTIM_SHOTWIDTH_Pos   (0UL)
 
#define TIMER1_CAPTIM_SHOTWIDTH_REG_CAPTIM_SHOTWIDTH_Msk   (0xffffUL)
 
#define TIMER1_CAPTIM_PRESCALER_REG_CAPTIM_PRESCALER_Pos   (0UL)
 
#define TIMER1_CAPTIM_PRESCALER_REG_CAPTIM_PRESCALER_Msk   (0xffffUL)
 
#define TIMER1_CAPTIM_CAPTURE_GPIO1_REG_CAPTIM_CAPTURE_GPIO1_Pos   (0UL)
 
#define TIMER1_CAPTIM_CAPTURE_GPIO1_REG_CAPTIM_CAPTURE_GPIO1_Msk   (0xffffUL)
 
#define TIMER1_CAPTIM_CAPTURE_GPIO2_REG_CAPTIM_CAPTURE_GPIO2_Pos   (0UL)
 
#define TIMER1_CAPTIM_CAPTURE_GPIO2_REG_CAPTIM_CAPTURE_GPIO2_Msk   (0xffffUL)
 
#define TIMER1_CAPTIM_PRESCALER_VAL_REG_CAPTIM_PRESCALER_VAL_Pos   (0UL)
 
#define TIMER1_CAPTIM_PRESCALER_VAL_REG_CAPTIM_PRESCALER_VAL_Msk   (0xffffUL)
 
#define TIMER1_CAPTIM_PWM_FREQ_REG_CAPTIM_PWM_FREQ_Pos   (0UL)
 
#define TIMER1_CAPTIM_PWM_FREQ_REG_CAPTIM_PWM_FREQ_Msk   (0xffffUL)
 
#define TIMER1_CAPTIM_PWM_DC_REG_CAPTIM_PWM_DC_Pos   (0UL)
 
#define TIMER1_CAPTIM_PWM_DC_REG_CAPTIM_PWM_DC_Msk   (0xffffUL)
 
#define TIMER1_CAPTIM_TIMER_HVAL_REG_CAPTIM_TIMER_HVALUE_Pos   (0UL)
 
#define TIMER1_CAPTIM_TIMER_HVAL_REG_CAPTIM_TIMER_HVALUE_Msk   (0xffffUL)
 
#define TIMER1_CAPTIM_RELOAD_HIGH_REG_CAPTIM_RELOAD_HIGH_Pos   (0UL)
 
#define TIMER1_CAPTIM_RELOAD_HIGH_REG_CAPTIM_RELOAD_HIGH_Msk   (0xffffUL)
 
#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG_CAPTIM_CAPTURE_HIGH_GPIO1_Pos   (0UL)
 
#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG_CAPTIM_CAPTURE_HIGH_GPIO1_Msk   (0xffffUL)
 
#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG_CAPTIM_CAPTURE_HIGH_GPIO2_Pos   (0UL)
 
#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG_CAPTIM_CAPTURE_HIGH_GPIO2_Msk   (0xffffUL)
 
#define TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG_CAPTIM_SHOTWIDTH_HIGH_Pos   (0UL)
 
#define TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG_CAPTIM_SHOTWIDTH_HIGH_Msk   (0xffffUL)
 
#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Pos   (0UL)
 
#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Msk   (0x1UL)
 
#define TRNG_TRNG_CTRL_REG_TRNG_MODE_Pos   (1UL)
 
#define TRNG_TRNG_CTRL_REG_TRNG_MODE_Msk   (0x2UL)
 
#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Pos   (0UL)
 
#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Msk   (0x1fUL)
 
#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Pos   (5UL)
 
#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Msk   (0x20UL)
 
#define TRNG_TRNG_VER_REG_TRNG_SVN_Pos   (0UL)
 
#define TRNG_TRNG_VER_REG_TRNG_SVN_Msk   (0xffffUL)
 
#define TRNG_TRNG_VER_REG_TRNG_MIN_Pos   (16UL)
 
#define TRNG_TRNG_VER_REG_TRNG_MIN_Msk   (0xff0000UL)
 
#define TRNG_TRNG_VER_REG_TRNG_MAJ_Pos   (24UL)
 
#define TRNG_TRNG_VER_REG_TRNG_MAJ_Msk   (0xff000000UL)
 
#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Pos   (0UL)
 
#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Msk   (0xffUL)
 
#define UART_UART_IER_DLH_REG_ERBFI_dlh0_Pos   (0UL)
 
#define UART_UART_IER_DLH_REG_ERBFI_dlh0_Msk   (0x1UL)
 
#define UART_UART_IER_DLH_REG_ETBEI_dlh1_Pos   (1UL)
 
#define UART_UART_IER_DLH_REG_ETBEI_dlh1_Msk   (0x2UL)
 
#define UART_UART_IER_DLH_REG_ELSI_dhl2_Pos   (2UL)
 
#define UART_UART_IER_DLH_REG_ELSI_dhl2_Msk   (0x4UL)
 
#define UART_UART_IER_DLH_REG_PTIME_dlh7_Pos   (7UL)
 
#define UART_UART_IER_DLH_REG_PTIME_dlh7_Msk   (0x80UL)
 
#define UART_UART_IIR_FCR_REG_IIR_FCR_Pos   (0UL)
 
#define UART_UART_IIR_FCR_REG_IIR_FCR_Msk   (0xffffUL)
 
#define UART_UART_LCR_REG_UART_DLS_Pos   (0UL)
 
#define UART_UART_LCR_REG_UART_DLS_Msk   (0x3UL)
 
#define UART_UART_LCR_REG_UART_STOP_Pos   (2UL)
 
#define UART_UART_LCR_REG_UART_STOP_Msk   (0x4UL)
 
#define UART_UART_LCR_REG_UART_PEN_Pos   (3UL)
 
#define UART_UART_LCR_REG_UART_PEN_Msk   (0x8UL)
 
#define UART_UART_LCR_REG_UART_EPS_Pos   (4UL)
 
#define UART_UART_LCR_REG_UART_EPS_Msk   (0x10UL)
 
#define UART_UART_LCR_REG_UART_BC_Pos   (6UL)
 
#define UART_UART_LCR_REG_UART_BC_Msk   (0x40UL)
 
#define UART_UART_LCR_REG_UART_DLAB_Pos   (7UL)
 
#define UART_UART_LCR_REG_UART_DLAB_Msk   (0x80UL)
 
#define UART_UART_MCR_REG_UART_OUT1_Pos   (2UL)
 
#define UART_UART_MCR_REG_UART_OUT1_Msk   (0x4UL)
 
#define UART_UART_MCR_REG_UART_OUT2_Pos   (3UL)
 
#define UART_UART_MCR_REG_UART_OUT2_Msk   (0x8UL)
 
#define UART_UART_MCR_REG_UART_LB_Pos   (4UL)
 
#define UART_UART_MCR_REG_UART_LB_Msk   (0x10UL)
 
#define UART_UART_MCR_REG_UART_SIRE_Pos   (6UL)
 
#define UART_UART_MCR_REG_UART_SIRE_Msk   (0x40UL)
 
#define UART_UART_LSR_REG_UART_DR_Pos   (0UL)
 
#define UART_UART_LSR_REG_UART_DR_Msk   (0x1UL)
 
#define UART_UART_LSR_REG_UART_OE_Pos   (1UL)
 
#define UART_UART_LSR_REG_UART_OE_Msk   (0x2UL)
 
#define UART_UART_LSR_REG_UART_PE_Pos   (2UL)
 
#define UART_UART_LSR_REG_UART_PE_Msk   (0x4UL)
 
#define UART_UART_LSR_REG_UART_FE_Pos   (3UL)
 
#define UART_UART_LSR_REG_UART_FE_Msk   (0x8UL)
 
#define UART_UART_LSR_REG_UART_BI_Pos   (4UL)
 
#define UART_UART_LSR_REG_UART_BI_Msk   (0x10UL)
 
#define UART_UART_LSR_REG_UART_THRE_Pos   (5UL)
 
#define UART_UART_LSR_REG_UART_THRE_Msk   (0x20UL)
 
#define UART_UART_LSR_REG_UART_TEMT_Pos   (6UL)
 
#define UART_UART_LSR_REG_UART_TEMT_Msk   (0x40UL)
 
#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Pos   (0UL)
 
#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Msk   (0xffUL)
 
#define UART_UART_USR_REG_UART_BUSY_Pos   (0UL)
 
#define UART_UART_USR_REG_UART_BUSY_Msk   (0x1UL)
 
#define UART_UART_SRR_REG_UART_UR_Pos   (0UL)
 
#define UART_UART_SRR_REG_UART_UR_Msk   (0x1UL)
 
#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos   (0UL)
 
#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk   (0x1UL)
 
#define UART_UART_DMASA_REG_DMASA_Pos   (0UL)
 
#define UART_UART_DMASA_REG_DMASA_Msk   (0x1UL)
 
#define UART_UART_DLF_REG_UART_DLF_Pos   (0UL)
 
#define UART_UART_DLF_REG_UART_DLF_Msk   (0xfUL)
 
#define UART_UART_CPR_REG_CPR_Pos   (0UL)
 
#define UART_UART_CPR_REG_CPR_Msk   (0xffffUL)
 
#define UART_UART_UCV_REG_UCV_Pos   (0UL)
 
#define UART_UART_UCV_REG_UCV_Msk   (0xffffUL)
 
#define UART_UART_CTR_REG_CTR_Pos   (0UL)
 
#define UART_UART_CTR_REG_CTR_Msk   (0xffffUL)
 
#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Pos   (0UL)
 
#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Msk   (0xffUL)
 
#define UART2_UART2_IER_DLH_REG_ERBFI_dlh0_Pos   (0UL)
 
#define UART2_UART2_IER_DLH_REG_ERBFI_dlh0_Msk   (0x1UL)
 
#define UART2_UART2_IER_DLH_REG_ETBEI_dlh1_Pos   (1UL)
 
#define UART2_UART2_IER_DLH_REG_ETBEI_dlh1_Msk   (0x2UL)
 
#define UART2_UART2_IER_DLH_REG_ELSI_dhl2_Pos   (2UL)
 
#define UART2_UART2_IER_DLH_REG_ELSI_dhl2_Msk   (0x4UL)
 
#define UART2_UART2_IER_DLH_REG_PTIME_dlh7_Pos   (7UL)
 
#define UART2_UART2_IER_DLH_REG_PTIME_dlh7_Msk   (0x80UL)
 
#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Pos   (0UL)
 
#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Msk   (0xffffUL)
 
#define UART2_UART2_LCR_REG_UART_DLS_Pos   (0UL)
 
#define UART2_UART2_LCR_REG_UART_DLS_Msk   (0x3UL)
 
#define UART2_UART2_LCR_REG_UART_STOP_Pos   (2UL)
 
#define UART2_UART2_LCR_REG_UART_STOP_Msk   (0x4UL)
 
#define UART2_UART2_LCR_REG_UART_PEN_Pos   (3UL)
 
#define UART2_UART2_LCR_REG_UART_PEN_Msk   (0x8UL)
 
#define UART2_UART2_LCR_REG_UART_EPS_Pos   (4UL)
 
#define UART2_UART2_LCR_REG_UART_EPS_Msk   (0x10UL)
 
#define UART2_UART2_LCR_REG_UART_BC_Pos   (6UL)
 
#define UART2_UART2_LCR_REG_UART_BC_Msk   (0x40UL)
 
#define UART2_UART2_LCR_REG_UART_DLAB_Pos   (7UL)
 
#define UART2_UART2_LCR_REG_UART_DLAB_Msk   (0x80UL)
 
#define UART2_UART2_MCR_REG_UART_RTS_Pos   (1UL)
 
#define UART2_UART2_MCR_REG_UART_RTS_Msk   (0x2UL)
 
#define UART2_UART2_MCR_REG_UART_OUT1_Pos   (2UL)
 
#define UART2_UART2_MCR_REG_UART_OUT1_Msk   (0x4UL)
 
#define UART2_UART2_MCR_REG_UART_OUT2_Pos   (3UL)
 
#define UART2_UART2_MCR_REG_UART_OUT2_Msk   (0x8UL)
 
#define UART2_UART2_MCR_REG_UART_LB_Pos   (4UL)
 
#define UART2_UART2_MCR_REG_UART_LB_Msk   (0x10UL)
 
#define UART2_UART2_MCR_REG_UART_AFCE_Pos   (5UL)
 
#define UART2_UART2_MCR_REG_UART_AFCE_Msk   (0x20UL)
 
#define UART2_UART2_MCR_REG_UART_SIRE_Pos   (6UL)
 
#define UART2_UART2_MCR_REG_UART_SIRE_Msk   (0x40UL)
 
#define UART2_UART2_LSR_REG_UART_DR_Pos   (0UL)
 
#define UART2_UART2_LSR_REG_UART_DR_Msk   (0x1UL)
 
#define UART2_UART2_LSR_REG_UART_OE_Pos   (1UL)
 
#define UART2_UART2_LSR_REG_UART_OE_Msk   (0x2UL)
 
#define UART2_UART2_LSR_REG_UART_PE_Pos   (2UL)
 
#define UART2_UART2_LSR_REG_UART_PE_Msk   (0x4UL)
 
#define UART2_UART2_LSR_REG_UART_FE_Pos   (3UL)
 
#define UART2_UART2_LSR_REG_UART_FE_Msk   (0x8UL)
 
#define UART2_UART2_LSR_REG_UART_BI_Pos   (4UL)
 
#define UART2_UART2_LSR_REG_UART_BI_Msk   (0x10UL)
 
#define UART2_UART2_LSR_REG_UART_THRE_Pos   (5UL)
 
#define UART2_UART2_LSR_REG_UART_THRE_Msk   (0x20UL)
 
#define UART2_UART2_LSR_REG_UART_TEMT_Pos   (6UL)
 
#define UART2_UART2_LSR_REG_UART_TEMT_Msk   (0x40UL)
 
#define UART2_UART2_LSR_REG_UART_RFE_Pos   (7UL)
 
#define UART2_UART2_LSR_REG_UART_RFE_Msk   (0x80UL)
 
#define UART2_UART2_MSR_REG_UART_DCTS_Pos   (0UL)
 
#define UART2_UART2_MSR_REG_UART_DCTS_Msk   (0x1UL)
 
#define UART2_UART2_MSR_REG_UART_CTS_Pos   (4UL)
 
#define UART2_UART2_MSR_REG_UART_CTS_Msk   (0x10UL)
 
#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Pos   (0UL)
 
#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Pos   (0UL)
 
#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Msk   (0xffUL)
 
#define UART2_UART2_FAR_REG_UART_FAR_Pos   (0UL)
 
#define UART2_UART2_FAR_REG_UART_FAR_Msk   (0x1UL)
 
#define UART2_UART2_USR_REG_UART_BUSY_Pos   (0UL)
 
#define UART2_UART2_USR_REG_UART_BUSY_Msk   (0x1UL)
 
#define UART2_UART2_USR_REG_UART_TFNF_Pos   (1UL)
 
#define UART2_UART2_USR_REG_UART_TFNF_Msk   (0x2UL)
 
#define UART2_UART2_USR_REG_UART_TFE_Pos   (2UL)
 
#define UART2_UART2_USR_REG_UART_TFE_Msk   (0x4UL)
 
#define UART2_UART2_USR_REG_UART_RFNE_Pos   (3UL)
 
#define UART2_UART2_USR_REG_UART_RFNE_Msk   (0x8UL)
 
#define UART2_UART2_USR_REG_UART_RFF_Pos   (4UL)
 
#define UART2_UART2_USR_REG_UART_RFF_Msk   (0x10UL)
 
#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos   (0UL)
 
#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk   (0xffffUL)
 
#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos   (0UL)
 
#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk   (0xffffUL)
 
#define UART2_UART2_SRR_REG_UART_UR_Pos   (0UL)
 
#define UART2_UART2_SRR_REG_UART_UR_Msk   (0x1UL)
 
#define UART2_UART2_SRR_REG_UART_RFR_Pos   (1UL)
 
#define UART2_UART2_SRR_REG_UART_RFR_Msk   (0x2UL)
 
#define UART2_UART2_SRR_REG_UART_XFR_Pos   (2UL)
 
#define UART2_UART2_SRR_REG_UART_XFR_Msk   (0x4UL)
 
#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos   (0UL)
 
#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk   (0x1UL)
 
#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos   (0UL)
 
#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk   (0x1UL)
 
#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos   (0UL)
 
#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk   (0x1UL)
 
#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos   (0UL)
 
#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk   (0x1UL)
 
#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos   (0UL)
 
#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk   (0x3UL)
 
#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos   (0UL)
 
#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk   (0x3UL)
 
#define UART2_UART2_HTX_REG_UART_HALT_TX_Pos   (0UL)
 
#define UART2_UART2_HTX_REG_UART_HALT_TX_Msk   (0x1UL)
 
#define UART2_UART2_DMASA_REG_DMASA_Pos   (0UL)
 
#define UART2_UART2_DMASA_REG_DMASA_Msk   (0x1UL)
 
#define UART2_UART2_DLF_REG_UART_DLF_Pos   (0UL)
 
#define UART2_UART2_DLF_REG_UART_DLF_Msk   (0xfUL)
 
#define UART2_UART2_CPR_REG_CPR_Pos   (0UL)
 
#define UART2_UART2_CPR_REG_CPR_Msk   (0xffffUL)
 
#define UART2_UART2_UCV_REG_UCV_Pos   (0UL)
 
#define UART2_UART2_UCV_REG_UCV_Msk   (0xffffUL)
 
#define UART2_UART2_CTR_REG_CTR_Pos   (0UL)
 
#define UART2_UART2_CTR_REG_CTR_Msk   (0xffffUL)
 
#define USB_USB_MCTRL_REG_USBEN_Pos   (0UL)
 
#define USB_USB_MCTRL_REG_USBEN_Msk   (0x1UL)
 
#define USB_USB_MCTRL_REG_USB_DBG_Pos   (1UL)
 
#define USB_USB_MCTRL_REG_USB_DBG_Msk   (0x2UL)
 
#define USB_USB_MCTRL_REG_USB_NAT_Pos   (3UL)
 
#define USB_USB_MCTRL_REG_USB_NAT_Msk   (0x8UL)
 
#define USB_USB_MCTRL_REG_LSMODE_Pos   (4UL)
 
#define USB_USB_MCTRL_REG_LSMODE_Msk   (0x10UL)
 
#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Pos   (0UL)
 
#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Msk   (0x1UL)
 
#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Pos   (1UL)
 
#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Msk   (0x2UL)
 
#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Pos   (2UL)
 
#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Msk   (0x4UL)
 
#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Pos   (3UL)
 
#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Msk   (0x8UL)
 
#define USB_USB_XCVDIAG_REG_USB_RCV_Pos   (5UL)
 
#define USB_USB_XCVDIAG_REG_USB_RCV_Msk   (0x20UL)
 
#define USB_USB_XCVDIAG_REG_USB_VMIN_Pos   (6UL)
 
#define USB_USB_XCVDIAG_REG_USB_VMIN_Msk   (0x40UL)
 
#define USB_USB_XCVDIAG_REG_USB_VPIN_Pos   (7UL)
 
#define USB_USB_XCVDIAG_REG_USB_VPIN_Msk   (0x80UL)
 
#define USB_USB_TCR_REG_USB_CADJ_Pos   (0UL)
 
#define USB_USB_TCR_REG_USB_CADJ_Msk   (0x1fUL)
 
#define USB_USB_TCR_REG_USB_VADJ_Pos   (5UL)
 
#define USB_USB_TCR_REG_USB_VADJ_Msk   (0xe0UL)
 
#define USB_USB_UTR_REG_USB_UTR_RES_Pos   (0UL)
 
#define USB_USB_UTR_REG_USB_UTR_RES_Msk   (0x1fUL)
 
#define USB_USB_UTR_REG_USB_SF_Pos   (5UL)
 
#define USB_USB_UTR_REG_USB_SF_Msk   (0x20UL)
 
#define USB_USB_UTR_REG_USB_NCRC_Pos   (6UL)
 
#define USB_USB_UTR_REG_USB_NCRC_Msk   (0x40UL)
 
#define USB_USB_UTR_REG_USB_DIAG_Pos   (7UL)
 
#define USB_USB_UTR_REG_USB_DIAG_Msk   (0x80UL)
 
#define USB_USB_FAR_REG_USB_AD_Pos   (0UL)
 
#define USB_USB_FAR_REG_USB_AD_Msk   (0x7fUL)
 
#define USB_USB_FAR_REG_USB_AD_EN_Pos   (7UL)
 
#define USB_USB_FAR_REG_USB_AD_EN_Msk   (0x80UL)
 
#define USB_USB_NFSR_REG_USB_NFS_Pos   (0UL)
 
#define USB_USB_NFSR_REG_USB_NFS_Msk   (0x3UL)
 
#define USB_USB_MAEV_REG_USB_WARN_Pos   (0UL)
 
#define USB_USB_MAEV_REG_USB_WARN_Msk   (0x1UL)
 
#define USB_USB_MAEV_REG_USB_ALT_Pos   (1UL)
 
#define USB_USB_MAEV_REG_USB_ALT_Msk   (0x2UL)
 
#define USB_USB_MAEV_REG_USB_TX_EV_Pos   (2UL)
 
#define USB_USB_MAEV_REG_USB_TX_EV_Msk   (0x4UL)
 
#define USB_USB_MAEV_REG_USB_FRAME_Pos   (3UL)
 
#define USB_USB_MAEV_REG_USB_FRAME_Msk   (0x8UL)
 
#define USB_USB_MAEV_REG_USB_NAK_Pos   (4UL)
 
#define USB_USB_MAEV_REG_USB_NAK_Msk   (0x10UL)
 
#define USB_USB_MAEV_REG_USB_ULD_Pos   (5UL)
 
#define USB_USB_MAEV_REG_USB_ULD_Msk   (0x20UL)
 
#define USB_USB_MAEV_REG_USB_RX_EV_Pos   (6UL)
 
#define USB_USB_MAEV_REG_USB_RX_EV_Msk   (0x40UL)
 
#define USB_USB_MAEV_REG_USB_INTR_Pos   (7UL)
 
#define USB_USB_MAEV_REG_USB_INTR_Msk   (0x80UL)
 
#define USB_USB_MAEV_REG_USB_EP0_TX_Pos   (8UL)
 
#define USB_USB_MAEV_REG_USB_EP0_TX_Msk   (0x100UL)
 
#define USB_USB_MAEV_REG_USB_EP0_RX_Pos   (9UL)
 
#define USB_USB_MAEV_REG_USB_EP0_RX_Msk   (0x200UL)
 
#define USB_USB_MAEV_REG_USB_EP0_NAK_Pos   (10UL)
 
#define USB_USB_MAEV_REG_USB_EP0_NAK_Msk   (0x400UL)
 
#define USB_USB_MAEV_REG_USB_CH_EV_Pos   (11UL)
 
#define USB_USB_MAEV_REG_USB_CH_EV_Msk   (0x800UL)
 
#define USB_USB_MAMSK_REG_USB_M_WARN_Pos   (0UL)
 
#define USB_USB_MAMSK_REG_USB_M_WARN_Msk   (0x1UL)
 
#define USB_USB_MAMSK_REG_USB_M_ALT_Pos   (1UL)
 
#define USB_USB_MAMSK_REG_USB_M_ALT_Msk   (0x2UL)
 
#define USB_USB_MAMSK_REG_USB_M_TX_EV_Pos   (2UL)
 
#define USB_USB_MAMSK_REG_USB_M_TX_EV_Msk   (0x4UL)
 
#define USB_USB_MAMSK_REG_USB_M_FRAME_Pos   (3UL)
 
#define USB_USB_MAMSK_REG_USB_M_FRAME_Msk   (0x8UL)
 
#define USB_USB_MAMSK_REG_USB_M_NAK_Pos   (4UL)
 
#define USB_USB_MAMSK_REG_USB_M_NAK_Msk   (0x10UL)
 
#define USB_USB_MAMSK_REG_USB_M_ULD_Pos   (5UL)
 
#define USB_USB_MAMSK_REG_USB_M_ULD_Msk   (0x20UL)
 
#define USB_USB_MAMSK_REG_USB_M_RX_EV_Pos   (6UL)
 
#define USB_USB_MAMSK_REG_USB_M_RX_EV_Msk   (0x40UL)
 
#define USB_USB_MAMSK_REG_USB_M_INTR_Pos   (7UL)
 
#define USB_USB_MAMSK_REG_USB_M_INTR_Msk   (0x80UL)
 
#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Pos   (8UL)
 
#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Msk   (0x100UL)
 
#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Pos   (9UL)
 
#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Msk   (0x200UL)
 
#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Pos   (10UL)
 
#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Msk   (0x400UL)
 
#define USB_USB_MAMSK_REG_USB_M_CH_EV_Pos   (11UL)
 
#define USB_USB_MAMSK_REG_USB_M_CH_EV_Msk   (0x800UL)
 
#define USB_USB_ALTEV_REG_USB_EOP_Pos   (3UL)
 
#define USB_USB_ALTEV_REG_USB_EOP_Msk   (0x8UL)
 
#define USB_USB_ALTEV_REG_USB_SD3_Pos   (4UL)
 
#define USB_USB_ALTEV_REG_USB_SD3_Msk   (0x10UL)
 
#define USB_USB_ALTEV_REG_USB_SD5_Pos   (5UL)
 
#define USB_USB_ALTEV_REG_USB_SD5_Msk   (0x20UL)
 
#define USB_USB_ALTEV_REG_USB_RESET_Pos   (6UL)
 
#define USB_USB_ALTEV_REG_USB_RESET_Msk   (0x40UL)
 
#define USB_USB_ALTEV_REG_USB_RESUME_Pos   (7UL)
 
#define USB_USB_ALTEV_REG_USB_RESUME_Msk   (0x80UL)
 
#define USB_USB_ALTMSK_REG_USB_M_EOP_Pos   (3UL)
 
#define USB_USB_ALTMSK_REG_USB_M_EOP_Msk   (0x8UL)
 
#define USB_USB_ALTMSK_REG_USB_M_SD3_Pos   (4UL)
 
#define USB_USB_ALTMSK_REG_USB_M_SD3_Msk   (0x10UL)
 
#define USB_USB_ALTMSK_REG_USB_M_SD5_Pos   (5UL)
 
#define USB_USB_ALTMSK_REG_USB_M_SD5_Msk   (0x20UL)
 
#define USB_USB_ALTMSK_REG_USB_M_RESET_Pos   (6UL)
 
#define USB_USB_ALTMSK_REG_USB_M_RESET_Msk   (0x40UL)
 
#define USB_USB_ALTMSK_REG_USB_M_RESUME_Pos   (7UL)
 
#define USB_USB_ALTMSK_REG_USB_M_RESUME_Msk   (0x80UL)
 
#define USB_USB_TXEV_REG_USB_TXFIFO31_Pos   (0UL)
 
#define USB_USB_TXEV_REG_USB_TXFIFO31_Msk   (0x7UL)
 
#define USB_USB_TXEV_REG_USB_TXUDRRN31_Pos   (4UL)
 
#define USB_USB_TXEV_REG_USB_TXUDRRN31_Msk   (0x70UL)
 
#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Pos   (0UL)
 
#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Msk   (0x7UL)
 
#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Pos   (4UL)
 
#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Msk   (0x70UL)
 
#define USB_USB_RXEV_REG_USB_RXFIFO31_Pos   (0UL)
 
#define USB_USB_RXEV_REG_USB_RXFIFO31_Msk   (0x7UL)
 
#define USB_USB_RXEV_REG_USB_RXOVRRN31_Pos   (4UL)
 
#define USB_USB_RXEV_REG_USB_RXOVRRN31_Msk   (0x70UL)
 
#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Pos   (0UL)
 
#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Msk   (0x7UL)
 
#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Pos   (4UL)
 
#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Msk   (0x70UL)
 
#define USB_USB_NAKEV_REG_USB_IN31_Pos   (0UL)
 
#define USB_USB_NAKEV_REG_USB_IN31_Msk   (0x7UL)
 
#define USB_USB_NAKEV_REG_USB_OUT31_Pos   (4UL)
 
#define USB_USB_NAKEV_REG_USB_OUT31_Msk   (0x70UL)
 
#define USB_USB_NAKMSK_REG_USB_M_IN31_Pos   (0UL)
 
#define USB_USB_NAKMSK_REG_USB_M_IN31_Msk   (0x7UL)
 
#define USB_USB_NAKMSK_REG_USB_M_OUT31_Pos   (4UL)
 
#define USB_USB_NAKMSK_REG_USB_M_OUT31_Msk   (0x70UL)
 
#define USB_USB_FWEV_REG_USB_TXWARN31_Pos   (0UL)
 
#define USB_USB_FWEV_REG_USB_TXWARN31_Msk   (0x7UL)
 
#define USB_USB_FWEV_REG_USB_RXWARN31_Pos   (4UL)
 
#define USB_USB_FWEV_REG_USB_RXWARN31_Msk   (0x70UL)
 
#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Pos   (0UL)
 
#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Msk   (0x7UL)
 
#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos   (4UL)
 
#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Msk   (0x70UL)
 
#define USB_USB_FNH_REG_USB_FN_10_8_Pos   (0UL)
 
#define USB_USB_FNH_REG_USB_FN_10_8_Msk   (0x7UL)
 
#define USB_USB_FNH_REG_USB_RFC_Pos   (5UL)
 
#define USB_USB_FNH_REG_USB_RFC_Msk   (0x20UL)
 
#define USB_USB_FNH_REG_USB_UL_Pos   (6UL)
 
#define USB_USB_FNH_REG_USB_UL_Msk   (0x40UL)
 
#define USB_USB_FNH_REG_USB_MF_Pos   (7UL)
 
#define USB_USB_FNH_REG_USB_MF_Msk   (0x80UL)
 
#define USB_USB_FNL_REG_USB_FN_Pos   (0UL)
 
#define USB_USB_FNL_REG_USB_FN_Msk   (0xffUL)
 
#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Pos   (0UL)
 
#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Msk   (0x1UL)
 
#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Pos   (1UL)
 
#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Msk   (0x2UL)
 
#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Pos   (2UL)
 
#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Msk   (0x4UL)
 
#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Pos   (4UL)
 
#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Msk   (0x10UL)
 
#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Pos   (5UL)
 
#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Msk   (0x20UL)
 
#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Pos   (6UL)
 
#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Msk   (0x40UL)
 
#define USB_USB_UX20CDR_REG_RPU_TEST7_Pos   (7UL)
 
#define USB_USB_UX20CDR_REG_RPU_TEST7_Msk   (0x80UL)
 
#define USB_USB_EPC0_REG_USB_EP_Pos   (0UL)
 
#define USB_USB_EPC0_REG_USB_EP_Msk   (0xfUL)
 
#define USB_USB_EPC0_REG_USB_DEF_Pos   (6UL)
 
#define USB_USB_EPC0_REG_USB_DEF_Msk   (0x40UL)
 
#define USB_USB_EPC0_REG_USB_STALL_Pos   (7UL)
 
#define USB_USB_EPC0_REG_USB_STALL_Msk   (0x80UL)
 
#define USB_USB_TXD0_REG_USB_TXFD_Pos   (0UL)
 
#define USB_USB_TXD0_REG_USB_TXFD_Msk   (0xffUL)
 
#define USB_USB_TXS0_REG_USB_TCOUNT_Pos   (0UL)
 
#define USB_USB_TXS0_REG_USB_TCOUNT_Msk   (0x1fUL)
 
#define USB_USB_TXS0_REG_USB_TX_DONE_Pos   (5UL)
 
#define USB_USB_TXS0_REG_USB_TX_DONE_Msk   (0x20UL)
 
#define USB_USB_TXS0_REG_USB_ACK_STAT_Pos   (6UL)
 
#define USB_USB_TXS0_REG_USB_ACK_STAT_Msk   (0x40UL)
 
#define USB_USB_TXC0_REG_USB_TX_EN_Pos   (0UL)
 
#define USB_USB_TXC0_REG_USB_TX_EN_Msk   (0x1UL)
 
#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Pos   (2UL)
 
#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Msk   (0x4UL)
 
#define USB_USB_TXC0_REG_USB_FLUSH_Pos   (3UL)
 
#define USB_USB_TXC0_REG_USB_FLUSH_Msk   (0x8UL)
 
#define USB_USB_TXC0_REG_USB_IGN_IN_Pos   (4UL)
 
#define USB_USB_TXC0_REG_USB_IGN_IN_Msk   (0x10UL)
 
#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Pos   (0UL)
 
#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Msk   (0x1UL)
 
#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Pos   (1UL)
 
#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Msk   (0x2UL)
 
#define USB_USB_RXD0_REG_USB_RXFD_Pos   (0UL)
 
#define USB_USB_RXD0_REG_USB_RXFD_Msk   (0xffUL)
 
#define USB_USB_RXS0_REG_USB_RCOUNT_Pos   (0UL)
 
#define USB_USB_RXS0_REG_USB_RCOUNT_Msk   (0xfUL)
 
#define USB_USB_RXS0_REG_USB_RX_LAST_Pos   (4UL)
 
#define USB_USB_RXS0_REG_USB_RX_LAST_Msk   (0x10UL)
 
#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Pos   (5UL)
 
#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Msk   (0x20UL)
 
#define USB_USB_RXS0_REG_USB_SETUP_Pos   (6UL)
 
#define USB_USB_RXS0_REG_USB_SETUP_Msk   (0x40UL)
 
#define USB_USB_RXC0_REG_USB_RX_EN_Pos   (0UL)
 
#define USB_USB_RXC0_REG_USB_RX_EN_Msk   (0x1UL)
 
#define USB_USB_RXC0_REG_USB_IGN_OUT_Pos   (1UL)
 
#define USB_USB_RXC0_REG_USB_IGN_OUT_Msk   (0x2UL)
 
#define USB_USB_RXC0_REG_USB_IGN_SETUP_Pos   (2UL)
 
#define USB_USB_RXC0_REG_USB_IGN_SETUP_Msk   (0x4UL)
 
#define USB_USB_RXC0_REG_USB_FLUSH_Pos   (3UL)
 
#define USB_USB_RXC0_REG_USB_FLUSH_Msk   (0x8UL)
 
#define USB_USB_EPC1_REG_USB_EP_Pos   (0UL)
 
#define USB_USB_EPC1_REG_USB_EP_Msk   (0xfUL)
 
#define USB_USB_EPC1_REG_USB_EP_EN_Pos   (4UL)
 
#define USB_USB_EPC1_REG_USB_EP_EN_Msk   (0x10UL)
 
#define USB_USB_EPC1_REG_USB_ISO_Pos   (5UL)
 
#define USB_USB_EPC1_REG_USB_ISO_Msk   (0x20UL)
 
#define USB_USB_EPC1_REG_USB_STALL_Pos   (7UL)
 
#define USB_USB_EPC1_REG_USB_STALL_Msk   (0x80UL)
 
#define USB_USB_TXD1_REG_USB_TXFD_Pos   (0UL)
 
#define USB_USB_TXD1_REG_USB_TXFD_Msk   (0xffUL)
 
#define USB_USB_TXS1_REG_USB_TCOUNT_Pos   (0UL)
 
#define USB_USB_TXS1_REG_USB_TCOUNT_Msk   (0x1fUL)
 
#define USB_USB_TXS1_REG_USB_TX_DONE_Pos   (5UL)
 
#define USB_USB_TXS1_REG_USB_TX_DONE_Msk   (0x20UL)
 
#define USB_USB_TXS1_REG_USB_ACK_STAT_Pos   (6UL)
 
#define USB_USB_TXS1_REG_USB_ACK_STAT_Msk   (0x40UL)
 
#define USB_USB_TXS1_REG_USB_TX_URUN_Pos   (7UL)
 
#define USB_USB_TXS1_REG_USB_TX_URUN_Msk   (0x80UL)
 
#define USB_USB_TXC1_REG_USB_TX_EN_Pos   (0UL)
 
#define USB_USB_TXC1_REG_USB_TX_EN_Msk   (0x1UL)
 
#define USB_USB_TXC1_REG_USB_LAST_Pos   (1UL)
 
#define USB_USB_TXC1_REG_USB_LAST_Msk   (0x2UL)
 
#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Pos   (2UL)
 
#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Msk   (0x4UL)
 
#define USB_USB_TXC1_REG_USB_FLUSH_Pos   (3UL)
 
#define USB_USB_TXC1_REG_USB_FLUSH_Msk   (0x8UL)
 
#define USB_USB_TXC1_REG_USB_RFF_Pos   (4UL)
 
#define USB_USB_TXC1_REG_USB_RFF_Msk   (0x10UL)
 
#define USB_USB_TXC1_REG_USB_TFWL_Pos   (5UL)
 
#define USB_USB_TXC1_REG_USB_TFWL_Msk   (0x60UL)
 
#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Pos   (7UL)
 
#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Msk   (0x80UL)
 
#define USB_USB_EPC2_REG_USB_EP_Pos   (0UL)
 
#define USB_USB_EPC2_REG_USB_EP_Msk   (0xfUL)
 
#define USB_USB_EPC2_REG_USB_EP_EN_Pos   (4UL)
 
#define USB_USB_EPC2_REG_USB_EP_EN_Msk   (0x10UL)
 
#define USB_USB_EPC2_REG_USB_ISO_Pos   (5UL)
 
#define USB_USB_EPC2_REG_USB_ISO_Msk   (0x20UL)
 
#define USB_USB_EPC2_REG_USB_STALL_Pos   (7UL)
 
#define USB_USB_EPC2_REG_USB_STALL_Msk   (0x80UL)
 
#define USB_USB_RXD1_REG_USB_RXFD_Pos   (0UL)
 
#define USB_USB_RXD1_REG_USB_RXFD_Msk   (0xffUL)
 
#define USB_USB_RXS1_REG_USB_RCOUNT_Pos   (0UL)
 
#define USB_USB_RXS1_REG_USB_RCOUNT_Msk   (0xfUL)
 
#define USB_USB_RXS1_REG_USB_RX_LAST_Pos   (4UL)
 
#define USB_USB_RXS1_REG_USB_RX_LAST_Msk   (0x10UL)
 
#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Pos   (5UL)
 
#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Msk   (0x20UL)
 
#define USB_USB_RXS1_REG_USB_SETUP_Pos   (6UL)
 
#define USB_USB_RXS1_REG_USB_SETUP_Msk   (0x40UL)
 
#define USB_USB_RXS1_REG_USB_RX_ERR_Pos   (7UL)
 
#define USB_USB_RXS1_REG_USB_RX_ERR_Msk   (0x80UL)
 
#define USB_USB_RXC1_REG_USB_RX_EN_Pos   (0UL)
 
#define USB_USB_RXC1_REG_USB_RX_EN_Msk   (0x1UL)
 
#define USB_USB_RXC1_REG_USB_IGN_SETUP_Pos   (2UL)
 
#define USB_USB_RXC1_REG_USB_IGN_SETUP_Msk   (0x4UL)
 
#define USB_USB_RXC1_REG_USB_FLUSH_Pos   (3UL)
 
#define USB_USB_RXC1_REG_USB_FLUSH_Msk   (0x8UL)
 
#define USB_USB_RXC1_REG_USB_RFWL_Pos   (5UL)
 
#define USB_USB_RXC1_REG_USB_RFWL_Msk   (0x60UL)
 
#define USB_USB_EPC3_REG_USB_EP_Pos   (0UL)
 
#define USB_USB_EPC3_REG_USB_EP_Msk   (0xfUL)
 
#define USB_USB_EPC3_REG_USB_EP_EN_Pos   (4UL)
 
#define USB_USB_EPC3_REG_USB_EP_EN_Msk   (0x10UL)
 
#define USB_USB_EPC3_REG_USB_ISO_Pos   (5UL)
 
#define USB_USB_EPC3_REG_USB_ISO_Msk   (0x20UL)
 
#define USB_USB_EPC3_REG_USB_STALL_Pos   (7UL)
 
#define USB_USB_EPC3_REG_USB_STALL_Msk   (0x80UL)
 
#define USB_USB_TXD2_REG_USB_TXFD_Pos   (0UL)
 
#define USB_USB_TXD2_REG_USB_TXFD_Msk   (0xffUL)
 
#define USB_USB_TXS2_REG_USB_TCOUNT_Pos   (0UL)
 
#define USB_USB_TXS2_REG_USB_TCOUNT_Msk   (0x1fUL)
 
#define USB_USB_TXS2_REG_USB_TX_DONE_Pos   (5UL)
 
#define USB_USB_TXS2_REG_USB_TX_DONE_Msk   (0x20UL)
 
#define USB_USB_TXS2_REG_USB_ACK_STAT_Pos   (6UL)
 
#define USB_USB_TXS2_REG_USB_ACK_STAT_Msk   (0x40UL)
 
#define USB_USB_TXS2_REG_USB_TX_URUN_Pos   (7UL)
 
#define USB_USB_TXS2_REG_USB_TX_URUN_Msk   (0x80UL)
 
#define USB_USB_TXC2_REG_USB_TX_EN_Pos   (0UL)
 
#define USB_USB_TXC2_REG_USB_TX_EN_Msk   (0x1UL)
 
#define USB_USB_TXC2_REG_USB_LAST_Pos   (1UL)
 
#define USB_USB_TXC2_REG_USB_LAST_Msk   (0x2UL)
 
#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Pos   (2UL)
 
#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Msk   (0x4UL)
 
#define USB_USB_TXC2_REG_USB_FLUSH_Pos   (3UL)
 
#define USB_USB_TXC2_REG_USB_FLUSH_Msk   (0x8UL)
 
#define USB_USB_TXC2_REG_USB_RFF_Pos   (4UL)
 
#define USB_USB_TXC2_REG_USB_RFF_Msk   (0x10UL)
 
#define USB_USB_TXC2_REG_USB_TFWL_Pos   (5UL)
 
#define USB_USB_TXC2_REG_USB_TFWL_Msk   (0x60UL)
 
#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Pos   (7UL)
 
#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Msk   (0x80UL)
 
#define USB_USB_EPC4_REG_USB_EP_Pos   (0UL)
 
#define USB_USB_EPC4_REG_USB_EP_Msk   (0xfUL)
 
#define USB_USB_EPC4_REG_USB_EP_EN_Pos   (4UL)
 
#define USB_USB_EPC4_REG_USB_EP_EN_Msk   (0x10UL)
 
#define USB_USB_EPC4_REG_USB_ISO_Pos   (5UL)
 
#define USB_USB_EPC4_REG_USB_ISO_Msk   (0x20UL)
 
#define USB_USB_EPC4_REG_USB_STALL_Pos   (7UL)
 
#define USB_USB_EPC4_REG_USB_STALL_Msk   (0x80UL)
 
#define USB_USB_RXD2_REG_USB_RXFD_Pos   (0UL)
 
#define USB_USB_RXD2_REG_USB_RXFD_Msk   (0xffUL)
 
#define USB_USB_RXS2_REG_USB_RCOUNT_Pos   (0UL)
 
#define USB_USB_RXS2_REG_USB_RCOUNT_Msk   (0xfUL)
 
#define USB_USB_RXS2_REG_USB_RX_LAST_Pos   (4UL)
 
#define USB_USB_RXS2_REG_USB_RX_LAST_Msk   (0x10UL)
 
#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Pos   (5UL)
 
#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Msk   (0x20UL)
 
#define USB_USB_RXS2_REG_USB_SETUP_Pos   (6UL)
 
#define USB_USB_RXS2_REG_USB_SETUP_Msk   (0x40UL)
 
#define USB_USB_RXS2_REG_USB_RX_ERR_Pos   (7UL)
 
#define USB_USB_RXS2_REG_USB_RX_ERR_Msk   (0x80UL)
 
#define USB_USB_RXC2_REG_USB_RX_EN_Pos   (0UL)
 
#define USB_USB_RXC2_REG_USB_RX_EN_Msk   (0x1UL)
 
#define USB_USB_RXC2_REG_USB_IGN_SETUP_Pos   (2UL)
 
#define USB_USB_RXC2_REG_USB_IGN_SETUP_Msk   (0x4UL)
 
#define USB_USB_RXC2_REG_USB_FLUSH_Pos   (3UL)
 
#define USB_USB_RXC2_REG_USB_FLUSH_Msk   (0x8UL)
 
#define USB_USB_RXC2_REG_USB_RFWL_Pos   (5UL)
 
#define USB_USB_RXC2_REG_USB_RFWL_Msk   (0x60UL)
 
#define USB_USB_EPC5_REG_USB_EP_Pos   (0UL)
 
#define USB_USB_EPC5_REG_USB_EP_Msk   (0xfUL)
 
#define USB_USB_EPC5_REG_USB_EP_EN_Pos   (4UL)
 
#define USB_USB_EPC5_REG_USB_EP_EN_Msk   (0x10UL)
 
#define USB_USB_EPC5_REG_USB_ISO_Pos   (5UL)
 
#define USB_USB_EPC5_REG_USB_ISO_Msk   (0x20UL)
 
#define USB_USB_EPC5_REG_USB_STALL_Pos   (7UL)
 
#define USB_USB_EPC5_REG_USB_STALL_Msk   (0x80UL)
 
#define USB_USB_TXD3_REG_USB_TXFD_Pos   (0UL)
 
#define USB_USB_TXD3_REG_USB_TXFD_Msk   (0xffUL)
 
#define USB_USB_TXS3_REG_USB_TCOUNT_Pos   (0UL)
 
#define USB_USB_TXS3_REG_USB_TCOUNT_Msk   (0x1fUL)
 
#define USB_USB_TXS3_REG_USB_TX_DONE_Pos   (5UL)
 
#define USB_USB_TXS3_REG_USB_TX_DONE_Msk   (0x20UL)
 
#define USB_USB_TXS3_REG_USB_ACK_STAT_Pos   (6UL)
 
#define USB_USB_TXS3_REG_USB_ACK_STAT_Msk   (0x40UL)
 
#define USB_USB_TXS3_REG_USB_TX_URUN_Pos   (7UL)
 
#define USB_USB_TXS3_REG_USB_TX_URUN_Msk   (0x80UL)
 
#define USB_USB_TXC3_REG_USB_TX_EN_Pos   (0UL)
 
#define USB_USB_TXC3_REG_USB_TX_EN_Msk   (0x1UL)
 
#define USB_USB_TXC3_REG_USB_LAST_Pos   (1UL)
 
#define USB_USB_TXC3_REG_USB_LAST_Msk   (0x2UL)
 
#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Pos   (2UL)
 
#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Msk   (0x4UL)
 
#define USB_USB_TXC3_REG_USB_FLUSH_Pos   (3UL)
 
#define USB_USB_TXC3_REG_USB_FLUSH_Msk   (0x8UL)
 
#define USB_USB_TXC3_REG_USB_RFF_Pos   (4UL)
 
#define USB_USB_TXC3_REG_USB_RFF_Msk   (0x10UL)
 
#define USB_USB_TXC3_REG_USB_TFWL_Pos   (5UL)
 
#define USB_USB_TXC3_REG_USB_TFWL_Msk   (0x60UL)
 
#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Pos   (7UL)
 
#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Msk   (0x80UL)
 
#define USB_USB_EPC6_REG_USB_EP_Pos   (0UL)
 
#define USB_USB_EPC6_REG_USB_EP_Msk   (0xfUL)
 
#define USB_USB_EPC6_REG_USB_EP_EN_Pos   (4UL)
 
#define USB_USB_EPC6_REG_USB_EP_EN_Msk   (0x10UL)
 
#define USB_USB_EPC6_REG_USB_ISO_Pos   (5UL)
 
#define USB_USB_EPC6_REG_USB_ISO_Msk   (0x20UL)
 
#define USB_USB_EPC6_REG_USB_STALL_Pos   (7UL)
 
#define USB_USB_EPC6_REG_USB_STALL_Msk   (0x80UL)
 
#define USB_USB_RXD3_REG_USB_RXFD_Pos   (0UL)
 
#define USB_USB_RXD3_REG_USB_RXFD_Msk   (0xffUL)
 
#define USB_USB_RXS3_REG_USB_RCOUNT_Pos   (0UL)
 
#define USB_USB_RXS3_REG_USB_RCOUNT_Msk   (0xfUL)
 
#define USB_USB_RXS3_REG_USB_RX_LAST_Pos   (4UL)
 
#define USB_USB_RXS3_REG_USB_RX_LAST_Msk   (0x10UL)
 
#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Pos   (5UL)
 
#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Msk   (0x20UL)
 
#define USB_USB_RXS3_REG_USB_SETUP_Pos   (6UL)
 
#define USB_USB_RXS3_REG_USB_SETUP_Msk   (0x40UL)
 
#define USB_USB_RXS3_REG_USB_RX_ERR_Pos   (7UL)
 
#define USB_USB_RXS3_REG_USB_RX_ERR_Msk   (0x80UL)
 
#define USB_USB_RXC3_REG_USB_RX_EN_Pos   (0UL)
 
#define USB_USB_RXC3_REG_USB_RX_EN_Msk   (0x1UL)
 
#define USB_USB_RXC3_REG_USB_IGN_SETUP_Pos   (2UL)
 
#define USB_USB_RXC3_REG_USB_IGN_SETUP_Msk   (0x4UL)
 
#define USB_USB_RXC3_REG_USB_FLUSH_Pos   (3UL)
 
#define USB_USB_RXC3_REG_USB_FLUSH_Msk   (0x8UL)
 
#define USB_USB_RXC3_REG_USB_RFWL_Pos   (5UL)
 
#define USB_USB_RXC3_REG_USB_RFWL_Msk   (0x60UL)
 
#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Pos   (0UL)
 
#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Msk   (0x7UL)
 
#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Pos   (3UL)
 
#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Msk   (0x38UL)
 
#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Pos   (6UL)
 
#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Msk   (0x40UL)
 
#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Pos   (0UL)
 
#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Msk   (0x1UL)
 
#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Pos   (1UL)
 
#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Msk   (0x2UL)
 
#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Pos   (2UL)
 
#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Msk   (0x4UL)
 
#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Pos   (3UL)
 
#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Msk   (0x8UL)
 
#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Pos   (4UL)
 
#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Msk   (0x10UL)
 
#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Pos   (5UL)
 
#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Msk   (0x20UL)
 
#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Pos   (0UL)
 
#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Msk   (0x1UL)
 
#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Pos   (1UL)
 
#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Msk   (0x2UL)
 
#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Pos   (2UL)
 
#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Msk   (0x4UL)
 
#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Pos   (3UL)
 
#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Msk   (0x8UL)
 
#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Pos   (4UL)
 
#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Msk   (0x10UL)
 
#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Pos   (5UL)
 
#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Msk   (0x20UL)
 
#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Pos   (0UL)
 
#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Msk   (0x3fUL)
 
#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Pos   (6UL)
 
#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Msk   (0x40UL)
 
#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Pos   (7UL)
 
#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk   (0x80UL)
 
#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Pos   (0UL)
 
#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk   (0xffffUL)
 
#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Pos   (0UL)
 
#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Msk   (0xffUL)
 
#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Pos   (0UL)
 
#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Msk   (0xffUL)
 
#define WAKEUP_WKUP_SELECT_P2_REG_WKUP_SELECT_P2_Pos   (0UL)
 
#define WAKEUP_WKUP_SELECT_P2_REG_WKUP_SELECT_P2_Msk   (0x1fUL)
 
#define WAKEUP_WKUP_SELECT_P3_REG_WKUP_SELECT_P3_Pos   (0UL)
 
#define WAKEUP_WKUP_SELECT_P3_REG_WKUP_SELECT_P3_Msk   (0xffUL)
 
#define WAKEUP_WKUP_SELECT_P4_REG_WKUP_SELECT_P4_Pos   (0UL)
 
#define WAKEUP_WKUP_SELECT_P4_REG_WKUP_SELECT_P4_Msk   (0xffUL)
 
#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Pos   (0UL)
 
#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Msk   (0xffUL)
 
#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Pos   (0UL)
 
#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Msk   (0xffUL)
 
#define WAKEUP_WKUP_POL_P2_REG_WKUP_POL_P2_Pos   (0UL)
 
#define WAKEUP_WKUP_POL_P2_REG_WKUP_POL_P2_Msk   (0x1fUL)
 
#define WAKEUP_WKUP_POL_P3_REG_WKUP_POL_P3_Pos   (0UL)
 
#define WAKEUP_WKUP_POL_P3_REG_WKUP_POL_P3_Msk   (0xffUL)
 
#define WAKEUP_WKUP_POL_P4_REG_WKUP_POL_P4_Pos   (0UL)
 
#define WAKEUP_WKUP_POL_P4_REG_WKUP_POL_P4_Msk   (0xffUL)
 
#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P0_Pos   (0UL)
 
#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P0_Msk   (0xffUL)
 
#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P1_Pos   (8UL)
 
#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P1_Msk   (0xff00UL)
 
#define WAKEUP_WKUP_STATUS_1_REG_WKUP_STAT_P2_Pos   (0UL)
 
#define WAKEUP_WKUP_STATUS_1_REG_WKUP_STAT_P2_Msk   (0x1fUL)
 
#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P3_Pos   (0UL)
 
#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P3_Msk   (0xffUL)
 
#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P4_Pos   (8UL)
 
#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P4_Msk   (0xff00UL)
 
#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P0_Pos   (0UL)
 
#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P0_Msk   (0xffUL)
 
#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P1_Pos   (8UL)
 
#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P1_Msk   (0xff00UL)
 
#define WAKEUP_WKUP_CLEAR_1_REG_WKUP_CLEAR_P2_Pos   (0UL)
 
#define WAKEUP_WKUP_CLEAR_1_REG_WKUP_CLEAR_P2_Msk   (0x1fUL)
 
#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P3_Pos   (0UL)
 
#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P3_Msk   (0xffUL)
 
#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P4_Pos   (8UL)
 
#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P4_Msk   (0xff00UL)
 
#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Pos   (0UL)
 
#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Msk   (0xffUL)
 
#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Pos   (0UL)
 
#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Msk   (0xffUL)
 
#define WAKEUP_WKUP_SEL_GPIO_P2_REG_WKUP_SEL_GPIO_P2_Pos   (0UL)
 
#define WAKEUP_WKUP_SEL_GPIO_P2_REG_WKUP_SEL_GPIO_P2_Msk   (0x1fUL)
 
#define WAKEUP_WKUP_SEL_GPIO_P3_REG_WKUP_SEL_GPIO_P3_Pos   (0UL)
 
#define WAKEUP_WKUP_SEL_GPIO_P3_REG_WKUP_SEL_GPIO_P3_Msk   (0xffUL)
 
#define WAKEUP_WKUP_SEL_GPIO_P4_REG_WKUP_SEL_GPIO_P4_Pos   (0UL)
 
#define WAKEUP_WKUP_SEL_GPIO_P4_REG_WKUP_SEL_GPIO_P4_Msk   (0xffUL)
 
#define WDOG_WATCHDOG_REG_WDOG_VAL_Pos   (0UL)
 
#define WDOG_WATCHDOG_REG_WDOG_VAL_Msk   (0xffUL)
 
#define WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Pos   (8UL)
 
#define WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk   (0x100UL)
 
#define WDOG_WATCHDOG_REG_WDOG_WEN_Pos   (9UL)
 
#define WDOG_WATCHDOG_REG_WDOG_WEN_Msk   (0xfe00UL)
 
#define WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos   (0UL)
 
#define WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk   (0x1UL)
 
#define AES_HASH_BASE   0x40020000UL
 
#define ANAMISC_BASE   0x50001B00UL
 
#define APU_BASE   0x50004000UL
 
#define BLE_BASE   0x40000000UL
 
#define CACHE_BASE   0x400C3000UL
 
#define CHIP_VERSION_BASE   0x50003200UL
 
#define COEX_BASE   0x50002F00UL
 
#define CRG_PER_BASE   0x50001C00UL
 
#define CRG_TOP_BASE   0x50000000UL
 
#define DCDC_BASE   0x50000080UL
 
#define DEM_BASE   0x50002E00UL
 
#define DMA_BASE   0x50003500UL
 
#define ECC_BASE   0x50006000UL
 
#define FTDF_BASE   0x40080000UL
 
#define GP_TIMERS_BASE   0x50003400UL
 
#define GPADC_BASE   0x50001900UL
 
#define GPIO_BASE   0x50003000UL
 
#define GPREG_BASE   0x50003300UL
 
#define I2C_BASE   0x50001400UL
 
#define I2C2_BASE   0x50001500UL
 
#define IR_BASE   0x50001700UL
 
#define KBSCAN_BASE   0x50001600UL
 
#define OTPC_BASE   0x07F40000UL
 
#define PATCH_BASE   0x40050000UL
 
#define PLLDIG_BASE   0x50002D00UL
 
#define QSPIC_BASE   0x0C000000UL
 
#define QUAD_BASE   0x50001A00UL
 
#define RFCU_BASE   0x50002000UL
 
#define RFCU_POWER_BASE   0x50002200UL
 
#define RFPT_BASE   0x50003600UL
 
#define SPI_BASE   0x50001200UL
 
#define SPI2_BASE   0x50001300UL
 
#define TIMER1_BASE   0x50000200UL
 
#define TRNG_BASE   0x50005000UL
 
#define UART_BASE   0x50001000UL
 
#define UART2_BASE   0x50001100UL
 
#define USB_BASE   0x50001800UL
 
#define WAKEUP_BASE   0x50000100UL
 
#define WDOG_BASE   0x50003100UL
 
#define AES_HASH   ((AES_HASH_Type *) AES_HASH_BASE)
 
#define ANAMISC   ((ANAMISC_Type *) ANAMISC_BASE)
 
#define APU   ((APU_Type *) APU_BASE)
 
#define BLE   ((BLE_Type *) BLE_BASE)
 
#define CACHE   ((CACHE_Type *) CACHE_BASE)
 
#define CHIP_VERSION   ((CHIP_VERSION_Type *) CHIP_VERSION_BASE)
 
#define COEX   ((COEX_Type *) COEX_BASE)
 
#define CRG_PER   ((CRG_PER_Type *) CRG_PER_BASE)
 
#define CRG_TOP   ((CRG_TOP_Type *) CRG_TOP_BASE)
 
#define DCDC   ((DCDC_Type *) DCDC_BASE)
 
#define DEM   ((DEM_Type *) DEM_BASE)
 
#define DMA   ((DMA_Type *) DMA_BASE)
 
#define ECC   ((ECC_Type *) ECC_BASE)
 
#define FTDF   ((FTDF_Type *) FTDF_BASE)
 
#define GP_TIMERS   ((GP_TIMERS_Type *) GP_TIMERS_BASE)
 
#define GPADC   ((GPADC_Type *) GPADC_BASE)
 
#define GPIO   ((GPIO_Type *) GPIO_BASE)
 
#define GPREG   ((GPREG_Type *) GPREG_BASE)
 
#define I2C   ((I2C_Type *) I2C_BASE)
 
#define I2C2   ((I2C2_Type *) I2C2_BASE)
 
#define IR   ((IR_Type *) IR_BASE)
 
#define KBSCAN   ((KBSCAN_Type *) KBSCAN_BASE)
 
#define OTPC   ((OTPC_Type *) OTPC_BASE)
 
#define PATCH   ((PATCH_Type *) PATCH_BASE)
 
#define PLLDIG   ((PLLDIG_Type *) PLLDIG_BASE)
 
#define QSPIC   ((QSPIC_Type *) QSPIC_BASE)
 
#define QUAD   ((QUAD_Type *) QUAD_BASE)
 
#define RFCU   ((RFCU_Type *) RFCU_BASE)
 
#define RFCU_POWER   ((RFCU_POWER_Type *) RFCU_POWER_BASE)
 
#define RFPT   ((RFPT_Type *) RFPT_BASE)
 
#define SPI   ((SPI_Type *) SPI_BASE)
 
#define SPI2   ((SPI2_Type *) SPI2_BASE)
 
#define TIMER1   ((TIMER1_Type *) TIMER1_BASE)
 
#define TRNG   ((TRNG_Type *) TRNG_BASE)
 
#define UART   ((UART_Type *) UART_BASE)
 
#define UART2   ((UART2_Type *) UART2_BASE)
 
#define USB   ((USB_Type *) USB_BASE)
 
#define WAKEUP   ((WAKEUP_Type *) WAKEUP_BASE)
 
#define WDOG   ((WDOG_Type *) WDOG_BASE)
 

Detailed Description

< Cortex-M0 processor and core peripherals

< DA14680BA System

Macro Definition Documentation

◆ AES_HASH

#define AES_HASH   ((AES_HASH_Type *) AES_HASH_BASE)

Definition at line 12073 of file DA14680BA.h.

◆ AES_HASH_BASE

#define AES_HASH_BASE   0x40020000UL

Definition at line 12028 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Msk

#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Msk   (0x1UL)

AES_HASH CRYPTO_CLRIRQ_REG: CRYPTO_CLRIRQ (Bitfield-Mask: 0x01)

Definition at line 2592 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Pos

#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Pos   (0UL)

AES_HASH CRYPTO_CLRIRQ_REG: CRYPTO_CLRIRQ (Bit 0)

Definition at line 2591 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk   (0x20000UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_AES_KEXP (Bitfield-Mask: 0x01)

Definition at line 2564 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Pos   (17UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_AES_KEXP (Bit 17)

Definition at line 2563 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk   (0x60UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_AES_KEY_SZ (Bitfield-Mask: 0x03)

Definition at line 2552 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos   (5UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_AES_KEY_SZ (Bit 5)

Definition at line 2551 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk   (0xcUL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_ALG_MD (Bitfield-Mask: 0x03)

Definition at line 2548 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos   (2UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_ALG_MD (Bit 2)

Definition at line 2547 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Msk   (0x3UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_ALG (Bitfield-Mask: 0x03)

Definition at line 2546 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos   (0UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_ALG (Bit 0)

Definition at line 2545 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Msk   (0x80UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_ENCDEC (Bitfield-Mask: 0x01)

Definition at line 2554 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Pos   (7UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_ENCDEC (Bit 7)

Definition at line 2553 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Msk   (0xfc00UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_HASH_OUT_LEN (Bitfield-Mask: 0x3f)

Definition at line 2560 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Pos   (10UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_HASH_OUT_LEN (Bit 10)

Definition at line 2559 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk   (0x200UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_HASH_SEL (Bitfield-Mask: 0x01)

Definition at line 2558 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Pos   (9UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_HASH_SEL (Bit 9)

Definition at line 2557 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Msk   (0x100UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_IRQ_EN (Bitfield-Mask: 0x01)

Definition at line 2556 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Pos   (8UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_IRQ_EN (Bit 8)

Definition at line 2555 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk   (0x10000UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_MORE_IN (Bitfield-Mask: 0x01)

Definition at line 2562 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Pos   (16UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_MORE_IN (Bit 16)

Definition at line 2561 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk   (0x10UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_OUT_MD (Bitfield-Mask: 0x01)

Definition at line 2550 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Pos   (4UL)

AES_HASH CRYPTO_CTRL_REG: CRYPTO_OUT_MD (Bit 4)

Definition at line 2549 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Msk

#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Msk   (0xffffffffUL)

AES_HASH CRYPTO_DEST_ADDR_REG: CRYPTO_DEST_ADDR (Bitfield-Mask: 0xffffffff)

Definition at line 2580 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Pos

#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Pos   (0UL)

AES_HASH CRYPTO_DEST_ADDR_REG: CRYPTO_DEST_ADDR (Bit 0)

Definition at line 2579 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Msk

#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Msk   (0xffffffffUL)

AES_HASH CRYPTO_FETCH_ADDR_REG: CRYPTO_FETCH_ADDR (Bitfield-Mask: 0xffffffff)

Definition at line 2572 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Pos

#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Pos   (0UL)

AES_HASH CRYPTO_FETCH_ADDR_REG: CRYPTO_FETCH_ADDR (Bit 0)

Definition at line 2571 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Msk

#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Msk   (0xffffffffUL)

AES_HASH CRYPTO_KEYS_START: CRYPTO_KEY_X (Bitfield-Mask: 0xffffffff)

Definition at line 2612 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Pos

#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Pos   (0UL)

AES_HASH CRYPTO_KEYS_START: CRYPTO_KEY_X (Bit 0)

Definition at line 2611 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Msk

#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Msk   (0xffffffUL)

AES_HASH CRYPTO_LEN_REG: CRYPTO_LEN (Bitfield-Mask: 0xffffff)

Definition at line 2576 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Pos

#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Pos   (0UL)

AES_HASH CRYPTO_LEN_REG: CRYPTO_LEN (Bit 0)

Definition at line 2575 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Msk

#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Msk   (0xffffffffUL)

AES_HASH CRYPTO_MREG0_REG: CRYPTO_MREG0 (Bitfield-Mask: 0xffffffff)

Definition at line 2596 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Pos

#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Pos   (0UL)

AES_HASH CRYPTO_MREG0_REG: CRYPTO_MREG0 (Bit 0)

Definition at line 2595 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Msk

#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Msk   (0xffffffffUL)

AES_HASH CRYPTO_MREG1_REG: CRYPTO_MREG1 (Bitfield-Mask: 0xffffffff)

Definition at line 2600 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Pos

#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Pos   (0UL)

AES_HASH CRYPTO_MREG1_REG: CRYPTO_MREG1 (Bit 0)

Definition at line 2599 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Msk

#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Msk   (0xffffffffUL)

AES_HASH CRYPTO_MREG2_REG: CRYPTO_MREG2 (Bitfield-Mask: 0xffffffff)

Definition at line 2604 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Pos

#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Pos   (0UL)

AES_HASH CRYPTO_MREG2_REG: CRYPTO_MREG2 (Bit 0)

Definition at line 2603 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Msk

#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Msk   (0xffffffffUL)

AES_HASH CRYPTO_MREG3_REG: CRYPTO_MREG3 (Bitfield-Mask: 0xffffffff)

Definition at line 2608 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Pos

#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Pos   (0UL)

AES_HASH CRYPTO_MREG3_REG: CRYPTO_MREG3 (Bit 0)

Definition at line 2607 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_START_REG_CRYPTO_START_Msk

#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Msk   (0x1UL)

AES_HASH CRYPTO_START_REG: CRYPTO_START (Bitfield-Mask: 0x01)

Definition at line 2568 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_START_REG_CRYPTO_START_Pos

#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Pos   (0UL)

AES_HASH CRYPTO_START_REG: CRYPTO_START (Bit 0)

Definition at line 2567 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Msk

#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Msk   (0x1UL)

AES_HASH CRYPTO_STATUS_REG: CRYPTO_INACTIVE (Bitfield-Mask: 0x01)

Definition at line 2584 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Pos

#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Pos   (0UL)

AES_HASH CRYPTO_STATUS_REG: CRYPTO_INACTIVE (Bit 0)

Definition at line 2583 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk

#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk   (0x4UL)

AES_HASH CRYPTO_STATUS_REG: CRYPTO_IRQ_ST (Bitfield-Mask: 0x01)

Definition at line 2588 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Pos

#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Pos   (2UL)

AES_HASH CRYPTO_STATUS_REG: CRYPTO_IRQ_ST (Bit 2)

Definition at line 2587 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Msk

#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Msk   (0x2UL)

AES_HASH CRYPTO_STATUS_REG: CRYPTO_WAIT_FOR_IN (Bitfield-Mask: 0x01)

Definition at line 2586 of file DA14680BA.h.

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Pos

#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Pos   (1UL)

AES_HASH CRYPTO_STATUS_REG: CRYPTO_WAIT_FOR_IN (Bit 1)

Definition at line 2585 of file DA14680BA.h.

◆ ANAMISC

#define ANAMISC   ((ANAMISC_Type *) ANAMISC_BASE)

Definition at line 12074 of file DA14680BA.h.

◆ ANAMISC_ANA_TEST_REG_ACORE_TESTBUS_EN_Msk

#define ANAMISC_ANA_TEST_REG_ACORE_TESTBUS_EN_Msk   (0x10UL)

ANAMISC ANA_TEST_REG: ACORE_TESTBUS_EN (Bitfield-Mask: 0x01)

Definition at line 2624 of file DA14680BA.h.

◆ ANAMISC_ANA_TEST_REG_ACORE_TESTBUS_EN_Pos

#define ANAMISC_ANA_TEST_REG_ACORE_TESTBUS_EN_Pos   (4UL)

ANAMISC ANA_TEST_REG: ACORE_TESTBUS_EN (Bit 4)

Definition at line 2623 of file DA14680BA.h.

◆ ANAMISC_ANA_TEST_REG_TEST_STRUCTURE_Msk

#define ANAMISC_ANA_TEST_REG_TEST_STRUCTURE_Msk   (0xfUL)

ANAMISC ANA_TEST_REG: TEST_STRUCTURE (Bitfield-Mask: 0x0f)

Definition at line 2622 of file DA14680BA.h.

◆ ANAMISC_ANA_TEST_REG_TEST_STRUCTURE_Pos

#define ANAMISC_ANA_TEST_REG_TEST_STRUCTURE_Pos   (0UL)

ANAMISC ANA_TEST_REG: TEST_STRUCTURE (Bit 0)

Definition at line 2621 of file DA14680BA.h.

◆ ANAMISC_BASE

#define ANAMISC_BASE   0x50001B00UL

Definition at line 12029 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_CHARGE_CUR_Msk

#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_CUR_Msk   (0xf00UL)

ANAMISC CHARGER_CTRL1_REG: CHARGE_CUR (Bitfield-Mask: 0x0f)

Definition at line 2636 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_CHARGE_CUR_Pos

#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_CUR_Pos   (8UL)

ANAMISC CHARGER_CTRL1_REG: CHARGE_CUR (Bit 8)

Definition at line 2635 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_CHARGE_LEVEL_Msk

#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_LEVEL_Msk   (0x1fUL)

ANAMISC CHARGER_CTRL1_REG: CHARGE_LEVEL (Bitfield-Mask: 0x1f)

Definition at line 2628 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_CHARGE_LEVEL_Pos

#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_LEVEL_Pos   (0UL)

ANAMISC CHARGER_CTRL1_REG: CHARGE_LEVEL (Bit 0)

Definition at line 2627 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_CHARGE_ON_Msk

#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_ON_Msk   (0x20UL)

ANAMISC CHARGER_CTRL1_REG: CHARGE_ON (Bitfield-Mask: 0x01)

Definition at line 2630 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_CHARGE_ON_Pos

#define ANAMISC_CHARGER_CTRL1_REG_CHARGE_ON_Pos   (5UL)

ANAMISC CHARGER_CTRL1_REG: CHARGE_ON (Bit 5)

Definition at line 2629 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_DISABLE_Msk

#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_DISABLE_Msk   (0x4000UL)

ANAMISC CHARGER_CTRL1_REG: DIE_TEMP_DISABLE (Bitfield-Mask: 0x01)

Definition at line 2640 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_DISABLE_Pos

#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_DISABLE_Pos   (14UL)

ANAMISC CHARGER_CTRL1_REG: DIE_TEMP_DISABLE (Bit 14)

Definition at line 2639 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_SET_Msk

#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_SET_Msk   (0x3000UL)

ANAMISC CHARGER_CTRL1_REG: DIE_TEMP_SET (Bitfield-Mask: 0x03)

Definition at line 2638 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_SET_Pos

#define ANAMISC_CHARGER_CTRL1_REG_DIE_TEMP_SET_Pos   (12UL)

ANAMISC CHARGER_CTRL1_REG: DIE_TEMP_SET (Bit 12)

Definition at line 2637 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_NTC_DISABLE_Msk

#define ANAMISC_CHARGER_CTRL1_REG_NTC_DISABLE_Msk   (0x40UL)

ANAMISC CHARGER_CTRL1_REG: NTC_DISABLE (Bitfield-Mask: 0x01)

Definition at line 2632 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_NTC_DISABLE_Pos

#define ANAMISC_CHARGER_CTRL1_REG_NTC_DISABLE_Pos   (6UL)

ANAMISC CHARGER_CTRL1_REG: NTC_DISABLE (Bit 6)

Definition at line 2631 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_NTC_LOW_DISABLE_Msk

#define ANAMISC_CHARGER_CTRL1_REG_NTC_LOW_DISABLE_Msk   (0x80UL)

ANAMISC CHARGER_CTRL1_REG: NTC_LOW_DISABLE (Bitfield-Mask: 0x01)

Definition at line 2634 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL1_REG_NTC_LOW_DISABLE_Pos

#define ANAMISC_CHARGER_CTRL1_REG_NTC_LOW_DISABLE_Pos   (7UL)

ANAMISC CHARGER_CTRL1_REG: NTC_LOW_DISABLE (Bit 7)

Definition at line 2633 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL2_REG_CHARGER_TEST_Msk

#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_TEST_Msk   (0xe000UL)

ANAMISC CHARGER_CTRL2_REG: CHARGER_TEST (Bitfield-Mask: 0x07)

Definition at line 2650 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL2_REG_CHARGER_TEST_Pos

#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_TEST_Pos   (13UL)

ANAMISC CHARGER_CTRL2_REG: CHARGER_TEST (Bit 13)

Definition at line 2649 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL2_REG_CHARGER_VFLOAT_ADJ_Msk

#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_VFLOAT_ADJ_Msk   (0xf0UL)

ANAMISC CHARGER_CTRL2_REG: CHARGER_VFLOAT_ADJ (Bitfield-Mask: 0x0f)

Definition at line 2646 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL2_REG_CHARGER_VFLOAT_ADJ_Pos

#define ANAMISC_CHARGER_CTRL2_REG_CHARGER_VFLOAT_ADJ_Pos   (4UL)

ANAMISC CHARGER_CTRL2_REG: CHARGER_VFLOAT_ADJ (Bit 4)

Definition at line 2645 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL2_REG_CURRENT_GAIN_TRIM_Msk

#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_GAIN_TRIM_Msk   (0xfUL)

ANAMISC CHARGER_CTRL2_REG: CURRENT_GAIN_TRIM (Bitfield-Mask: 0x0f)

Definition at line 2644 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL2_REG_CURRENT_GAIN_TRIM_Pos

#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_GAIN_TRIM_Pos   (0UL)

ANAMISC CHARGER_CTRL2_REG: CURRENT_GAIN_TRIM (Bit 0)

Definition at line 2643 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL2_REG_CURRENT_OFFSET_TRIM_Msk

#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_OFFSET_TRIM_Msk   (0x1f00UL)

ANAMISC CHARGER_CTRL2_REG: CURRENT_OFFSET_TRIM (Bitfield-Mask: 0x1f)

Definition at line 2648 of file DA14680BA.h.

◆ ANAMISC_CHARGER_CTRL2_REG_CURRENT_OFFSET_TRIM_Pos

#define ANAMISC_CHARGER_CTRL2_REG_CURRENT_OFFSET_TRIM_Pos   (8UL)

ANAMISC CHARGER_CTRL2_REG: CURRENT_OFFSET_TRIM (Bit 8)

Definition at line 2647 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_HIGH_Msk

#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_HIGH_Msk   (0x20UL)

ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_HIGH (Bitfield-Mask: 0x01)

Definition at line 2664 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_HIGH_Pos

#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_HIGH_Pos   (5UL)

ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_HIGH (Bit 5)

Definition at line 2663 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_LOW_Msk

#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_LOW_Msk   (0x8UL)

ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_LOW (Bitfield-Mask: 0x01)

Definition at line 2660 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_LOW_Pos

#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_LOW_Pos   (3UL)

ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_LOW (Bit 3)

Definition at line 2659 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_OK_Msk

#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_OK_Msk   (0x10UL)

ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_OK (Bitfield-Mask: 0x01)

Definition at line 2662 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_OK_Pos

#define ANAMISC_CHARGER_STATUS_REG_CHARGER_BATTEMP_OK_Pos   (4UL)

ANAMISC CHARGER_STATUS_REG: CHARGER_BATTEMP_OK (Bit 4)

Definition at line 2661 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_CHARGER_CC_MODE_Msk

#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CC_MODE_Msk   (0x1UL)

ANAMISC CHARGER_STATUS_REG: CHARGER_CC_MODE (Bitfield-Mask: 0x01)

Definition at line 2654 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_CHARGER_CC_MODE_Pos

#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CC_MODE_Pos   (0UL)

ANAMISC CHARGER_STATUS_REG: CHARGER_CC_MODE (Bit 0)

Definition at line 2653 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_CHARGER_CV_MODE_Msk

#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CV_MODE_Msk   (0x2UL)

ANAMISC CHARGER_STATUS_REG: CHARGER_CV_MODE (Bitfield-Mask: 0x01)

Definition at line 2656 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_CHARGER_CV_MODE_Pos

#define ANAMISC_CHARGER_STATUS_REG_CHARGER_CV_MODE_Pos   (1UL)

ANAMISC CHARGER_STATUS_REG: CHARGER_CV_MODE (Bit 1)

Definition at line 2655 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_CHARGER_TMODE_PROT_Msk

#define ANAMISC_CHARGER_STATUS_REG_CHARGER_TMODE_PROT_Msk   (0x40UL)

ANAMISC CHARGER_STATUS_REG: CHARGER_TMODE_PROT (Bitfield-Mask: 0x01)

Definition at line 2666 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_CHARGER_TMODE_PROT_Pos

#define ANAMISC_CHARGER_STATUS_REG_CHARGER_TMODE_PROT_Pos   (6UL)

ANAMISC CHARGER_STATUS_REG: CHARGER_TMODE_PROT (Bit 6)

Definition at line 2665 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_END_OF_CHARGE_Msk

#define ANAMISC_CHARGER_STATUS_REG_END_OF_CHARGE_Msk   (0x4UL)

ANAMISC CHARGER_STATUS_REG: END_OF_CHARGE (Bitfield-Mask: 0x01)

Definition at line 2658 of file DA14680BA.h.

◆ ANAMISC_CHARGER_STATUS_REG_END_OF_CHARGE_Pos

#define ANAMISC_CHARGER_STATUS_REG_END_OF_CHARGE_Pos   (2UL)

ANAMISC CHARGER_STATUS_REG: END_OF_CHARGE (Bit 2)

Definition at line 2657 of file DA14680BA.h.

◆ ANAMISC_CLK_REF_CNT_REG_REF_CNT_VAL_Msk

#define ANAMISC_CLK_REF_CNT_REG_REF_CNT_VAL_Msk   (0xffffUL)

ANAMISC CLK_REF_CNT_REG: REF_CNT_VAL (Bitfield-Mask: 0xffff)

Definition at line 2782 of file DA14680BA.h.

◆ ANAMISC_CLK_REF_CNT_REG_REF_CNT_VAL_Pos

#define ANAMISC_CLK_REF_CNT_REG_REF_CNT_VAL_Pos   (0UL)

ANAMISC CLK_REF_CNT_REG: REF_CNT_VAL (Bit 0)

Definition at line 2781 of file DA14680BA.h.

◆ ANAMISC_CLK_REF_SEL_REG_REF_CAL_START_Msk

#define ANAMISC_CLK_REF_SEL_REG_REF_CAL_START_Msk   (0x4UL)

ANAMISC CLK_REF_SEL_REG: REF_CAL_START (Bitfield-Mask: 0x01)

Definition at line 2778 of file DA14680BA.h.

◆ ANAMISC_CLK_REF_SEL_REG_REF_CAL_START_Pos

#define ANAMISC_CLK_REF_SEL_REG_REF_CAL_START_Pos   (2UL)

ANAMISC CLK_REF_SEL_REG: REF_CAL_START (Bit 2)

Definition at line 2777 of file DA14680BA.h.

◆ ANAMISC_CLK_REF_SEL_REG_REF_CLK_SEL_Msk

#define ANAMISC_CLK_REF_SEL_REG_REF_CLK_SEL_Msk   (0x3UL)

ANAMISC CLK_REF_SEL_REG: REF_CLK_SEL (Bitfield-Mask: 0x03)

Definition at line 2776 of file DA14680BA.h.

◆ ANAMISC_CLK_REF_SEL_REG_REF_CLK_SEL_Pos

#define ANAMISC_CLK_REF_SEL_REG_REF_CLK_SEL_Pos   (0UL)

ANAMISC CLK_REF_SEL_REG: REF_CLK_SEL (Bit 0)

Definition at line 2775 of file DA14680BA.h.

◆ ANAMISC_CLK_REF_VAL_H_REG_XTAL_CNT_VAL_Msk

#define ANAMISC_CLK_REF_VAL_H_REG_XTAL_CNT_VAL_Msk   (0xffffUL)

ANAMISC CLK_REF_VAL_H_REG: XTAL_CNT_VAL (Bitfield-Mask: 0xffff)

Definition at line 2790 of file DA14680BA.h.

◆ ANAMISC_CLK_REF_VAL_H_REG_XTAL_CNT_VAL_Pos

#define ANAMISC_CLK_REF_VAL_H_REG_XTAL_CNT_VAL_Pos   (0UL)

ANAMISC CLK_REF_VAL_H_REG: XTAL_CNT_VAL (Bit 0)

Definition at line 2789 of file DA14680BA.h.

◆ ANAMISC_CLK_REF_VAL_L_REG_XTAL_CNT_VAL_Msk

#define ANAMISC_CLK_REF_VAL_L_REG_XTAL_CNT_VAL_Msk   (0xffffUL)

ANAMISC CLK_REF_VAL_L_REG: XTAL_CNT_VAL (Bitfield-Mask: 0xffff)

Definition at line 2786 of file DA14680BA.h.

◆ ANAMISC_CLK_REF_VAL_L_REG_XTAL_CNT_VAL_Pos

#define ANAMISC_CLK_REF_VAL_L_REG_XTAL_CNT_VAL_Pos   (0UL)

ANAMISC CLK_REF_VAL_L_REG: XTAL_CNT_VAL (Bit 0)

Definition at line 2785 of file DA14680BA.h.

◆ ANAMISC_SOC_ADD2CH_REG_SOC_ADD2CH_Msk

#define ANAMISC_SOC_ADD2CH_REG_SOC_ADD2CH_Msk   (0xffffUL)

ANAMISC SOC_ADD2CH_REG: SOC_ADD2CH (Bitfield-Mask: 0xffff)

Definition at line 2722 of file DA14680BA.h.

◆ ANAMISC_SOC_ADD2CH_REG_SOC_ADD2CH_Pos

#define ANAMISC_SOC_ADD2CH_REG_SOC_ADD2CH_Pos   (0UL)

ANAMISC SOC_ADD2CH_REG: SOC_ADD2CH (Bit 0)

Definition at line 2721 of file DA14680BA.h.

◆ ANAMISC_SOC_CHARGE_AVG_REG_CHARGE_AVG_Msk

#define ANAMISC_SOC_CHARGE_AVG_REG_CHARGE_AVG_Msk   (0xffffUL)

ANAMISC SOC_CHARGE_AVG_REG: CHARGE_AVG (Bitfield-Mask: 0xffff)

Definition at line 2738 of file DA14680BA.h.

◆ ANAMISC_SOC_CHARGE_AVG_REG_CHARGE_AVG_Pos

#define ANAMISC_SOC_CHARGE_AVG_REG_CHARGE_AVG_Pos   (0UL)

ANAMISC SOC_CHARGE_AVG_REG: CHARGE_AVG (Bit 0)

Definition at line 2737 of file DA14680BA.h.

◆ ANAMISC_SOC_CHARGE_CNTR1_REG_CHARGE_CNT1_Msk

#define ANAMISC_SOC_CHARGE_CNTR1_REG_CHARGE_CNT1_Msk   (0xffffUL)

ANAMISC SOC_CHARGE_CNTR1_REG: CHARGE_CNT1 (Bitfield-Mask: 0xffff)

Definition at line 2726 of file DA14680BA.h.

◆ ANAMISC_SOC_CHARGE_CNTR1_REG_CHARGE_CNT1_Pos

#define ANAMISC_SOC_CHARGE_CNTR1_REG_CHARGE_CNT1_Pos   (0UL)

ANAMISC SOC_CHARGE_CNTR1_REG: CHARGE_CNT1 (Bit 0)

Definition at line 2725 of file DA14680BA.h.

◆ ANAMISC_SOC_CHARGE_CNTR2_REG_CHARGE_CNT2_Msk

#define ANAMISC_SOC_CHARGE_CNTR2_REG_CHARGE_CNT2_Msk   (0xffffUL)

ANAMISC SOC_CHARGE_CNTR2_REG: CHARGE_CNT2 (Bitfield-Mask: 0xffff)

Definition at line 2730 of file DA14680BA.h.

◆ ANAMISC_SOC_CHARGE_CNTR2_REG_CHARGE_CNT2_Pos

#define ANAMISC_SOC_CHARGE_CNTR2_REG_CHARGE_CNT2_Pos   (0UL)

ANAMISC SOC_CHARGE_CNTR2_REG: CHARGE_CNT2 (Bit 0)

Definition at line 2729 of file DA14680BA.h.

◆ ANAMISC_SOC_CHARGE_CNTR3_REG_CHARGE_CNT3_Msk

#define ANAMISC_SOC_CHARGE_CNTR3_REG_CHARGE_CNT3_Msk   (0xffUL)

ANAMISC SOC_CHARGE_CNTR3_REG: CHARGE_CNT3 (Bitfield-Mask: 0xff)

Definition at line 2734 of file DA14680BA.h.

◆ ANAMISC_SOC_CHARGE_CNTR3_REG_CHARGE_CNT3_Pos

#define ANAMISC_SOC_CHARGE_CNTR3_REG_CHARGE_CNT3_Pos   (0UL)

ANAMISC SOC_CHARGE_CNTR3_REG: CHARGE_CNT3 (Bit 0)

Definition at line 2733 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_BIAS_Msk

#define ANAMISC_SOC_CTRL1_REG_SOC_BIAS_Msk   (0x3000UL)

ANAMISC SOC_CTRL1_REG: SOC_BIAS (Bitfield-Mask: 0x03)

Definition at line 2688 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_BIAS_Pos

#define ANAMISC_SOC_CTRL1_REG_SOC_BIAS_Pos   (12UL)

ANAMISC SOC_CTRL1_REG: SOC_BIAS (Bit 12)

Definition at line 2687 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_CINT_Msk

#define ANAMISC_SOC_CTRL1_REG_SOC_CINT_Msk   (0xc000UL)

ANAMISC SOC_CTRL1_REG: SOC_CINT (Bitfield-Mask: 0x03)

Definition at line 2690 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_CINT_Pos

#define ANAMISC_SOC_CTRL1_REG_SOC_CINT_Pos   (14UL)

ANAMISC SOC_CTRL1_REG: SOC_CINT (Bit 14)

Definition at line 2689 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_CLK_Msk

#define ANAMISC_SOC_CTRL1_REG_SOC_CLK_Msk   (0xe00UL)

ANAMISC SOC_CTRL1_REG: SOC_CLK (Bitfield-Mask: 0x07)

Definition at line 2686 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_CLK_Pos

#define ANAMISC_SOC_CTRL1_REG_SOC_CLK_Pos   (9UL)

ANAMISC SOC_CTRL1_REG: SOC_CLK (Bit 9)

Definition at line 2685 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_ENABLE_Msk

#define ANAMISC_SOC_CTRL1_REG_SOC_ENABLE_Msk   (0x1UL)

ANAMISC SOC_CTRL1_REG: SOC_ENABLE (Bitfield-Mask: 0x01)

Definition at line 2670 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_ENABLE_Pos

#define ANAMISC_SOC_CTRL1_REG_SOC_ENABLE_Pos   (0UL)

ANAMISC SOC_CTRL1_REG: SOC_ENABLE (Bit 0)

Definition at line 2669 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_GPIO_Msk

#define ANAMISC_SOC_CTRL1_REG_SOC_GPIO_Msk   (0x10UL)

ANAMISC SOC_CTRL1_REG: SOC_GPIO (Bitfield-Mask: 0x01)

Definition at line 2678 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_GPIO_Pos

#define ANAMISC_SOC_CTRL1_REG_SOC_GPIO_Pos   (4UL)

ANAMISC SOC_CTRL1_REG: SOC_GPIO (Bit 4)

Definition at line 2677 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_IDAC_Msk

#define ANAMISC_SOC_CTRL1_REG_SOC_IDAC_Msk   (0xc0UL)

ANAMISC SOC_CTRL1_REG: SOC_IDAC (Bitfield-Mask: 0x03)

Definition at line 2682 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_IDAC_Pos

#define ANAMISC_SOC_CTRL1_REG_SOC_IDAC_Pos   (6UL)

ANAMISC SOC_CTRL1_REG: SOC_IDAC (Bit 6)

Definition at line 2681 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_LPF_Msk

#define ANAMISC_SOC_CTRL1_REG_SOC_LPF_Msk   (0x100UL)

ANAMISC SOC_CTRL1_REG: SOC_LPF (Bitfield-Mask: 0x01)

Definition at line 2684 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_LPF_Pos

#define ANAMISC_SOC_CTRL1_REG_SOC_LPF_Pos   (8UL)

ANAMISC SOC_CTRL1_REG: SOC_LPF (Bit 8)

Definition at line 2683 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_MUTE_Msk

#define ANAMISC_SOC_CTRL1_REG_SOC_MUTE_Msk   (0x8UL)

ANAMISC SOC_CTRL1_REG: SOC_MUTE (Bitfield-Mask: 0x01)

Definition at line 2676 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_MUTE_Pos

#define ANAMISC_SOC_CTRL1_REG_SOC_MUTE_Pos   (3UL)

ANAMISC SOC_CTRL1_REG: SOC_MUTE (Bit 3)

Definition at line 2675 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_RESET_AVG_Msk

#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_AVG_Msk   (0x4UL)

ANAMISC SOC_CTRL1_REG: SOC_RESET_AVG (Bitfield-Mask: 0x01)

Definition at line 2674 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_RESET_AVG_Pos

#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_AVG_Pos   (2UL)

ANAMISC SOC_CTRL1_REG: SOC_RESET_AVG (Bit 2)

Definition at line 2673 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_RESET_CHARGE_Msk

#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_CHARGE_Msk   (0x2UL)

ANAMISC SOC_CTRL1_REG: SOC_RESET_CHARGE (Bitfield-Mask: 0x01)

Definition at line 2672 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_RESET_CHARGE_Pos

#define ANAMISC_SOC_CTRL1_REG_SOC_RESET_CHARGE_Pos   (1UL)

ANAMISC SOC_CTRL1_REG: SOC_RESET_CHARGE (Bit 1)

Definition at line 2671 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_SIGN_Msk

#define ANAMISC_SOC_CTRL1_REG_SOC_SIGN_Msk   (0x20UL)

ANAMISC SOC_CTRL1_REG: SOC_SIGN (Bitfield-Mask: 0x01)

Definition at line 2680 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL1_REG_SOC_SIGN_Pos

#define ANAMISC_SOC_CTRL1_REG_SOC_SIGN_Pos   (5UL)

ANAMISC SOC_CTRL1_REG: SOC_SIGN (Bit 5)

Definition at line 2679 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_CHOP_Msk

#define ANAMISC_SOC_CTRL2_REG_SOC_CHOP_Msk   (0x700UL)

ANAMISC SOC_CTRL2_REG: SOC_CHOP (Bitfield-Mask: 0x07)

Definition at line 2702 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_CHOP_Pos

#define ANAMISC_SOC_CTRL2_REG_SOC_CHOP_Pos   (8UL)

ANAMISC SOC_CTRL2_REG: SOC_CHOP (Bit 8)

Definition at line 2701 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_CMIREG_ENABLE_Msk

#define ANAMISC_SOC_CTRL2_REG_SOC_CMIREG_ENABLE_Msk   (0x800UL)

ANAMISC SOC_CTRL2_REG: SOC_CMIREG_ENABLE (Bitfield-Mask: 0x01)

Definition at line 2704 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_CMIREG_ENABLE_Pos

#define ANAMISC_SOC_CTRL2_REG_SOC_CMIREG_ENABLE_Pos   (11UL)

ANAMISC SOC_CTRL2_REG: SOC_CMIREG_ENABLE (Bit 11)

Definition at line 2703 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_DCYCLE_Msk

#define ANAMISC_SOC_CTRL2_REG_SOC_DCYCLE_Msk   (0x20UL)

ANAMISC SOC_CTRL2_REG: SOC_DCYCLE (Bitfield-Mask: 0x01)

Definition at line 2698 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_DCYCLE_Pos

#define ANAMISC_SOC_CTRL2_REG_SOC_DCYCLE_Pos   (5UL)

ANAMISC SOC_CTRL2_REG: SOC_DCYCLE (Bit 5)

Definition at line 2697 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_DYNAVG_Msk

#define ANAMISC_SOC_CTRL2_REG_SOC_DYNAVG_Msk   (0x8000UL)

ANAMISC SOC_CTRL2_REG: SOC_DYNAVG (Bitfield-Mask: 0x01)

Definition at line 2708 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_DYNAVG_Pos

#define ANAMISC_SOC_CTRL2_REG_SOC_DYNAVG_Pos   (15UL)

ANAMISC SOC_CTRL2_REG: SOC_DYNAVG (Bit 15)

Definition at line 2707 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_ICM_Msk

#define ANAMISC_SOC_CTRL2_REG_SOC_ICM_Msk   (0xc0UL)

ANAMISC SOC_CTRL2_REG: SOC_ICM (Bitfield-Mask: 0x03)

Definition at line 2700 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_ICM_Pos

#define ANAMISC_SOC_CTRL2_REG_SOC_ICM_Pos   (6UL)

ANAMISC SOC_CTRL2_REG: SOC_ICM (Bit 6)

Definition at line 2699 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_MAW_Msk

#define ANAMISC_SOC_CTRL2_REG_SOC_MAW_Msk   (0x7000UL)

ANAMISC SOC_CTRL2_REG: SOC_MAW (Bitfield-Mask: 0x07)

Definition at line 2706 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_MAW_Pos

#define ANAMISC_SOC_CTRL2_REG_SOC_MAW_Pos   (12UL)

ANAMISC SOC_CTRL2_REG: SOC_MAW (Bit 12)

Definition at line 2705 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_RVI_Msk

#define ANAMISC_SOC_CTRL2_REG_SOC_RVI_Msk   (0x3UL)

ANAMISC SOC_CTRL2_REG: SOC_RVI (Bitfield-Mask: 0x03)

Definition at line 2694 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_RVI_Pos

#define ANAMISC_SOC_CTRL2_REG_SOC_RVI_Pos   (0UL)

ANAMISC SOC_CTRL2_REG: SOC_RVI (Bit 0)

Definition at line 2693 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_SCYCLE_Msk

#define ANAMISC_SOC_CTRL2_REG_SOC_SCYCLE_Msk   (0x1cUL)

ANAMISC SOC_CTRL2_REG: SOC_SCYCLE (Bitfield-Mask: 0x07)

Definition at line 2696 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL2_REG_SOC_SCYCLE_Pos

#define ANAMISC_SOC_CTRL2_REG_SOC_SCYCLE_Pos   (2UL)

ANAMISC SOC_CTRL2_REG: SOC_SCYCLE (Bit 2)

Definition at line 2695 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL3_REG_SOC_DYNHYS_Msk

#define ANAMISC_SOC_CTRL3_REG_SOC_DYNHYS_Msk   (0x8UL)

ANAMISC SOC_CTRL3_REG: SOC_DYNHYS (Bitfield-Mask: 0x01)

Definition at line 2716 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL3_REG_SOC_DYNHYS_Pos

#define ANAMISC_SOC_CTRL3_REG_SOC_DYNHYS_Pos   (3UL)

ANAMISC SOC_CTRL3_REG: SOC_DYNHYS (Bit 3)

Definition at line 2715 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL3_REG_SOC_DYNTARG_Msk

#define ANAMISC_SOC_CTRL3_REG_SOC_DYNTARG_Msk   (0x4UL)

ANAMISC SOC_CTRL3_REG: SOC_DYNTARG (Bitfield-Mask: 0x01)

Definition at line 2714 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL3_REG_SOC_DYNTARG_Pos

#define ANAMISC_SOC_CTRL3_REG_SOC_DYNTARG_Pos   (2UL)

ANAMISC SOC_CTRL3_REG: SOC_DYNTARG (Bit 2)

Definition at line 2713 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL3_REG_SOC_VCMI_Msk

#define ANAMISC_SOC_CTRL3_REG_SOC_VCMI_Msk   (0x30UL)

ANAMISC SOC_CTRL3_REG: SOC_VCMI (Bitfield-Mask: 0x03)

Definition at line 2718 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL3_REG_SOC_VCMI_Pos

#define ANAMISC_SOC_CTRL3_REG_SOC_VCMI_Pos   (4UL)

ANAMISC SOC_CTRL3_REG: SOC_VCMI (Bit 4)

Definition at line 2717 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL3_REG_SOC_VSAT_Msk

#define ANAMISC_SOC_CTRL3_REG_SOC_VSAT_Msk   (0x3UL)

ANAMISC SOC_CTRL3_REG: SOC_VSAT (Bitfield-Mask: 0x03)

Definition at line 2712 of file DA14680BA.h.

◆ ANAMISC_SOC_CTRL3_REG_SOC_VSAT_Pos

#define ANAMISC_SOC_CTRL3_REG_SOC_VSAT_Pos   (0UL)

ANAMISC SOC_CTRL3_REG: SOC_VSAT (Bit 0)

Definition at line 2711 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_IN_REG_SOC_EXT_IDAC_EN_Msk

#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_IDAC_EN_Msk   (0x8000UL)

ANAMISC SOC_EXT_IN_REG: SOC_EXT_IDAC_EN (Bitfield-Mask: 0x01)

Definition at line 2758 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_IN_REG_SOC_EXT_IDAC_EN_Pos

#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_IDAC_EN_Pos   (15UL)

ANAMISC SOC_EXT_IN_REG: SOC_EXT_IDAC_EN (Bit 15)

Definition at line 2757 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_IN_REG_SOC_EXT_SCYCLE_EN_Msk

#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_SCYCLE_EN_Msk   (0x4000UL)

ANAMISC SOC_EXT_IN_REG: SOC_EXT_SCYCLE_EN (Bitfield-Mask: 0x01)

Definition at line 2756 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_IN_REG_SOC_EXT_SCYCLE_EN_Pos

#define ANAMISC_SOC_EXT_IN_REG_SOC_EXT_SCYCLE_EN_Pos   (14UL)

ANAMISC SOC_EXT_IN_REG: SOC_EXT_SCYCLE_EN (Bit 14)

Definition at line 2755 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_SIGN_Msk

#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_SIGN_Msk   (0x200UL)

ANAMISC SOC_EXT_IN_REG: SOC_IDAC_SIGN (Bitfield-Mask: 0x01)

Definition at line 2750 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_SIGN_Pos

#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_SIGN_Pos   (9UL)

ANAMISC SOC_EXT_IN_REG: SOC_IDAC_SIGN (Bit 9)

Definition at line 2749 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_VAL_Msk

#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_VAL_Msk   (0x1ffUL)

ANAMISC SOC_EXT_IN_REG: SOC_IDAC_VAL (Bitfield-Mask: 0x1ff)

Definition at line 2748 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_VAL_Pos

#define ANAMISC_SOC_EXT_IN_REG_SOC_IDAC_VAL_Pos   (0UL)

ANAMISC SOC_EXT_IN_REG: SOC_IDAC_VAL (Bit 0)

Definition at line 2747 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_IN_REG_SOC_NR_SCYCLE_Msk

#define ANAMISC_SOC_EXT_IN_REG_SOC_NR_SCYCLE_Msk   (0x3800UL)

ANAMISC SOC_EXT_IN_REG: SOC_NR_SCYCLE (Bitfield-Mask: 0x07)

Definition at line 2754 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_IN_REG_SOC_NR_SCYCLE_Pos

#define ANAMISC_SOC_EXT_IN_REG_SOC_NR_SCYCLE_Pos   (11UL)

ANAMISC SOC_EXT_IN_REG: SOC_NR_SCYCLE (Bit 11)

Definition at line 2753 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_IN_REG_SOC_RDAC_DIS_Msk

#define ANAMISC_SOC_EXT_IN_REG_SOC_RDAC_DIS_Msk   (0x400UL)

ANAMISC SOC_EXT_IN_REG: SOC_RDAC_DIS (Bitfield-Mask: 0x01)

Definition at line 2752 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_IN_REG_SOC_RDAC_DIS_Pos

#define ANAMISC_SOC_EXT_IN_REG_SOC_RDAC_DIS_Pos   (10UL)

ANAMISC SOC_EXT_IN_REG: SOC_RDAC_DIS (Bit 10)

Definition at line 2751 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_OUT_REG_SOC_CTRL_EVENT_Msk

#define ANAMISC_SOC_EXT_OUT_REG_SOC_CTRL_EVENT_Msk   (0x100UL)

ANAMISC SOC_EXT_OUT_REG: SOC_CTRL_EVENT (Bitfield-Mask: 0x01)

Definition at line 2772 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_OUT_REG_SOC_CTRL_EVENT_Pos

#define ANAMISC_SOC_EXT_OUT_REG_SOC_CTRL_EVENT_Pos   (8UL)

ANAMISC SOC_EXT_OUT_REG: SOC_CTRL_EVENT (Bit 8)

Definition at line 2771 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_OUT_REG_SOC_HIGH_LIM_Msk

#define ANAMISC_SOC_EXT_OUT_REG_SOC_HIGH_LIM_Msk   (0x1UL)

ANAMISC SOC_EXT_OUT_REG: SOC_HIGH_LIM (Bitfield-Mask: 0x01)

Definition at line 2762 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_OUT_REG_SOC_HIGH_LIM_Pos

#define ANAMISC_SOC_EXT_OUT_REG_SOC_HIGH_LIM_Pos   (0UL)

ANAMISC SOC_EXT_OUT_REG: SOC_HIGH_LIM (Bit 0)

Definition at line 2761 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_OUT_REG_SOC_LOWLIM_COMP_Msk

#define ANAMISC_SOC_EXT_OUT_REG_SOC_LOWLIM_COMP_Msk   (0x2UL)

ANAMISC SOC_EXT_OUT_REG: SOC_LOWLIM_COMP (Bitfield-Mask: 0x01)

Definition at line 2764 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_OUT_REG_SOC_LOWLIM_COMP_Pos

#define ANAMISC_SOC_EXT_OUT_REG_SOC_LOWLIM_COMP_Pos   (1UL)

ANAMISC SOC_EXT_OUT_REG: SOC_LOWLIM_COMP (Bit 1)

Definition at line 2763 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_OUT_REG_SOC_POS_COMP_Msk

#define ANAMISC_SOC_EXT_OUT_REG_SOC_POS_COMP_Msk   (0x4UL)

ANAMISC SOC_EXT_OUT_REG: SOC_POS_COMP (Bitfield-Mask: 0x01)

Definition at line 2766 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_OUT_REG_SOC_POS_COMP_Pos

#define ANAMISC_SOC_EXT_OUT_REG_SOC_POS_COMP_Pos   (2UL)

ANAMISC SOC_EXT_OUT_REG: SOC_POS_COMP (Bit 2)

Definition at line 2765 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_OUT_REG_SOC_RISING_COMP_Msk

#define ANAMISC_SOC_EXT_OUT_REG_SOC_RISING_COMP_Msk   (0x8UL)

ANAMISC SOC_EXT_OUT_REG: SOC_RISING_COMP (Bitfield-Mask: 0x01)

Definition at line 2768 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_OUT_REG_SOC_RISING_COMP_Pos

#define ANAMISC_SOC_EXT_OUT_REG_SOC_RISING_COMP_Pos   (3UL)

ANAMISC SOC_EXT_OUT_REG: SOC_RISING_COMP (Bit 3)

Definition at line 2767 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_OUT_REG_SOC_STATE_Msk

#define ANAMISC_SOC_EXT_OUT_REG_SOC_STATE_Msk   (0xf0UL)

ANAMISC SOC_EXT_OUT_REG: SOC_STATE (Bitfield-Mask: 0x0f)

Definition at line 2770 of file DA14680BA.h.

◆ ANAMISC_SOC_EXT_OUT_REG_SOC_STATE_Pos

#define ANAMISC_SOC_EXT_OUT_REG_SOC_STATE_Pos   (4UL)

ANAMISC SOC_EXT_OUT_REG: SOC_STATE (Bit 4)

Definition at line 2769 of file DA14680BA.h.

◆ ANAMISC_SOC_STATUS_REG_SOC_INT_LOCKED_Msk

#define ANAMISC_SOC_STATUS_REG_SOC_INT_LOCKED_Msk   (0x2UL)

ANAMISC SOC_STATUS_REG: SOC_INT_LOCKED (Bitfield-Mask: 0x01)

Definition at line 2744 of file DA14680BA.h.

◆ ANAMISC_SOC_STATUS_REG_SOC_INT_LOCKED_Pos

#define ANAMISC_SOC_STATUS_REG_SOC_INT_LOCKED_Pos   (1UL)

ANAMISC SOC_STATUS_REG: SOC_INT_LOCKED (Bit 1)

Definition at line 2743 of file DA14680BA.h.

◆ ANAMISC_SOC_STATUS_REG_SOC_INT_OVERLOAD_Msk

#define ANAMISC_SOC_STATUS_REG_SOC_INT_OVERLOAD_Msk   (0x1UL)

ANAMISC SOC_STATUS_REG: SOC_INT_OVERLOAD (Bitfield-Mask: 0x01)

Definition at line 2742 of file DA14680BA.h.

◆ ANAMISC_SOC_STATUS_REG_SOC_INT_OVERLOAD_Pos

#define ANAMISC_SOC_STATUS_REG_SOC_INT_OVERLOAD_Pos   (0UL)

ANAMISC SOC_STATUS_REG: SOC_INT_OVERLOAD (Bit 0)

Definition at line 2741 of file DA14680BA.h.

◆ APU

#define APU   ((APU_Type *) APU_BASE)

Definition at line 12075 of file DA14680BA.h.

◆ APU_APU_MUX_REG_PCM1_MUX_IN_Msk

#define APU_APU_MUX_REG_PCM1_MUX_IN_Msk   (0x38UL)

APU APU_MUX_REG: PCM1_MUX_IN (Bitfield-Mask: 0x07)

Definition at line 2868 of file DA14680BA.h.

◆ APU_APU_MUX_REG_PCM1_MUX_IN_Pos

#define APU_APU_MUX_REG_PCM1_MUX_IN_Pos   (3UL)

APU APU_MUX_REG: PCM1_MUX_IN (Bit 3)

Definition at line 2867 of file DA14680BA.h.

◆ APU_APU_MUX_REG_PDM1_MUX_IN_Msk

#define APU_APU_MUX_REG_PDM1_MUX_IN_Msk   (0x40UL)

APU APU_MUX_REG: PDM1_MUX_IN (Bitfield-Mask: 0x01)

Definition at line 2870 of file DA14680BA.h.

◆ APU_APU_MUX_REG_PDM1_MUX_IN_Pos

#define APU_APU_MUX_REG_PDM1_MUX_IN_Pos   (6UL)

APU APU_MUX_REG: PDM1_MUX_IN (Bit 6)

Definition at line 2869 of file DA14680BA.h.

◆ APU_APU_MUX_REG_SRC1_MUX_IN_Msk

#define APU_APU_MUX_REG_SRC1_MUX_IN_Msk   (0x7UL)

APU APU_MUX_REG: SRC1_MUX_IN (Bitfield-Mask: 0x07)

Definition at line 2866 of file DA14680BA.h.

◆ APU_APU_MUX_REG_SRC1_MUX_IN_Pos

#define APU_APU_MUX_REG_SRC1_MUX_IN_Pos   (0UL)

APU APU_MUX_REG: SRC1_MUX_IN (Bit 0)

Definition at line 2865 of file DA14680BA.h.

◆ APU_BASE

#define APU_BASE   0x50004000UL

Definition at line 12030 of file DA14680BA.h.

◆ APU_COEF0A_SET1_REG_SRC_COEF10_Msk

#define APU_COEF0A_SET1_REG_SRC_COEF10_Msk   (0xffffUL)

APU COEF0A_SET1_REG: SRC_COEF10 (Bitfield-Mask: 0xffff)

Definition at line 2904 of file DA14680BA.h.

◆ APU_COEF0A_SET1_REG_SRC_COEF10_Pos

#define APU_COEF0A_SET1_REG_SRC_COEF10_Pos   (0UL)

APU COEF0A_SET1_REG: SRC_COEF10 (Bit 0)

Definition at line 2903 of file DA14680BA.h.

◆ APU_COEF10_SET1_REG_SRC_COEF0_Msk

#define APU_COEF10_SET1_REG_SRC_COEF0_Msk   (0xffffUL)

APU COEF10_SET1_REG: SRC_COEF0 (Bitfield-Mask: 0xffff)

Definition at line 2874 of file DA14680BA.h.

◆ APU_COEF10_SET1_REG_SRC_COEF0_Pos

#define APU_COEF10_SET1_REG_SRC_COEF0_Pos   (0UL)

APU COEF10_SET1_REG: SRC_COEF0 (Bit 0)

Definition at line 2873 of file DA14680BA.h.

◆ APU_COEF10_SET1_REG_SRC_COEF1_Msk

#define APU_COEF10_SET1_REG_SRC_COEF1_Msk   (0xffff0000UL)

APU COEF10_SET1_REG: SRC_COEF1 (Bitfield-Mask: 0xffff)

Definition at line 2876 of file DA14680BA.h.

◆ APU_COEF10_SET1_REG_SRC_COEF1_Pos

#define APU_COEF10_SET1_REG_SRC_COEF1_Pos   (16UL)

APU COEF10_SET1_REG: SRC_COEF1 (Bit 16)

Definition at line 2875 of file DA14680BA.h.

◆ APU_COEF32_SET1_REG_SRC_COEF2_Msk

#define APU_COEF32_SET1_REG_SRC_COEF2_Msk   (0xffffUL)

APU COEF32_SET1_REG: SRC_COEF2 (Bitfield-Mask: 0xffff)

Definition at line 2880 of file DA14680BA.h.

◆ APU_COEF32_SET1_REG_SRC_COEF2_Pos

#define APU_COEF32_SET1_REG_SRC_COEF2_Pos   (0UL)

APU COEF32_SET1_REG: SRC_COEF2 (Bit 0)

Definition at line 2879 of file DA14680BA.h.

◆ APU_COEF32_SET1_REG_SRC_COEF3_Msk

#define APU_COEF32_SET1_REG_SRC_COEF3_Msk   (0xffff0000UL)

APU COEF32_SET1_REG: SRC_COEF3 (Bitfield-Mask: 0xffff)

Definition at line 2882 of file DA14680BA.h.

◆ APU_COEF32_SET1_REG_SRC_COEF3_Pos

#define APU_COEF32_SET1_REG_SRC_COEF3_Pos   (16UL)

APU COEF32_SET1_REG: SRC_COEF3 (Bit 16)

Definition at line 2881 of file DA14680BA.h.

◆ APU_COEF54_SET1_REG_SRC_COEF4_Msk

#define APU_COEF54_SET1_REG_SRC_COEF4_Msk   (0xffffUL)

APU COEF54_SET1_REG: SRC_COEF4 (Bitfield-Mask: 0xffff)

Definition at line 2886 of file DA14680BA.h.

◆ APU_COEF54_SET1_REG_SRC_COEF4_Pos

#define APU_COEF54_SET1_REG_SRC_COEF4_Pos   (0UL)

APU COEF54_SET1_REG: SRC_COEF4 (Bit 0)

Definition at line 2885 of file DA14680BA.h.

◆ APU_COEF54_SET1_REG_SRC_COEF5_Msk

#define APU_COEF54_SET1_REG_SRC_COEF5_Msk   (0xffff0000UL)

APU COEF54_SET1_REG: SRC_COEF5 (Bitfield-Mask: 0xffff)

Definition at line 2888 of file DA14680BA.h.

◆ APU_COEF54_SET1_REG_SRC_COEF5_Pos

#define APU_COEF54_SET1_REG_SRC_COEF5_Pos   (16UL)

APU COEF54_SET1_REG: SRC_COEF5 (Bit 16)

Definition at line 2887 of file DA14680BA.h.

◆ APU_COEF76_SET1_REG_SRC_COEF6_Msk

#define APU_COEF76_SET1_REG_SRC_COEF6_Msk   (0xffffUL)

APU COEF76_SET1_REG: SRC_COEF6 (Bitfield-Mask: 0xffff)

Definition at line 2892 of file DA14680BA.h.

◆ APU_COEF76_SET1_REG_SRC_COEF6_Pos

#define APU_COEF76_SET1_REG_SRC_COEF6_Pos   (0UL)

APU COEF76_SET1_REG: SRC_COEF6 (Bit 0)

Definition at line 2891 of file DA14680BA.h.

◆ APU_COEF76_SET1_REG_SRC_COEF7_Msk

#define APU_COEF76_SET1_REG_SRC_COEF7_Msk   (0xffff0000UL)

APU COEF76_SET1_REG: SRC_COEF7 (Bitfield-Mask: 0xffff)

Definition at line 2894 of file DA14680BA.h.

◆ APU_COEF76_SET1_REG_SRC_COEF7_Pos

#define APU_COEF76_SET1_REG_SRC_COEF7_Pos   (16UL)

APU COEF76_SET1_REG: SRC_COEF7 (Bit 16)

Definition at line 2893 of file DA14680BA.h.

◆ APU_COEF98_SET1_REG_SRC_COEF8_Msk

#define APU_COEF98_SET1_REG_SRC_COEF8_Msk   (0xffffUL)

APU COEF98_SET1_REG: SRC_COEF8 (Bitfield-Mask: 0xffff)

Definition at line 2898 of file DA14680BA.h.

◆ APU_COEF98_SET1_REG_SRC_COEF8_Pos

#define APU_COEF98_SET1_REG_SRC_COEF8_Pos   (0UL)

APU COEF98_SET1_REG: SRC_COEF8 (Bit 0)

Definition at line 2897 of file DA14680BA.h.

◆ APU_COEF98_SET1_REG_SRC_COEF9_Msk

#define APU_COEF98_SET1_REG_SRC_COEF9_Msk   (0xffff0000UL)

APU COEF98_SET1_REG: SRC_COEF9 (Bitfield-Mask: 0xffff)

Definition at line 2900 of file DA14680BA.h.

◆ APU_COEF98_SET1_REG_SRC_COEF9_Pos

#define APU_COEF98_SET1_REG_SRC_COEF9_Pos   (16UL)

APU COEF98_SET1_REG: SRC_COEF9 (Bit 16)

Definition at line 2899 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_CH_DEL_Msk

#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Msk   (0xf800UL)

APU PCM1_CTRL_REG: PCM_CH_DEL (Bitfield-Mask: 0x1f)

Definition at line 2924 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_CH_DEL_Pos

#define APU_PCM1_CTRL_REG_PCM_CH_DEL_Pos   (11UL)

APU PCM1_CTRL_REG: PCM_CH_DEL (Bit 11)

Definition at line 2923 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_CLK_BIT_Msk

#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Msk   (0x400UL)

APU PCM1_CTRL_REG: PCM_CLK_BIT (Bitfield-Mask: 0x01)

Definition at line 2922 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_CLK_BIT_Pos

#define APU_PCM1_CTRL_REG_PCM_CLK_BIT_Pos   (10UL)

APU PCM1_CTRL_REG: PCM_CLK_BIT (Bit 10)

Definition at line 2921 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_CLKINV_Msk

#define APU_PCM1_CTRL_REG_PCM_CLKINV_Msk   (0x100UL)

APU PCM1_CTRL_REG: PCM_CLKINV (Bitfield-Mask: 0x01)

Definition at line 2918 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_CLKINV_Pos

#define APU_PCM1_CTRL_REG_PCM_CLKINV_Pos   (8UL)

APU PCM1_CTRL_REG: PCM_CLKINV (Bit 8)

Definition at line 2917 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_EN_Msk

#define APU_PCM1_CTRL_REG_PCM_EN_Msk   (0x1UL)

APU PCM1_CTRL_REG: PCM_EN (Bitfield-Mask: 0x01)

Definition at line 2908 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_EN_Pos

#define APU_PCM1_CTRL_REG_PCM_EN_Pos   (0UL)

APU PCM1_CTRL_REG: PCM_EN (Bit 0)

Definition at line 2907 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_FSC_DIV_Msk

#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Msk   (0xfff00000UL)

APU PCM1_CTRL_REG: PCM_FSC_DIV (Bitfield-Mask: 0xfff)

Definition at line 2928 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_FSC_DIV_Pos

#define APU_PCM1_CTRL_REG_PCM_FSC_DIV_Pos   (20UL)

APU PCM1_CTRL_REG: PCM_FSC_DIV (Bit 20)

Definition at line 2927 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Msk

#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Msk   (0x10000UL)

APU PCM1_CTRL_REG: PCM_FSC_EDGE (Bitfield-Mask: 0x01)

Definition at line 2926 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Pos

#define APU_PCM1_CTRL_REG_PCM_FSC_EDGE_Pos   (16UL)

APU PCM1_CTRL_REG: PCM_FSC_EDGE (Bit 16)

Definition at line 2925 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_FSCDEL_Msk

#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Msk   (0x40UL)

APU PCM1_CTRL_REG: PCM_FSCDEL (Bitfield-Mask: 0x01)

Definition at line 2914 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_FSCDEL_Pos

#define APU_PCM1_CTRL_REG_PCM_FSCDEL_Pos   (6UL)

APU PCM1_CTRL_REG: PCM_FSCDEL (Bit 6)

Definition at line 2913 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_FSCINV_Msk

#define APU_PCM1_CTRL_REG_PCM_FSCINV_Msk   (0x200UL)

APU PCM1_CTRL_REG: PCM_FSCINV (Bitfield-Mask: 0x01)

Definition at line 2920 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_FSCINV_Pos

#define APU_PCM1_CTRL_REG_PCM_FSCINV_Pos   (9UL)

APU PCM1_CTRL_REG: PCM_FSCINV (Bit 9)

Definition at line 2919 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_FSCLEN_Msk

#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Msk   (0x3cUL)

APU PCM1_CTRL_REG: PCM_FSCLEN (Bitfield-Mask: 0x0f)

Definition at line 2912 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_FSCLEN_Pos

#define APU_PCM1_CTRL_REG_PCM_FSCLEN_Pos   (2UL)

APU PCM1_CTRL_REG: PCM_FSCLEN (Bit 2)

Definition at line 2911 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_MASTER_Msk

#define APU_PCM1_CTRL_REG_PCM_MASTER_Msk   (0x2UL)

APU PCM1_CTRL_REG: PCM_MASTER (Bitfield-Mask: 0x01)

Definition at line 2910 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_MASTER_Pos

#define APU_PCM1_CTRL_REG_PCM_MASTER_Pos   (1UL)

APU PCM1_CTRL_REG: PCM_MASTER (Bit 1)

Definition at line 2909 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_PPOD_Msk

#define APU_PCM1_CTRL_REG_PCM_PPOD_Msk   (0x80UL)

APU PCM1_CTRL_REG: PCM_PPOD (Bitfield-Mask: 0x01)

Definition at line 2916 of file DA14680BA.h.

◆ APU_PCM1_CTRL_REG_PCM_PPOD_Pos

#define APU_PCM1_CTRL_REG_PCM_PPOD_Pos   (7UL)

APU PCM1_CTRL_REG: PCM_PPOD (Bit 7)

Definition at line 2915 of file DA14680BA.h.

◆ APU_PCM1_IN1_REG_PCM_IN_Msk

#define APU_PCM1_IN1_REG_PCM_IN_Msk   (0xffffffffUL)

APU PCM1_IN1_REG: PCM_IN (Bitfield-Mask: 0xffffffff)

Definition at line 2932 of file DA14680BA.h.

◆ APU_PCM1_IN1_REG_PCM_IN_Pos

#define APU_PCM1_IN1_REG_PCM_IN_Pos   (0UL)

APU PCM1_IN1_REG: PCM_IN (Bit 0)

Definition at line 2931 of file DA14680BA.h.

◆ APU_PCM1_IN2_REG_PCM_IN_Msk

#define APU_PCM1_IN2_REG_PCM_IN_Msk   (0xffffffffUL)

APU PCM1_IN2_REG: PCM_IN (Bitfield-Mask: 0xffffffff)

Definition at line 2936 of file DA14680BA.h.

◆ APU_PCM1_IN2_REG_PCM_IN_Pos

#define APU_PCM1_IN2_REG_PCM_IN_Pos   (0UL)

APU PCM1_IN2_REG: PCM_IN (Bit 0)

Definition at line 2935 of file DA14680BA.h.

◆ APU_PCM1_OUT1_REG_PCM_OUT_Msk

#define APU_PCM1_OUT1_REG_PCM_OUT_Msk   (0xffffffffUL)

APU PCM1_OUT1_REG: PCM_OUT (Bitfield-Mask: 0xffffffff)

Definition at line 2940 of file DA14680BA.h.

◆ APU_PCM1_OUT1_REG_PCM_OUT_Pos

#define APU_PCM1_OUT1_REG_PCM_OUT_Pos   (0UL)

APU PCM1_OUT1_REG: PCM_OUT (Bit 0)

Definition at line 2939 of file DA14680BA.h.

◆ APU_PCM1_OUT2_REG_PCM_OUT_Msk

#define APU_PCM1_OUT2_REG_PCM_OUT_Msk   (0xffffffffUL)

APU PCM1_OUT2_REG: PCM_OUT (Bitfield-Mask: 0xffffffff)

Definition at line 2944 of file DA14680BA.h.

◆ APU_PCM1_OUT2_REG_PCM_OUT_Pos

#define APU_PCM1_OUT2_REG_PCM_OUT_Pos   (0UL)

APU PCM1_OUT2_REG: PCM_OUT (Bit 0)

Definition at line 2943 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Msk

#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Msk   (0x80UL)

APU SRC1_CTRL_REG: SRC_DITHER_DISABLE (Bitfield-Mask: 0x01)

Definition at line 2810 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Pos

#define APU_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Pos   (7UL)

APU SRC1_CTRL_REG: SRC_DITHER_DISABLE (Bit 7)

Definition at line 2809 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_EN_Msk

#define APU_SRC1_CTRL_REG_SRC_EN_Msk   (0x1UL)

APU SRC1_CTRL_REG: SRC_EN (Bitfield-Mask: 0x01)

Definition at line 2800 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_EN_Pos

#define APU_SRC1_CTRL_REG_SRC_EN_Pos   (0UL)

APU SRC1_CTRL_REG: SRC_EN (Bit 0)

Definition at line 2799 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_AMODE_Msk

#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Msk   (0x2UL)

APU SRC1_CTRL_REG: SRC_IN_AMODE (Bitfield-Mask: 0x01)

Definition at line 2802 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_AMODE_Pos

#define APU_SRC1_CTRL_REG_SRC_IN_AMODE_Pos   (1UL)

APU SRC1_CTRL_REG: SRC_IN_AMODE (Bit 1)

Definition at line 2801 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Msk

#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Msk   (0x4UL)

APU SRC1_CTRL_REG: SRC_IN_CAL_BYPASS (Bitfield-Mask: 0x01)

Definition at line 2804 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Pos

#define APU_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Pos   (2UL)

APU SRC1_CTRL_REG: SRC_IN_CAL_BYPASS (Bit 2)

Definition at line 2803 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_DS_Msk

#define APU_SRC1_CTRL_REG_SRC_IN_DS_Msk   (0x30UL)

APU SRC1_CTRL_REG: SRC_IN_DS (Bitfield-Mask: 0x03)

Definition at line 2806 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_DS_Pos

#define APU_SRC1_CTRL_REG_SRC_IN_DS_Pos   (4UL)

APU SRC1_CTRL_REG: SRC_IN_DS (Bit 4)

Definition at line 2805 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Msk

#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Msk   (0x1000000UL)

APU SRC1_CTRL_REG: SRC_IN_FLOWCLR (Bitfield-Mask: 0x01)

Definition at line 2830 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Pos

#define APU_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Pos   (24UL)

APU SRC1_CTRL_REG: SRC_IN_FLOWCLR (Bit 24)

Definition at line 2829 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_OK_Msk

#define APU_SRC1_CTRL_REG_SRC_IN_OK_Msk   (0x40UL)

APU SRC1_CTRL_REG: SRC_IN_OK (Bitfield-Mask: 0x01)

Definition at line 2808 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_OK_Pos

#define APU_SRC1_CTRL_REG_SRC_IN_OK_Pos   (6UL)

APU SRC1_CTRL_REG: SRC_IN_OK (Bit 6)

Definition at line 2807 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Msk

#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Msk   (0x100000UL)

APU SRC1_CTRL_REG: SRC_IN_OVFLOW (Bitfield-Mask: 0x01)

Definition at line 2822 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Pos

#define APU_SRC1_CTRL_REG_SRC_IN_OVFLOW_Pos   (20UL)

APU SRC1_CTRL_REG: SRC_IN_OVFLOW (Bit 20)

Definition at line 2821 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Msk

#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Msk   (0x200000UL)

APU SRC1_CTRL_REG: SRC_IN_UNFLOW (Bitfield-Mask: 0x01)

Definition at line 2824 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Pos

#define APU_SRC1_CTRL_REG_SRC_IN_UNFLOW_Pos   (21UL)

APU SRC1_CTRL_REG: SRC_IN_UNFLOW (Bit 21)

Definition at line 2823 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Msk

#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Msk   (0x2000UL)

APU SRC1_CTRL_REG: SRC_OUT_AMODE (Bitfield-Mask: 0x01)

Definition at line 2812 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Pos

#define APU_SRC1_CTRL_REG_SRC_OUT_AMODE_Pos   (13UL)

APU SRC1_CTRL_REG: SRC_OUT_AMODE (Bit 13)

Definition at line 2811 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk

#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk   (0x4000UL)

APU SRC1_CTRL_REG: SRC_OUT_CAL_BYPASS (Bitfield-Mask: 0x01)

Definition at line 2814 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos

#define APU_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos   (14UL)

APU SRC1_CTRL_REG: SRC_OUT_CAL_BYPASS (Bit 14)

Definition at line 2813 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Msk

#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Msk   (0x2000000UL)

APU SRC1_CTRL_REG: SRC_OUT_FLOWCLR (Bitfield-Mask: 0x01)

Definition at line 2832 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Pos

#define APU_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Pos   (25UL)

APU SRC1_CTRL_REG: SRC_OUT_FLOWCLR (Bit 25)

Definition at line 2831 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_OK_Msk

#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Msk   (0x40000UL)

APU SRC1_CTRL_REG: SRC_OUT_OK (Bitfield-Mask: 0x01)

Definition at line 2818 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_OK_Pos

#define APU_SRC1_CTRL_REG_SRC_OUT_OK_Pos   (18UL)

APU SRC1_CTRL_REG: SRC_OUT_OK (Bit 18)

Definition at line 2817 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Msk

#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Msk   (0x400000UL)

APU SRC1_CTRL_REG: SRC_OUT_OVFLOW (Bitfield-Mask: 0x01)

Definition at line 2826 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Pos

#define APU_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Pos   (22UL)

APU SRC1_CTRL_REG: SRC_OUT_OVFLOW (Bit 22)

Definition at line 2825 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Msk

#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Msk   (0x800000UL)

APU SRC1_CTRL_REG: SRC_OUT_UNFLOW (Bitfield-Mask: 0x01)

Definition at line 2828 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Pos

#define APU_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Pos   (23UL)

APU SRC1_CTRL_REG: SRC_OUT_UNFLOW (Bit 23)

Definition at line 2827 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_US_Msk

#define APU_SRC1_CTRL_REG_SRC_OUT_US_Msk   (0x30000UL)

APU SRC1_CTRL_REG: SRC_OUT_US (Bitfield-Mask: 0x03)

Definition at line 2816 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_OUT_US_Pos

#define APU_SRC1_CTRL_REG_SRC_OUT_US_Pos   (16UL)

APU SRC1_CTRL_REG: SRC_OUT_US (Bit 16)

Definition at line 2815 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Msk

#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Msk   (0xc000000UL)

APU SRC1_CTRL_REG: SRC_PDM_DI_DEL (Bitfield-Mask: 0x03)

Definition at line 2834 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Pos

#define APU_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Pos   (26UL)

APU SRC1_CTRL_REG: SRC_PDM_DI_DEL (Bit 26)

Definition at line 2833 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Msk

#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Msk   (0xc0000000UL)

APU SRC1_CTRL_REG: SRC_PDM_DO_DEL (Bitfield-Mask: 0x03)

Definition at line 2838 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Pos

#define APU_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Pos   (30UL)

APU SRC1_CTRL_REG: SRC_PDM_DO_DEL (Bit 30)

Definition at line 2837 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_PDM_MODE_Msk

#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Msk   (0x30000000UL)

APU SRC1_CTRL_REG: SRC_PDM_MODE (Bitfield-Mask: 0x03)

Definition at line 2836 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_PDM_MODE_Pos

#define APU_SRC1_CTRL_REG_SRC_PDM_MODE_Pos   (28UL)

APU SRC1_CTRL_REG: SRC_PDM_MODE (Bit 28)

Definition at line 2835 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_RESYNC_Msk

#define APU_SRC1_CTRL_REG_SRC_RESYNC_Msk   (0x80000UL)

APU SRC1_CTRL_REG: SRC_RESYNC (Bitfield-Mask: 0x01)

Definition at line 2820 of file DA14680BA.h.

◆ APU_SRC1_CTRL_REG_SRC_RESYNC_Pos

#define APU_SRC1_CTRL_REG_SRC_RESYNC_Pos   (19UL)

APU SRC1_CTRL_REG: SRC_RESYNC (Bit 19)

Definition at line 2819 of file DA14680BA.h.

◆ APU_SRC1_IN1_REG_SRC_IN_Msk

#define APU_SRC1_IN1_REG_SRC_IN_Msk   (0xffffff00UL)

APU SRC1_IN1_REG: SRC_IN (Bitfield-Mask: 0xffffff)

Definition at line 2850 of file DA14680BA.h.

◆ APU_SRC1_IN1_REG_SRC_IN_Pos

#define APU_SRC1_IN1_REG_SRC_IN_Pos   (8UL)

APU SRC1_IN1_REG: SRC_IN (Bit 8)

Definition at line 2849 of file DA14680BA.h.

◆ APU_SRC1_IN2_REG_SRC_IN_Msk

#define APU_SRC1_IN2_REG_SRC_IN_Msk   (0xffffff00UL)

APU SRC1_IN2_REG: SRC_IN (Bitfield-Mask: 0xffffff)

Definition at line 2854 of file DA14680BA.h.

◆ APU_SRC1_IN2_REG_SRC_IN_Pos

#define APU_SRC1_IN2_REG_SRC_IN_Pos   (8UL)

APU SRC1_IN2_REG: SRC_IN (Bit 8)

Definition at line 2853 of file DA14680BA.h.

◆ APU_SRC1_IN_FS_REG_SRC_IN_FS_Msk

#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Msk   (0xffffffUL)

APU SRC1_IN_FS_REG: SRC_IN_FS (Bitfield-Mask: 0xffffff)

Definition at line 2842 of file DA14680BA.h.

◆ APU_SRC1_IN_FS_REG_SRC_IN_FS_Pos

#define APU_SRC1_IN_FS_REG_SRC_IN_FS_Pos   (0UL)

APU SRC1_IN_FS_REG: SRC_IN_FS (Bit 0)

Definition at line 2841 of file DA14680BA.h.

◆ APU_SRC1_OUT1_REG_SRC_OUT_Msk

#define APU_SRC1_OUT1_REG_SRC_OUT_Msk   (0xffffff00UL)

APU SRC1_OUT1_REG: SRC_OUT (Bitfield-Mask: 0xffffff)

Definition at line 2858 of file DA14680BA.h.

◆ APU_SRC1_OUT1_REG_SRC_OUT_Pos

#define APU_SRC1_OUT1_REG_SRC_OUT_Pos   (8UL)

APU SRC1_OUT1_REG: SRC_OUT (Bit 8)

Definition at line 2857 of file DA14680BA.h.

◆ APU_SRC1_OUT2_REG_SRC_OUT_Msk

#define APU_SRC1_OUT2_REG_SRC_OUT_Msk   (0xffffff00UL)

APU SRC1_OUT2_REG: SRC_OUT (Bitfield-Mask: 0xffffff)

Definition at line 2862 of file DA14680BA.h.

◆ APU_SRC1_OUT2_REG_SRC_OUT_Pos

#define APU_SRC1_OUT2_REG_SRC_OUT_Pos   (8UL)

APU SRC1_OUT2_REG: SRC_OUT (Bit 8)

Definition at line 2861 of file DA14680BA.h.

◆ APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Msk

#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Msk   (0xffffffUL)

APU SRC1_OUT_FS_REG: SRC_OUT_FS (Bitfield-Mask: 0xffffff)

Definition at line 2846 of file DA14680BA.h.

◆ APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Pos

#define APU_SRC1_OUT_FS_REG_SRC_OUT_FS_Pos   (0UL)

APU SRC1_OUT_FS_REG: SRC_OUT_FS (Bit 0)

Definition at line 2845 of file DA14680BA.h.

◆ BLE

#define BLE   ((BLE_Type *) BLE_BASE)

Definition at line 12076 of file DA14680BA.h.

◆ BLE_BASE

#define BLE_BASE   0x40000000UL

Definition at line 12031 of file DA14680BA.h.

◆ BLE_BLE_ACTSCANSTAT_REG_BACKOFF_Msk

#define BLE_BLE_ACTSCANSTAT_REG_BACKOFF_Msk   (0x1ff0000UL)

BLE BLE_ACTSCANSTAT_REG: BACKOFF (Bitfield-Mask: 0x1ff)

Definition at line 3288 of file DA14680BA.h.

◆ BLE_BLE_ACTSCANSTAT_REG_BACKOFF_Pos

#define BLE_BLE_ACTSCANSTAT_REG_BACKOFF_Pos   (16UL)

BLE BLE_ACTSCANSTAT_REG: BACKOFF (Bit 16)

Definition at line 3287 of file DA14680BA.h.

◆ BLE_BLE_ACTSCANSTAT_REG_UPPERLIMIT_Msk

#define BLE_BLE_ACTSCANSTAT_REG_UPPERLIMIT_Msk   (0x1ffUL)

BLE BLE_ACTSCANSTAT_REG: UPPERLIMIT (Bitfield-Mask: 0x1ff)

Definition at line 3286 of file DA14680BA.h.

◆ BLE_BLE_ACTSCANSTAT_REG_UPPERLIMIT_Pos

#define BLE_BLE_ACTSCANSTAT_REG_UPPERLIMIT_Pos   (0UL)

BLE BLE_ACTSCANSTAT_REG: UPPERLIMIT (Bit 0)

Definition at line 3285 of file DA14680BA.h.

◆ BLE_BLE_ADVCHMAP_REG_ADVCHMAP_Msk

#define BLE_BLE_ADVCHMAP_REG_ADVCHMAP_Msk   (0x7UL)

BLE BLE_ADVCHMAP_REG: ADVCHMAP (Bitfield-Mask: 0x07)

Definition at line 3278 of file DA14680BA.h.

◆ BLE_BLE_ADVCHMAP_REG_ADVCHMAP_Pos

#define BLE_BLE_ADVCHMAP_REG_ADVCHMAP_Pos   (0UL)

BLE BLE_ADVCHMAP_REG: ADVCHMAP (Bit 0)

Definition at line 3277 of file DA14680BA.h.

◆ BLE_BLE_ADVTIM_REG_ADVINT_Msk

#define BLE_BLE_ADVTIM_REG_ADVINT_Msk   (0x3fffUL)

BLE BLE_ADVTIM_REG: ADVINT (Bitfield-Mask: 0x3fff)

Definition at line 3282 of file DA14680BA.h.

◆ BLE_BLE_ADVTIM_REG_ADVINT_Pos

#define BLE_BLE_ADVTIM_REG_ADVINT_Pos   (0UL)

BLE BLE_ADVTIM_REG: ADVINT (Bit 0)

Definition at line 3281 of file DA14680BA.h.

◆ BLE_BLE_AESCNTL_REG_AES_MODE_Msk

#define BLE_BLE_AESCNTL_REG_AES_MODE_Msk   (0x2UL)

BLE BLE_AESCNTL_REG: AES_MODE (Bitfield-Mask: 0x01)

Definition at line 3308 of file DA14680BA.h.

◆ BLE_BLE_AESCNTL_REG_AES_MODE_Pos

#define BLE_BLE_AESCNTL_REG_AES_MODE_Pos   (1UL)

BLE BLE_AESCNTL_REG: AES_MODE (Bit 1)

Definition at line 3307 of file DA14680BA.h.

◆ BLE_BLE_AESCNTL_REG_AES_START_Msk

#define BLE_BLE_AESCNTL_REG_AES_START_Msk   (0x1UL)

BLE BLE_AESCNTL_REG: AES_START (Bitfield-Mask: 0x01)

Definition at line 3306 of file DA14680BA.h.

◆ BLE_BLE_AESCNTL_REG_AES_START_Pos

#define BLE_BLE_AESCNTL_REG_AES_START_Pos   (0UL)

BLE BLE_AESCNTL_REG: AES_START (Bit 0)

Definition at line 3305 of file DA14680BA.h.

◆ BLE_BLE_AESKEY127_96_REG_AESKEY127_96_Msk

#define BLE_BLE_AESKEY127_96_REG_AESKEY127_96_Msk   (0xffffffffUL)

BLE BLE_AESKEY127_96_REG: AESKEY127_96 (Bitfield-Mask: 0xffffffff)

Definition at line 3324 of file DA14680BA.h.

◆ BLE_BLE_AESKEY127_96_REG_AESKEY127_96_Pos

#define BLE_BLE_AESKEY127_96_REG_AESKEY127_96_Pos   (0UL)

BLE BLE_AESKEY127_96_REG: AESKEY127_96 (Bit 0)

Definition at line 3323 of file DA14680BA.h.

◆ BLE_BLE_AESKEY31_0_REG_AESKEY31_0_Msk

#define BLE_BLE_AESKEY31_0_REG_AESKEY31_0_Msk   (0xffffffffUL)

BLE BLE_AESKEY31_0_REG: AESKEY31_0 (Bitfield-Mask: 0xffffffff)

Definition at line 3312 of file DA14680BA.h.

◆ BLE_BLE_AESKEY31_0_REG_AESKEY31_0_Pos

#define BLE_BLE_AESKEY31_0_REG_AESKEY31_0_Pos   (0UL)

BLE BLE_AESKEY31_0_REG: AESKEY31_0 (Bit 0)

Definition at line 3311 of file DA14680BA.h.

◆ BLE_BLE_AESKEY63_32_REG_AESKEY63_32_Msk

#define BLE_BLE_AESKEY63_32_REG_AESKEY63_32_Msk   (0xffffffffUL)

BLE BLE_AESKEY63_32_REG: AESKEY63_32 (Bitfield-Mask: 0xffffffff)

Definition at line 3316 of file DA14680BA.h.

◆ BLE_BLE_AESKEY63_32_REG_AESKEY63_32_Pos

#define BLE_BLE_AESKEY63_32_REG_AESKEY63_32_Pos   (0UL)

BLE BLE_AESKEY63_32_REG: AESKEY63_32 (Bit 0)

Definition at line 3315 of file DA14680BA.h.

◆ BLE_BLE_AESKEY95_64_REG_AESKEY95_64_Msk

#define BLE_BLE_AESKEY95_64_REG_AESKEY95_64_Msk   (0xffffffffUL)

BLE BLE_AESKEY95_64_REG: AESKEY95_64 (Bitfield-Mask: 0xffffffff)

Definition at line 3320 of file DA14680BA.h.

◆ BLE_BLE_AESKEY95_64_REG_AESKEY95_64_Pos

#define BLE_BLE_AESKEY95_64_REG_AESKEY95_64_Pos   (0UL)

BLE BLE_AESKEY95_64_REG: AESKEY95_64 (Bit 0)

Definition at line 3319 of file DA14680BA.h.

◆ BLE_BLE_AESPTR_REG_AESPTR_Msk

#define BLE_BLE_AESPTR_REG_AESPTR_Msk   (0xffffUL)

BLE BLE_AESPTR_REG: AESPTR (Bitfield-Mask: 0xffff)

Definition at line 3328 of file DA14680BA.h.

◆ BLE_BLE_AESPTR_REG_AESPTR_Pos

#define BLE_BLE_AESPTR_REG_AESPTR_Pos   (0UL)

BLE BLE_AESPTR_REG: AESPTR (Bit 0)

Definition at line 3327 of file DA14680BA.h.

◆ BLE_BLE_BASETIMECNT_REG_BASETIMECNT_Msk

#define BLE_BLE_BASETIMECNT_REG_BASETIMECNT_Msk   (0x7ffffffUL)

BLE BLE_BASETIMECNT_REG: BASETIMECNT (Bitfield-Mask: 0x7ffffff)

Definition at line 3116 of file DA14680BA.h.

◆ BLE_BLE_BASETIMECNT_REG_BASETIMECNT_Pos

#define BLE_BLE_BASETIMECNT_REG_BASETIMECNT_Pos   (0UL)

BLE BLE_BASETIMECNT_REG: BASETIMECNT (Bit 0)

Definition at line 3115 of file DA14680BA.h.

◆ BLE_BLE_BASETIMECNTCORR_REG_BASETIMECNTCORR_Msk

#define BLE_BLE_BASETIMECNTCORR_REG_BASETIMECNTCORR_Msk   (0x7ffffffUL)

BLE BLE_BASETIMECNTCORR_REG: BASETIMECNTCORR (Bitfield-Mask: 0x7ffffff)

Definition at line 3174 of file DA14680BA.h.

◆ BLE_BLE_BASETIMECNTCORR_REG_BASETIMECNTCORR_Pos

#define BLE_BLE_BASETIMECNTCORR_REG_BASETIMECNTCORR_Pos   (0UL)

BLE BLE_BASETIMECNTCORR_REG: BASETIMECNTCORR (Bit 0)

Definition at line 3173 of file DA14680BA.h.

◆ BLE_BLE_BDADDRL_REG_BDADDRL_Msk

#define BLE_BLE_BDADDRL_REG_BDADDRL_Msk   (0xffffffffUL)

BLE BLE_BDADDRL_REG: BDADDRL (Bitfield-Mask: 0xffffffff)

Definition at line 3124 of file DA14680BA.h.

◆ BLE_BLE_BDADDRL_REG_BDADDRL_Pos

#define BLE_BLE_BDADDRL_REG_BDADDRL_Pos   (0UL)

BLE BLE_BDADDRL_REG: BDADDRL (Bit 0)

Definition at line 3123 of file DA14680BA.h.

◆ BLE_BLE_BDADDRU_REG_BDADDRU_Msk

#define BLE_BLE_BDADDRU_REG_BDADDRU_Msk   (0xffffUL)

BLE BLE_BDADDRU_REG: BDADDRU (Bitfield-Mask: 0xffff)

Definition at line 3128 of file DA14680BA.h.

◆ BLE_BLE_BDADDRU_REG_BDADDRU_Pos

#define BLE_BLE_BDADDRU_REG_BDADDRU_Pos   (0UL)

BLE BLE_BDADDRU_REG: BDADDRU (Bit 0)

Definition at line 3127 of file DA14680BA.h.

◆ BLE_BLE_BDADDRU_REG_PRIV_NPUB_Msk

#define BLE_BLE_BDADDRU_REG_PRIV_NPUB_Msk   (0x10000UL)

BLE BLE_BDADDRU_REG: PRIV_NPUB (Bitfield-Mask: 0x01)

Definition at line 3130 of file DA14680BA.h.

◆ BLE_BLE_BDADDRU_REG_PRIV_NPUB_Pos

#define BLE_BLE_BDADDRU_REG_PRIV_NPUB_Pos   (16UL)

BLE BLE_BDADDRU_REG: PRIV_NPUB (Bit 16)

Definition at line 3129 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM0_Msk

#define BLE_BLE_BLEMPRIO0_REG_BLEM0_Msk   (0xfUL)

BLE BLE_BLEMPRIO0_REG: BLEM0 (Bitfield-Mask: 0x0f)

Definition at line 3410 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM0_Pos

#define BLE_BLE_BLEMPRIO0_REG_BLEM0_Pos   (0UL)

BLE BLE_BLEMPRIO0_REG: BLEM0 (Bit 0)

Definition at line 3409 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM1_Msk

#define BLE_BLE_BLEMPRIO0_REG_BLEM1_Msk   (0xf0UL)

BLE BLE_BLEMPRIO0_REG: BLEM1 (Bitfield-Mask: 0x0f)

Definition at line 3412 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM1_Pos

#define BLE_BLE_BLEMPRIO0_REG_BLEM1_Pos   (4UL)

BLE BLE_BLEMPRIO0_REG: BLEM1 (Bit 4)

Definition at line 3411 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM2_Msk

#define BLE_BLE_BLEMPRIO0_REG_BLEM2_Msk   (0xf00UL)

BLE BLE_BLEMPRIO0_REG: BLEM2 (Bitfield-Mask: 0x0f)

Definition at line 3414 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM2_Pos

#define BLE_BLE_BLEMPRIO0_REG_BLEM2_Pos   (8UL)

BLE BLE_BLEMPRIO0_REG: BLEM2 (Bit 8)

Definition at line 3413 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM3_Msk

#define BLE_BLE_BLEMPRIO0_REG_BLEM3_Msk   (0xf000UL)

BLE BLE_BLEMPRIO0_REG: BLEM3 (Bitfield-Mask: 0x0f)

Definition at line 3416 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM3_Pos

#define BLE_BLE_BLEMPRIO0_REG_BLEM3_Pos   (12UL)

BLE BLE_BLEMPRIO0_REG: BLEM3 (Bit 12)

Definition at line 3415 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM4_Msk

#define BLE_BLE_BLEMPRIO0_REG_BLEM4_Msk   (0xf0000UL)

BLE BLE_BLEMPRIO0_REG: BLEM4 (Bitfield-Mask: 0x0f)

Definition at line 3418 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM4_Pos

#define BLE_BLE_BLEMPRIO0_REG_BLEM4_Pos   (16UL)

BLE BLE_BLEMPRIO0_REG: BLEM4 (Bit 16)

Definition at line 3417 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM5_Msk

#define BLE_BLE_BLEMPRIO0_REG_BLEM5_Msk   (0xf00000UL)

BLE BLE_BLEMPRIO0_REG: BLEM5 (Bitfield-Mask: 0x0f)

Definition at line 3420 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM5_Pos

#define BLE_BLE_BLEMPRIO0_REG_BLEM5_Pos   (20UL)

BLE BLE_BLEMPRIO0_REG: BLEM5 (Bit 20)

Definition at line 3419 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM6_Msk

#define BLE_BLE_BLEMPRIO0_REG_BLEM6_Msk   (0xf000000UL)

BLE BLE_BLEMPRIO0_REG: BLEM6 (Bitfield-Mask: 0x0f)

Definition at line 3422 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM6_Pos

#define BLE_BLE_BLEMPRIO0_REG_BLEM6_Pos   (24UL)

BLE BLE_BLEMPRIO0_REG: BLEM6 (Bit 24)

Definition at line 3421 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM7_Msk

#define BLE_BLE_BLEMPRIO0_REG_BLEM7_Msk   (0xf0000000UL)

BLE BLE_BLEMPRIO0_REG: BLEM7 (Bitfield-Mask: 0x0f)

Definition at line 3424 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO0_REG_BLEM7_Pos

#define BLE_BLE_BLEMPRIO0_REG_BLEM7_Pos   (28UL)

BLE BLE_BLEMPRIO0_REG: BLEM7 (Bit 28)

Definition at line 3423 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO1_REG_BLEMDEFAULT_Msk

#define BLE_BLE_BLEMPRIO1_REG_BLEMDEFAULT_Msk   (0xf0000000UL)

BLE BLE_BLEMPRIO1_REG: BLEMDEFAULT (Bitfield-Mask: 0x0f)

Definition at line 3428 of file DA14680BA.h.

◆ BLE_BLE_BLEMPRIO1_REG_BLEMDEFAULT_Pos

#define BLE_BLE_BLEMPRIO1_REG_BLEMDEFAULT_Pos   (28UL)

BLE BLE_BLEMPRIO1_REG: BLEMDEFAULT (Bit 28)

Definition at line 3427 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BB_ONLY_Msk

#define BLE_BLE_CNTL2_REG_BB_ONLY_Msk   (0x40000UL)

BLE BLE_CNTL2_REG: BB_ONLY (Bitfield-Mask: 0x01)

Definition at line 3456 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BB_ONLY_Pos

#define BLE_BLE_CNTL2_REG_BB_ONLY_Pos   (18UL)

BLE BLE_CNTL2_REG: BB_ONLY (Bit 18)

Definition at line 3455 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_CLK_SEL_Msk

#define BLE_BLE_CNTL2_REG_BLE_CLK_SEL_Msk   (0x7e00UL)

BLE BLE_CNTL2_REG: BLE_CLK_SEL (Bitfield-Mask: 0x3f)

Definition at line 3448 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_CLK_SEL_Pos

#define BLE_BLE_CNTL2_REG_BLE_CLK_SEL_Pos   (9UL)

BLE BLE_CNTL2_REG: BLE_CLK_SEL (Bit 9)

Definition at line 3447 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_CLK_STAT_Msk

#define BLE_BLE_CNTL2_REG_BLE_CLK_STAT_Msk   (0x40UL)

BLE BLE_CNTL2_REG: BLE_CLK_STAT (Bitfield-Mask: 0x01)

Definition at line 3442 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_CLK_STAT_Pos

#define BLE_BLE_CNTL2_REG_BLE_CLK_STAT_Pos   (6UL)

BLE BLE_CNTL2_REG: BLE_CLK_STAT (Bit 6)

Definition at line 3441 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_Msk

#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_Msk   (0x8UL)

BLE BLE_CNTL2_REG: BLE_DIAG_OVR (Bitfield-Mask: 0x01)

Definition at line 3438 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_Pos

#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_Pos   (3UL)

BLE BLE_CNTL2_REG: BLE_DIAG_OVR (Bit 3)

Definition at line 3437 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_SEL_Msk

#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_SEL_Msk   (0x30UL)

BLE BLE_CNTL2_REG: BLE_DIAG_OVR_SEL (Bitfield-Mask: 0x03)

Definition at line 3440 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_SEL_Pos

#define BLE_BLE_CNTL2_REG_BLE_DIAG_OVR_SEL_Pos   (4UL)

BLE BLE_CNTL2_REG: BLE_DIAG_OVR_SEL (Bit 4)

Definition at line 3439 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_PTI_SOURCE_SEL_Msk

#define BLE_BLE_CNTL2_REG_BLE_PTI_SOURCE_SEL_Msk   (0x20000UL)

BLE BLE_CNTL2_REG: BLE_PTI_SOURCE_SEL (Bitfield-Mask: 0x01)

Definition at line 3454 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_PTI_SOURCE_SEL_Pos

#define BLE_BLE_CNTL2_REG_BLE_PTI_SOURCE_SEL_Pos   (17UL)

BLE BLE_CNTL2_REG: BLE_PTI_SOURCE_SEL (Bit 17)

Definition at line 3453 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_RSSI_SEL_Msk

#define BLE_BLE_CNTL2_REG_BLE_RSSI_SEL_Msk   (0x200000UL)

BLE BLE_CNTL2_REG: BLE_RSSI_SEL (Bitfield-Mask: 0x01)

Definition at line 3462 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_RSSI_SEL_Pos

#define BLE_BLE_CNTL2_REG_BLE_RSSI_SEL_Pos   (21UL)

BLE BLE_CNTL2_REG: BLE_RSSI_SEL (Bit 21)

Definition at line 3461 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_TRANSACTION_MODE_Msk

#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_MODE_Msk   (0x10000UL)

BLE BLE_CNTL2_REG: BLE_TRANSACTION_MODE (Bitfield-Mask: 0x01)

Definition at line 3452 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_TRANSACTION_MODE_Pos

#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_MODE_Pos   (16UL)

BLE BLE_CNTL2_REG: BLE_TRANSACTION_MODE (Bit 16)

Definition at line 3451 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_TRANSACTION_SRC_Msk

#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_SRC_Msk   (0x8000UL)

BLE BLE_CNTL2_REG: BLE_TRANSACTION_SRC (Bitfield-Mask: 0x01)

Definition at line 3450 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_TRANSACTION_SRC_Pos

#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_SRC_Pos   (15UL)

BLE BLE_CNTL2_REG: BLE_TRANSACTION_SRC (Bit 15)

Definition at line 3449 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_TRANSACTION_START_Msk

#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_START_Msk   (0xffc00000UL)

BLE BLE_CNTL2_REG: BLE_TRANSACTION_START (Bitfield-Mask: 0x3ff)

Definition at line 3464 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_BLE_TRANSACTION_START_Pos

#define BLE_BLE_CNTL2_REG_BLE_TRANSACTION_START_Pos   (22UL)

BLE BLE_CNTL2_REG: BLE_TRANSACTION_START (Bit 22)

Definition at line 3463 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_EMACCERRACK_Msk

#define BLE_BLE_CNTL2_REG_EMACCERRACK_Msk   (0x2UL)

BLE BLE_CNTL2_REG: EMACCERRACK (Bitfield-Mask: 0x01)

Definition at line 3434 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_EMACCERRACK_Pos

#define BLE_BLE_CNTL2_REG_EMACCERRACK_Pos   (1UL)

BLE BLE_CNTL2_REG: EMACCERRACK (Bit 1)

Definition at line 3433 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_EMACCERRMSK_Msk

#define BLE_BLE_CNTL2_REG_EMACCERRMSK_Msk   (0x4UL)

BLE BLE_CNTL2_REG: EMACCERRMSK (Bitfield-Mask: 0x01)

Definition at line 3436 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_EMACCERRMSK_Pos

#define BLE_BLE_CNTL2_REG_EMACCERRMSK_Pos   (2UL)

BLE BLE_CNTL2_REG: EMACCERRMSK (Bit 2)

Definition at line 3435 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_EMACCERRSTAT_Msk

#define BLE_BLE_CNTL2_REG_EMACCERRSTAT_Msk   (0x1UL)

BLE BLE_CNTL2_REG: EMACCERRSTAT (Bitfield-Mask: 0x01)

Definition at line 3432 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_EMACCERRSTAT_Pos

#define BLE_BLE_CNTL2_REG_EMACCERRSTAT_Pos   (0UL)

BLE BLE_CNTL2_REG: EMACCERRSTAT (Bit 0)

Definition at line 3431 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_MON_LP_CLK_Msk

#define BLE_BLE_CNTL2_REG_MON_LP_CLK_Msk   (0x80UL)

BLE BLE_CNTL2_REG: MON_LP_CLK (Bitfield-Mask: 0x01)

Definition at line 3444 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_MON_LP_CLK_Pos

#define BLE_BLE_CNTL2_REG_MON_LP_CLK_Pos   (7UL)

BLE BLE_CNTL2_REG: MON_LP_CLK (Bit 7)

Definition at line 3443 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_RADIO_PWRDN_ALLOW_Msk

#define BLE_BLE_CNTL2_REG_RADIO_PWRDN_ALLOW_Msk   (0x100UL)

BLE BLE_CNTL2_REG: RADIO_PWRDN_ALLOW (Bitfield-Mask: 0x01)

Definition at line 3446 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_RADIO_PWRDN_ALLOW_Pos

#define BLE_BLE_CNTL2_REG_RADIO_PWRDN_ALLOW_Pos   (8UL)

BLE BLE_CNTL2_REG: RADIO_PWRDN_ALLOW (Bit 8)

Definition at line 3445 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_SW_RPL_SPI_Msk

#define BLE_BLE_CNTL2_REG_SW_RPL_SPI_Msk   (0x80000UL)

BLE BLE_CNTL2_REG: SW_RPL_SPI (Bitfield-Mask: 0x01)

Definition at line 3458 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_SW_RPL_SPI_Pos

#define BLE_BLE_CNTL2_REG_SW_RPL_SPI_Pos   (19UL)

BLE BLE_CNTL2_REG: SW_RPL_SPI (Bit 19)

Definition at line 3457 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_WAKEUPLPSTAT_Msk

#define BLE_BLE_CNTL2_REG_WAKEUPLPSTAT_Msk   (0x100000UL)

BLE BLE_CNTL2_REG: WAKEUPLPSTAT (Bitfield-Mask: 0x01)

Definition at line 3460 of file DA14680BA.h.

◆ BLE_BLE_CNTL2_REG_WAKEUPLPSTAT_Pos

#define BLE_BLE_CNTL2_REG_WAKEUPLPSTAT_Pos   (20UL)

BLE BLE_CNTL2_REG: WAKEUPLPSTAT (Bit 20)

Definition at line 3459 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL0_REG_COEX_EN_Msk

#define BLE_BLE_COEXIFCNTL0_REG_COEX_EN_Msk   (0x1UL)

BLE BLE_COEXIFCNTL0_REG: COEX_EN (Bitfield-Mask: 0x01)

Definition at line 3386 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL0_REG_COEX_EN_Pos

#define BLE_BLE_COEXIFCNTL0_REG_COEX_EN_Pos   (0UL)

BLE BLE_COEXIFCNTL0_REG: COEX_EN (Bit 0)

Definition at line 3385 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL0_REG_SYNCGEN_EN_Msk

#define BLE_BLE_COEXIFCNTL0_REG_SYNCGEN_EN_Msk   (0x2UL)

BLE BLE_COEXIFCNTL0_REG: SYNCGEN_EN (Bitfield-Mask: 0x01)

Definition at line 3388 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL0_REG_SYNCGEN_EN_Pos

#define BLE_BLE_COEXIFCNTL0_REG_SYNCGEN_EN_Pos   (1UL)

BLE BLE_COEXIFCNTL0_REG: SYNCGEN_EN (Bit 1)

Definition at line 3387 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL0_REG_WLANRXMSK_Msk

#define BLE_BLE_COEXIFCNTL0_REG_WLANRXMSK_Msk   (0x30UL)

BLE BLE_COEXIFCNTL0_REG: WLANRXMSK (Bitfield-Mask: 0x03)

Definition at line 3390 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL0_REG_WLANRXMSK_Pos

#define BLE_BLE_COEXIFCNTL0_REG_WLANRXMSK_Pos   (4UL)

BLE BLE_COEXIFCNTL0_REG: WLANRXMSK (Bit 4)

Definition at line 3389 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL0_REG_WLANTXMSK_Msk

#define BLE_BLE_COEXIFCNTL0_REG_WLANTXMSK_Msk   (0xc0UL)

BLE BLE_COEXIFCNTL0_REG: WLANTXMSK (Bitfield-Mask: 0x03)

Definition at line 3392 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL0_REG_WLANTXMSK_Pos

#define BLE_BLE_COEXIFCNTL0_REG_WLANTXMSK_Pos   (6UL)

BLE BLE_COEXIFCNTL0_REG: WLANTXMSK (Bit 6)

Definition at line 3391 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL0_REG_WLCRXPRIOMODE_Msk

#define BLE_BLE_COEXIFCNTL0_REG_WLCRXPRIOMODE_Msk   (0x300000UL)

BLE BLE_COEXIFCNTL0_REG: WLCRXPRIOMODE (Bitfield-Mask: 0x03)

Definition at line 3396 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL0_REG_WLCRXPRIOMODE_Pos

#define BLE_BLE_COEXIFCNTL0_REG_WLCRXPRIOMODE_Pos   (20UL)

BLE BLE_COEXIFCNTL0_REG: WLCRXPRIOMODE (Bit 20)

Definition at line 3395 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL0_REG_WLCTXPRIOMODE_Msk

#define BLE_BLE_COEXIFCNTL0_REG_WLCTXPRIOMODE_Msk   (0x30000UL)

BLE BLE_COEXIFCNTL0_REG: WLCTXPRIOMODE (Bitfield-Mask: 0x03)

Definition at line 3394 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL0_REG_WLCTXPRIOMODE_Pos

#define BLE_BLE_COEXIFCNTL0_REG_WLCTXPRIOMODE_Pos   (16UL)

BLE BLE_COEXIFCNTL0_REG: WLCTXPRIOMODE (Bit 16)

Definition at line 3393 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL1_REG_WLCPDELAY_Msk

#define BLE_BLE_COEXIFCNTL1_REG_WLCPDELAY_Msk   (0x7fUL)

BLE BLE_COEXIFCNTL1_REG: WLCPDELAY (Bitfield-Mask: 0x7f)

Definition at line 3400 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL1_REG_WLCPDELAY_Pos

#define BLE_BLE_COEXIFCNTL1_REG_WLCPDELAY_Pos   (0UL)

BLE BLE_COEXIFCNTL1_REG: WLCPDELAY (Bit 0)

Definition at line 3399 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL1_REG_WLCPDURATION_Msk

#define BLE_BLE_COEXIFCNTL1_REG_WLCPDURATION_Msk   (0x7f00UL)

BLE BLE_COEXIFCNTL1_REG: WLCPDURATION (Bitfield-Mask: 0x7f)

Definition at line 3402 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL1_REG_WLCPDURATION_Pos

#define BLE_BLE_COEXIFCNTL1_REG_WLCPDURATION_Pos   (8UL)

BLE BLE_COEXIFCNTL1_REG: WLCPDURATION (Bit 8)

Definition at line 3401 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL1_REG_WLCPRXTHR_Msk

#define BLE_BLE_COEXIFCNTL1_REG_WLCPRXTHR_Msk   (0x1f000000UL)

BLE BLE_COEXIFCNTL1_REG: WLCPRXTHR (Bitfield-Mask: 0x1f)

Definition at line 3406 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL1_REG_WLCPRXTHR_Pos

#define BLE_BLE_COEXIFCNTL1_REG_WLCPRXTHR_Pos   (24UL)

BLE BLE_COEXIFCNTL1_REG: WLCPRXTHR (Bit 24)

Definition at line 3405 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL1_REG_WLCPTXTHR_Msk

#define BLE_BLE_COEXIFCNTL1_REG_WLCPTXTHR_Msk   (0x1f0000UL)

BLE BLE_COEXIFCNTL1_REG: WLCPTXTHR (Bitfield-Mask: 0x1f)

Definition at line 3404 of file DA14680BA.h.

◆ BLE_BLE_COEXIFCNTL1_REG_WLCPTXTHR_Pos

#define BLE_BLE_COEXIFCNTL1_REG_WLCPTXTHR_Pos   (16UL)

BLE BLE_COEXIFCNTL1_REG: WLCPTXTHR (Bit 16)

Definition at line 3403 of file DA14680BA.h.

◆ BLE_BLE_CURRENTRXDESCPTR_REG_CURRENTRXDESCPTR_Msk

#define BLE_BLE_CURRENTRXDESCPTR_REG_CURRENTRXDESCPTR_Msk   (0x7fffUL)

BLE BLE_CURRENTRXDESCPTR_REG: CURRENTRXDESCPTR (Bitfield-Mask: 0x7fff)

Definition at line 3134 of file DA14680BA.h.

◆ BLE_BLE_CURRENTRXDESCPTR_REG_CURRENTRXDESCPTR_Pos

#define BLE_BLE_CURRENTRXDESCPTR_REG_CURRENTRXDESCPTR_Pos   (0UL)

BLE BLE_CURRENTRXDESCPTR_REG: CURRENTRXDESCPTR (Bit 0)

Definition at line 3133 of file DA14680BA.h.

◆ BLE_BLE_CURRENTRXDESCPTR_REG_ETPTR_Msk

#define BLE_BLE_CURRENTRXDESCPTR_REG_ETPTR_Msk   (0xffff0000UL)

BLE BLE_CURRENTRXDESCPTR_REG: ETPTR (Bitfield-Mask: 0xffff)

Definition at line 3136 of file DA14680BA.h.

◆ BLE_BLE_CURRENTRXDESCPTR_REG_ETPTR_Pos

#define BLE_BLE_CURRENTRXDESCPTR_REG_ETPTR_Pos   (16UL)

BLE BLE_CURRENTRXDESCPTR_REG: ETPTR (Bit 16)

Definition at line 3135 of file DA14680BA.h.

◆ BLE_BLE_DEBUGADDMAX_REG_EM_ADDMAX_Msk

#define BLE_BLE_DEBUGADDMAX_REG_EM_ADDMAX_Msk   (0xffffUL)

BLE BLE_DEBUGADDMAX_REG: EM_ADDMAX (Bitfield-Mask: 0xffff)

Definition at line 3206 of file DA14680BA.h.

◆ BLE_BLE_DEBUGADDMAX_REG_EM_ADDMAX_Pos

#define BLE_BLE_DEBUGADDMAX_REG_EM_ADDMAX_Pos   (0UL)

BLE BLE_DEBUGADDMAX_REG: EM_ADDMAX (Bit 0)

Definition at line 3205 of file DA14680BA.h.

◆ BLE_BLE_DEBUGADDMAX_REG_REG_ADDMAX_Msk

#define BLE_BLE_DEBUGADDMAX_REG_REG_ADDMAX_Msk   (0xffff0000UL)

BLE BLE_DEBUGADDMAX_REG: REG_ADDMAX (Bitfield-Mask: 0xffff)

Definition at line 3208 of file DA14680BA.h.

◆ BLE_BLE_DEBUGADDMAX_REG_REG_ADDMAX_Pos

#define BLE_BLE_DEBUGADDMAX_REG_REG_ADDMAX_Pos   (16UL)

BLE BLE_DEBUGADDMAX_REG: REG_ADDMAX (Bit 16)

Definition at line 3207 of file DA14680BA.h.

◆ BLE_BLE_DEBUGADDMIN_REG_EM_ADDMIN_Msk

#define BLE_BLE_DEBUGADDMIN_REG_EM_ADDMIN_Msk   (0xffffUL)

BLE BLE_DEBUGADDMIN_REG: EM_ADDMIN (Bitfield-Mask: 0xffff)

Definition at line 3212 of file DA14680BA.h.

◆ BLE_BLE_DEBUGADDMIN_REG_EM_ADDMIN_Pos

#define BLE_BLE_DEBUGADDMIN_REG_EM_ADDMIN_Pos   (0UL)

BLE BLE_DEBUGADDMIN_REG: EM_ADDMIN (Bit 0)

Definition at line 3211 of file DA14680BA.h.

◆ BLE_BLE_DEBUGADDMIN_REG_REG_ADDMIN_Msk

#define BLE_BLE_DEBUGADDMIN_REG_REG_ADDMIN_Msk   (0xffff0000UL)

BLE BLE_DEBUGADDMIN_REG: REG_ADDMIN (Bitfield-Mask: 0xffff)

Definition at line 3214 of file DA14680BA.h.

◆ BLE_BLE_DEBUGADDMIN_REG_REG_ADDMIN_Pos

#define BLE_BLE_DEBUGADDMIN_REG_REG_ADDMIN_Pos   (16UL)

BLE BLE_DEBUGADDMIN_REG: REG_ADDMIN (Bit 16)

Definition at line 3213 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_CORR_EN_Msk

#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_CORR_EN_Msk   (0x8UL)

BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_CORR_EN (Bitfield-Mask: 0x01)

Definition at line 3144 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_CORR_EN_Pos

#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_CORR_EN_Pos   (3UL)

BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_CORR_EN (Bit 3)

Definition at line 3143 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_IRQ_EN_Msk

#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_IRQ_EN_Msk   (0x3UL)

BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_IRQ_EN (Bitfield-Mask: 0x03)

Definition at line 3140 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_IRQ_EN_Pos

#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_IRQ_EN_Pos   (0UL)

BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_IRQ_EN (Bit 0)

Definition at line 3139 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_ON_Msk

#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_ON_Msk   (0x4UL)

BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_ON (Bitfield-Mask: 0x01)

Definition at line 3142 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_ON_Pos

#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_ON_Pos   (2UL)

BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_ON (Bit 2)

Definition at line 3141 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_STAT_Msk

#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_STAT_Msk   (0x8000UL)

BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_STAT (Bitfield-Mask: 0x01)

Definition at line 3148 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_STAT_Pos

#define BLE_BLE_DEEPSLCNTL_REG_DEEP_SLEEP_STAT_Pos   (15UL)

BLE BLE_DEEPSLCNTL_REG: DEEP_SLEEP_STAT (Bit 15)

Definition at line 3147 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLCNTL_REG_EXTWKUPDSB_Msk

#define BLE_BLE_DEEPSLCNTL_REG_EXTWKUPDSB_Msk   (0x80000000UL)

BLE BLE_DEEPSLCNTL_REG: EXTWKUPDSB (Bitfield-Mask: 0x01)

Definition at line 3150 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLCNTL_REG_EXTWKUPDSB_Pos

#define BLE_BLE_DEEPSLCNTL_REG_EXTWKUPDSB_Pos   (31UL)

BLE BLE_DEEPSLCNTL_REG: EXTWKUPDSB (Bit 31)

Definition at line 3149 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLCNTL_REG_SOFT_WAKEUP_REQ_Msk

#define BLE_BLE_DEEPSLCNTL_REG_SOFT_WAKEUP_REQ_Msk   (0x10UL)

BLE BLE_DEEPSLCNTL_REG: SOFT_WAKEUP_REQ (Bitfield-Mask: 0x01)

Definition at line 3146 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLCNTL_REG_SOFT_WAKEUP_REQ_Pos

#define BLE_BLE_DEEPSLCNTL_REG_SOFT_WAKEUP_REQ_Pos   (4UL)

BLE BLE_DEEPSLCNTL_REG: SOFT_WAKEUP_REQ (Bit 4)

Definition at line 3145 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLSTAT_REG_DEEPSLDUR_Msk

#define BLE_BLE_DEEPSLSTAT_REG_DEEPSLDUR_Msk   (0xffffffffUL)

BLE BLE_DEEPSLSTAT_REG: DEEPSLDUR (Bitfield-Mask: 0xffffffff)

Definition at line 3158 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLSTAT_REG_DEEPSLDUR_Pos

#define BLE_BLE_DEEPSLSTAT_REG_DEEPSLDUR_Pos   (0UL)

BLE BLE_DEEPSLSTAT_REG: DEEPSLDUR (Bit 0)

Definition at line 3157 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLWKUP_REG_DEEPSLTIME_Msk

#define BLE_BLE_DEEPSLWKUP_REG_DEEPSLTIME_Msk   (0xffffffffUL)

BLE BLE_DEEPSLWKUP_REG: DEEPSLTIME (Bitfield-Mask: 0xffffffff)

Definition at line 3154 of file DA14680BA.h.

◆ BLE_BLE_DEEPSLWKUP_REG_DEEPSLTIME_Pos

#define BLE_BLE_DEEPSLWKUP_REG_DEEPSLTIME_Pos   (0UL)

BLE BLE_DEEPSLWKUP_REG: DEEPSLTIME (Bit 0)

Definition at line 3153 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG4_EN_Msk

#define BLE_BLE_DIAGCNTL2_REG_DIAG4_EN_Msk   (0x80UL)

BLE BLE_DIAGCNTL2_REG: DIAG4_EN (Bitfield-Mask: 0x01)

Definition at line 3474 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG4_EN_Pos

#define BLE_BLE_DIAGCNTL2_REG_DIAG4_EN_Pos   (7UL)

BLE BLE_DIAGCNTL2_REG: DIAG4_EN (Bit 7)

Definition at line 3473 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG4_Msk

#define BLE_BLE_DIAGCNTL2_REG_DIAG4_Msk   (0x3fUL)

BLE BLE_DIAGCNTL2_REG: DIAG4 (Bitfield-Mask: 0x3f)

Definition at line 3472 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG4_Pos

#define BLE_BLE_DIAGCNTL2_REG_DIAG4_Pos   (0UL)

BLE BLE_DIAGCNTL2_REG: DIAG4 (Bit 0)

Definition at line 3471 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG5_EN_Msk

#define BLE_BLE_DIAGCNTL2_REG_DIAG5_EN_Msk   (0x8000UL)

BLE BLE_DIAGCNTL2_REG: DIAG5_EN (Bitfield-Mask: 0x01)

Definition at line 3478 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG5_EN_Pos

#define BLE_BLE_DIAGCNTL2_REG_DIAG5_EN_Pos   (15UL)

BLE BLE_DIAGCNTL2_REG: DIAG5_EN (Bit 15)

Definition at line 3477 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG5_Msk

#define BLE_BLE_DIAGCNTL2_REG_DIAG5_Msk   (0x3f00UL)

BLE BLE_DIAGCNTL2_REG: DIAG5 (Bitfield-Mask: 0x3f)

Definition at line 3476 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG5_Pos

#define BLE_BLE_DIAGCNTL2_REG_DIAG5_Pos   (8UL)

BLE BLE_DIAGCNTL2_REG: DIAG5 (Bit 8)

Definition at line 3475 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG6_EN_Msk

#define BLE_BLE_DIAGCNTL2_REG_DIAG6_EN_Msk   (0x800000UL)

BLE BLE_DIAGCNTL2_REG: DIAG6_EN (Bitfield-Mask: 0x01)

Definition at line 3482 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG6_EN_Pos

#define BLE_BLE_DIAGCNTL2_REG_DIAG6_EN_Pos   (23UL)

BLE BLE_DIAGCNTL2_REG: DIAG6_EN (Bit 23)

Definition at line 3481 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG6_Msk

#define BLE_BLE_DIAGCNTL2_REG_DIAG6_Msk   (0x3f0000UL)

BLE BLE_DIAGCNTL2_REG: DIAG6 (Bitfield-Mask: 0x3f)

Definition at line 3480 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG6_Pos

#define BLE_BLE_DIAGCNTL2_REG_DIAG6_Pos   (16UL)

BLE BLE_DIAGCNTL2_REG: DIAG6 (Bit 16)

Definition at line 3479 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG7_EN_Msk

#define BLE_BLE_DIAGCNTL2_REG_DIAG7_EN_Msk   (0x80000000UL)

BLE BLE_DIAGCNTL2_REG: DIAG7_EN (Bitfield-Mask: 0x01)

Definition at line 3486 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG7_EN_Pos

#define BLE_BLE_DIAGCNTL2_REG_DIAG7_EN_Pos   (31UL)

BLE BLE_DIAGCNTL2_REG: DIAG7_EN (Bit 31)

Definition at line 3485 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG7_Msk

#define BLE_BLE_DIAGCNTL2_REG_DIAG7_Msk   (0x3f000000UL)

BLE BLE_DIAGCNTL2_REG: DIAG7 (Bitfield-Mask: 0x3f)

Definition at line 3484 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL2_REG_DIAG7_Pos

#define BLE_BLE_DIAGCNTL2_REG_DIAG7_Pos   (24UL)

BLE BLE_DIAGCNTL2_REG: DIAG7 (Bit 24)

Definition at line 3483 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG0_BIT_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG0_BIT_Msk   (0x7UL)

BLE BLE_DIAGCNTL3_REG: DIAG0_BIT (Bitfield-Mask: 0x07)

Definition at line 3490 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG0_BIT_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG0_BIT_Pos   (0UL)

BLE BLE_DIAGCNTL3_REG: DIAG0_BIT (Bit 0)

Definition at line 3489 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG0_INV_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG0_INV_Msk   (0x8UL)

BLE BLE_DIAGCNTL3_REG: DIAG0_INV (Bitfield-Mask: 0x01)

Definition at line 3492 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG0_INV_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG0_INV_Pos   (3UL)

BLE BLE_DIAGCNTL3_REG: DIAG0_INV (Bit 3)

Definition at line 3491 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG1_BIT_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG1_BIT_Msk   (0x70UL)

BLE BLE_DIAGCNTL3_REG: DIAG1_BIT (Bitfield-Mask: 0x07)

Definition at line 3494 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG1_BIT_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG1_BIT_Pos   (4UL)

BLE BLE_DIAGCNTL3_REG: DIAG1_BIT (Bit 4)

Definition at line 3493 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG1_INV_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG1_INV_Msk   (0x80UL)

BLE BLE_DIAGCNTL3_REG: DIAG1_INV (Bitfield-Mask: 0x01)

Definition at line 3496 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG1_INV_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG1_INV_Pos   (7UL)

BLE BLE_DIAGCNTL3_REG: DIAG1_INV (Bit 7)

Definition at line 3495 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG2_BIT_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG2_BIT_Msk   (0x700UL)

BLE BLE_DIAGCNTL3_REG: DIAG2_BIT (Bitfield-Mask: 0x07)

Definition at line 3498 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG2_BIT_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG2_BIT_Pos   (8UL)

BLE BLE_DIAGCNTL3_REG: DIAG2_BIT (Bit 8)

Definition at line 3497 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG2_INV_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG2_INV_Msk   (0x800UL)

BLE BLE_DIAGCNTL3_REG: DIAG2_INV (Bitfield-Mask: 0x01)

Definition at line 3500 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG2_INV_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG2_INV_Pos   (11UL)

BLE BLE_DIAGCNTL3_REG: DIAG2_INV (Bit 11)

Definition at line 3499 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG3_BIT_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG3_BIT_Msk   (0x7000UL)

BLE BLE_DIAGCNTL3_REG: DIAG3_BIT (Bitfield-Mask: 0x07)

Definition at line 3502 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG3_BIT_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG3_BIT_Pos   (12UL)

BLE BLE_DIAGCNTL3_REG: DIAG3_BIT (Bit 12)

Definition at line 3501 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG3_INV_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG3_INV_Msk   (0x8000UL)

BLE BLE_DIAGCNTL3_REG: DIAG3_INV (Bitfield-Mask: 0x01)

Definition at line 3504 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG3_INV_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG3_INV_Pos   (15UL)

BLE BLE_DIAGCNTL3_REG: DIAG3_INV (Bit 15)

Definition at line 3503 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG4_BIT_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG4_BIT_Msk   (0x70000UL)

BLE BLE_DIAGCNTL3_REG: DIAG4_BIT (Bitfield-Mask: 0x07)

Definition at line 3506 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG4_BIT_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG4_BIT_Pos   (16UL)

BLE BLE_DIAGCNTL3_REG: DIAG4_BIT (Bit 16)

Definition at line 3505 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG4_INV_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG4_INV_Msk   (0x80000UL)

BLE BLE_DIAGCNTL3_REG: DIAG4_INV (Bitfield-Mask: 0x01)

Definition at line 3508 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG4_INV_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG4_INV_Pos   (19UL)

BLE BLE_DIAGCNTL3_REG: DIAG4_INV (Bit 19)

Definition at line 3507 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG5_BIT_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG5_BIT_Msk   (0x700000UL)

BLE BLE_DIAGCNTL3_REG: DIAG5_BIT (Bitfield-Mask: 0x07)

Definition at line 3510 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG5_BIT_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG5_BIT_Pos   (20UL)

BLE BLE_DIAGCNTL3_REG: DIAG5_BIT (Bit 20)

Definition at line 3509 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG5_INV_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG5_INV_Msk   (0x800000UL)

BLE BLE_DIAGCNTL3_REG: DIAG5_INV (Bitfield-Mask: 0x01)

Definition at line 3512 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG5_INV_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG5_INV_Pos   (23UL)

BLE BLE_DIAGCNTL3_REG: DIAG5_INV (Bit 23)

Definition at line 3511 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG6_BIT_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG6_BIT_Msk   (0x7000000UL)

BLE BLE_DIAGCNTL3_REG: DIAG6_BIT (Bitfield-Mask: 0x07)

Definition at line 3514 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG6_BIT_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG6_BIT_Pos   (24UL)

BLE BLE_DIAGCNTL3_REG: DIAG6_BIT (Bit 24)

Definition at line 3513 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG6_INV_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG6_INV_Msk   (0x8000000UL)

BLE BLE_DIAGCNTL3_REG: DIAG6_INV (Bitfield-Mask: 0x01)

Definition at line 3516 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG6_INV_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG6_INV_Pos   (27UL)

BLE BLE_DIAGCNTL3_REG: DIAG6_INV (Bit 27)

Definition at line 3515 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG7_BIT_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG7_BIT_Msk   (0x70000000UL)

BLE BLE_DIAGCNTL3_REG: DIAG7_BIT (Bitfield-Mask: 0x07)

Definition at line 3518 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG7_BIT_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG7_BIT_Pos   (28UL)

BLE BLE_DIAGCNTL3_REG: DIAG7_BIT (Bit 28)

Definition at line 3517 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG7_INV_Msk

#define BLE_BLE_DIAGCNTL3_REG_DIAG7_INV_Msk   (0x80000000UL)

BLE BLE_DIAGCNTL3_REG: DIAG7_INV (Bitfield-Mask: 0x01)

Definition at line 3520 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL3_REG_DIAG7_INV_Pos

#define BLE_BLE_DIAGCNTL3_REG_DIAG7_INV_Pos   (31UL)

BLE BLE_DIAGCNTL3_REG: DIAG7_INV (Bit 31)

Definition at line 3519 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG0_EN_Msk

#define BLE_BLE_DIAGCNTL_REG_DIAG0_EN_Msk   (0x80UL)

BLE BLE_DIAGCNTL_REG: DIAG0_EN (Bitfield-Mask: 0x01)

Definition at line 3180 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG0_EN_Pos

#define BLE_BLE_DIAGCNTL_REG_DIAG0_EN_Pos   (7UL)

BLE BLE_DIAGCNTL_REG: DIAG0_EN (Bit 7)

Definition at line 3179 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG0_Msk

#define BLE_BLE_DIAGCNTL_REG_DIAG0_Msk   (0x3fUL)

BLE BLE_DIAGCNTL_REG: DIAG0 (Bitfield-Mask: 0x3f)

Definition at line 3178 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG0_Pos

#define BLE_BLE_DIAGCNTL_REG_DIAG0_Pos   (0UL)

BLE BLE_DIAGCNTL_REG: DIAG0 (Bit 0)

Definition at line 3177 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG1_EN_Msk

#define BLE_BLE_DIAGCNTL_REG_DIAG1_EN_Msk   (0x8000UL)

BLE BLE_DIAGCNTL_REG: DIAG1_EN (Bitfield-Mask: 0x01)

Definition at line 3184 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG1_EN_Pos

#define BLE_BLE_DIAGCNTL_REG_DIAG1_EN_Pos   (15UL)

BLE BLE_DIAGCNTL_REG: DIAG1_EN (Bit 15)

Definition at line 3183 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG1_Msk

#define BLE_BLE_DIAGCNTL_REG_DIAG1_Msk   (0x3f00UL)

BLE BLE_DIAGCNTL_REG: DIAG1 (Bitfield-Mask: 0x3f)

Definition at line 3182 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG1_Pos

#define BLE_BLE_DIAGCNTL_REG_DIAG1_Pos   (8UL)

BLE BLE_DIAGCNTL_REG: DIAG1 (Bit 8)

Definition at line 3181 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG2_EN_Msk

#define BLE_BLE_DIAGCNTL_REG_DIAG2_EN_Msk   (0x800000UL)

BLE BLE_DIAGCNTL_REG: DIAG2_EN (Bitfield-Mask: 0x01)

Definition at line 3188 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG2_EN_Pos

#define BLE_BLE_DIAGCNTL_REG_DIAG2_EN_Pos   (23UL)

BLE BLE_DIAGCNTL_REG: DIAG2_EN (Bit 23)

Definition at line 3187 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG2_Msk

#define BLE_BLE_DIAGCNTL_REG_DIAG2_Msk   (0x3f0000UL)

BLE BLE_DIAGCNTL_REG: DIAG2 (Bitfield-Mask: 0x3f)

Definition at line 3186 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG2_Pos

#define BLE_BLE_DIAGCNTL_REG_DIAG2_Pos   (16UL)

BLE BLE_DIAGCNTL_REG: DIAG2 (Bit 16)

Definition at line 3185 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG3_EN_Msk

#define BLE_BLE_DIAGCNTL_REG_DIAG3_EN_Msk   (0x80000000UL)

BLE BLE_DIAGCNTL_REG: DIAG3_EN (Bitfield-Mask: 0x01)

Definition at line 3192 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG3_EN_Pos

#define BLE_BLE_DIAGCNTL_REG_DIAG3_EN_Pos   (31UL)

BLE BLE_DIAGCNTL_REG: DIAG3_EN (Bit 31)

Definition at line 3191 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG3_Msk

#define BLE_BLE_DIAGCNTL_REG_DIAG3_Msk   (0x3f000000UL)

BLE BLE_DIAGCNTL_REG: DIAG3 (Bitfield-Mask: 0x3f)

Definition at line 3190 of file DA14680BA.h.

◆ BLE_BLE_DIAGCNTL_REG_DIAG3_Pos

#define BLE_BLE_DIAGCNTL_REG_DIAG3_Pos   (24UL)

BLE BLE_DIAGCNTL_REG: DIAG3 (Bit 24)

Definition at line 3189 of file DA14680BA.h.

◆ BLE_BLE_DIAGSTAT_REG_DIAG0STAT_Msk

#define BLE_BLE_DIAGSTAT_REG_DIAG0STAT_Msk   (0xffUL)

BLE BLE_DIAGSTAT_REG: DIAG0STAT (Bitfield-Mask: 0xff)

Definition at line 3196 of file DA14680BA.h.

◆ BLE_BLE_DIAGSTAT_REG_DIAG0STAT_Pos

#define BLE_BLE_DIAGSTAT_REG_DIAG0STAT_Pos   (0UL)

BLE BLE_DIAGSTAT_REG: DIAG0STAT (Bit 0)

Definition at line 3195 of file DA14680BA.h.

◆ BLE_BLE_DIAGSTAT_REG_DIAG1STAT_Msk

#define BLE_BLE_DIAGSTAT_REG_DIAG1STAT_Msk   (0xff00UL)

BLE BLE_DIAGSTAT_REG: DIAG1STAT (Bitfield-Mask: 0xff)

Definition at line 3198 of file DA14680BA.h.

◆ BLE_BLE_DIAGSTAT_REG_DIAG1STAT_Pos

#define BLE_BLE_DIAGSTAT_REG_DIAG1STAT_Pos   (8UL)

BLE BLE_DIAGSTAT_REG: DIAG1STAT (Bit 8)

Definition at line 3197 of file DA14680BA.h.

◆ BLE_BLE_DIAGSTAT_REG_DIAG2STAT_Msk

#define BLE_BLE_DIAGSTAT_REG_DIAG2STAT_Msk   (0xff0000UL)

BLE BLE_DIAGSTAT_REG: DIAG2STAT (Bitfield-Mask: 0xff)

Definition at line 3200 of file DA14680BA.h.

◆ BLE_BLE_DIAGSTAT_REG_DIAG2STAT_Pos

#define BLE_BLE_DIAGSTAT_REG_DIAG2STAT_Pos   (16UL)

BLE BLE_DIAGSTAT_REG: DIAG2STAT (Bit 16)

Definition at line 3199 of file DA14680BA.h.

◆ BLE_BLE_DIAGSTAT_REG_DIAG3STAT_Msk

#define BLE_BLE_DIAGSTAT_REG_DIAG3STAT_Msk   (0xff000000UL)

BLE BLE_DIAGSTAT_REG: DIAG3STAT (Bitfield-Mask: 0xff)

Definition at line 3202 of file DA14680BA.h.

◆ BLE_BLE_DIAGSTAT_REG_DIAG3STAT_Pos

#define BLE_BLE_DIAGSTAT_REG_DIAG3STAT_Pos   (24UL)

BLE BLE_DIAGSTAT_REG: DIAG3STAT (Bit 24)

Definition at line 3201 of file DA14680BA.h.

◆ BLE_BLE_EM_BASE_REG_BLE_EM_BASE_16_10_Msk

#define BLE_BLE_EM_BASE_REG_BLE_EM_BASE_16_10_Msk   (0x1fc00UL)

BLE BLE_EM_BASE_REG: BLE_EM_BASE_16_10 (Bitfield-Mask: 0x7f)

Definition at line 3468 of file DA14680BA.h.

◆ BLE_BLE_EM_BASE_REG_BLE_EM_BASE_16_10_Pos

#define BLE_BLE_EM_BASE_REG_BLE_EM_BASE_16_10_Pos   (10UL)

BLE BLE_EM_BASE_REG: BLE_EM_BASE_16_10 (Bit 10)

Definition at line 3467 of file DA14680BA.h.

◆ BLE_BLE_ENBPRESET_REG_TWEXT_Msk

#define BLE_BLE_ENBPRESET_REG_TWEXT_Msk   (0xffe00000UL)

BLE BLE_ENBPRESET_REG: TWEXT (Bitfield-Mask: 0x7ff)

Definition at line 3166 of file DA14680BA.h.

◆ BLE_BLE_ENBPRESET_REG_TWEXT_Pos

#define BLE_BLE_ENBPRESET_REG_TWEXT_Pos   (21UL)

BLE BLE_ENBPRESET_REG: TWEXT (Bit 21)

Definition at line 3165 of file DA14680BA.h.

◆ BLE_BLE_ENBPRESET_REG_TWIRQ_RESET_Msk

#define BLE_BLE_ENBPRESET_REG_TWIRQ_RESET_Msk   (0x3ffUL)

BLE BLE_ENBPRESET_REG: TWIRQ_RESET (Bitfield-Mask: 0x3ff)

Definition at line 3162 of file DA14680BA.h.

◆ BLE_BLE_ENBPRESET_REG_TWIRQ_RESET_Pos

#define BLE_BLE_ENBPRESET_REG_TWIRQ_RESET_Pos   (0UL)

BLE BLE_ENBPRESET_REG: TWIRQ_RESET (Bit 0)

Definition at line 3161 of file DA14680BA.h.

◆ BLE_BLE_ENBPRESET_REG_TWIRQ_SET_Msk

#define BLE_BLE_ENBPRESET_REG_TWIRQ_SET_Msk   (0x1ffc00UL)

BLE BLE_ENBPRESET_REG: TWIRQ_SET (Bitfield-Mask: 0x7ff)

Definition at line 3164 of file DA14680BA.h.

◆ BLE_BLE_ENBPRESET_REG_TWIRQ_SET_Pos

#define BLE_BLE_ENBPRESET_REG_TWIRQ_SET_Pos   (10UL)

BLE BLE_ENBPRESET_REG: TWIRQ_SET (Bit 10)

Definition at line 3163 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_ADV_UNDERRUN_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_ADV_UNDERRUN_Msk   (0x400UL)

BLE BLE_ERRORTYPESTAT_REG: ADV_UNDERRUN (Bitfield-Mask: 0x01)

Definition at line 3238 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_ADV_UNDERRUN_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_ADV_UNDERRUN_Pos   (10UL)

BLE BLE_ERRORTYPESTAT_REG: ADV_UNDERRUN (Bit 10)

Definition at line 3237 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_CONCEVTIRQ_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_CONCEVTIRQ_ERROR_Msk   (0x20000UL)

BLE BLE_ERRORTYPESTAT_REG: CONCEVTIRQ_ERROR (Bitfield-Mask: 0x01)

Definition at line 3252 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_CONCEVTIRQ_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_CONCEVTIRQ_ERROR_Pos   (17UL)

BLE BLE_ERRORTYPESTAT_REG: CONCEVTIRQ_ERROR (Bit 17)

Definition at line 3251 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_CSFORMAT_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_CSFORMAT_ERROR_Msk   (0x1000UL)

BLE BLE_ERRORTYPESTAT_REG: CSFORMAT_ERROR (Bitfield-Mask: 0x01)

Definition at line 3242 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_CSFORMAT_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_CSFORMAT_ERROR_Pos   (12UL)

BLE BLE_ERRORTYPESTAT_REG: CSFORMAT_ERROR (Bit 12)

Definition at line 3241 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_EVT_CNTL_APFM_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_EVT_CNTL_APFM_ERROR_Msk   (0x80UL)

BLE BLE_ERRORTYPESTAT_REG: EVT_CNTL_APFM_ERROR (Bitfield-Mask: 0x01)

Definition at line 3232 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_EVT_CNTL_APFM_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_EVT_CNTL_APFM_ERROR_Pos   (7UL)

BLE BLE_ERRORTYPESTAT_REG: EVT_CNTL_APFM_ERROR (Bit 7)

Definition at line 3231 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_APFM_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_APFM_ERROR_Msk   (0x40UL)

BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_APFM_ERROR (Bitfield-Mask: 0x01)

Definition at line 3230 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_APFM_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_APFM_ERROR_Pos   (6UL)

BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_APFM_ERROR (Bit 6)

Definition at line 3229 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_EMACC_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_EMACC_ERROR_Msk   (0x10UL)

BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_EMACC_ERROR (Bitfield-Mask: 0x01)

Definition at line 3226 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_EMACC_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_EMACC_ERROR_Pos   (4UL)

BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_EMACC_ERROR (Bit 4)

Definition at line 3225 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_ENTRY_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_ENTRY_ERROR_Msk   (0x20UL)

BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_ENTRY_ERROR (Bitfield-Mask: 0x01)

Definition at line 3228 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_ENTRY_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_EVT_SCHDL_ENTRY_ERROR_Pos   (5UL)

BLE BLE_ERRORTYPESTAT_REG: EVT_SCHDL_ENTRY_ERROR (Bit 5)

Definition at line 3227 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_IFS_UNDERRUN_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_IFS_UNDERRUN_Msk   (0x200UL)

BLE BLE_ERRORTYPESTAT_REG: IFS_UNDERRUN (Bitfield-Mask: 0x01)

Definition at line 3236 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_IFS_UNDERRUN_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_IFS_UNDERRUN_Pos   (9UL)

BLE BLE_ERRORTYPESTAT_REG: IFS_UNDERRUN (Bit 9)

Definition at line 3235 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_LLCHMAP_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_LLCHMAP_ERROR_Msk   (0x800UL)

BLE BLE_ERRORTYPESTAT_REG: LLCHMAP_ERROR (Bitfield-Mask: 0x01)

Definition at line 3240 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_LLCHMAP_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_LLCHMAP_ERROR_Pos   (11UL)

BLE BLE_ERRORTYPESTAT_REG: LLCHMAP_ERROR (Bit 11)

Definition at line 3239 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_PKTCNTL_EMACC_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_PKTCNTL_EMACC_ERROR_Msk   (0x4UL)

BLE BLE_ERRORTYPESTAT_REG: PKTCNTL_EMACC_ERROR (Bitfield-Mask: 0x01)

Definition at line 3222 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_PKTCNTL_EMACC_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_PKTCNTL_EMACC_ERROR_Pos   (2UL)

BLE BLE_ERRORTYPESTAT_REG: PKTCNTL_EMACC_ERROR (Bit 2)

Definition at line 3221 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_RADIO_EMACC_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_RADIO_EMACC_ERROR_Msk   (0x8UL)

BLE BLE_ERRORTYPESTAT_REG: RADIO_EMACC_ERROR (Bitfield-Mask: 0x01)

Definition at line 3224 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_RADIO_EMACC_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_RADIO_EMACC_ERROR_Pos   (3UL)

BLE BLE_ERRORTYPESTAT_REG: RADIO_EMACC_ERROR (Bit 3)

Definition at line 3223 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_RXCRYPT_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_RXCRYPT_ERROR_Msk   (0x2UL)

BLE BLE_ERRORTYPESTAT_REG: RXCRYPT_ERROR (Bitfield-Mask: 0x01)

Definition at line 3220 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_RXCRYPT_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_RXCRYPT_ERROR_Pos   (1UL)

BLE BLE_ERRORTYPESTAT_REG: RXCRYPT_ERROR (Bit 1)

Definition at line 3219 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_RXDATA_PTR_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_RXDATA_PTR_ERROR_Msk   (0x10000UL)

BLE BLE_ERRORTYPESTAT_REG: RXDATA_PTR_ERROR (Bitfield-Mask: 0x01)

Definition at line 3250 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_RXDATA_PTR_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_RXDATA_PTR_ERROR_Pos   (16UL)

BLE BLE_ERRORTYPESTAT_REG: RXDATA_PTR_ERROR (Bit 16)

Definition at line 3249 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_RXDESC_EMPTY_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_RXDESC_EMPTY_ERROR_Msk   (0x4000UL)

BLE BLE_ERRORTYPESTAT_REG: RXDESC_EMPTY_ERROR (Bitfield-Mask: 0x01)

Definition at line 3246 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_RXDESC_EMPTY_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_RXDESC_EMPTY_ERROR_Pos   (14UL)

BLE BLE_ERRORTYPESTAT_REG: RXDESC_EMPTY_ERROR (Bit 14)

Definition at line 3245 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_TXCRYPT_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_TXCRYPT_ERROR_Msk   (0x1UL)

BLE BLE_ERRORTYPESTAT_REG: TXCRYPT_ERROR (Bitfield-Mask: 0x01)

Definition at line 3218 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_TXCRYPT_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_TXCRYPT_ERROR_Pos   (0UL)

BLE BLE_ERRORTYPESTAT_REG: TXCRYPT_ERROR (Bit 0)

Definition at line 3217 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_TXDATA_PTR_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_TXDATA_PTR_ERROR_Msk   (0x8000UL)

BLE BLE_ERRORTYPESTAT_REG: TXDATA_PTR_ERROR (Bitfield-Mask: 0x01)

Definition at line 3248 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_TXDATA_PTR_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_TXDATA_PTR_ERROR_Pos   (15UL)

BLE BLE_ERRORTYPESTAT_REG: TXDATA_PTR_ERROR (Bit 15)

Definition at line 3247 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_TXDESC_EMPTY_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_TXDESC_EMPTY_ERROR_Msk   (0x2000UL)

BLE BLE_ERRORTYPESTAT_REG: TXDESC_EMPTY_ERROR (Bitfield-Mask: 0x01)

Definition at line 3244 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_TXDESC_EMPTY_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_TXDESC_EMPTY_ERROR_Pos   (13UL)

BLE BLE_ERRORTYPESTAT_REG: TXDESC_EMPTY_ERROR (Bit 13)

Definition at line 3243 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_WHITELIST_ERROR_Msk

#define BLE_BLE_ERRORTYPESTAT_REG_WHITELIST_ERROR_Msk   (0x100UL)

BLE BLE_ERRORTYPESTAT_REG: WHITELIST_ERROR (Bitfield-Mask: 0x01)

Definition at line 3234 of file DA14680BA.h.

◆ BLE_BLE_ERRORTYPESTAT_REG_WHITELIST_ERROR_Pos

#define BLE_BLE_ERRORTYPESTAT_REG_WHITELIST_ERROR_Pos   (8UL)

BLE BLE_ERRORTYPESTAT_REG: WHITELIST_ERROR (Bit 8)

Definition at line 3233 of file DA14680BA.h.

◆ BLE_BLE_FINECNTCORR_REG_FINECNTCORR_Msk

#define BLE_BLE_FINECNTCORR_REG_FINECNTCORR_Msk   (0x3ffUL)

BLE BLE_FINECNTCORR_REG: FINECNTCORR (Bitfield-Mask: 0x3ff)

Definition at line 3170 of file DA14680BA.h.

◆ BLE_BLE_FINECNTCORR_REG_FINECNTCORR_Pos

#define BLE_BLE_FINECNTCORR_REG_FINECNTCORR_Pos   (0UL)

BLE BLE_FINECNTCORR_REG: FINECNTCORR (Bit 0)

Definition at line 3169 of file DA14680BA.h.

◆ BLE_BLE_FINETIMECNT_REG_FINECNT_Msk

#define BLE_BLE_FINETIMECNT_REG_FINECNT_Msk   (0x3ffUL)

BLE BLE_FINETIMECNT_REG: FINECNT (Bitfield-Mask: 0x3ff)

Definition at line 3120 of file DA14680BA.h.

◆ BLE_BLE_FINETIMECNT_REG_FINECNT_Pos

#define BLE_BLE_FINETIMECNT_REG_FINECNT_Pos   (0UL)

BLE BLE_FINETIMECNT_REG: FINECNT (Bit 0)

Definition at line 3119 of file DA14680BA.h.

◆ BLE_BLE_FINETIMTGT_REG_FINETARGET_Msk

#define BLE_BLE_FINETIMTGT_REG_FINETARGET_Msk   (0x7ffffffUL)

BLE BLE_FINETIMTGT_REG: FINETARGET (Bitfield-Mask: 0x7ffffff)

Definition at line 3378 of file DA14680BA.h.

◆ BLE_BLE_FINETIMTGT_REG_FINETARGET_Pos

#define BLE_BLE_FINETIMTGT_REG_FINETARGET_Pos   (0UL)

BLE BLE_FINETIMTGT_REG: FINETARGET (Bit 0)

Definition at line 3377 of file DA14680BA.h.

◆ BLE_BLE_GROSSTIMTGT_REG_GROSSTARGET_Msk

#define BLE_BLE_GROSSTIMTGT_REG_GROSSTARGET_Msk   (0x7fffffUL)

BLE BLE_GROSSTIMTGT_REG: GROSSTARGET (Bitfield-Mask: 0x7fffff)

Definition at line 3374 of file DA14680BA.h.

◆ BLE_BLE_GROSSTIMTGT_REG_GROSSTARGET_Pos

#define BLE_BLE_GROSSTIMTGT_REG_GROSSTARGET_Pos   (0UL)

BLE BLE_GROSSTIMTGT_REG: GROSSTARGET (Bit 0)

Definition at line 3373 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_CRYPTINTACK_Msk

#define BLE_BLE_INTACK_REG_CRYPTINTACK_Msk   (0x10UL)

BLE BLE_INTACK_REG: CRYPTINTACK (Bitfield-Mask: 0x01)

Definition at line 3102 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_CRYPTINTACK_Pos

#define BLE_BLE_INTACK_REG_CRYPTINTACK_Pos   (4UL)

BLE BLE_INTACK_REG: CRYPTINTACK (Bit 4)

Definition at line 3101 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_CSCNTINTACK_Msk

#define BLE_BLE_INTACK_REG_CSCNTINTACK_Msk   (0x1UL)

BLE BLE_INTACK_REG: CSCNTINTACK (Bitfield-Mask: 0x01)

Definition at line 3094 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_CSCNTINTACK_Pos

#define BLE_BLE_INTACK_REG_CSCNTINTACK_Pos   (0UL)

BLE BLE_INTACK_REG: CSCNTINTACK (Bit 0)

Definition at line 3093 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_ERRORINTACK_Msk

#define BLE_BLE_INTACK_REG_ERRORINTACK_Msk   (0x20UL)

BLE BLE_INTACK_REG: ERRORINTACK (Bitfield-Mask: 0x01)

Definition at line 3104 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_ERRORINTACK_Pos

#define BLE_BLE_INTACK_REG_ERRORINTACK_Pos   (5UL)

BLE BLE_INTACK_REG: ERRORINTACK (Bit 5)

Definition at line 3103 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_EVENTAPFAINTACK_Msk

#define BLE_BLE_INTACK_REG_EVENTAPFAINTACK_Msk   (0x100UL)

BLE BLE_INTACK_REG: EVENTAPFAINTACK (Bitfield-Mask: 0x01)

Definition at line 3110 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_EVENTAPFAINTACK_Pos

#define BLE_BLE_INTACK_REG_EVENTAPFAINTACK_Pos   (8UL)

BLE BLE_INTACK_REG: EVENTAPFAINTACK (Bit 8)

Definition at line 3109 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_EVENTINTACK_Msk

#define BLE_BLE_INTACK_REG_EVENTINTACK_Msk   (0x8UL)

BLE BLE_INTACK_REG: EVENTINTACK (Bitfield-Mask: 0x01)

Definition at line 3100 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_EVENTINTACK_Pos

#define BLE_BLE_INTACK_REG_EVENTINTACK_Pos   (3UL)

BLE BLE_INTACK_REG: EVENTINTACK (Bit 3)

Definition at line 3099 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_FINETGTIMINTACK_Msk

#define BLE_BLE_INTACK_REG_FINETGTIMINTACK_Msk   (0x80UL)

BLE BLE_INTACK_REG: FINETGTIMINTACK (Bitfield-Mask: 0x01)

Definition at line 3108 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_FINETGTIMINTACK_Pos

#define BLE_BLE_INTACK_REG_FINETGTIMINTACK_Pos   (7UL)

BLE BLE_INTACK_REG: FINETGTIMINTACK (Bit 7)

Definition at line 3107 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_GROSSTGTIMINTACK_Msk

#define BLE_BLE_INTACK_REG_GROSSTGTIMINTACK_Msk   (0x40UL)

BLE BLE_INTACK_REG: GROSSTGTIMINTACK (Bitfield-Mask: 0x01)

Definition at line 3106 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_GROSSTGTIMINTACK_Pos

#define BLE_BLE_INTACK_REG_GROSSTGTIMINTACK_Pos   (6UL)

BLE BLE_INTACK_REG: GROSSTGTIMINTACK (Bit 6)

Definition at line 3105 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_RXINTACK_Msk

#define BLE_BLE_INTACK_REG_RXINTACK_Msk   (0x2UL)

BLE BLE_INTACK_REG: RXINTACK (Bitfield-Mask: 0x01)

Definition at line 3096 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_RXINTACK_Pos

#define BLE_BLE_INTACK_REG_RXINTACK_Pos   (1UL)

BLE BLE_INTACK_REG: RXINTACK (Bit 1)

Definition at line 3095 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_SLPINTACK_Msk

#define BLE_BLE_INTACK_REG_SLPINTACK_Msk   (0x4UL)

BLE BLE_INTACK_REG: SLPINTACK (Bitfield-Mask: 0x01)

Definition at line 3098 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_SLPINTACK_Pos

#define BLE_BLE_INTACK_REG_SLPINTACK_Pos   (2UL)

BLE BLE_INTACK_REG: SLPINTACK (Bit 2)

Definition at line 3097 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_SWINTACK_Msk

#define BLE_BLE_INTACK_REG_SWINTACK_Msk   (0x200UL)

BLE BLE_INTACK_REG: SWINTACK (Bitfield-Mask: 0x01)

Definition at line 3112 of file DA14680BA.h.

◆ BLE_BLE_INTACK_REG_SWINTACK_Pos

#define BLE_BLE_INTACK_REG_SWINTACK_Pos   (9UL)

BLE BLE_INTACK_REG: SWINTACK (Bit 9)

Definition at line 3111 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_CRYPTINTMSK_Msk

#define BLE_BLE_INTCNTL_REG_CRYPTINTMSK_Msk   (0x10UL)

BLE BLE_INTCNTL_REG: CRYPTINTMSK (Bitfield-Mask: 0x01)

Definition at line 3034 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_CRYPTINTMSK_Pos

#define BLE_BLE_INTCNTL_REG_CRYPTINTMSK_Pos   (4UL)

BLE BLE_INTCNTL_REG: CRYPTINTMSK (Bit 4)

Definition at line 3033 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_CSCNTDEVMSK_Msk

#define BLE_BLE_INTCNTL_REG_CSCNTDEVMSK_Msk   (0x8000UL)

BLE BLE_INTCNTL_REG: CSCNTDEVMSK (Bitfield-Mask: 0x01)

Definition at line 3046 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_CSCNTDEVMSK_Pos

#define BLE_BLE_INTCNTL_REG_CSCNTDEVMSK_Pos   (15UL)

BLE BLE_INTCNTL_REG: CSCNTDEVMSK (Bit 15)

Definition at line 3045 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_CSCNTINTMSK_Msk

#define BLE_BLE_INTCNTL_REG_CSCNTINTMSK_Msk   (0x1UL)

BLE BLE_INTCNTL_REG: CSCNTINTMSK (Bitfield-Mask: 0x01)

Definition at line 3026 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_CSCNTINTMSK_Pos

#define BLE_BLE_INTCNTL_REG_CSCNTINTMSK_Pos   (0UL)

BLE BLE_INTCNTL_REG: CSCNTINTMSK (Bit 0)

Definition at line 3025 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_ERRORINTMSK_Msk

#define BLE_BLE_INTCNTL_REG_ERRORINTMSK_Msk   (0x20UL)

BLE BLE_INTCNTL_REG: ERRORINTMSK (Bitfield-Mask: 0x01)

Definition at line 3036 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_ERRORINTMSK_Pos

#define BLE_BLE_INTCNTL_REG_ERRORINTMSK_Pos   (5UL)

BLE BLE_INTCNTL_REG: ERRORINTMSK (Bit 5)

Definition at line 3035 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_EVENTAPFAINTMSK_Msk

#define BLE_BLE_INTCNTL_REG_EVENTAPFAINTMSK_Msk   (0x100UL)

BLE BLE_INTCNTL_REG: EVENTAPFAINTMSK (Bitfield-Mask: 0x01)

Definition at line 3042 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_EVENTAPFAINTMSK_Pos

#define BLE_BLE_INTCNTL_REG_EVENTAPFAINTMSK_Pos   (8UL)

BLE BLE_INTCNTL_REG: EVENTAPFAINTMSK (Bit 8)

Definition at line 3041 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_EVENTINTMSK_Msk

#define BLE_BLE_INTCNTL_REG_EVENTINTMSK_Msk   (0x8UL)

BLE BLE_INTCNTL_REG: EVENTINTMSK (Bitfield-Mask: 0x01)

Definition at line 3032 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_EVENTINTMSK_Pos

#define BLE_BLE_INTCNTL_REG_EVENTINTMSK_Pos   (3UL)

BLE BLE_INTCNTL_REG: EVENTINTMSK (Bit 3)

Definition at line 3031 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_FINETGTIMINTMSK_Msk

#define BLE_BLE_INTCNTL_REG_FINETGTIMINTMSK_Msk   (0x80UL)

BLE BLE_INTCNTL_REG: FINETGTIMINTMSK (Bitfield-Mask: 0x01)

Definition at line 3040 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_FINETGTIMINTMSK_Pos

#define BLE_BLE_INTCNTL_REG_FINETGTIMINTMSK_Pos   (7UL)

BLE BLE_INTCNTL_REG: FINETGTIMINTMSK (Bit 7)

Definition at line 3039 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_GROSSTGTIMINTMSK_Msk

#define BLE_BLE_INTCNTL_REG_GROSSTGTIMINTMSK_Msk   (0x40UL)

BLE BLE_INTCNTL_REG: GROSSTGTIMINTMSK (Bitfield-Mask: 0x01)

Definition at line 3038 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_GROSSTGTIMINTMSK_Pos

#define BLE_BLE_INTCNTL_REG_GROSSTGTIMINTMSK_Pos   (6UL)

BLE BLE_INTCNTL_REG: GROSSTGTIMINTMSK (Bit 6)

Definition at line 3037 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_RXINTMSK_Msk

#define BLE_BLE_INTCNTL_REG_RXINTMSK_Msk   (0x2UL)

BLE BLE_INTCNTL_REG: RXINTMSK (Bitfield-Mask: 0x01)

Definition at line 3028 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_RXINTMSK_Pos

#define BLE_BLE_INTCNTL_REG_RXINTMSK_Pos   (1UL)

BLE BLE_INTCNTL_REG: RXINTMSK (Bit 1)

Definition at line 3027 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_SLPINTMSK_Msk

#define BLE_BLE_INTCNTL_REG_SLPINTMSK_Msk   (0x4UL)

BLE BLE_INTCNTL_REG: SLPINTMSK (Bitfield-Mask: 0x01)

Definition at line 3030 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_SLPINTMSK_Pos

#define BLE_BLE_INTCNTL_REG_SLPINTMSK_Pos   (2UL)

BLE BLE_INTCNTL_REG: SLPINTMSK (Bit 2)

Definition at line 3029 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_SWINTMSK_Msk

#define BLE_BLE_INTCNTL_REG_SWINTMSK_Msk   (0x200UL)

BLE BLE_INTCNTL_REG: SWINTMSK (Bitfield-Mask: 0x01)

Definition at line 3044 of file DA14680BA.h.

◆ BLE_BLE_INTCNTL_REG_SWINTMSK_Pos

#define BLE_BLE_INTCNTL_REG_SWINTMSK_Pos   (9UL)

BLE BLE_INTCNTL_REG: SWINTMSK (Bit 9)

Definition at line 3043 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_CRYPTINTRAWSTAT_Msk

#define BLE_BLE_INTRAWSTAT_REG_CRYPTINTRAWSTAT_Msk   (0x10UL)

BLE BLE_INTRAWSTAT_REG: CRYPTINTRAWSTAT (Bitfield-Mask: 0x01)

Definition at line 3080 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_CRYPTINTRAWSTAT_Pos

#define BLE_BLE_INTRAWSTAT_REG_CRYPTINTRAWSTAT_Pos   (4UL)

BLE BLE_INTRAWSTAT_REG: CRYPTINTRAWSTAT (Bit 4)

Definition at line 3079 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_CSCNTINTRAWSTAT_Msk

#define BLE_BLE_INTRAWSTAT_REG_CSCNTINTRAWSTAT_Msk   (0x1UL)

BLE BLE_INTRAWSTAT_REG: CSCNTINTRAWSTAT (Bitfield-Mask: 0x01)

Definition at line 3072 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_CSCNTINTRAWSTAT_Pos

#define BLE_BLE_INTRAWSTAT_REG_CSCNTINTRAWSTAT_Pos   (0UL)

BLE BLE_INTRAWSTAT_REG: CSCNTINTRAWSTAT (Bit 0)

Definition at line 3071 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_ERRORINTRAWSTAT_Msk

#define BLE_BLE_INTRAWSTAT_REG_ERRORINTRAWSTAT_Msk   (0x20UL)

BLE BLE_INTRAWSTAT_REG: ERRORINTRAWSTAT (Bitfield-Mask: 0x01)

Definition at line 3082 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_ERRORINTRAWSTAT_Pos

#define BLE_BLE_INTRAWSTAT_REG_ERRORINTRAWSTAT_Pos   (5UL)

BLE BLE_INTRAWSTAT_REG: ERRORINTRAWSTAT (Bit 5)

Definition at line 3081 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_EVENTAPFAINTRAWSTAT_Msk

#define BLE_BLE_INTRAWSTAT_REG_EVENTAPFAINTRAWSTAT_Msk   (0x100UL)

BLE BLE_INTRAWSTAT_REG: EVENTAPFAINTRAWSTAT (Bitfield-Mask: 0x01)

Definition at line 3088 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_EVENTAPFAINTRAWSTAT_Pos

#define BLE_BLE_INTRAWSTAT_REG_EVENTAPFAINTRAWSTAT_Pos   (8UL)

BLE BLE_INTRAWSTAT_REG: EVENTAPFAINTRAWSTAT (Bit 8)

Definition at line 3087 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_EVENTINTRAWSTAT_Msk

#define BLE_BLE_INTRAWSTAT_REG_EVENTINTRAWSTAT_Msk   (0x8UL)

BLE BLE_INTRAWSTAT_REG: EVENTINTRAWSTAT (Bitfield-Mask: 0x01)

Definition at line 3078 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_EVENTINTRAWSTAT_Pos

#define BLE_BLE_INTRAWSTAT_REG_EVENTINTRAWSTAT_Pos   (3UL)

BLE BLE_INTRAWSTAT_REG: EVENTINTRAWSTAT (Bit 3)

Definition at line 3077 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_FINETGTIMINTRAWSTAT_Msk

#define BLE_BLE_INTRAWSTAT_REG_FINETGTIMINTRAWSTAT_Msk   (0x80UL)

BLE BLE_INTRAWSTAT_REG: FINETGTIMINTRAWSTAT (Bitfield-Mask: 0x01)

Definition at line 3086 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_FINETGTIMINTRAWSTAT_Pos

#define BLE_BLE_INTRAWSTAT_REG_FINETGTIMINTRAWSTAT_Pos   (7UL)

BLE BLE_INTRAWSTAT_REG: FINETGTIMINTRAWSTAT (Bit 7)

Definition at line 3085 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_GROSSTGTIMINTRAWSTAT_Msk

#define BLE_BLE_INTRAWSTAT_REG_GROSSTGTIMINTRAWSTAT_Msk   (0x40UL)

BLE BLE_INTRAWSTAT_REG: GROSSTGTIMINTRAWSTAT (Bitfield-Mask: 0x01)

Definition at line 3084 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_GROSSTGTIMINTRAWSTAT_Pos

#define BLE_BLE_INTRAWSTAT_REG_GROSSTGTIMINTRAWSTAT_Pos   (6UL)

BLE BLE_INTRAWSTAT_REG: GROSSTGTIMINTRAWSTAT (Bit 6)

Definition at line 3083 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_RXINTRAWSTAT_Msk

#define BLE_BLE_INTRAWSTAT_REG_RXINTRAWSTAT_Msk   (0x2UL)

BLE BLE_INTRAWSTAT_REG: RXINTRAWSTAT (Bitfield-Mask: 0x01)

Definition at line 3074 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_RXINTRAWSTAT_Pos

#define BLE_BLE_INTRAWSTAT_REG_RXINTRAWSTAT_Pos   (1UL)

BLE BLE_INTRAWSTAT_REG: RXINTRAWSTAT (Bit 1)

Definition at line 3073 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_SLPINTRAWSTAT_Msk

#define BLE_BLE_INTRAWSTAT_REG_SLPINTRAWSTAT_Msk   (0x4UL)

BLE BLE_INTRAWSTAT_REG: SLPINTRAWSTAT (Bitfield-Mask: 0x01)

Definition at line 3076 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_SLPINTRAWSTAT_Pos

#define BLE_BLE_INTRAWSTAT_REG_SLPINTRAWSTAT_Pos   (2UL)

BLE BLE_INTRAWSTAT_REG: SLPINTRAWSTAT (Bit 2)

Definition at line 3075 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_SWINTRAWSTAT_Msk

#define BLE_BLE_INTRAWSTAT_REG_SWINTRAWSTAT_Msk   (0x200UL)

BLE BLE_INTRAWSTAT_REG: SWINTRAWSTAT (Bitfield-Mask: 0x01)

Definition at line 3090 of file DA14680BA.h.

◆ BLE_BLE_INTRAWSTAT_REG_SWINTRAWSTAT_Pos

#define BLE_BLE_INTRAWSTAT_REG_SWINTRAWSTAT_Pos   (9UL)

BLE BLE_INTRAWSTAT_REG: SWINTRAWSTAT (Bit 9)

Definition at line 3089 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_CRYPTINTSTAT_Msk

#define BLE_BLE_INTSTAT_REG_CRYPTINTSTAT_Msk   (0x10UL)

BLE BLE_INTSTAT_REG: CRYPTINTSTAT (Bitfield-Mask: 0x01)

Definition at line 3058 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_CRYPTINTSTAT_Pos

#define BLE_BLE_INTSTAT_REG_CRYPTINTSTAT_Pos   (4UL)

BLE BLE_INTSTAT_REG: CRYPTINTSTAT (Bit 4)

Definition at line 3057 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_CSCNTINTSTAT_Msk

#define BLE_BLE_INTSTAT_REG_CSCNTINTSTAT_Msk   (0x1UL)

BLE BLE_INTSTAT_REG: CSCNTINTSTAT (Bitfield-Mask: 0x01)

Definition at line 3050 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_CSCNTINTSTAT_Pos

#define BLE_BLE_INTSTAT_REG_CSCNTINTSTAT_Pos   (0UL)

BLE BLE_INTSTAT_REG: CSCNTINTSTAT (Bit 0)

Definition at line 3049 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_ERRORINTSTAT_Msk

#define BLE_BLE_INTSTAT_REG_ERRORINTSTAT_Msk   (0x20UL)

BLE BLE_INTSTAT_REG: ERRORINTSTAT (Bitfield-Mask: 0x01)

Definition at line 3060 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_ERRORINTSTAT_Pos

#define BLE_BLE_INTSTAT_REG_ERRORINTSTAT_Pos   (5UL)

BLE BLE_INTSTAT_REG: ERRORINTSTAT (Bit 5)

Definition at line 3059 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_EVENTAPFAINTSTAT_Msk

#define BLE_BLE_INTSTAT_REG_EVENTAPFAINTSTAT_Msk   (0x100UL)

BLE BLE_INTSTAT_REG: EVENTAPFAINTSTAT (Bitfield-Mask: 0x01)

Definition at line 3066 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_EVENTAPFAINTSTAT_Pos

#define BLE_BLE_INTSTAT_REG_EVENTAPFAINTSTAT_Pos   (8UL)

BLE BLE_INTSTAT_REG: EVENTAPFAINTSTAT (Bit 8)

Definition at line 3065 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_EVENTINTSTAT_Msk

#define BLE_BLE_INTSTAT_REG_EVENTINTSTAT_Msk   (0x8UL)

BLE BLE_INTSTAT_REG: EVENTINTSTAT (Bitfield-Mask: 0x01)

Definition at line 3056 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_EVENTINTSTAT_Pos

#define BLE_BLE_INTSTAT_REG_EVENTINTSTAT_Pos   (3UL)

BLE BLE_INTSTAT_REG: EVENTINTSTAT (Bit 3)

Definition at line 3055 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_FINETGTIMINTSTAT_Msk

#define BLE_BLE_INTSTAT_REG_FINETGTIMINTSTAT_Msk   (0x80UL)

BLE BLE_INTSTAT_REG: FINETGTIMINTSTAT (Bitfield-Mask: 0x01)

Definition at line 3064 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_FINETGTIMINTSTAT_Pos

#define BLE_BLE_INTSTAT_REG_FINETGTIMINTSTAT_Pos   (7UL)

BLE BLE_INTSTAT_REG: FINETGTIMINTSTAT (Bit 7)

Definition at line 3063 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_GROSSTGTIMINTSTAT_Msk

#define BLE_BLE_INTSTAT_REG_GROSSTGTIMINTSTAT_Msk   (0x40UL)

BLE BLE_INTSTAT_REG: GROSSTGTIMINTSTAT (Bitfield-Mask: 0x01)

Definition at line 3062 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_GROSSTGTIMINTSTAT_Pos

#define BLE_BLE_INTSTAT_REG_GROSSTGTIMINTSTAT_Pos   (6UL)

BLE BLE_INTSTAT_REG: GROSSTGTIMINTSTAT (Bit 6)

Definition at line 3061 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_RXINTSTAT_Msk

#define BLE_BLE_INTSTAT_REG_RXINTSTAT_Msk   (0x2UL)

BLE BLE_INTSTAT_REG: RXINTSTAT (Bitfield-Mask: 0x01)

Definition at line 3052 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_RXINTSTAT_Pos

#define BLE_BLE_INTSTAT_REG_RXINTSTAT_Pos   (1UL)

BLE BLE_INTSTAT_REG: RXINTSTAT (Bit 1)

Definition at line 3051 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_SLPINTSTAT_Msk

#define BLE_BLE_INTSTAT_REG_SLPINTSTAT_Msk   (0x4UL)

BLE BLE_INTSTAT_REG: SLPINTSTAT (Bitfield-Mask: 0x01)

Definition at line 3054 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_SLPINTSTAT_Pos

#define BLE_BLE_INTSTAT_REG_SLPINTSTAT_Pos   (2UL)

BLE BLE_INTSTAT_REG: SLPINTSTAT (Bit 2)

Definition at line 3053 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_SWINTSTAT_Msk

#define BLE_BLE_INTSTAT_REG_SWINTSTAT_Msk   (0x200UL)

BLE BLE_INTSTAT_REG: SWINTSTAT (Bitfield-Mask: 0x01)

Definition at line 3068 of file DA14680BA.h.

◆ BLE_BLE_INTSTAT_REG_SWINTSTAT_Pos

#define BLE_BLE_INTSTAT_REG_SWINTSTAT_Pos   (9UL)

BLE BLE_INTSTAT_REG: SWINTSTAT (Bit 9)

Definition at line 3067 of file DA14680BA.h.

◆ BLE_BLE_RADIOCNTL0_REG_field246rsv_Msk

#define BLE_BLE_RADIOCNTL0_REG_field246rsv_Msk   (0x1cUL)

BLE BLE_RADIOCNTL0_REG: field246rsv (Bitfield-Mask: 0x07)

Definition at line 3260 of file DA14680BA.h.

◆ BLE_BLE_RADIOCNTL0_REG_field246rsv_Pos

#define BLE_BLE_RADIOCNTL0_REG_field246rsv_Pos   (2UL)

BLE BLE_RADIOCNTL0_REG: field246rsv (Bit 2)

Definition at line 3259 of file DA14680BA.h.

◆ BLE_BLE_RADIOCNTL1_REG_XRFSEL_Msk

#define BLE_BLE_RADIOCNTL1_REG_XRFSEL_Msk   (0x1f0000UL)

BLE BLE_RADIOCNTL1_REG: XRFSEL (Bitfield-Mask: 0x1f)

Definition at line 3264 of file DA14680BA.h.

◆ BLE_BLE_RADIOCNTL1_REG_XRFSEL_Pos

#define BLE_BLE_RADIOCNTL1_REG_XRFSEL_Pos   (16UL)

BLE BLE_RADIOCNTL1_REG: XRFSEL (Bit 16)

Definition at line 3263 of file DA14680BA.h.

◆ BLE_BLE_RADIOPWRUPDN_REG_RTRIP_DELAY_Msk

#define BLE_BLE_RADIOPWRUPDN_REG_RTRIP_DELAY_Msk   (0x7f000000UL)

BLE BLE_RADIOPWRUPDN_REG: RTRIP_DELAY (Bitfield-Mask: 0x7f)

Definition at line 3274 of file DA14680BA.h.

◆ BLE_BLE_RADIOPWRUPDN_REG_RTRIP_DELAY_Pos

#define BLE_BLE_RADIOPWRUPDN_REG_RTRIP_DELAY_Pos   (24UL)

BLE BLE_RADIOPWRUPDN_REG: RTRIP_DELAY (Bit 24)

Definition at line 3273 of file DA14680BA.h.

◆ BLE_BLE_RADIOPWRUPDN_REG_RXPWRUP_Msk

#define BLE_BLE_RADIOPWRUPDN_REG_RXPWRUP_Msk   (0xff0000UL)

BLE BLE_RADIOPWRUPDN_REG: RXPWRUP (Bitfield-Mask: 0xff)

Definition at line 3272 of file DA14680BA.h.

◆ BLE_BLE_RADIOPWRUPDN_REG_RXPWRUP_Pos

#define BLE_BLE_RADIOPWRUPDN_REG_RXPWRUP_Pos   (16UL)

BLE BLE_RADIOPWRUPDN_REG: RXPWRUP (Bit 16)

Definition at line 3271 of file DA14680BA.h.

◆ BLE_BLE_RADIOPWRUPDN_REG_TXPWRDN_Msk

#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRDN_Msk   (0xf00UL)

BLE BLE_RADIOPWRUPDN_REG: TXPWRDN (Bitfield-Mask: 0x0f)

Definition at line 3270 of file DA14680BA.h.

◆ BLE_BLE_RADIOPWRUPDN_REG_TXPWRDN_Pos

#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRDN_Pos   (8UL)

BLE BLE_RADIOPWRUPDN_REG: TXPWRDN (Bit 8)

Definition at line 3269 of file DA14680BA.h.

◆ BLE_BLE_RADIOPWRUPDN_REG_TXPWRUP_Msk

#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRUP_Msk   (0xffUL)

BLE BLE_RADIOPWRUPDN_REG: TXPWRUP (Bitfield-Mask: 0xff)

Definition at line 3268 of file DA14680BA.h.

◆ BLE_BLE_RADIOPWRUPDN_REG_TXPWRUP_Pos

#define BLE_BLE_RADIOPWRUPDN_REG_TXPWRUP_Pos   (0UL)

BLE BLE_RADIOPWRUPDN_REG: TXPWRUP (Bit 0)

Definition at line 3267 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_INFINITERX_Msk

#define BLE_BLE_RFTESTCNTL_REG_INFINITERX_Msk   (0x80000000UL)

BLE BLE_RFTESTCNTL_REG: INFINITERX (Bitfield-Mask: 0x01)

Definition at line 3354 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_INFINITERX_Pos

#define BLE_BLE_RFTESTCNTL_REG_INFINITERX_Pos   (31UL)

BLE BLE_RFTESTCNTL_REG: INFINITERX (Bit 31)

Definition at line 3353 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_INFINITETX_Msk

#define BLE_BLE_RFTESTCNTL_REG_INFINITETX_Msk   (0x8000UL)

BLE BLE_RFTESTCNTL_REG: INFINITETX (Bitfield-Mask: 0x01)

Definition at line 3350 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_INFINITETX_Pos

#define BLE_BLE_RFTESTCNTL_REG_INFINITETX_Pos   (15UL)

BLE BLE_RFTESTCNTL_REG: INFINITETX (Bit 15)

Definition at line 3349 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_PRBSTYPE_Msk

#define BLE_BLE_RFTESTCNTL_REG_PRBSTYPE_Msk   (0x2000UL)

BLE BLE_RFTESTCNTL_REG: PRBSTYPE (Bitfield-Mask: 0x01)

Definition at line 3346 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_PRBSTYPE_Pos

#define BLE_BLE_RFTESTCNTL_REG_PRBSTYPE_Pos   (13UL)

BLE BLE_RFTESTCNTL_REG: PRBSTYPE (Bit 13)

Definition at line 3345 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_RXPKTCNTEN_Msk

#define BLE_BLE_RFTESTCNTL_REG_RXPKTCNTEN_Msk   (0x8000000UL)

BLE BLE_RFTESTCNTL_REG: RXPKTCNTEN (Bitfield-Mask: 0x01)

Definition at line 3352 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_RXPKTCNTEN_Pos

#define BLE_BLE_RFTESTCNTL_REG_RXPKTCNTEN_Pos   (27UL)

BLE BLE_RFTESTCNTL_REG: RXPKTCNTEN (Bit 27)

Definition at line 3351 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_TXLENGTH_Msk

#define BLE_BLE_RFTESTCNTL_REG_TXLENGTH_Msk   (0x1ffUL)

BLE BLE_RFTESTCNTL_REG: TXLENGTH (Bitfield-Mask: 0x1ff)

Definition at line 3340 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_TXLENGTH_Pos

#define BLE_BLE_RFTESTCNTL_REG_TXLENGTH_Pos   (0UL)

BLE BLE_RFTESTCNTL_REG: TXLENGTH (Bit 0)

Definition at line 3339 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_TXLENGTHSRC_Msk

#define BLE_BLE_RFTESTCNTL_REG_TXLENGTHSRC_Msk   (0x4000UL)

BLE BLE_RFTESTCNTL_REG: TXLENGTHSRC (Bitfield-Mask: 0x01)

Definition at line 3348 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_TXLENGTHSRC_Pos

#define BLE_BLE_RFTESTCNTL_REG_TXLENGTHSRC_Pos   (14UL)

BLE BLE_RFTESTCNTL_REG: TXLENGTHSRC (Bit 14)

Definition at line 3347 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_TXPKTCNTEN_Msk

#define BLE_BLE_RFTESTCNTL_REG_TXPKTCNTEN_Msk   (0x800UL)

BLE BLE_RFTESTCNTL_REG: TXPKTCNTEN (Bitfield-Mask: 0x01)

Definition at line 3342 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_TXPKTCNTEN_Pos

#define BLE_BLE_RFTESTCNTL_REG_TXPKTCNTEN_Pos   (11UL)

BLE BLE_RFTESTCNTL_REG: TXPKTCNTEN (Bit 11)

Definition at line 3341 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_TXPLDSRC_Msk

#define BLE_BLE_RFTESTCNTL_REG_TXPLDSRC_Msk   (0x1000UL)

BLE BLE_RFTESTCNTL_REG: TXPLDSRC (Bitfield-Mask: 0x01)

Definition at line 3344 of file DA14680BA.h.

◆ BLE_BLE_RFTESTCNTL_REG_TXPLDSRC_Pos

#define BLE_BLE_RFTESTCNTL_REG_TXPLDSRC_Pos   (12UL)

BLE BLE_RFTESTCNTL_REG: TXPLDSRC (Bit 12)

Definition at line 3343 of file DA14680BA.h.

◆ BLE_BLE_RFTESTRXSTAT_REG_RXPKTCNT_Msk

#define BLE_BLE_RFTESTRXSTAT_REG_RXPKTCNT_Msk   (0xffffffffUL)

BLE BLE_RFTESTRXSTAT_REG: RXPKTCNT (Bitfield-Mask: 0xffffffff)

Definition at line 3362 of file DA14680BA.h.

◆ BLE_BLE_RFTESTRXSTAT_REG_RXPKTCNT_Pos

#define BLE_BLE_RFTESTRXSTAT_REG_RXPKTCNT_Pos   (0UL)

BLE BLE_RFTESTRXSTAT_REG: RXPKTCNT (Bit 0)

Definition at line 3361 of file DA14680BA.h.

◆ BLE_BLE_RFTESTTXSTAT_REG_TXPKTCNT_Msk

#define BLE_BLE_RFTESTTXSTAT_REG_TXPKTCNT_Msk   (0xffffffffUL)

BLE BLE_RFTESTTXSTAT_REG: TXPKTCNT (Bitfield-Mask: 0xffffffff)

Definition at line 3358 of file DA14680BA.h.

◆ BLE_BLE_RFTESTTXSTAT_REG_TXPKTCNT_Pos

#define BLE_BLE_RFTESTTXSTAT_REG_TXPKTCNT_Pos   (0UL)

BLE BLE_RFTESTTXSTAT_REG: TXPKTCNT (Bit 0)

Definition at line 3357 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_ADVERT_ABORT_Msk

#define BLE_BLE_RWBLECNTL_REG_ADVERT_ABORT_Msk   (0x2000000UL)

BLE BLE_RWBLECNTL_REG: ADVERT_ABORT (Bitfield-Mask: 0x01)

Definition at line 2980 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_ADVERT_ABORT_Pos

#define BLE_BLE_RWBLECNTL_REG_ADVERT_ABORT_Pos   (25UL)

BLE BLE_RWBLECNTL_REG: ADVERT_ABORT (Bit 25)

Definition at line 2979 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_ADVERTFILT_EN_Msk

#define BLE_BLE_RWBLECNTL_REG_ADVERTFILT_EN_Msk   (0x200UL)

BLE BLE_RWBLECNTL_REG: ADVERTFILT_EN (Bitfield-Mask: 0x01)

Definition at line 2960 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_ADVERTFILT_EN_Pos

#define BLE_BLE_RWBLECNTL_REG_ADVERTFILT_EN_Pos   (9UL)

BLE BLE_RWBLECNTL_REG: ADVERTFILT_EN (Bit 9)

Definition at line 2959 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_CORR_MODE_Msk

#define BLE_BLE_RWBLECNTL_REG_CORR_MODE_Msk   (0x3000UL)

BLE BLE_RWBLECNTL_REG: CORR_MODE (Bitfield-Mask: 0x03)

Definition at line 2962 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_CORR_MODE_Pos

#define BLE_BLE_RWBLECNTL_REG_CORR_MODE_Pos   (12UL)

BLE BLE_RWBLECNTL_REG: CORR_MODE (Bit 12)

Definition at line 2961 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_CRC_DSB_Msk

#define BLE_BLE_RWBLECNTL_REG_CRC_DSB_Msk   (0x20000UL)

BLE BLE_RWBLECNTL_REG: CRC_DSB (Bitfield-Mask: 0x01)

Definition at line 2966 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_CRC_DSB_Pos

#define BLE_BLE_RWBLECNTL_REG_CRC_DSB_Pos   (17UL)

BLE BLE_RWBLECNTL_REG: CRC_DSB (Bit 17)

Definition at line 2965 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_CRYPT_DSB_Msk

#define BLE_BLE_RWBLECNTL_REG_CRYPT_DSB_Msk   (0x80000UL)

BLE BLE_RWBLECNTL_REG: CRYPT_DSB (Bitfield-Mask: 0x01)

Definition at line 2970 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_CRYPT_DSB_Pos

#define BLE_BLE_RWBLECNTL_REG_CRYPT_DSB_Pos   (19UL)

BLE BLE_RWBLECNTL_REG: CRYPT_DSB (Bit 19)

Definition at line 2969 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_HOP_REMAP_DSB_Msk

#define BLE_BLE_RWBLECNTL_REG_HOP_REMAP_DSB_Msk   (0x10000UL)

BLE BLE_RWBLECNTL_REG: HOP_REMAP_DSB (Bitfield-Mask: 0x01)

Definition at line 2964 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_HOP_REMAP_DSB_Pos

#define BLE_BLE_RWBLECNTL_REG_HOP_REMAP_DSB_Pos   (16UL)

BLE BLE_RWBLECNTL_REG: HOP_REMAP_DSB (Bit 16)

Definition at line 2963 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_MASTER_SOFT_RST_Msk

#define BLE_BLE_RWBLECNTL_REG_MASTER_SOFT_RST_Msk   (0x80000000UL)

BLE BLE_RWBLECNTL_REG: MASTER_SOFT_RST (Bitfield-Mask: 0x01)

Definition at line 2990 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_MASTER_SOFT_RST_Pos

#define BLE_BLE_RWBLECNTL_REG_MASTER_SOFT_RST_Pos   (31UL)

BLE BLE_RWBLECNTL_REG: MASTER_SOFT_RST (Bit 31)

Definition at line 2989 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_MASTER_TGSOFT_RST_Msk

#define BLE_BLE_RWBLECNTL_REG_MASTER_TGSOFT_RST_Msk   (0x40000000UL)

BLE BLE_RWBLECNTL_REG: MASTER_TGSOFT_RST (Bitfield-Mask: 0x01)

Definition at line 2988 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_MASTER_TGSOFT_RST_Pos

#define BLE_BLE_RWBLECNTL_REG_MASTER_TGSOFT_RST_Pos   (30UL)

BLE BLE_RWBLECNTL_REG: MASTER_TGSOFT_RST (Bit 30)

Definition at line 2987 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_MD_DSB_Msk

#define BLE_BLE_RWBLECNTL_REG_MD_DSB_Msk   (0x400000UL)

BLE BLE_RWBLECNTL_REG: MD_DSB (Bitfield-Mask: 0x01)

Definition at line 2976 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_MD_DSB_Pos

#define BLE_BLE_RWBLECNTL_REG_MD_DSB_Pos   (22UL)

BLE BLE_RWBLECNTL_REG: MD_DSB (Bit 22)

Definition at line 2975 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_NESN_DSB_Msk

#define BLE_BLE_RWBLECNTL_REG_NESN_DSB_Msk   (0x100000UL)

BLE BLE_RWBLECNTL_REG: NESN_DSB (Bitfield-Mask: 0x01)

Definition at line 2972 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_NESN_DSB_Pos

#define BLE_BLE_RWBLECNTL_REG_NESN_DSB_Pos   (20UL)

BLE BLE_RWBLECNTL_REG: NESN_DSB (Bit 20)

Definition at line 2971 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_REG_SOFT_RST_Msk

#define BLE_BLE_RWBLECNTL_REG_REG_SOFT_RST_Msk   (0x20000000UL)

BLE BLE_RWBLECNTL_REG: REG_SOFT_RST (Bitfield-Mask: 0x01)

Definition at line 2986 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_REG_SOFT_RST_Pos

#define BLE_BLE_RWBLECNTL_REG_REG_SOFT_RST_Pos   (29UL)

BLE BLE_RWBLECNTL_REG: REG_SOFT_RST (Bit 29)

Definition at line 2985 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_RFTEST_ABORT_Msk

#define BLE_BLE_RWBLECNTL_REG_RFTEST_ABORT_Msk   (0x4000000UL)

BLE BLE_RWBLECNTL_REG: RFTEST_ABORT (Bitfield-Mask: 0x01)

Definition at line 2982 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_RFTEST_ABORT_Pos

#define BLE_BLE_RWBLECNTL_REG_RFTEST_ABORT_Pos   (26UL)

BLE BLE_RWBLECNTL_REG: RFTEST_ABORT (Bit 26)

Definition at line 2981 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_RWBLE_EN_Msk

#define BLE_BLE_RWBLECNTL_REG_RWBLE_EN_Msk   (0x100UL)

BLE BLE_RWBLECNTL_REG: RWBLE_EN (Bitfield-Mask: 0x01)

Definition at line 2958 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_RWBLE_EN_Pos

#define BLE_BLE_RWBLECNTL_REG_RWBLE_EN_Pos   (8UL)

BLE BLE_RWBLECNTL_REG: RWBLE_EN (Bit 8)

Definition at line 2957 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_RXWINSZDEF_Msk

#define BLE_BLE_RWBLECNTL_REG_RXWINSZDEF_Msk   (0xf0UL)

BLE BLE_RWBLECNTL_REG: RXWINSZDEF (Bitfield-Mask: 0x0f)

Definition at line 2956 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_RXWINSZDEF_Pos

#define BLE_BLE_RWBLECNTL_REG_RXWINSZDEF_Pos   (4UL)

BLE BLE_RWBLECNTL_REG: RXWINSZDEF (Bit 4)

Definition at line 2955 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_SCAN_ABORT_Msk

#define BLE_BLE_RWBLECNTL_REG_SCAN_ABORT_Msk   (0x1000000UL)

BLE BLE_RWBLECNTL_REG: SCAN_ABORT (Bitfield-Mask: 0x01)

Definition at line 2978 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_SCAN_ABORT_Pos

#define BLE_BLE_RWBLECNTL_REG_SCAN_ABORT_Pos   (24UL)

BLE BLE_RWBLECNTL_REG: SCAN_ABORT (Bit 24)

Definition at line 2977 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_SN_DSB_Msk

#define BLE_BLE_RWBLECNTL_REG_SN_DSB_Msk   (0x200000UL)

BLE BLE_RWBLECNTL_REG: SN_DSB (Bitfield-Mask: 0x01)

Definition at line 2974 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_SN_DSB_Pos

#define BLE_BLE_RWBLECNTL_REG_SN_DSB_Pos   (21UL)

BLE BLE_RWBLECNTL_REG: SN_DSB (Bit 21)

Definition at line 2973 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_SWINT_REQ_Msk

#define BLE_BLE_RWBLECNTL_REG_SWINT_REQ_Msk   (0x10000000UL)

BLE BLE_RWBLECNTL_REG: SWINT_REQ (Bitfield-Mask: 0x01)

Definition at line 2984 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_SWINT_REQ_Pos

#define BLE_BLE_RWBLECNTL_REG_SWINT_REQ_Pos   (28UL)

BLE BLE_RWBLECNTL_REG: SWINT_REQ (Bit 28)

Definition at line 2983 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_SYNCERR_Msk

#define BLE_BLE_RWBLECNTL_REG_SYNCERR_Msk   (0x7UL)

BLE BLE_RWBLECNTL_REG: SYNCERR (Bitfield-Mask: 0x07)

Definition at line 2954 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_SYNCERR_Pos

#define BLE_BLE_RWBLECNTL_REG_SYNCERR_Pos   (0UL)

BLE BLE_RWBLECNTL_REG: SYNCERR (Bit 0)

Definition at line 2953 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_WHIT_DSB_Msk

#define BLE_BLE_RWBLECNTL_REG_WHIT_DSB_Msk   (0x40000UL)

BLE BLE_RWBLECNTL_REG: WHIT_DSB (Bitfield-Mask: 0x01)

Definition at line 2968 of file DA14680BA.h.

◆ BLE_BLE_RWBLECNTL_REG_WHIT_DSB_Pos

#define BLE_BLE_RWBLECNTL_REG_WHIT_DSB_Pos   (18UL)

BLE BLE_RWBLECNTL_REG: WHIT_DSB (Bit 18)

Definition at line 2967 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_ADD_WIDTH_Msk

#define BLE_BLE_RWBLECONF_REG_ADD_WIDTH_Msk   (0x3f000000UL)

BLE BLE_RWBLECONF_REG: ADD_WIDTH (Bitfield-Mask: 0x3f)

Definition at line 3022 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_ADD_WIDTH_Pos

#define BLE_BLE_RWBLECONF_REG_ADD_WIDTH_Pos   (24UL)

BLE BLE_RWBLECONF_REG: ADD_WIDTH (Bit 24)

Definition at line 3021 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_BUSWIDTH_Msk

#define BLE_BLE_RWBLECONF_REG_BUSWIDTH_Msk   (0x1UL)

BLE BLE_RWBLECONF_REG: BUSWIDTH (Bitfield-Mask: 0x01)

Definition at line 3004 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_BUSWIDTH_Pos

#define BLE_BLE_RWBLECONF_REG_BUSWIDTH_Pos   (0UL)

BLE BLE_RWBLECONF_REG: BUSWIDTH (Bit 0)

Definition at line 3003 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_CLK_SEL_Msk

#define BLE_BLE_RWBLECONF_REG_CLK_SEL_Msk   (0x3f00UL)

BLE BLE_RWBLECONF_REG: CLK_SEL (Bitfield-Mask: 0x3f)

Definition at line 3018 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_CLK_SEL_Pos

#define BLE_BLE_RWBLECONF_REG_CLK_SEL_Pos   (8UL)

BLE BLE_RWBLECONF_REG: CLK_SEL (Bit 8)

Definition at line 3017 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_COEX_Msk

#define BLE_BLE_RWBLECONF_REG_COEX_Msk   (0x8UL)

BLE BLE_RWBLECONF_REG: COEX (Bitfield-Mask: 0x01)

Definition at line 3010 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_COEX_Pos

#define BLE_BLE_RWBLECONF_REG_COEX_Pos   (3UL)

BLE BLE_RWBLECONF_REG: COEX (Bit 3)

Definition at line 3009 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_DECIPHER_Msk

#define BLE_BLE_RWBLECONF_REG_DECIPHER_Msk   (0x40UL)

BLE BLE_RWBLECONF_REG: DECIPHER (Bitfield-Mask: 0x01)

Definition at line 3016 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_DECIPHER_Pos

#define BLE_BLE_RWBLECONF_REG_DECIPHER_Pos   (6UL)

BLE BLE_RWBLECONF_REG: DECIPHER (Bit 6)

Definition at line 3015 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_DMMODE_Msk

#define BLE_BLE_RWBLECONF_REG_DMMODE_Msk   (0x20UL)

BLE BLE_RWBLECONF_REG: DMMODE (Bitfield-Mask: 0x01)

Definition at line 3014 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_DMMODE_Pos

#define BLE_BLE_RWBLECONF_REG_DMMODE_Pos   (5UL)

BLE BLE_RWBLECONF_REG: DMMODE (Bit 5)

Definition at line 3013 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_INTMODE_Msk

#define BLE_BLE_RWBLECONF_REG_INTMODE_Msk   (0x10UL)

BLE BLE_RWBLECONF_REG: INTMODE (Bitfield-Mask: 0x01)

Definition at line 3012 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_INTMODE_Pos

#define BLE_BLE_RWBLECONF_REG_INTMODE_Pos   (4UL)

BLE BLE_RWBLECONF_REG: INTMODE (Bit 4)

Definition at line 3011 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_RFIF_Msk

#define BLE_BLE_RWBLECONF_REG_RFIF_Msk   (0x7f0000UL)

BLE BLE_RWBLECONF_REG: RFIF (Bitfield-Mask: 0x7f)

Definition at line 3020 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_RFIF_Pos

#define BLE_BLE_RWBLECONF_REG_RFIF_Pos   (16UL)

BLE BLE_RWBLECONF_REG: RFIF (Bit 16)

Definition at line 3019 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_USECRYPT_Msk

#define BLE_BLE_RWBLECONF_REG_USECRYPT_Msk   (0x2UL)

BLE BLE_RWBLECONF_REG: USECRYPT (Bitfield-Mask: 0x01)

Definition at line 3006 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_USECRYPT_Pos

#define BLE_BLE_RWBLECONF_REG_USECRYPT_Pos   (1UL)

BLE BLE_RWBLECONF_REG: USECRYPT (Bit 1)

Definition at line 3005 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_USEDBG_Msk

#define BLE_BLE_RWBLECONF_REG_USEDBG_Msk   (0x4UL)

BLE BLE_RWBLECONF_REG: USEDBG (Bitfield-Mask: 0x01)

Definition at line 3008 of file DA14680BA.h.

◆ BLE_BLE_RWBLECONF_REG_USEDBG_Pos

#define BLE_BLE_RWBLECONF_REG_USEDBG_Pos   (2UL)

BLE BLE_RWBLECONF_REG: USEDBG (Bit 2)

Definition at line 3007 of file DA14680BA.h.

◆ BLE_BLE_RXMICVAL_REG_RXMICVAL_Msk

#define BLE_BLE_RXMICVAL_REG_RXMICVAL_Msk   (0xffffffffUL)

BLE BLE_RXMICVAL_REG: RXMICVAL (Bitfield-Mask: 0xffffffff)

Definition at line 3336 of file DA14680BA.h.

◆ BLE_BLE_RXMICVAL_REG_RXMICVAL_Pos

#define BLE_BLE_RXMICVAL_REG_RXMICVAL_Pos   (0UL)

BLE BLE_RXMICVAL_REG: RXMICVAL (Bit 0)

Definition at line 3335 of file DA14680BA.h.

◆ BLE_BLE_SAMPLECLK_REG_SAMP_Msk

#define BLE_BLE_SAMPLECLK_REG_SAMP_Msk   (0x1UL)

BLE BLE_SAMPLECLK_REG: SAMP (Bitfield-Mask: 0x01)

Definition at line 3382 of file DA14680BA.h.

◆ BLE_BLE_SAMPLECLK_REG_SAMP_Pos

#define BLE_BLE_SAMPLECLK_REG_SAMP_Pos   (0UL)

BLE BLE_SAMPLECLK_REG: SAMP (Bit 0)

Definition at line 3381 of file DA14680BA.h.

◆ BLE_BLE_SWPROFILING_REG_SWPROFVAL_Msk

#define BLE_BLE_SWPROFILING_REG_SWPROFVAL_Msk   (0xffffffffUL)

BLE BLE_SWPROFILING_REG: SWPROFVAL (Bitfield-Mask: 0xffffffff)

Definition at line 3256 of file DA14680BA.h.

◆ BLE_BLE_SWPROFILING_REG_SWPROFVAL_Pos

#define BLE_BLE_SWPROFILING_REG_SWPROFVAL_Pos   (0UL)

BLE BLE_SWPROFILING_REG: SWPROFVAL (Bit 0)

Definition at line 3255 of file DA14680BA.h.

◆ BLE_BLE_TIMGENCNTL_REG_APFM_EN_Msk

#define BLE_BLE_TIMGENCNTL_REG_APFM_EN_Msk   (0x80000000UL)

BLE BLE_TIMGENCNTL_REG: APFM_EN (Bitfield-Mask: 0x01)

Definition at line 3370 of file DA14680BA.h.

◆ BLE_BLE_TIMGENCNTL_REG_APFM_EN_Pos

#define BLE_BLE_TIMGENCNTL_REG_APFM_EN_Pos   (31UL)

BLE BLE_TIMGENCNTL_REG: APFM_EN (Bit 31)

Definition at line 3369 of file DA14680BA.h.

◆ BLE_BLE_TIMGENCNTL_REG_PREFETCH_TIME_Msk

#define BLE_BLE_TIMGENCNTL_REG_PREFETCH_TIME_Msk   (0x1ffUL)

BLE BLE_TIMGENCNTL_REG: PREFETCH_TIME (Bitfield-Mask: 0x1ff)

Definition at line 3366 of file DA14680BA.h.

◆ BLE_BLE_TIMGENCNTL_REG_PREFETCH_TIME_Pos

#define BLE_BLE_TIMGENCNTL_REG_PREFETCH_TIME_Pos   (0UL)

BLE BLE_TIMGENCNTL_REG: PREFETCH_TIME (Bit 0)

Definition at line 3365 of file DA14680BA.h.

◆ BLE_BLE_TIMGENCNTL_REG_PREFETCHABORT_TIME_Msk

#define BLE_BLE_TIMGENCNTL_REG_PREFETCHABORT_TIME_Msk   (0x3ff0000UL)

BLE BLE_TIMGENCNTL_REG: PREFETCHABORT_TIME (Bitfield-Mask: 0x3ff)

Definition at line 3368 of file DA14680BA.h.

◆ BLE_BLE_TIMGENCNTL_REG_PREFETCHABORT_TIME_Pos

#define BLE_BLE_TIMGENCNTL_REG_PREFETCHABORT_TIME_Pos   (16UL)

BLE BLE_TIMGENCNTL_REG: PREFETCHABORT_TIME (Bit 16)

Definition at line 3367 of file DA14680BA.h.

◆ BLE_BLE_TXMICVAL_REG_TXMICVAL_Msk

#define BLE_BLE_TXMICVAL_REG_TXMICVAL_Msk   (0xffffffffUL)

BLE BLE_TXMICVAL_REG: TXMICVAL (Bitfield-Mask: 0xffffffff)

Definition at line 3332 of file DA14680BA.h.

◆ BLE_BLE_TXMICVAL_REG_TXMICVAL_Pos

#define BLE_BLE_TXMICVAL_REG_TXMICVAL_Pos   (0UL)

BLE BLE_TXMICVAL_REG: TXMICVAL (Bit 0)

Definition at line 3331 of file DA14680BA.h.

◆ BLE_BLE_VERSION_REG_BUILD_Msk

#define BLE_BLE_VERSION_REG_BUILD_Msk   (0xffUL)

BLE BLE_VERSION_REG: BUILD (Bitfield-Mask: 0xff)

Definition at line 2994 of file DA14680BA.h.

◆ BLE_BLE_VERSION_REG_BUILD_Pos

#define BLE_BLE_VERSION_REG_BUILD_Pos   (0UL)

BLE BLE_VERSION_REG: BUILD (Bit 0)

Definition at line 2993 of file DA14680BA.h.

◆ BLE_BLE_VERSION_REG_REL_Msk

#define BLE_BLE_VERSION_REG_REL_Msk   (0xff0000UL)

BLE BLE_VERSION_REG: REL (Bitfield-Mask: 0xff)

Definition at line 2998 of file DA14680BA.h.

◆ BLE_BLE_VERSION_REG_REL_Pos

#define BLE_BLE_VERSION_REG_REL_Pos   (16UL)

BLE BLE_VERSION_REG: REL (Bit 16)

Definition at line 2997 of file DA14680BA.h.

◆ BLE_BLE_VERSION_REG_TYP_Msk

#define BLE_BLE_VERSION_REG_TYP_Msk   (0xff000000UL)

BLE BLE_VERSION_REG: TYP (Bitfield-Mask: 0xff)

Definition at line 3000 of file DA14680BA.h.

◆ BLE_BLE_VERSION_REG_TYP_Pos

#define BLE_BLE_VERSION_REG_TYP_Pos   (24UL)

BLE BLE_VERSION_REG: TYP (Bit 24)

Definition at line 2999 of file DA14680BA.h.

◆ BLE_BLE_VERSION_REG_UPG_Msk

#define BLE_BLE_VERSION_REG_UPG_Msk   (0xff00UL)

BLE BLE_VERSION_REG: UPG (Bitfield-Mask: 0xff)

Definition at line 2996 of file DA14680BA.h.

◆ BLE_BLE_VERSION_REG_UPG_Pos

#define BLE_BLE_VERSION_REG_UPG_Pos   (8UL)

BLE BLE_VERSION_REG: UPG (Bit 8)

Definition at line 2995 of file DA14680BA.h.

◆ BLE_BLE_WLNBDEV_REG_NBPRIVDEV_Msk

#define BLE_BLE_WLNBDEV_REG_NBPRIVDEV_Msk   (0xff00UL)

BLE BLE_WLNBDEV_REG: NBPRIVDEV (Bitfield-Mask: 0xff)

Definition at line 3302 of file DA14680BA.h.

◆ BLE_BLE_WLNBDEV_REG_NBPRIVDEV_Pos

#define BLE_BLE_WLNBDEV_REG_NBPRIVDEV_Pos   (8UL)

BLE BLE_WLNBDEV_REG: NBPRIVDEV (Bit 8)

Definition at line 3301 of file DA14680BA.h.

◆ BLE_BLE_WLNBDEV_REG_NBPUBDEV_Msk

#define BLE_BLE_WLNBDEV_REG_NBPUBDEV_Msk   (0xffUL)

BLE BLE_WLNBDEV_REG: NBPUBDEV (Bitfield-Mask: 0xff)

Definition at line 3300 of file DA14680BA.h.

◆ BLE_BLE_WLNBDEV_REG_NBPUBDEV_Pos

#define BLE_BLE_WLNBDEV_REG_NBPUBDEV_Pos   (0UL)

BLE BLE_WLNBDEV_REG: NBPUBDEV (Bit 0)

Definition at line 3299 of file DA14680BA.h.

◆ BLE_BLE_WLPRIVADDPTR_REG_WLPRIVADDPTR_Msk

#define BLE_BLE_WLPRIVADDPTR_REG_WLPRIVADDPTR_Msk   (0xffffUL)

BLE BLE_WLPRIVADDPTR_REG: WLPRIVADDPTR (Bitfield-Mask: 0xffff)

Definition at line 3296 of file DA14680BA.h.

◆ BLE_BLE_WLPRIVADDPTR_REG_WLPRIVADDPTR_Pos

#define BLE_BLE_WLPRIVADDPTR_REG_WLPRIVADDPTR_Pos   (0UL)

BLE BLE_WLPRIVADDPTR_REG: WLPRIVADDPTR (Bit 0)

Definition at line 3295 of file DA14680BA.h.

◆ BLE_BLE_WLPUBADDPTR_REG_WLPUBADDPTR_Msk

#define BLE_BLE_WLPUBADDPTR_REG_WLPUBADDPTR_Msk   (0xffffUL)

BLE BLE_WLPUBADDPTR_REG: WLPUBADDPTR (Bitfield-Mask: 0xffff)

Definition at line 3292 of file DA14680BA.h.

◆ BLE_BLE_WLPUBADDPTR_REG_WLPUBADDPTR_Pos

#define BLE_BLE_WLPUBADDPTR_REG_WLPUBADDPTR_Pos   (0UL)

BLE BLE_WLPUBADDPTR_REG: WLPUBADDPTR (Bit 0)

Definition at line 3291 of file DA14680BA.h.

◆ CACHE

#define CACHE   ((CACHE_Type *) CACHE_BASE)

Definition at line 12077 of file DA14680BA.h.

◆ CACHE_BASE

#define CACHE_BASE   0x400C3000UL

Definition at line 12032 of file DA14680BA.h.

◆ CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Msk

#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Msk   (0x3UL)

CACHE CACHE_ASSOCCFG_REG: CACHE_ASSOC (Bitfield-Mask: 0x03)

Definition at line 3540 of file DA14680BA.h.

◆ CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Pos

#define CACHE_CACHE_ASSOCCFG_REG_CACHE_ASSOC_Pos   (0UL)

CACHE CACHE_ASSOCCFG_REG: CACHE_ASSOC (Bit 0)

Definition at line 3539 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Msk

#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Msk   (0x1UL)

CACHE CACHE_CTRL1_REG: CACHE_FLUSH (Bitfield-Mask: 0x01)

Definition at line 3530 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Pos

#define CACHE_CACHE_CTRL1_REG_CACHE_FLUSH_Pos   (0UL)

CACHE CACHE_CTRL1_REG: CACHE_FLUSH (Bit 0)

Definition at line 3529 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL1_REG_CACHE_RES1_Msk

#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Msk   (0x2UL)

CACHE CACHE_CTRL1_REG: CACHE_RES1 (Bitfield-Mask: 0x01)

Definition at line 3532 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL1_REG_CACHE_RES1_Pos

#define CACHE_CACHE_CTRL1_REG_CACHE_RES1_Pos   (1UL)

CACHE CACHE_CTRL1_REG: CACHE_RES1 (Bit 1)

Definition at line 3531 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk

#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk   (0x400UL)

CACHE CACHE_CTRL2_REG: CACHE_CGEN (Bitfield-Mask: 0x01)

Definition at line 3548 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos

#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos   (10UL)

CACHE CACHE_CTRL2_REG: CACHE_CGEN (Bit 10)

Definition at line 3547 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk

#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk   (0x1ffUL)

CACHE CACHE_CTRL2_REG: CACHE_LEN (Bitfield-Mask: 0x1ff)

Definition at line 3544 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos

#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos   (0UL)

CACHE CACHE_CTRL2_REG: CACHE_LEN (Bit 0)

Definition at line 3543 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL2_REG_CACHE_WEN_Msk

#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Msk   (0x200UL)

CACHE CACHE_CTRL2_REG: CACHE_WEN (Bitfield-Mask: 0x01)

Definition at line 3546 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL2_REG_CACHE_WEN_Pos

#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Pos   (9UL)

CACHE CACHE_CTRL2_REG: CACHE_WEN (Bit 9)

Definition at line 3545 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_OTP_CACHED_Msk

#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_OTP_CACHED_Msk   (0x800UL)

CACHE CACHE_CTRL2_REG: ENABLE_ALSO_OTP_CACHED (Bitfield-Mask: 0x01)

Definition at line 3550 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_OTP_CACHED_Pos

#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_OTP_CACHED_Pos   (11UL)

CACHE CACHE_CTRL2_REG: ENABLE_ALSO_OTP_CACHED (Bit 11)

Definition at line 3549 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_QSPIFLASH_CACHED_Msk

#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_QSPIFLASH_CACHED_Msk   (0x1000UL)

CACHE CACHE_CTRL2_REG: ENABLE_ALSO_QSPIFLASH_CACHED (Bitfield-Mask: 0x01)

Definition at line 3552 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_QSPIFLASH_CACHED_Pos

#define CACHE_CACHE_CTRL2_REG_ENABLE_ALSO_QSPIFLASH_CACHED_Pos   (12UL)

CACHE CACHE_CTRL2_REG: ENABLE_ALSO_QSPIFLASH_CACHED (Bit 12)

Definition at line 3551 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL3_REG_CACHE_ASSOCIATIVITY_RESET_VALUE_Msk

#define CACHE_CACHE_CTRL3_REG_CACHE_ASSOCIATIVITY_RESET_VALUE_Msk   (0x3UL)

CACHE CACHE_CTRL3_REG: CACHE_ASSOCIATIVITY_RESET_VALUE (Bitfield-Mask: 0x03)

Definition at line 3556 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL3_REG_CACHE_ASSOCIATIVITY_RESET_VALUE_Pos

#define CACHE_CACHE_CTRL3_REG_CACHE_ASSOCIATIVITY_RESET_VALUE_Pos   (0UL)

CACHE CACHE_CTRL3_REG: CACHE_ASSOCIATIVITY_RESET_VALUE (Bit 0)

Definition at line 3555 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL3_REG_CACHE_CONTROLLER_RESET_Msk

#define CACHE_CACHE_CTRL3_REG_CACHE_CONTROLLER_RESET_Msk   (0x80UL)

CACHE CACHE_CTRL3_REG: CACHE_CONTROLLER_RESET (Bitfield-Mask: 0x01)

Definition at line 3562 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL3_REG_CACHE_CONTROLLER_RESET_Pos

#define CACHE_CACHE_CTRL3_REG_CACHE_CONTROLLER_RESET_Pos   (7UL)

CACHE CACHE_CTRL3_REG: CACHE_CONTROLLER_RESET (Bit 7)

Definition at line 3561 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL3_REG_CACHE_LINE_SIZE_RESET_VALUE_Msk

#define CACHE_CACHE_CTRL3_REG_CACHE_LINE_SIZE_RESET_VALUE_Msk   (0xcUL)

CACHE CACHE_CTRL3_REG: CACHE_LINE_SIZE_RESET_VALUE (Bitfield-Mask: 0x03)

Definition at line 3558 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL3_REG_CACHE_LINE_SIZE_RESET_VALUE_Pos

#define CACHE_CACHE_CTRL3_REG_CACHE_LINE_SIZE_RESET_VALUE_Pos   (2UL)

CACHE CACHE_CTRL3_REG: CACHE_LINE_SIZE_RESET_VALUE (Bit 2)

Definition at line 3557 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL3_REG_CACHE_RAM_SIZE_RESET_VALUE_Msk

#define CACHE_CACHE_CTRL3_REG_CACHE_RAM_SIZE_RESET_VALUE_Msk   (0x70UL)

CACHE CACHE_CTRL3_REG: CACHE_RAM_SIZE_RESET_VALUE (Bitfield-Mask: 0x07)

Definition at line 3560 of file DA14680BA.h.

◆ CACHE_CACHE_CTRL3_REG_CACHE_RAM_SIZE_RESET_VALUE_Pos

#define CACHE_CACHE_CTRL3_REG_CACHE_RAM_SIZE_RESET_VALUE_Pos   (4UL)

CACHE CACHE_CTRL3_REG: CACHE_RAM_SIZE_RESET_VALUE (Bit 4)

Definition at line 3559 of file DA14680BA.h.

◆ CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Msk

#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Msk   (0x3UL)

CACHE CACHE_LNSIZECFG_REG: CACHE_LINE (Bitfield-Mask: 0x03)

Definition at line 3536 of file DA14680BA.h.

◆ CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Pos

#define CACHE_CACHE_LNSIZECFG_REG_CACHE_LINE_Pos   (0UL)

CACHE CACHE_LNSIZECFG_REG: CACHE_LINE (Bit 0)

Definition at line 3535 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk   (0x2UL)

CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_MASK (Bitfield-Mask: 0x01)

Definition at line 3576 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos   (1UL)

CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_MASK (Bit 1)

Definition at line 3575 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_THRES_STATUS_Msk

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_THRES_STATUS_Msk   (0x8UL)

CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_THRES_STATUS (Bitfield-Mask: 0x01)

Definition at line 3580 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_THRES_STATUS_Pos

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_THRES_STATUS_Pos   (3UL)

CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_THRES_STATUS (Bit 3)

Definition at line 3579 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk   (0x4UL)

CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_TINT_STATUS (Bitfield-Mask: 0x01)

Definition at line 3578 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos   (2UL)

CACHE CACHE_MRM_CTRL_REG: MRM_IRQ_TINT_STATUS (Bit 2)

Definition at line 3577 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_START_Msk

#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Msk   (0x1UL)

CACHE CACHE_MRM_CTRL_REG: MRM_START (Bitfield-Mask: 0x01)

Definition at line 3574 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_START_Pos

#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Pos   (0UL)

CACHE CACHE_MRM_CTRL_REG: MRM_START (Bit 0)

Definition at line 3573 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Msk

#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Msk   (0x7ffffUL)

CACHE CACHE_MRM_HITS_REG: MRM_HITS (Bitfield-Mask: 0x7ffff)

Definition at line 3566 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Pos

#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Pos   (0UL)

CACHE CACHE_MRM_HITS_REG: MRM_HITS (Bit 0)

Definition at line 3565 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk

#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk   (0x3ffffUL)

CACHE CACHE_MRM_MISSES_REG: MRM_MISSES (Bitfield-Mask: 0x3ffff)

Definition at line 3570 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos

#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos   (0UL)

CACHE CACHE_MRM_MISSES_REG: MRM_MISSES (Bit 0)

Definition at line 3569 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_THRES_REG_MRM_THRES_Msk

#define CACHE_CACHE_MRM_THRES_REG_MRM_THRES_Msk   (0x3ffffUL)

CACHE CACHE_MRM_THRES_REG: MRM_THRES (Bitfield-Mask: 0x3ffff)

Definition at line 3588 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_THRES_REG_MRM_THRES_Pos

#define CACHE_CACHE_MRM_THRES_REG_MRM_THRES_Pos   (0UL)

CACHE CACHE_MRM_THRES_REG: MRM_THRES (Bit 0)

Definition at line 3587 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk

#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk   (0x3ffffUL)

CACHE CACHE_MRM_TINT_REG: MRM_TINT (Bitfield-Mask: 0x3ffff)

Definition at line 3584 of file DA14680BA.h.

◆ CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Pos

#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Pos   (0UL)

CACHE CACHE_MRM_TINT_REG: MRM_TINT (Bit 0)

Definition at line 3583 of file DA14680BA.h.

◆ CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Msk

#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Msk   (0x1UL)

CACHE SWD_RESET_REG: SWD_HW_RESET_REQ (Bitfield-Mask: 0x01)

Definition at line 3592 of file DA14680BA.h.

◆ CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Pos

#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Pos   (0UL)

CACHE SWD_RESET_REG: SWD_HW_RESET_REQ (Bit 0)

Definition at line 3591 of file DA14680BA.h.

◆ CHIP_VERSION

#define CHIP_VERSION   ((CHIP_VERSION_Type *) CHIP_VERSION_BASE)

Definition at line 12078 of file DA14680BA.h.

◆ CHIP_VERSION_BASE

#define CHIP_VERSION_BASE   0x50003200UL

Definition at line 12033 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_CONFIG1_REG_CHIP_CONFIG1_Msk

#define CHIP_VERSION_CHIP_CONFIG1_REG_CHIP_CONFIG1_Msk   (0xffUL)

CHIP_VERSION CHIP_CONFIG1_REG: CHIP_CONFIG1 (Bitfield-Mask: 0xff)

Definition at line 3622 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_CONFIG1_REG_CHIP_CONFIG1_Pos

#define CHIP_VERSION_CHIP_CONFIG1_REG_CHIP_CONFIG1_Pos   (0UL)

CHIP_VERSION CHIP_CONFIG1_REG: CHIP_CONFIG1 (Bit 0)

Definition at line 3621 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_CONFIG2_REG_CHIP_CONFIG2_Msk

#define CHIP_VERSION_CHIP_CONFIG2_REG_CHIP_CONFIG2_Msk   (0xffUL)

CHIP_VERSION CHIP_CONFIG2_REG: CHIP_CONFIG2 (Bitfield-Mask: 0xff)

Definition at line 3626 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_CONFIG2_REG_CHIP_CONFIG2_Pos

#define CHIP_VERSION_CHIP_CONFIG2_REG_CHIP_CONFIG2_Pos   (0UL)

CHIP_VERSION CHIP_CONFIG2_REG: CHIP_CONFIG2 (Bit 0)

Definition at line 3625 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_CONFIG3_REG_CHIP_CONFIG3_Msk

#define CHIP_VERSION_CHIP_CONFIG3_REG_CHIP_CONFIG3_Msk   (0xffUL)

CHIP_VERSION CHIP_CONFIG3_REG: CHIP_CONFIG3 (Bitfield-Mask: 0xff)

Definition at line 3630 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_CONFIG3_REG_CHIP_CONFIG3_Pos

#define CHIP_VERSION_CHIP_CONFIG3_REG_CHIP_CONFIG3_Pos   (0UL)

CHIP_VERSION CHIP_CONFIG3_REG: CHIP_CONFIG3 (Bit 0)

Definition at line 3629 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk

#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk   (0xffUL)

CHIP_VERSION CHIP_ID1_REG: CHIP_ID1 (Bitfield-Mask: 0xff)

Definition at line 3602 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Pos

#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Pos   (0UL)

CHIP_VERSION CHIP_ID1_REG: CHIP_ID1 (Bit 0)

Definition at line 3601 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk

#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk   (0xffUL)

CHIP_VERSION CHIP_ID2_REG: CHIP_ID2 (Bitfield-Mask: 0xff)

Definition at line 3606 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Pos

#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Pos   (0UL)

CHIP_VERSION CHIP_ID2_REG: CHIP_ID2 (Bit 0)

Definition at line 3605 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk

#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk   (0xffUL)

CHIP_VERSION CHIP_ID3_REG: CHIP_ID3 (Bitfield-Mask: 0xff)

Definition at line 3610 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Pos

#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Pos   (0UL)

CHIP_VERSION CHIP_ID3_REG: CHIP_ID3 (Bit 0)

Definition at line 3609 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_REVISION_REG_REVISION_ID_Msk

#define CHIP_VERSION_CHIP_REVISION_REG_REVISION_ID_Msk   (0xffUL)

CHIP_VERSION CHIP_REVISION_REG: REVISION_ID (Bitfield-Mask: 0xff)

Definition at line 3618 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_REVISION_REG_REVISION_ID_Pos

#define CHIP_VERSION_CHIP_REVISION_REG_REVISION_ID_Pos   (0UL)

CHIP_VERSION CHIP_REVISION_REG: REVISION_ID (Bit 0)

Definition at line 3617 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Msk

#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Msk   (0xfUL)

CHIP_VERSION CHIP_SWC_REG: CHIP_SWC (Bitfield-Mask: 0x0f)

Definition at line 3614 of file DA14680BA.h.

◆ CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Pos

#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Pos   (0UL)

CHIP_VERSION CHIP_SWC_REG: CHIP_SWC (Bit 0)

Definition at line 3613 of file DA14680BA.h.

◆ COEX

#define COEX   ((COEX_Type *) COEX_BASE)

Definition at line 12079 of file DA14680BA.h.

◆ COEX_BASE

#define COEX_BASE   0x50002F00UL

Definition at line 12034 of file DA14680BA.h.

◆ COEX_COEX_BLE_PTI_REG_COEX_BLE_PTI_Msk

#define COEX_COEX_BLE_PTI_REG_COEX_BLE_PTI_Msk   (0x7UL)

COEX COEX_BLE_PTI_REG: COEX_BLE_PTI (Bitfield-Mask: 0x07)

Definition at line 3736 of file DA14680BA.h.

◆ COEX_COEX_BLE_PTI_REG_COEX_BLE_PTI_Pos

#define COEX_COEX_BLE_PTI_REG_COEX_BLE_PTI_Pos   (0UL)

COEX COEX_BLE_PTI_REG: COEX_BLE_PTI (Bit 0)

Definition at line 3735 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_DECISION_SW_ALL_Msk

#define COEX_COEX_CTRL_REG_DECISION_SW_ALL_Msk   (0x2UL)

COEX COEX_CTRL_REG: DECISION_SW_ALL (Bitfield-Mask: 0x01)

Definition at line 3642 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_DECISION_SW_ALL_Pos

#define COEX_COEX_CTRL_REG_DECISION_SW_ALL_Pos   (1UL)

COEX COEX_CTRL_REG: DECISION_SW_ALL (Bit 1)

Definition at line 3641 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_IGNORE_BLE_Msk

#define COEX_COEX_CTRL_REG_IGNORE_BLE_Msk   (0x8000UL)

COEX COEX_CTRL_REG: IGNORE_BLE (Bitfield-Mask: 0x01)

Definition at line 3666 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_IGNORE_BLE_Pos

#define COEX_COEX_CTRL_REG_IGNORE_BLE_Pos   (15UL)

COEX COEX_CTRL_REG: IGNORE_BLE (Bit 15)

Definition at line 3665 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_IGNORE_EXT_Msk

#define COEX_COEX_CTRL_REG_IGNORE_EXT_Msk   (0x2000UL)

COEX COEX_CTRL_REG: IGNORE_EXT (Bitfield-Mask: 0x01)

Definition at line 3662 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_IGNORE_EXT_Pos

#define COEX_COEX_CTRL_REG_IGNORE_EXT_Pos   (13UL)

COEX COEX_CTRL_REG: IGNORE_EXT (Bit 13)

Definition at line 3661 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_IGNORE_FTDF_Msk

#define COEX_COEX_CTRL_REG_IGNORE_FTDF_Msk   (0x4000UL)

COEX COEX_CTRL_REG: IGNORE_FTDF (Bitfield-Mask: 0x01)

Definition at line 3664 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_IGNORE_FTDF_Pos

#define COEX_COEX_CTRL_REG_IGNORE_FTDF_Pos   (14UL)

COEX COEX_CTRL_REG: IGNORE_FTDF (Bit 14)

Definition at line 3663 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_PRGING_ARBITER_Msk

#define COEX_COEX_CTRL_REG_PRGING_ARBITER_Msk   (0x1UL)

COEX COEX_CTRL_REG: PRGING_ARBITER (Bitfield-Mask: 0x01)

Definition at line 3640 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_PRGING_ARBITER_Pos

#define COEX_COEX_CTRL_REG_PRGING_ARBITER_Pos   (0UL)

COEX COEX_CTRL_REG: PRGING_ARBITER (Bit 0)

Definition at line 3639 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SEL_BLE_PTI_Msk

#define COEX_COEX_CTRL_REG_SEL_BLE_PTI_Msk   (0x200UL)

COEX COEX_CTRL_REG: SEL_BLE_PTI (Bitfield-Mask: 0x01)

Definition at line 3656 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SEL_BLE_PTI_Pos

#define COEX_COEX_CTRL_REG_SEL_BLE_PTI_Pos   (9UL)

COEX COEX_CTRL_REG: SEL_BLE_PTI (Bit 9)

Definition at line 3655 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SEL_BLE_RADIO_BUSY_Msk

#define COEX_COEX_CTRL_REG_SEL_BLE_RADIO_BUSY_Msk   (0x1800UL)

COEX COEX_CTRL_REG: SEL_BLE_RADIO_BUSY (Bitfield-Mask: 0x03)

Definition at line 3660 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SEL_BLE_RADIO_BUSY_Pos

#define COEX_COEX_CTRL_REG_SEL_BLE_RADIO_BUSY_Pos   (11UL)

COEX COEX_CTRL_REG: SEL_BLE_RADIO_BUSY (Bit 11)

Definition at line 3659 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SEL_BLE_WLAN_TX_RX_Msk

#define COEX_COEX_CTRL_REG_SEL_BLE_WLAN_TX_RX_Msk   (0x400UL)

COEX COEX_CTRL_REG: SEL_BLE_WLAN_TX_RX (Bitfield-Mask: 0x01)

Definition at line 3658 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SEL_BLE_WLAN_TX_RX_Pos

#define COEX_COEX_CTRL_REG_SEL_BLE_WLAN_TX_RX_Pos   (10UL)

COEX COEX_CTRL_REG: SEL_BLE_WLAN_TX_RX (Bit 10)

Definition at line 3657 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SEL_COEX_DIAG_Msk

#define COEX_COEX_CTRL_REG_SEL_COEX_DIAG_Msk   (0x60UL)

COEX COEX_CTRL_REG: SEL_COEX_DIAG (Bitfield-Mask: 0x03)

Definition at line 3650 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SEL_COEX_DIAG_Pos

#define COEX_COEX_CTRL_REG_SEL_COEX_DIAG_Pos   (5UL)

COEX COEX_CTRL_REG: SEL_COEX_DIAG (Bit 5)

Definition at line 3649 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SEL_FTDF_CCA_Msk

#define COEX_COEX_CTRL_REG_SEL_FTDF_CCA_Msk   (0x80UL)

COEX COEX_CTRL_REG: SEL_FTDF_CCA (Bitfield-Mask: 0x01)

Definition at line 3652 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SEL_FTDF_CCA_Pos

#define COEX_COEX_CTRL_REG_SEL_FTDF_CCA_Pos   (7UL)

COEX COEX_CTRL_REG: SEL_FTDF_CCA (Bit 7)

Definition at line 3651 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SEL_FTDF_PTI_Msk

#define COEX_COEX_CTRL_REG_SEL_FTDF_PTI_Msk   (0x100UL)

COEX COEX_CTRL_REG: SEL_FTDF_PTI (Bitfield-Mask: 0x01)

Definition at line 3654 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SEL_FTDF_PTI_Pos

#define COEX_COEX_CTRL_REG_SEL_FTDF_PTI_Pos   (8UL)

COEX COEX_CTRL_REG: SEL_FTDF_PTI (Bit 8)

Definition at line 3653 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SMART_ACT_IMPL_Msk

#define COEX_COEX_CTRL_REG_SMART_ACT_IMPL_Msk   (0x10UL)

COEX COEX_CTRL_REG: SMART_ACT_IMPL (Bitfield-Mask: 0x01)

Definition at line 3648 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_SMART_ACT_IMPL_Pos

#define COEX_COEX_CTRL_REG_SMART_ACT_IMPL_Pos   (4UL)

COEX COEX_CTRL_REG: SMART_ACT_IMPL (Bit 4)

Definition at line 3647 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_TXRX_MON_BLE_ALL_Msk

#define COEX_COEX_CTRL_REG_TXRX_MON_BLE_ALL_Msk   (0x8UL)

COEX COEX_CTRL_REG: TXRX_MON_BLE_ALL (Bitfield-Mask: 0x01)

Definition at line 3646 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_TXRX_MON_BLE_ALL_Pos

#define COEX_COEX_CTRL_REG_TXRX_MON_BLE_ALL_Pos   (3UL)

COEX COEX_CTRL_REG: TXRX_MON_BLE_ALL (Bit 3)

Definition at line 3645 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_TXRX_MON_FTDF_ALL_Msk

#define COEX_COEX_CTRL_REG_TXRX_MON_FTDF_ALL_Msk   (0x4UL)

COEX COEX_CTRL_REG: TXRX_MON_FTDF_ALL (Bitfield-Mask: 0x01)

Definition at line 3644 of file DA14680BA.h.

◆ COEX_COEX_CTRL_REG_TXRX_MON_FTDF_ALL_Pos

#define COEX_COEX_CTRL_REG_TXRX_MON_FTDF_ALL_Pos   (2UL)

COEX COEX_CTRL_REG: TXRX_MON_FTDF_ALL (Bit 2)

Definition at line 3643 of file DA14680BA.h.

◆ COEX_COEX_FTDF_PTI_REG_COEX_FTDF_PTI_Msk

#define COEX_COEX_FTDF_PTI_REG_COEX_FTDF_PTI_Msk   (0x7UL)

COEX COEX_FTDF_PTI_REG: COEX_FTDF_PTI (Bitfield-Mask: 0x07)

Definition at line 3740 of file DA14680BA.h.

◆ COEX_COEX_FTDF_PTI_REG_COEX_FTDF_PTI_Pos

#define COEX_COEX_FTDF_PTI_REG_COEX_FTDF_PTI_Pos   (0UL)

COEX COEX_FTDF_PTI_REG: COEX_FTDF_PTI (Bit 0)

Definition at line 3739 of file DA14680BA.h.

◆ COEX_COEX_INT_MASK_REG_IRQ_DECISION_SW_Msk

#define COEX_COEX_INT_MASK_REG_IRQ_DECISION_SW_Msk   (0x200UL)

COEX COEX_INT_MASK_REG: IRQ_DECISION_SW (Bitfield-Mask: 0x01)

Definition at line 3718 of file DA14680BA.h.

◆ COEX_COEX_INT_MASK_REG_IRQ_DECISION_SW_Pos

#define COEX_COEX_INT_MASK_REG_IRQ_DECISION_SW_Pos   (9UL)

COEX COEX_INT_MASK_REG: IRQ_DECISION_SW (Bit 9)

Definition at line 3717 of file DA14680BA.h.

◆ COEX_COEX_INT_MASK_REG_IRQ_TXRX_MON_Msk

#define COEX_COEX_INT_MASK_REG_IRQ_TXRX_MON_Msk   (0x100UL)

COEX COEX_INT_MASK_REG: IRQ_TXRX_MON (Bitfield-Mask: 0x01)

Definition at line 3716 of file DA14680BA.h.

◆ COEX_COEX_INT_MASK_REG_IRQ_TXRX_MON_Pos

#define COEX_COEX_INT_MASK_REG_IRQ_TXRX_MON_Pos   (8UL)

COEX COEX_INT_MASK_REG: IRQ_TXRX_MON (Bit 8)

Definition at line 3715 of file DA14680BA.h.

◆ COEX_COEX_INT_STAT_REG_IRQ_DECISION_SW_Msk

#define COEX_COEX_INT_STAT_REG_IRQ_DECISION_SW_Msk   (0x200UL)

COEX COEX_INT_STAT_REG: IRQ_DECISION_SW (Bitfield-Mask: 0x01)

Definition at line 3732 of file DA14680BA.h.

◆ COEX_COEX_INT_STAT_REG_IRQ_DECISION_SW_Pos

#define COEX_COEX_INT_STAT_REG_IRQ_DECISION_SW_Pos   (9UL)

COEX COEX_INT_STAT_REG: IRQ_DECISION_SW (Bit 9)

Definition at line 3731 of file DA14680BA.h.

◆ COEX_COEX_INT_STAT_REG_IRQ_TXRX_MON_Msk

#define COEX_COEX_INT_STAT_REG_IRQ_TXRX_MON_Msk   (0x100UL)

COEX COEX_INT_STAT_REG: IRQ_TXRX_MON (Bitfield-Mask: 0x01)

Definition at line 3730 of file DA14680BA.h.

◆ COEX_COEX_INT_STAT_REG_IRQ_TXRX_MON_Pos

#define COEX_COEX_INT_STAT_REG_IRQ_TXRX_MON_Pos   (8UL)

COEX COEX_INT_STAT_REG: IRQ_TXRX_MON (Bit 8)

Definition at line 3729 of file DA14680BA.h.

◆ COEX_COEX_INT_STAT_REG_TXRX_MON_OVWR_Msk

#define COEX_COEX_INT_STAT_REG_TXRX_MON_OVWR_Msk   (0x80UL)

COEX COEX_INT_STAT_REG: TXRX_MON_OVWR (Bitfield-Mask: 0x01)

Definition at line 3728 of file DA14680BA.h.

◆ COEX_COEX_INT_STAT_REG_TXRX_MON_OVWR_Pos

#define COEX_COEX_INT_STAT_REG_TXRX_MON_OVWR_Pos   (7UL)

COEX COEX_INT_STAT_REG: TXRX_MON_OVWR (Bit 7)

Definition at line 3727 of file DA14680BA.h.

◆ COEX_COEX_INT_STAT_REG_TXRX_MON_PASSED_Msk

#define COEX_COEX_INT_STAT_REG_TXRX_MON_PASSED_Msk   (0x40UL)

COEX COEX_INT_STAT_REG: TXRX_MON_PASSED (Bitfield-Mask: 0x01)

Definition at line 3726 of file DA14680BA.h.

◆ COEX_COEX_INT_STAT_REG_TXRX_MON_PASSED_Pos

#define COEX_COEX_INT_STAT_REG_TXRX_MON_PASSED_Pos   (6UL)

COEX COEX_INT_STAT_REG: TXRX_MON_PASSED (Bit 6)

Definition at line 3725 of file DA14680BA.h.

◆ COEX_COEX_INT_STAT_REG_TXRX_MON_PTR_Msk

#define COEX_COEX_INT_STAT_REG_TXRX_MON_PTR_Msk   (0xfUL)

COEX COEX_INT_STAT_REG: TXRX_MON_PTR (Bitfield-Mask: 0x0f)

Definition at line 3722 of file DA14680BA.h.

◆ COEX_COEX_INT_STAT_REG_TXRX_MON_PTR_Pos

#define COEX_COEX_INT_STAT_REG_TXRX_MON_PTR_Pos   (0UL)

COEX COEX_INT_STAT_REG: TXRX_MON_PTR (Bit 0)

Definition at line 3721 of file DA14680BA.h.

◆ COEX_COEX_INT_STAT_REG_TXRX_MON_TX_Msk

#define COEX_COEX_INT_STAT_REG_TXRX_MON_TX_Msk   (0x20UL)

COEX COEX_INT_STAT_REG: TXRX_MON_TX (Bitfield-Mask: 0x01)

Definition at line 3724 of file DA14680BA.h.

◆ COEX_COEX_INT_STAT_REG_TXRX_MON_TX_Pos

#define COEX_COEX_INT_STAT_REG_TXRX_MON_TX_Pos   (5UL)

COEX COEX_INT_STAT_REG: TXRX_MON_TX (Bit 5)

Definition at line 3723 of file DA14680BA.h.

◆ COEX_COEX_PRI10_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI10_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI10_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3800 of file DA14680BA.h.

◆ COEX_COEX_PRI10_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI10_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI10_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3799 of file DA14680BA.h.

◆ COEX_COEX_PRI10_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI10_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI10_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3798 of file DA14680BA.h.

◆ COEX_COEX_PRI10_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI10_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI10_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3797 of file DA14680BA.h.

◆ COEX_COEX_PRI11_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI11_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI11_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3806 of file DA14680BA.h.

◆ COEX_COEX_PRI11_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI11_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI11_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3805 of file DA14680BA.h.

◆ COEX_COEX_PRI11_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI11_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI11_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3804 of file DA14680BA.h.

◆ COEX_COEX_PRI11_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI11_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI11_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3803 of file DA14680BA.h.

◆ COEX_COEX_PRI12_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI12_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI12_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3812 of file DA14680BA.h.

◆ COEX_COEX_PRI12_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI12_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI12_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3811 of file DA14680BA.h.

◆ COEX_COEX_PRI12_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI12_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI12_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3810 of file DA14680BA.h.

◆ COEX_COEX_PRI12_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI12_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI12_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3809 of file DA14680BA.h.

◆ COEX_COEX_PRI13_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI13_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI13_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3818 of file DA14680BA.h.

◆ COEX_COEX_PRI13_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI13_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI13_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3817 of file DA14680BA.h.

◆ COEX_COEX_PRI13_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI13_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI13_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3816 of file DA14680BA.h.

◆ COEX_COEX_PRI13_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI13_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI13_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3815 of file DA14680BA.h.

◆ COEX_COEX_PRI14_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI14_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI14_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3824 of file DA14680BA.h.

◆ COEX_COEX_PRI14_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI14_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI14_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3823 of file DA14680BA.h.

◆ COEX_COEX_PRI14_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI14_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI14_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3822 of file DA14680BA.h.

◆ COEX_COEX_PRI14_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI14_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI14_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3821 of file DA14680BA.h.

◆ COEX_COEX_PRI15_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI15_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI15_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3830 of file DA14680BA.h.

◆ COEX_COEX_PRI15_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI15_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI15_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3829 of file DA14680BA.h.

◆ COEX_COEX_PRI15_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI15_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI15_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3828 of file DA14680BA.h.

◆ COEX_COEX_PRI15_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI15_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI15_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3827 of file DA14680BA.h.

◆ COEX_COEX_PRI1_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI1_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI1_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3746 of file DA14680BA.h.

◆ COEX_COEX_PRI1_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI1_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI1_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3745 of file DA14680BA.h.

◆ COEX_COEX_PRI1_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI1_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI1_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3744 of file DA14680BA.h.

◆ COEX_COEX_PRI1_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI1_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI1_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3743 of file DA14680BA.h.

◆ COEX_COEX_PRI2_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI2_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI2_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3752 of file DA14680BA.h.

◆ COEX_COEX_PRI2_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI2_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI2_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3751 of file DA14680BA.h.

◆ COEX_COEX_PRI2_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI2_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI2_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3750 of file DA14680BA.h.

◆ COEX_COEX_PRI2_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI2_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI2_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3749 of file DA14680BA.h.

◆ COEX_COEX_PRI3_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI3_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI3_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3758 of file DA14680BA.h.

◆ COEX_COEX_PRI3_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI3_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI3_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3757 of file DA14680BA.h.

◆ COEX_COEX_PRI3_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI3_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI3_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3756 of file DA14680BA.h.

◆ COEX_COEX_PRI3_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI3_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI3_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3755 of file DA14680BA.h.

◆ COEX_COEX_PRI4_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI4_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI4_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3764 of file DA14680BA.h.

◆ COEX_COEX_PRI4_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI4_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI4_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3763 of file DA14680BA.h.

◆ COEX_COEX_PRI4_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI4_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI4_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3762 of file DA14680BA.h.

◆ COEX_COEX_PRI4_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI4_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI4_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3761 of file DA14680BA.h.

◆ COEX_COEX_PRI5_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI5_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI5_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3770 of file DA14680BA.h.

◆ COEX_COEX_PRI5_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI5_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI5_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3769 of file DA14680BA.h.

◆ COEX_COEX_PRI5_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI5_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI5_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3768 of file DA14680BA.h.

◆ COEX_COEX_PRI5_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI5_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI5_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3767 of file DA14680BA.h.

◆ COEX_COEX_PRI6_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI6_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI6_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3776 of file DA14680BA.h.

◆ COEX_COEX_PRI6_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI6_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI6_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3775 of file DA14680BA.h.

◆ COEX_COEX_PRI6_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI6_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI6_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3774 of file DA14680BA.h.

◆ COEX_COEX_PRI6_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI6_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI6_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3773 of file DA14680BA.h.

◆ COEX_COEX_PRI7_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI7_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI7_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3782 of file DA14680BA.h.

◆ COEX_COEX_PRI7_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI7_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI7_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3781 of file DA14680BA.h.

◆ COEX_COEX_PRI7_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI7_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI7_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3780 of file DA14680BA.h.

◆ COEX_COEX_PRI7_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI7_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI7_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3779 of file DA14680BA.h.

◆ COEX_COEX_PRI8_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI8_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI8_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3788 of file DA14680BA.h.

◆ COEX_COEX_PRI8_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI8_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI8_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3787 of file DA14680BA.h.

◆ COEX_COEX_PRI8_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI8_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI8_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3786 of file DA14680BA.h.

◆ COEX_COEX_PRI8_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI8_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI8_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3785 of file DA14680BA.h.

◆ COEX_COEX_PRI9_REG_COEX_PRI_MAC_Msk

#define COEX_COEX_PRI9_REG_COEX_PRI_MAC_Msk   (0x18UL)

COEX COEX_PRI9_REG: COEX_PRI_MAC (Bitfield-Mask: 0x03)

Definition at line 3794 of file DA14680BA.h.

◆ COEX_COEX_PRI9_REG_COEX_PRI_MAC_Pos

#define COEX_COEX_PRI9_REG_COEX_PRI_MAC_Pos   (3UL)

COEX COEX_PRI9_REG: COEX_PRI_MAC (Bit 3)

Definition at line 3793 of file DA14680BA.h.

◆ COEX_COEX_PRI9_REG_COEX_PRI_PTI_Msk

#define COEX_COEX_PRI9_REG_COEX_PRI_PTI_Msk   (0x7UL)

COEX COEX_PRI9_REG: COEX_PRI_PTI (Bitfield-Mask: 0x07)

Definition at line 3792 of file DA14680BA.h.

◆ COEX_COEX_PRI9_REG_COEX_PRI_PTI_Pos

#define COEX_COEX_PRI9_REG_COEX_PRI_PTI_Pos   (0UL)

COEX COEX_PRI9_REG: COEX_PRI_PTI (Bit 0)

Definition at line 3791 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_BLE_ACTIVE_Msk

#define COEX_COEX_STAT2_REG_COEX_BLE_ACTIVE_Msk   (0x200UL)

COEX COEX_STAT2_REG: COEX_BLE_ACTIVE (Bitfield-Mask: 0x01)

Definition at line 3704 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_BLE_ACTIVE_Pos

#define COEX_COEX_STAT2_REG_COEX_BLE_ACTIVE_Pos   (9UL)

COEX COEX_STAT2_REG: COEX_BLE_ACTIVE (Bit 9)

Definition at line 3703 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_BLE_PTI_INT_Msk

#define COEX_COEX_STAT2_REG_COEX_BLE_PTI_INT_Msk   (0x7000UL)

COEX COEX_STAT2_REG: COEX_BLE_PTI_INT (Bitfield-Mask: 0x07)

Definition at line 3710 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_BLE_PTI_INT_Pos

#define COEX_COEX_STAT2_REG_COEX_BLE_PTI_INT_Pos   (12UL)

COEX COEX_STAT2_REG: COEX_BLE_PTI_INT (Bit 12)

Definition at line 3709 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_BLE_RX_EN_Msk

#define COEX_COEX_STAT2_REG_COEX_BLE_RX_EN_Msk   (0x400UL)

COEX COEX_STAT2_REG: COEX_BLE_RX_EN (Bitfield-Mask: 0x01)

Definition at line 3706 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_BLE_RX_EN_Pos

#define COEX_COEX_STAT2_REG_COEX_BLE_RX_EN_Pos   (10UL)

COEX COEX_STAT2_REG: COEX_BLE_RX_EN (Bit 10)

Definition at line 3705 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_BLE_TX_EN_Msk

#define COEX_COEX_STAT2_REG_COEX_BLE_TX_EN_Msk   (0x800UL)

COEX COEX_STAT2_REG: COEX_BLE_TX_EN (Bitfield-Mask: 0x01)

Definition at line 3708 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_BLE_TX_EN_Pos

#define COEX_COEX_STAT2_REG_COEX_BLE_TX_EN_Pos   (11UL)

COEX COEX_STAT2_REG: COEX_BLE_TX_EN (Bit 11)

Definition at line 3707 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_DECISION_WITH_CLOSING_Msk

#define COEX_COEX_STAT2_REG_COEX_DECISION_WITH_CLOSING_Msk   (0x7UL)

COEX COEX_STAT2_REG: COEX_DECISION_WITH_CLOSING (Bitfield-Mask: 0x07)

Definition at line 3694 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_DECISION_WITH_CLOSING_Pos

#define COEX_COEX_STAT2_REG_COEX_DECISION_WITH_CLOSING_Pos   (0UL)

COEX COEX_STAT2_REG: COEX_DECISION_WITH_CLOSING (Bit 0)

Definition at line 3693 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_EXT_ACT_Msk

#define COEX_COEX_STAT2_REG_COEX_EXT_ACT_Msk   (0x8000UL)

COEX COEX_STAT2_REG: COEX_EXT_ACT (Bitfield-Mask: 0x01)

Definition at line 3712 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_EXT_ACT_Pos

#define COEX_COEX_STAT2_REG_COEX_EXT_ACT_Pos   (15UL)

COEX COEX_STAT2_REG: COEX_EXT_ACT (Bit 15)

Definition at line 3711 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_FTDF_ACTIVE_Msk

#define COEX_COEX_STAT2_REG_COEX_FTDF_ACTIVE_Msk   (0x8UL)

COEX COEX_STAT2_REG: COEX_FTDF_ACTIVE (Bitfield-Mask: 0x01)

Definition at line 3696 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_FTDF_ACTIVE_Pos

#define COEX_COEX_STAT2_REG_COEX_FTDF_ACTIVE_Pos   (3UL)

COEX COEX_STAT2_REG: COEX_FTDF_ACTIVE (Bit 3)

Definition at line 3695 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_FTDF_PTI_INT_Msk

#define COEX_COEX_STAT2_REG_COEX_FTDF_PTI_INT_Msk   (0x1c0UL)

COEX COEX_STAT2_REG: COEX_FTDF_PTI_INT (Bitfield-Mask: 0x07)

Definition at line 3702 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_FTDF_PTI_INT_Pos

#define COEX_COEX_STAT2_REG_COEX_FTDF_PTI_INT_Pos   (6UL)

COEX COEX_STAT2_REG: COEX_FTDF_PTI_INT (Bit 6)

Definition at line 3701 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_FTDF_RX_EN_Msk

#define COEX_COEX_STAT2_REG_COEX_FTDF_RX_EN_Msk   (0x10UL)

COEX COEX_STAT2_REG: COEX_FTDF_RX_EN (Bitfield-Mask: 0x01)

Definition at line 3698 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_FTDF_RX_EN_Pos

#define COEX_COEX_STAT2_REG_COEX_FTDF_RX_EN_Pos   (4UL)

COEX COEX_STAT2_REG: COEX_FTDF_RX_EN (Bit 4)

Definition at line 3697 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_FTDF_TX_EN_Msk

#define COEX_COEX_STAT2_REG_COEX_FTDF_TX_EN_Msk   (0x20UL)

COEX COEX_STAT2_REG: COEX_FTDF_TX_EN (Bitfield-Mask: 0x01)

Definition at line 3700 of file DA14680BA.h.

◆ COEX_COEX_STAT2_REG_COEX_FTDF_TX_EN_Pos

#define COEX_COEX_STAT2_REG_COEX_FTDF_TX_EN_Pos   (5UL)

COEX COEX_STAT2_REG: COEX_FTDF_TX_EN (Bit 5)

Definition at line 3699 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_COEX_CLOSING_Msk

#define COEX_COEX_STAT_REG_COEX_CLOSING_Msk   (0x80UL)

COEX COEX_STAT_REG: COEX_CLOSING (Bitfield-Mask: 0x01)

Definition at line 3674 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_COEX_CLOSING_Pos

#define COEX_COEX_STAT_REG_COEX_CLOSING_Pos   (7UL)

COEX COEX_STAT_REG: COEX_CLOSING (Bit 7)

Definition at line 3673 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_COEX_DECISION_Msk

#define COEX_COEX_STAT_REG_COEX_DECISION_Msk   (0x60UL)

COEX COEX_STAT_REG: COEX_DECISION (Bitfield-Mask: 0x03)

Definition at line 3672 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_COEX_DECISION_Pos

#define COEX_COEX_STAT_REG_COEX_DECISION_Pos   (5UL)

COEX COEX_STAT_REG: COEX_DECISION (Bit 5)

Definition at line 3671 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_COEX_DECISION_PTR_Msk

#define COEX_COEX_STAT_REG_COEX_DECISION_PTR_Msk   (0xfUL)

COEX COEX_STAT_REG: COEX_DECISION_PTR (Bitfield-Mask: 0x0f)

Definition at line 3670 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_COEX_DECISION_PTR_Pos

#define COEX_COEX_STAT_REG_COEX_DECISION_PTR_Pos   (0UL)

COEX COEX_STAT_REG: COEX_DECISION_PTR (Bit 0)

Definition at line 3669 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_COEX_RADIO_BUSY_Msk

#define COEX_COEX_STAT_REG_COEX_RADIO_BUSY_Msk   (0x1000UL)

COEX COEX_STAT_REG: COEX_RADIO_BUSY (Bitfield-Mask: 0x01)

Definition at line 3684 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_COEX_RADIO_BUSY_Pos

#define COEX_COEX_STAT_REG_COEX_RADIO_BUSY_Pos   (12UL)

COEX COEX_STAT_REG: COEX_RADIO_BUSY (Bit 12)

Definition at line 3683 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_EXT_ACT0_Msk

#define COEX_COEX_STAT_REG_EXT_ACT0_Msk   (0x400UL)

COEX COEX_STAT_REG: EXT_ACT0 (Bitfield-Mask: 0x01)

Definition at line 3680 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_EXT_ACT0_Pos

#define COEX_COEX_STAT_REG_EXT_ACT0_Pos   (10UL)

COEX COEX_STAT_REG: EXT_ACT0 (Bit 10)

Definition at line 3679 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_EXT_ACT1_Msk

#define COEX_COEX_STAT_REG_EXT_ACT1_Msk   (0x800UL)

COEX COEX_STAT_REG: EXT_ACT1 (Bitfield-Mask: 0x01)

Definition at line 3682 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_EXT_ACT1_Pos

#define COEX_COEX_STAT_REG_EXT_ACT1_Pos   (11UL)

COEX COEX_STAT_REG: EXT_ACT1 (Bit 11)

Definition at line 3681 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_IGNORE_BLE_STAT_Msk

#define COEX_COEX_STAT_REG_IGNORE_BLE_STAT_Msk   (0x8000UL)

COEX COEX_STAT_REG: IGNORE_BLE_STAT (Bitfield-Mask: 0x01)

Definition at line 3690 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_IGNORE_BLE_STAT_Pos

#define COEX_COEX_STAT_REG_IGNORE_BLE_STAT_Pos   (15UL)

COEX COEX_STAT_REG: IGNORE_BLE_STAT (Bit 15)

Definition at line 3689 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_IGNORE_EXT_STAT_Msk

#define COEX_COEX_STAT_REG_IGNORE_EXT_STAT_Msk   (0x2000UL)

COEX COEX_STAT_REG: IGNORE_EXT_STAT (Bitfield-Mask: 0x01)

Definition at line 3686 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_IGNORE_EXT_STAT_Pos

#define COEX_COEX_STAT_REG_IGNORE_EXT_STAT_Pos   (13UL)

COEX COEX_STAT_REG: IGNORE_EXT_STAT (Bit 13)

Definition at line 3685 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_IGNORE_FTDF_STAT_Msk

#define COEX_COEX_STAT_REG_IGNORE_FTDF_STAT_Msk   (0x4000UL)

COEX COEX_STAT_REG: IGNORE_FTDF_STAT (Bitfield-Mask: 0x01)

Definition at line 3688 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_IGNORE_FTDF_STAT_Pos

#define COEX_COEX_STAT_REG_IGNORE_FTDF_STAT_Pos   (14UL)

COEX COEX_STAT_REG: IGNORE_FTDF_STAT (Bit 14)

Definition at line 3687 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_SMART_ACT_Msk

#define COEX_COEX_STAT_REG_SMART_ACT_Msk   (0x100UL)

COEX COEX_STAT_REG: SMART_ACT (Bitfield-Mask: 0x01)

Definition at line 3676 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_SMART_ACT_Pos

#define COEX_COEX_STAT_REG_SMART_ACT_Pos   (8UL)

COEX COEX_STAT_REG: SMART_ACT (Bit 8)

Definition at line 3675 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_SMART_PRI_Msk

#define COEX_COEX_STAT_REG_SMART_PRI_Msk   (0x200UL)

COEX COEX_STAT_REG: SMART_PRI (Bitfield-Mask: 0x01)

Definition at line 3678 of file DA14680BA.h.

◆ COEX_COEX_STAT_REG_SMART_PRI_Pos

#define COEX_COEX_STAT_REG_SMART_PRI_Pos   (9UL)

COEX COEX_STAT_REG: SMART_PRI (Bit 9)

Definition at line 3677 of file DA14680BA.h.

◆ CRG_PER

#define CRG_PER   ((CRG_PER_Type *) CRG_PER_BASE)

Definition at line 12080 of file DA14680BA.h.

◆ CRG_PER_BASE

#define CRG_PER_BASE   0x50001C00UL

Definition at line 12035 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_ADC_CLK_SEL_Msk

#define CRG_PER_CLK_PER_REG_ADC_CLK_SEL_Msk   (0x800UL)

CRG_PER CLK_PER_REG: ADC_CLK_SEL (Bitfield-Mask: 0x01)

Definition at line 3858 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_ADC_CLK_SEL_Pos

#define CRG_PER_CLK_PER_REG_ADC_CLK_SEL_Pos   (11UL)

CRG_PER CLK_PER_REG: ADC_CLK_SEL (Bit 11)

Definition at line 3857 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_I2C_CLK_SEL_Msk

#define CRG_PER_CLK_PER_REG_I2C_CLK_SEL_Msk   (0x200UL)

CRG_PER CLK_PER_REG: I2C_CLK_SEL (Bitfield-Mask: 0x01)

Definition at line 3854 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_I2C_CLK_SEL_Pos

#define CRG_PER_CLK_PER_REG_I2C_CLK_SEL_Pos   (9UL)

CRG_PER CLK_PER_REG: I2C_CLK_SEL (Bit 9)

Definition at line 3853 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_I2C_ENABLE_Msk

#define CRG_PER_CLK_PER_REG_I2C_ENABLE_Msk   (0x4UL)

CRG_PER CLK_PER_REG: I2C_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3844 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_I2C_ENABLE_Pos

#define CRG_PER_CLK_PER_REG_I2C_ENABLE_Pos   (2UL)

CRG_PER CLK_PER_REG: I2C_ENABLE (Bit 2)

Definition at line 3843 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_IR_CLK_ENABLE_Msk

#define CRG_PER_CLK_PER_REG_IR_CLK_ENABLE_Msk   (0x10UL)

CRG_PER CLK_PER_REG: IR_CLK_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3848 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_IR_CLK_ENABLE_Pos

#define CRG_PER_CLK_PER_REG_IR_CLK_ENABLE_Pos   (4UL)

CRG_PER CLK_PER_REG: IR_CLK_ENABLE (Bit 4)

Definition at line 3847 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_KBSCAN_CLK_SEL_Msk

#define CRG_PER_CLK_PER_REG_KBSCAN_CLK_SEL_Msk   (0x400UL)

CRG_PER CLK_PER_REG: KBSCAN_CLK_SEL (Bitfield-Mask: 0x01)

Definition at line 3856 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_KBSCAN_CLK_SEL_Pos

#define CRG_PER_CLK_PER_REG_KBSCAN_CLK_SEL_Pos   (10UL)

CRG_PER CLK_PER_REG: KBSCAN_CLK_SEL (Bit 10)

Definition at line 3855 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_KBSCAN_ENABLE_Msk

#define CRG_PER_CLK_PER_REG_KBSCAN_ENABLE_Msk   (0x20UL)

CRG_PER CLK_PER_REG: KBSCAN_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3850 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_KBSCAN_ENABLE_Pos

#define CRG_PER_CLK_PER_REG_KBSCAN_ENABLE_Pos   (5UL)

CRG_PER CLK_PER_REG: KBSCAN_ENABLE (Bit 5)

Definition at line 3849 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_QUAD_ENABLE_Msk

#define CRG_PER_CLK_PER_REG_QUAD_ENABLE_Msk   (0x8UL)

CRG_PER CLK_PER_REG: QUAD_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3846 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_QUAD_ENABLE_Pos

#define CRG_PER_CLK_PER_REG_QUAD_ENABLE_Pos   (3UL)

CRG_PER CLK_PER_REG: QUAD_ENABLE (Bit 3)

Definition at line 3845 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_SPI_CLK_SEL_Msk

#define CRG_PER_CLK_PER_REG_SPI_CLK_SEL_Msk   (0x100UL)

CRG_PER CLK_PER_REG: SPI_CLK_SEL (Bitfield-Mask: 0x01)

Definition at line 3852 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_SPI_CLK_SEL_Pos

#define CRG_PER_CLK_PER_REG_SPI_CLK_SEL_Pos   (8UL)

CRG_PER CLK_PER_REG: SPI_CLK_SEL (Bit 8)

Definition at line 3851 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_SPI_ENABLE_Msk

#define CRG_PER_CLK_PER_REG_SPI_ENABLE_Msk   (0x2UL)

CRG_PER CLK_PER_REG: SPI_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3842 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_SPI_ENABLE_Pos

#define CRG_PER_CLK_PER_REG_SPI_ENABLE_Pos   (1UL)

CRG_PER CLK_PER_REG: SPI_ENABLE (Bit 1)

Definition at line 3841 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_UART_ENABLE_Msk

#define CRG_PER_CLK_PER_REG_UART_ENABLE_Msk   (0x1UL)

CRG_PER CLK_PER_REG: UART_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3840 of file DA14680BA.h.

◆ CRG_PER_CLK_PER_REG_UART_ENABLE_Pos

#define CRG_PER_CLK_PER_REG_UART_ENABLE_Pos   (0UL)

CRG_PER CLK_PER_REG: UART_ENABLE (Bit 0)

Definition at line 3839 of file DA14680BA.h.

◆ CRG_PER_EH_REG_EH_EN_Msk

#define CRG_PER_EH_REG_EH_EN_Msk   (0x1UL)

CRG_PER EH_REG: EH_EN (Bitfield-Mask: 0x01)

Definition at line 3888 of file DA14680BA.h.

◆ CRG_PER_EH_REG_EH_EN_Pos

#define CRG_PER_EH_REG_EH_EN_Pos   (0UL)

CRG_PER EH_REG: EH_EN (Bit 0)

Definition at line 3887 of file DA14680BA.h.

◆ CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Msk

#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Msk   (0x1000UL)

CRG_PER PCM_DIV_REG: CLK_PCM_EN (Bitfield-Mask: 0x01)

Definition at line 3864 of file DA14680BA.h.

◆ CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Pos

#define CRG_PER_PCM_DIV_REG_CLK_PCM_EN_Pos   (12UL)

CRG_PER PCM_DIV_REG: CLK_PCM_EN (Bit 12)

Definition at line 3863 of file DA14680BA.h.

◆ CRG_PER_PCM_DIV_REG_PCM_DIV_Msk

#define CRG_PER_PCM_DIV_REG_PCM_DIV_Msk   (0xfffUL)

CRG_PER PCM_DIV_REG: PCM_DIV (Bitfield-Mask: 0xfff)

Definition at line 3862 of file DA14680BA.h.

◆ CRG_PER_PCM_DIV_REG_PCM_DIV_Pos

#define CRG_PER_PCM_DIV_REG_PCM_DIV_Pos   (0UL)

CRG_PER PCM_DIV_REG: PCM_DIV (Bit 0)

Definition at line 3861 of file DA14680BA.h.

◆ CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Msk

#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Msk   (0x2000UL)

CRG_PER PCM_DIV_REG: PCM_SRC_SEL (Bitfield-Mask: 0x01)

Definition at line 3866 of file DA14680BA.h.

◆ CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Pos

#define CRG_PER_PCM_DIV_REG_PCM_SRC_SEL_Pos   (13UL)

CRG_PER PCM_DIV_REG: PCM_SRC_SEL (Bit 13)

Definition at line 3865 of file DA14680BA.h.

◆ CRG_PER_PCM_FDIV_REG_PCM_FDIV_Msk

#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Msk   (0xffffUL)

CRG_PER PCM_FDIV_REG: PCM_FDIV (Bitfield-Mask: 0xffff)

Definition at line 3870 of file DA14680BA.h.

◆ CRG_PER_PCM_FDIV_REG_PCM_FDIV_Pos

#define CRG_PER_PCM_FDIV_REG_PCM_FDIV_Pos   (0UL)

CRG_PER PCM_FDIV_REG: PCM_FDIV (Bit 0)

Definition at line 3869 of file DA14680BA.h.

◆ CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Msk

#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Msk   (0x100UL)

CRG_PER PDM_DIV_REG: CLK_PDM_EN (Bitfield-Mask: 0x01)

Definition at line 3876 of file DA14680BA.h.

◆ CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Pos

#define CRG_PER_PDM_DIV_REG_CLK_PDM_EN_Pos   (8UL)

CRG_PER PDM_DIV_REG: CLK_PDM_EN (Bit 8)

Definition at line 3875 of file DA14680BA.h.

◆ CRG_PER_PDM_DIV_REG_PDM_DIV_Msk

#define CRG_PER_PDM_DIV_REG_PDM_DIV_Msk   (0xffUL)

CRG_PER PDM_DIV_REG: PDM_DIV (Bitfield-Mask: 0xff)

Definition at line 3874 of file DA14680BA.h.

◆ CRG_PER_PDM_DIV_REG_PDM_DIV_Pos

#define CRG_PER_PDM_DIV_REG_PDM_DIV_Pos   (0UL)

CRG_PER PDM_DIV_REG: PDM_DIV (Bit 0)

Definition at line 3873 of file DA14680BA.h.

◆ CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Msk

#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Msk   (0x200UL)

CRG_PER PDM_DIV_REG: PDM_MASTER_MODE (Bitfield-Mask: 0x01)

Definition at line 3878 of file DA14680BA.h.

◆ CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Pos

#define CRG_PER_PDM_DIV_REG_PDM_MASTER_MODE_Pos   (9UL)

CRG_PER PDM_DIV_REG: PDM_MASTER_MODE (Bit 9)

Definition at line 3877 of file DA14680BA.h.

◆ CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Msk

#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Msk   (0x100UL)

CRG_PER SRC_DIV_REG: CLK_SRC_EN (Bitfield-Mask: 0x01)

Definition at line 3884 of file DA14680BA.h.

◆ CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Pos

#define CRG_PER_SRC_DIV_REG_CLK_SRC_EN_Pos   (8UL)

CRG_PER SRC_DIV_REG: CLK_SRC_EN (Bit 8)

Definition at line 3883 of file DA14680BA.h.

◆ CRG_PER_SRC_DIV_REG_SRC_DIV_Msk

#define CRG_PER_SRC_DIV_REG_SRC_DIV_Msk   (0xffUL)

CRG_PER SRC_DIV_REG: SRC_DIV (Bitfield-Mask: 0xff)

Definition at line 3882 of file DA14680BA.h.

◆ CRG_PER_SRC_DIV_REG_SRC_DIV_Pos

#define CRG_PER_SRC_DIV_REG_SRC_DIV_Pos   (0UL)

CRG_PER SRC_DIV_REG: SRC_DIV (Bit 0)

Definition at line 3881 of file DA14680BA.h.

◆ CRG_PER_USBPAD_REG_USBPAD_EN_Msk

#define CRG_PER_USBPAD_REG_USBPAD_EN_Msk   (0x1UL)

CRG_PER USBPAD_REG: USBPAD_EN (Bitfield-Mask: 0x01)

Definition at line 3892 of file DA14680BA.h.

◆ CRG_PER_USBPAD_REG_USBPAD_EN_Pos

#define CRG_PER_USBPAD_REG_USBPAD_EN_Pos   (0UL)

CRG_PER USBPAD_REG: USBPAD_EN (Bit 0)

Definition at line 3891 of file DA14680BA.h.

◆ CRG_PER_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Msk

#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Msk   (0x2UL)

CRG_PER USBPAD_REG: USBPHY_FORCE_SW1_OFF (Bitfield-Mask: 0x01)

Definition at line 3894 of file DA14680BA.h.

◆ CRG_PER_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Pos

#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW1_OFF_Pos   (1UL)

CRG_PER USBPAD_REG: USBPHY_FORCE_SW1_OFF (Bit 1)

Definition at line 3893 of file DA14680BA.h.

◆ CRG_PER_USBPAD_REG_USBPHY_FORCE_SW2_ON_Msk

#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW2_ON_Msk   (0x4UL)

CRG_PER USBPAD_REG: USBPHY_FORCE_SW2_ON (Bitfield-Mask: 0x01)

Definition at line 3896 of file DA14680BA.h.

◆ CRG_PER_USBPAD_REG_USBPHY_FORCE_SW2_ON_Pos

#define CRG_PER_USBPAD_REG_USBPHY_FORCE_SW2_ON_Pos   (2UL)

CRG_PER USBPAD_REG: USBPHY_FORCE_SW2_ON (Bit 2)

Definition at line 3895 of file DA14680BA.h.

◆ CRG_TOP

#define CRG_TOP   ((CRG_TOP_Type *) CRG_TOP_BASE)

Definition at line 12081 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Msk   (0x40UL)

CRG_TOP ANA_STATUS_REG: BANDGAP_OK (Bitfield-Mask: 0x01)

Definition at line 4156 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Pos   (6UL)

CRG_TOP ANA_STATUS_REG: BANDGAP_OK (Bit 6)

Definition at line 4155 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_1V8_FLASH_HIGH_Msk

#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_FLASH_HIGH_Msk   (0x4000UL)

CRG_TOP ANA_STATUS_REG: COMP_1V8_FLASH_HIGH (Bitfield-Mask: 0x01)

Definition at line 4172 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_1V8_FLASH_HIGH_Pos

#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_FLASH_HIGH_Pos   (14UL)

CRG_TOP ANA_STATUS_REG: COMP_1V8_FLASH_HIGH (Bit 14)

Definition at line 4171 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_1V8_PA_HIGH_Msk

#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_PA_HIGH_Msk   (0x8000UL)

CRG_TOP ANA_STATUS_REG: COMP_1V8_PA_HIGH (Bitfield-Mask: 0x01)

Definition at line 4174 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_1V8_PA_HIGH_Pos

#define CRG_TOP_ANA_STATUS_REG_COMP_1V8_PA_HIGH_Pos   (15UL)

CRG_TOP ANA_STATUS_REG: COMP_1V8_PA_HIGH (Bit 15)

Definition at line 4173 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_V33_HIGH_Msk

#define CRG_TOP_ANA_STATUS_REG_COMP_V33_HIGH_Msk   (0x2000UL)

CRG_TOP ANA_STATUS_REG: COMP_V33_HIGH (Bitfield-Mask: 0x01)

Definition at line 4170 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_V33_HIGH_Pos

#define CRG_TOP_ANA_STATUS_REG_COMP_V33_HIGH_Pos   (13UL)

CRG_TOP ANA_STATUS_REG: COMP_V33_HIGH (Bit 13)

Definition at line 4169 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_VBAT_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_OK_Msk   (0x2UL)

CRG_TOP ANA_STATUS_REG: COMP_VBAT_OK (Bitfield-Mask: 0x01)

Definition at line 4146 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_VBAT_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_COMP_VBAT_OK_Pos   (1UL)

CRG_TOP ANA_STATUS_REG: COMP_VBAT_OK (Bit 1)

Definition at line 4145 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Msk

#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Msk   (0x800UL)

CRG_TOP ANA_STATUS_REG: COMP_VBUS_HIGH (Bitfield-Mask: 0x01)

Definition at line 4166 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Pos

#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_HIGH_Pos   (11UL)

CRG_TOP ANA_STATUS_REG: COMP_VBUS_HIGH (Bit 11)

Definition at line 4165 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Msk

#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Msk   (0x1000UL)

CRG_TOP ANA_STATUS_REG: COMP_VBUS_LOW (Bitfield-Mask: 0x01)

Definition at line 4168 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Pos

#define CRG_TOP_ANA_STATUS_REG_COMP_VBUS_LOW_Pos   (12UL)

CRG_TOP ANA_STATUS_REG: COMP_VBUS_LOW (Bit 12)

Definition at line 4167 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_VDD_HIGH_Msk

#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_HIGH_Msk   (0x80UL)

CRG_TOP ANA_STATUS_REG: COMP_VDD_HIGH (Bitfield-Mask: 0x01)

Definition at line 4158 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_COMP_VDD_HIGH_Pos

#define CRG_TOP_ANA_STATUS_REG_COMP_VDD_HIGH_Pos   (7UL)

CRG_TOP ANA_STATUS_REG: COMP_VDD_HIGH (Bit 7)

Definition at line 4157 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_LDO_1V8_FLASH_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_FLASH_OK_Msk   (0x400UL)

CRG_TOP ANA_STATUS_REG: LDO_1V8_FLASH_OK (Bitfield-Mask: 0x01)

Definition at line 4164 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_LDO_1V8_FLASH_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_FLASH_OK_Pos   (10UL)

CRG_TOP ANA_STATUS_REG: LDO_1V8_FLASH_OK (Bit 10)

Definition at line 4163 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_LDO_1V8_PA_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_PA_OK_Msk   (0x200UL)

CRG_TOP ANA_STATUS_REG: LDO_1V8_PA_OK (Bitfield-Mask: 0x01)

Definition at line 4162 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_LDO_1V8_PA_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_LDO_1V8_PA_OK_Pos   (9UL)

CRG_TOP ANA_STATUS_REG: LDO_1V8_PA_OK (Bit 9)

Definition at line 4161 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Msk   (0x100UL)

CRG_TOP ANA_STATUS_REG: LDO_CORE_OK (Bitfield-Mask: 0x01)

Definition at line 4160 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Pos   (8UL)

CRG_TOP ANA_STATUS_REG: LDO_CORE_OK (Bit 8)

Definition at line 4159 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Msk   (0x1UL)

CRG_TOP ANA_STATUS_REG: LDO_RADIO_OK (Bitfield-Mask: 0x01)

Definition at line 4144 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_LDO_RADIO_OK_Pos   (0UL)

CRG_TOP ANA_STATUS_REG: LDO_RADIO_OK (Bit 0)

Definition at line 4143 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_USB_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_USB_OK_Msk   (0x20UL)

CRG_TOP ANA_STATUS_REG: LDO_SUPPLY_USB_OK (Bitfield-Mask: 0x01)

Definition at line 4154 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_USB_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_USB_OK_Pos   (5UL)

CRG_TOP ANA_STATUS_REG: LDO_SUPPLY_USB_OK (Bit 5)

Definition at line 4153 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_VBAT_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_VBAT_OK_Msk   (0x10UL)

CRG_TOP ANA_STATUS_REG: LDO_SUPPLY_VBAT_OK (Bitfield-Mask: 0x01)

Definition at line 4152 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_VBAT_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_LDO_SUPPLY_VBAT_OK_Pos   (4UL)

CRG_TOP ANA_STATUS_REG: LDO_SUPPLY_VBAT_OK (Bit 4)

Definition at line 4151 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_NEWBAT_Msk

#define CRG_TOP_ANA_STATUS_REG_NEWBAT_Msk   (0x8UL)

CRG_TOP ANA_STATUS_REG: NEWBAT (Bitfield-Mask: 0x01)

Definition at line 4150 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_NEWBAT_Pos

#define CRG_TOP_ANA_STATUS_REG_NEWBAT_Pos   (3UL)

CRG_TOP ANA_STATUS_REG: NEWBAT (Bit 3)

Definition at line 4149 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk

#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Msk   (0x4UL)

CRG_TOP ANA_STATUS_REG: VBUS_AVAILABLE (Bitfield-Mask: 0x01)

Definition at line 4148 of file DA14680BA.h.

◆ CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Pos

#define CRG_TOP_ANA_STATUS_REG_VBUS_AVAILABLE_Pos   (2UL)

CRG_TOP ANA_STATUS_REG: VBUS_AVAILABLE (Bit 2)

Definition at line 4147 of file DA14680BA.h.

◆ CRG_TOP_AON_SPARE_REG_EN_BATSYS_RET_Msk

#define CRG_TOP_AON_SPARE_REG_EN_BATSYS_RET_Msk   (0x4UL)

CRG_TOP AON_SPARE_REG: EN_BATSYS_RET (Bitfield-Mask: 0x01)

Definition at line 4376 of file DA14680BA.h.

◆ CRG_TOP_AON_SPARE_REG_EN_BATSYS_RET_Pos

#define CRG_TOP_AON_SPARE_REG_EN_BATSYS_RET_Pos   (2UL)

CRG_TOP AON_SPARE_REG: EN_BATSYS_RET (Bit 2)

Definition at line 4375 of file DA14680BA.h.

◆ CRG_TOP_AON_SPARE_REG_EN_BUSSYS_RET_Msk

#define CRG_TOP_AON_SPARE_REG_EN_BUSSYS_RET_Msk   (0x8UL)

CRG_TOP AON_SPARE_REG: EN_BUSSYS_RET (Bitfield-Mask: 0x01)

Definition at line 4378 of file DA14680BA.h.

◆ CRG_TOP_AON_SPARE_REG_EN_BUSSYS_RET_Pos

#define CRG_TOP_AON_SPARE_REG_EN_BUSSYS_RET_Pos   (3UL)

CRG_TOP AON_SPARE_REG: EN_BUSSYS_RET (Bit 3)

Definition at line 4377 of file DA14680BA.h.

◆ CRG_TOP_AON_SPARE_REG_OSC16_HOLD_AMP_REG_Msk

#define CRG_TOP_AON_SPARE_REG_OSC16_HOLD_AMP_REG_Msk   (0x1UL)

CRG_TOP AON_SPARE_REG: OSC16_HOLD_AMP_REG (Bitfield-Mask: 0x01)

Definition at line 4372 of file DA14680BA.h.

◆ CRG_TOP_AON_SPARE_REG_OSC16_HOLD_AMP_REG_Pos

#define CRG_TOP_AON_SPARE_REG_OSC16_HOLD_AMP_REG_Pos   (0UL)

CRG_TOP AON_SPARE_REG: OSC16_HOLD_AMP_REG (Bit 0)

Definition at line 4371 of file DA14680BA.h.

◆ CRG_TOP_AON_SPARE_REG_OSC16_SH_DISABLE_Msk

#define CRG_TOP_AON_SPARE_REG_OSC16_SH_DISABLE_Msk   (0x2UL)

CRG_TOP AON_SPARE_REG: OSC16_SH_DISABLE (Bitfield-Mask: 0x01)

Definition at line 4374 of file DA14680BA.h.

◆ CRG_TOP_AON_SPARE_REG_OSC16_SH_DISABLE_Pos

#define CRG_TOP_AON_SPARE_REG_OSC16_SH_DISABLE_Pos   (1UL)

CRG_TOP AON_SPARE_REG: OSC16_SH_DISABLE (Bit 1)

Definition at line 4373 of file DA14680BA.h.

◆ CRG_TOP_BANDGAP_REG_BGR_ITRIM_Msk

#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Msk   (0x3e0UL)

CRG_TOP BANDGAP_REG: BGR_ITRIM (Bitfield-Mask: 0x1f)

Definition at line 4136 of file DA14680BA.h.

◆ CRG_TOP_BANDGAP_REG_BGR_ITRIM_Pos

#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Pos   (5UL)

CRG_TOP BANDGAP_REG: BGR_ITRIM (Bit 5)

Definition at line 4135 of file DA14680BA.h.

◆ CRG_TOP_BANDGAP_REG_BGR_TRIM_Msk

#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Msk   (0x1fUL)

CRG_TOP BANDGAP_REG: BGR_TRIM (Bitfield-Mask: 0x1f)

Definition at line 4134 of file DA14680BA.h.

◆ CRG_TOP_BANDGAP_REG_BGR_TRIM_Pos

#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Pos   (0UL)

CRG_TOP BANDGAP_REG: BGR_TRIM (Bit 0)

Definition at line 4133 of file DA14680BA.h.

◆ CRG_TOP_BANDGAP_REG_LDO_SLEEP_TRIM_Msk

#define CRG_TOP_BANDGAP_REG_LDO_SLEEP_TRIM_Msk   (0x3c00UL)

CRG_TOP BANDGAP_REG: LDO_SLEEP_TRIM (Bitfield-Mask: 0x0f)

Definition at line 4138 of file DA14680BA.h.

◆ CRG_TOP_BANDGAP_REG_LDO_SLEEP_TRIM_Pos

#define CRG_TOP_BANDGAP_REG_LDO_SLEEP_TRIM_Pos   (10UL)

CRG_TOP BANDGAP_REG: LDO_SLEEP_TRIM (Bit 10)

Definition at line 4137 of file DA14680BA.h.

◆ CRG_TOP_BANDGAP_REG_LDO_SUPPLY_USE_BGREF_Msk

#define CRG_TOP_BANDGAP_REG_LDO_SUPPLY_USE_BGREF_Msk   (0x4000UL)

CRG_TOP BANDGAP_REG: LDO_SUPPLY_USE_BGREF (Bitfield-Mask: 0x01)

Definition at line 4140 of file DA14680BA.h.

◆ CRG_TOP_BANDGAP_REG_LDO_SUPPLY_USE_BGREF_Pos

#define CRG_TOP_BANDGAP_REG_LDO_SUPPLY_USE_BGREF_Pos   (14UL)

CRG_TOP BANDGAP_REG: LDO_SUPPLY_USE_BGREF (Bit 14)

Definition at line 4139 of file DA14680BA.h.

◆ CRG_TOP_BASE

#define CRG_TOP_BASE   0x50000000UL

Definition at line 12036 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_1V8_FLASH_EN_Msk

#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_FLASH_EN_Msk   (0x10UL)

CRG_TOP BOD_CTRL2_REG: BOD_1V8_FLASH_EN (Bitfield-Mask: 0x01)

Definition at line 4238 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_1V8_FLASH_EN_Pos

#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_FLASH_EN_Pos   (4UL)

CRG_TOP BOD_CTRL2_REG: BOD_1V8_FLASH_EN (Bit 4)

Definition at line 4237 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_1V8_PA_EN_Msk

#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_PA_EN_Msk   (0x8UL)

CRG_TOP BOD_CTRL2_REG: BOD_1V8_PA_EN (Bitfield-Mask: 0x01)

Definition at line 4236 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_1V8_PA_EN_Pos

#define CRG_TOP_BOD_CTRL2_REG_BOD_1V8_PA_EN_Pos   (3UL)

CRG_TOP BOD_CTRL2_REG: BOD_1V8_PA_EN (Bit 3)

Definition at line 4235 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_RESET_EN_Msk

#define CRG_TOP_BOD_CTRL2_REG_BOD_RESET_EN_Msk   (0x1UL)

CRG_TOP BOD_CTRL2_REG: BOD_RESET_EN (Bitfield-Mask: 0x01)

Definition at line 4230 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_RESET_EN_Pos

#define CRG_TOP_BOD_CTRL2_REG_BOD_RESET_EN_Pos   (0UL)

CRG_TOP BOD_CTRL2_REG: BOD_RESET_EN (Bit 0)

Definition at line 4229 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_V14_EN_Msk

#define CRG_TOP_BOD_CTRL2_REG_BOD_V14_EN_Msk   (0x40UL)

CRG_TOP BOD_CTRL2_REG: BOD_V14_EN (Bitfield-Mask: 0x01)

Definition at line 4242 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_V14_EN_Pos

#define CRG_TOP_BOD_CTRL2_REG_BOD_V14_EN_Pos   (6UL)

CRG_TOP BOD_CTRL2_REG: BOD_V14_EN (Bit 6)

Definition at line 4241 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_V33_EN_Msk

#define CRG_TOP_BOD_CTRL2_REG_BOD_V33_EN_Msk   (0x4UL)

CRG_TOP BOD_CTRL2_REG: BOD_V33_EN (Bitfield-Mask: 0x01)

Definition at line 4234 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_V33_EN_Pos

#define CRG_TOP_BOD_CTRL2_REG_BOD_V33_EN_Pos   (2UL)

CRG_TOP BOD_CTRL2_REG: BOD_V33_EN (Bit 2)

Definition at line 4233 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_VBAT_EN_Msk

#define CRG_TOP_BOD_CTRL2_REG_BOD_VBAT_EN_Msk   (0x20UL)

CRG_TOP BOD_CTRL2_REG: BOD_VBAT_EN (Bitfield-Mask: 0x01)

Definition at line 4240 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_VBAT_EN_Pos

#define CRG_TOP_BOD_CTRL2_REG_BOD_VBAT_EN_Pos   (5UL)

CRG_TOP BOD_CTRL2_REG: BOD_VBAT_EN (Bit 5)

Definition at line 4239 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_VDD_EN_Msk

#define CRG_TOP_BOD_CTRL2_REG_BOD_VDD_EN_Msk   (0x2UL)

CRG_TOP BOD_CTRL2_REG: BOD_VDD_EN (Bitfield-Mask: 0x01)

Definition at line 4232 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL2_REG_BOD_VDD_EN_Pos

#define CRG_TOP_BOD_CTRL2_REG_BOD_VDD_EN_Pos   (1UL)

CRG_TOP BOD_CTRL2_REG: BOD_VDD_EN (Bit 1)

Definition at line 4231 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL_REG_BOD_1V4_TRIM_Msk

#define CRG_TOP_BOD_CTRL_REG_BOD_1V4_TRIM_Msk   (0x30UL)

CRG_TOP BOD_CTRL_REG: BOD_1V4_TRIM (Bitfield-Mask: 0x03)

Definition at line 4222 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL_REG_BOD_1V4_TRIM_Pos

#define CRG_TOP_BOD_CTRL_REG_BOD_1V4_TRIM_Pos   (4UL)

CRG_TOP BOD_CTRL_REG: BOD_1V4_TRIM (Bit 4)

Definition at line 4221 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL_REG_BOD_1V8_TRIM_Msk

#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_TRIM_Msk   (0xcUL)

CRG_TOP BOD_CTRL_REG: BOD_1V8_TRIM (Bitfield-Mask: 0x03)

Definition at line 4220 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL_REG_BOD_1V8_TRIM_Pos

#define CRG_TOP_BOD_CTRL_REG_BOD_1V8_TRIM_Pos   (2UL)

CRG_TOP BOD_CTRL_REG: BOD_1V8_TRIM (Bit 2)

Definition at line 4219 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL_REG_BOD_V33_TRIM_Msk

#define CRG_TOP_BOD_CTRL_REG_BOD_V33_TRIM_Msk   (0xc0UL)

CRG_TOP BOD_CTRL_REG: BOD_V33_TRIM (Bitfield-Mask: 0x03)

Definition at line 4224 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL_REG_BOD_V33_TRIM_Pos

#define CRG_TOP_BOD_CTRL_REG_BOD_V33_TRIM_Pos   (6UL)

CRG_TOP BOD_CTRL_REG: BOD_V33_TRIM (Bit 6)

Definition at line 4223 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL_REG_BOD_VDD_LVL_Msk

#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_LVL_Msk   (0x700UL)

CRG_TOP BOD_CTRL_REG: BOD_VDD_LVL (Bitfield-Mask: 0x07)

Definition at line 4226 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL_REG_BOD_VDD_LVL_Pos

#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_LVL_Pos   (8UL)

CRG_TOP BOD_CTRL_REG: BOD_VDD_LVL (Bit 8)

Definition at line 4225 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL_REG_BOD_VDD_TRIM_Msk

#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_TRIM_Msk   (0x3UL)

CRG_TOP BOD_CTRL_REG: BOD_VDD_TRIM (Bitfield-Mask: 0x03)

Definition at line 4218 of file DA14680BA.h.

◆ CRG_TOP_BOD_CTRL_REG_BOD_VDD_TRIM_Pos

#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_TRIM_Pos   (0UL)

CRG_TOP BOD_CTRL_REG: BOD_VDD_TRIM (Bit 0)

Definition at line 4217 of file DA14680BA.h.

◆ CRG_TOP_BOD_STATUS_REG_BOD_1V8_FLASH_LOW_Msk

#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_FLASH_LOW_Msk   (0x4UL)

CRG_TOP BOD_STATUS_REG: BOD_1V8_FLASH_LOW (Bitfield-Mask: 0x01)

Definition at line 4250 of file DA14680BA.h.

◆ CRG_TOP_BOD_STATUS_REG_BOD_1V8_FLASH_LOW_Pos

#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_FLASH_LOW_Pos   (2UL)

CRG_TOP BOD_STATUS_REG: BOD_1V8_FLASH_LOW (Bit 2)

Definition at line 4249 of file DA14680BA.h.

◆ CRG_TOP_BOD_STATUS_REG_BOD_1V8_PA_LOW_Msk

#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_PA_LOW_Msk   (0x2UL)

CRG_TOP BOD_STATUS_REG: BOD_1V8_PA_LOW (Bitfield-Mask: 0x01)

Definition at line 4248 of file DA14680BA.h.

◆ CRG_TOP_BOD_STATUS_REG_BOD_1V8_PA_LOW_Pos

#define CRG_TOP_BOD_STATUS_REG_BOD_1V8_PA_LOW_Pos   (1UL)

CRG_TOP BOD_STATUS_REG: BOD_1V8_PA_LOW (Bit 1)

Definition at line 4247 of file DA14680BA.h.

◆ CRG_TOP_BOD_STATUS_REG_BOD_V14_LOW_Msk

#define CRG_TOP_BOD_STATUS_REG_BOD_V14_LOW_Msk   (0x20UL)

CRG_TOP BOD_STATUS_REG: BOD_V14_LOW (Bitfield-Mask: 0x01)

Definition at line 4256 of file DA14680BA.h.

◆ CRG_TOP_BOD_STATUS_REG_BOD_V14_LOW_Pos

#define CRG_TOP_BOD_STATUS_REG_BOD_V14_LOW_Pos   (5UL)

CRG_TOP BOD_STATUS_REG: BOD_V14_LOW (Bit 5)

Definition at line 4255 of file DA14680BA.h.

◆ CRG_TOP_BOD_STATUS_REG_BOD_V33_LOW_Msk

#define CRG_TOP_BOD_STATUS_REG_BOD_V33_LOW_Msk   (0x8UL)

CRG_TOP BOD_STATUS_REG: BOD_V33_LOW (Bitfield-Mask: 0x01)

Definition at line 4252 of file DA14680BA.h.

◆ CRG_TOP_BOD_STATUS_REG_BOD_V33_LOW_Pos

#define CRG_TOP_BOD_STATUS_REG_BOD_V33_LOW_Pos   (3UL)

CRG_TOP BOD_STATUS_REG: BOD_V33_LOW (Bit 3)

Definition at line 4251 of file DA14680BA.h.

◆ CRG_TOP_BOD_STATUS_REG_BOD_VBAT_LOW_Msk

#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_LOW_Msk   (0x10UL)

CRG_TOP BOD_STATUS_REG: BOD_VBAT_LOW (Bitfield-Mask: 0x01)

Definition at line 4254 of file DA14680BA.h.

◆ CRG_TOP_BOD_STATUS_REG_BOD_VBAT_LOW_Pos

#define CRG_TOP_BOD_STATUS_REG_BOD_VBAT_LOW_Pos   (4UL)

CRG_TOP BOD_STATUS_REG: BOD_VBAT_LOW (Bit 4)

Definition at line 4253 of file DA14680BA.h.

◆ CRG_TOP_BOD_STATUS_REG_BOD_VDD_LOW_Msk

#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_LOW_Msk   (0x1UL)

CRG_TOP BOD_STATUS_REG: BOD_VDD_LOW (Bitfield-Mask: 0x01)

Definition at line 4246 of file DA14680BA.h.

◆ CRG_TOP_BOD_STATUS_REG_BOD_VDD_LOW_Pos

#define CRG_TOP_BOD_STATUS_REG_BOD_VDD_LOW_Pos   (0UL)

CRG_TOP BOD_STATUS_REG: BOD_VDD_LOW (Bit 0)

Definition at line 4245 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Msk

#define CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Msk   (0x1UL)

CRG_TOP CLK_16M_REG: RC16M_ENABLE (Bitfield-Mask: 0x01)

Definition at line 4102 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Pos

#define CRG_TOP_CLK_16M_REG_RC16M_ENABLE_Pos   (0UL)

CRG_TOP CLK_16M_REG: RC16M_ENABLE (Bit 0)

Definition at line 4101 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_RC16M_STARTUP_DISABLE_Msk

#define CRG_TOP_CLK_16M_REG_RC16M_STARTUP_DISABLE_Msk   (0x8000UL)

CRG_TOP CLK_16M_REG: RC16M_STARTUP_DISABLE (Bitfield-Mask: 0x01)

Definition at line 4118 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_RC16M_STARTUP_DISABLE_Pos

#define CRG_TOP_CLK_16M_REG_RC16M_STARTUP_DISABLE_Pos   (15UL)

CRG_TOP CLK_16M_REG: RC16M_STARTUP_DISABLE (Bit 15)

Definition at line 4117 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_RC16M_TRIM_Msk

#define CRG_TOP_CLK_16M_REG_RC16M_TRIM_Msk   (0x1eUL)

CRG_TOP CLK_16M_REG: RC16M_TRIM (Bitfield-Mask: 0x0f)

Definition at line 4104 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_RC16M_TRIM_Pos

#define CRG_TOP_CLK_16M_REG_RC16M_TRIM_Pos   (1UL)

CRG_TOP CLK_16M_REG: RC16M_TRIM (Bit 1)

Definition at line 4103 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_XTAL16_AMP_TRIM_Msk

#define CRG_TOP_CLK_16M_REG_XTAL16_AMP_TRIM_Msk   (0x1c00UL)

CRG_TOP CLK_16M_REG: XTAL16_AMP_TRIM (Bitfield-Mask: 0x07)

Definition at line 4112 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_XTAL16_AMP_TRIM_Pos

#define CRG_TOP_CLK_16M_REG_XTAL16_AMP_TRIM_Pos   (10UL)

CRG_TOP CLK_16M_REG: XTAL16_AMP_TRIM (Bit 10)

Definition at line 4111 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_XTAL16_CUR_SET_Msk

#define CRG_TOP_CLK_16M_REG_XTAL16_CUR_SET_Msk   (0xe0UL)

CRG_TOP CLK_16M_REG: XTAL16_CUR_SET (Bitfield-Mask: 0x07)

Definition at line 4106 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_XTAL16_CUR_SET_Pos

#define CRG_TOP_CLK_16M_REG_XTAL16_CUR_SET_Pos   (5UL)

CRG_TOP CLK_16M_REG: XTAL16_CUR_SET (Bit 5)

Definition at line 4105 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_XTAL16_EXT_CLK_ENABLE_Msk

#define CRG_TOP_CLK_16M_REG_XTAL16_EXT_CLK_ENABLE_Msk   (0x200UL)

CRG_TOP CLK_16M_REG: XTAL16_EXT_CLK_ENABLE (Bitfield-Mask: 0x01)

Definition at line 4110 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_XTAL16_EXT_CLK_ENABLE_Pos

#define CRG_TOP_CLK_16M_REG_XTAL16_EXT_CLK_ENABLE_Pos   (9UL)

CRG_TOP CLK_16M_REG: XTAL16_EXT_CLK_ENABLE (Bit 9)

Definition at line 4109 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_XTAL16_HPASS_FLT_EN_Msk

#define CRG_TOP_CLK_16M_REG_XTAL16_HPASS_FLT_EN_Msk   (0x4000UL)

CRG_TOP CLK_16M_REG: XTAL16_HPASS_FLT_EN (Bitfield-Mask: 0x01)

Definition at line 4116 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_XTAL16_HPASS_FLT_EN_Pos

#define CRG_TOP_CLK_16M_REG_XTAL16_HPASS_FLT_EN_Pos   (14UL)

CRG_TOP CLK_16M_REG: XTAL16_HPASS_FLT_EN (Bit 14)

Definition at line 4115 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_XTAL16_MAX_CURRENT_Msk

#define CRG_TOP_CLK_16M_REG_XTAL16_MAX_CURRENT_Msk   (0x100UL)

CRG_TOP CLK_16M_REG: XTAL16_MAX_CURRENT (Bitfield-Mask: 0x01)

Definition at line 4108 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_XTAL16_MAX_CURRENT_Pos

#define CRG_TOP_CLK_16M_REG_XTAL16_MAX_CURRENT_Pos   (8UL)

CRG_TOP CLK_16M_REG: XTAL16_MAX_CURRENT (Bit 8)

Definition at line 4107 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_XTAL16_SPIKE_FLT_BYPASS_Msk

#define CRG_TOP_CLK_16M_REG_XTAL16_SPIKE_FLT_BYPASS_Msk   (0x2000UL)

CRG_TOP CLK_16M_REG: XTAL16_SPIKE_FLT_BYPASS (Bitfield-Mask: 0x01)

Definition at line 4114 of file DA14680BA.h.

◆ CRG_TOP_CLK_16M_REG_XTAL16_SPIKE_FLT_BYPASS_Pos

#define CRG_TOP_CLK_16M_REG_XTAL16_SPIKE_FLT_BYPASS_Pos   (13UL)

CRG_TOP CLK_16M_REG: XTAL16_SPIKE_FLT_BYPASS (Bit 13)

Definition at line 4113 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_RC32K_ENABLE_Msk

#define CRG_TOP_CLK_32K_REG_RC32K_ENABLE_Msk   (0x80UL)

CRG_TOP CLK_32K_REG: RC32K_ENABLE (Bitfield-Mask: 0x01)

Definition at line 4092 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_RC32K_ENABLE_Pos

#define CRG_TOP_CLK_32K_REG_RC32K_ENABLE_Pos   (7UL)

CRG_TOP CLK_32K_REG: RC32K_ENABLE (Bit 7)

Definition at line 4091 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_RC32K_TRIM_Msk

#define CRG_TOP_CLK_32K_REG_RC32K_TRIM_Msk   (0xf00UL)

CRG_TOP CLK_32K_REG: RC32K_TRIM (Bitfield-Mask: 0x0f)

Definition at line 4094 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_RC32K_TRIM_Pos

#define CRG_TOP_CLK_32K_REG_RC32K_TRIM_Pos   (8UL)

CRG_TOP CLK_32K_REG: RC32K_TRIM (Bit 8)

Definition at line 4093 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_XTAL32K_CUR_Msk

#define CRG_TOP_CLK_32K_REG_XTAL32K_CUR_Msk   (0x78UL)

CRG_TOP CLK_32K_REG: XTAL32K_CUR (Bitfield-Mask: 0x0f)

Definition at line 4090 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_XTAL32K_CUR_Pos

#define CRG_TOP_CLK_32K_REG_XTAL32K_CUR_Pos   (3UL)

CRG_TOP CLK_32K_REG: XTAL32K_CUR (Bit 3)

Definition at line 4089 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_XTAL32K_DISABLE_AMPREG_Msk

#define CRG_TOP_CLK_32K_REG_XTAL32K_DISABLE_AMPREG_Msk   (0x1000UL)

CRG_TOP CLK_32K_REG: XTAL32K_DISABLE_AMPREG (Bitfield-Mask: 0x01)

Definition at line 4096 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_XTAL32K_DISABLE_AMPREG_Pos

#define CRG_TOP_CLK_32K_REG_XTAL32K_DISABLE_AMPREG_Pos   (12UL)

CRG_TOP CLK_32K_REG: XTAL32K_DISABLE_AMPREG (Bit 12)

Definition at line 4095 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_XTAL32K_ENABLE_Msk

#define CRG_TOP_CLK_32K_REG_XTAL32K_ENABLE_Msk   (0x1UL)

CRG_TOP CLK_32K_REG: XTAL32K_ENABLE (Bitfield-Mask: 0x01)

Definition at line 4086 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_XTAL32K_ENABLE_Pos

#define CRG_TOP_CLK_32K_REG_XTAL32K_ENABLE_Pos   (0UL)

CRG_TOP CLK_32K_REG: XTAL32K_ENABLE (Bit 0)

Definition at line 4085 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_XTAL32K_RBIAS_Msk

#define CRG_TOP_CLK_32K_REG_XTAL32K_RBIAS_Msk   (0x6UL)

CRG_TOP CLK_32K_REG: XTAL32K_RBIAS (Bitfield-Mask: 0x03)

Definition at line 4088 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_XTAL32K_RBIAS_Pos

#define CRG_TOP_CLK_32K_REG_XTAL32K_RBIAS_Pos   (1UL)

CRG_TOP CLK_32K_REG: XTAL32K_RBIAS (Bit 1)

Definition at line 4087 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_XTAL32K_XTAL1_BIAS_DISABLE_Msk

#define CRG_TOP_CLK_32K_REG_XTAL32K_XTAL1_BIAS_DISABLE_Msk   (0x2000UL)

CRG_TOP CLK_32K_REG: XTAL32K_XTAL1_BIAS_DISABLE (Bitfield-Mask: 0x01)

Definition at line 4098 of file DA14680BA.h.

◆ CRG_TOP_CLK_32K_REG_XTAL32K_XTAL1_BIAS_DISABLE_Pos

#define CRG_TOP_CLK_32K_REG_XTAL32K_XTAL1_BIAS_DISABLE_Pos   (13UL)

CRG_TOP CLK_32K_REG: XTAL32K_XTAL1_BIAS_DISABLE (Bit 13)

Definition at line 4097 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk

#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk   (0x40UL)

CRG_TOP CLK_AMBA_REG: AES_CLK_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3910 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Pos

#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Pos   (6UL)

CRG_TOP CLK_AMBA_REG: AES_CLK_ENABLE (Bit 6)

Definition at line 3909 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_ECC_CLK_ENABLE_Msk

#define CRG_TOP_CLK_AMBA_REG_ECC_CLK_ENABLE_Msk   (0x80UL)

CRG_TOP CLK_AMBA_REG: ECC_CLK_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3912 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_ECC_CLK_ENABLE_Pos

#define CRG_TOP_CLK_AMBA_REG_ECC_CLK_ENABLE_Pos   (7UL)

CRG_TOP CLK_AMBA_REG: ECC_CLK_ENABLE (Bit 7)

Definition at line 3911 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk

#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk   (0x7UL)

CRG_TOP CLK_AMBA_REG: HCLK_DIV (Bitfield-Mask: 0x07)

Definition at line 3906 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Pos

#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Pos   (0UL)

CRG_TOP CLK_AMBA_REG: HCLK_DIV (Bit 0)

Definition at line 3905 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk

#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Msk   (0x200UL)

CRG_TOP CLK_AMBA_REG: OTP_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3916 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Pos

#define CRG_TOP_CLK_AMBA_REG_OTP_ENABLE_Pos   (9UL)

CRG_TOP CLK_AMBA_REG: OTP_ENABLE (Bit 9)

Definition at line 3915 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk

#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk   (0x30UL)

CRG_TOP CLK_AMBA_REG: PCLK_DIV (Bitfield-Mask: 0x03)

Definition at line 3908 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Pos

#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Pos   (4UL)

CRG_TOP CLK_AMBA_REG: PCLK_DIV (Bit 4)

Definition at line 3907 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Msk

#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Msk   (0xc00UL)

CRG_TOP CLK_AMBA_REG: QSPI_DIV (Bitfield-Mask: 0x03)

Definition at line 3918 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Pos

#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Pos   (10UL)

CRG_TOP CLK_AMBA_REG: QSPI_DIV (Bit 10)

Definition at line 3917 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Msk

#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Msk   (0x1000UL)

CRG_TOP CLK_AMBA_REG: QSPI_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3920 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Pos

#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Pos   (12UL)

CRG_TOP CLK_AMBA_REG: QSPI_ENABLE (Bit 12)

Definition at line 3919 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Msk

#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Msk   (0x100UL)

CRG_TOP CLK_AMBA_REG: TRNG_CLK_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3914 of file DA14680BA.h.

◆ CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Pos

#define CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Pos   (8UL)

CRG_TOP CLK_AMBA_REG: TRNG_CLK_ENABLE (Bit 8)

Definition at line 3913 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_CLK32K_SOURCE_Msk

#define CRG_TOP_CLK_CTRL_REG_CLK32K_SOURCE_Msk   (0x300UL)

CRG_TOP CLK_CTRL_REG: CLK32K_SOURCE (Bitfield-Mask: 0x03)

Definition at line 3960 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_CLK32K_SOURCE_Pos

#define CRG_TOP_CLK_CTRL_REG_CLK32K_SOURCE_Pos   (8UL)

CRG_TOP CLK_CTRL_REG: CLK32K_SOURCE (Bit 8)

Definition at line 3959 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_DIVN_SHIFT_SEL_Msk

#define CRG_TOP_CLK_CTRL_REG_DIVN_SHIFT_SEL_Msk   (0x400UL)

CRG_TOP CLK_CTRL_REG: DIVN_SHIFT_SEL (Bitfield-Mask: 0x01)

Definition at line 3962 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_DIVN_SHIFT_SEL_Pos

#define CRG_TOP_CLK_CTRL_REG_DIVN_SHIFT_SEL_Pos   (10UL)

CRG_TOP CLK_CTRL_REG: DIVN_SHIFT_SEL (Bit 10)

Definition at line 3961 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_DIVN_SYNC_LEVEL_Msk

#define CRG_TOP_CLK_CTRL_REG_DIVN_SYNC_LEVEL_Msk   (0x80UL)

CRG_TOP CLK_CTRL_REG: DIVN_SYNC_LEVEL (Bitfield-Mask: 0x01)

Definition at line 3958 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_DIVN_SYNC_LEVEL_Pos

#define CRG_TOP_CLK_CTRL_REG_DIVN_SYNC_LEVEL_Pos   (7UL)

CRG_TOP CLK_CTRL_REG: DIVN_SYNC_LEVEL (Bit 7)

Definition at line 3957 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_DIVN_XTAL32M_MODE_Msk

#define CRG_TOP_CLK_CTRL_REG_DIVN_XTAL32M_MODE_Msk   (0x40UL)

CRG_TOP CLK_CTRL_REG: DIVN_XTAL32M_MODE (Bitfield-Mask: 0x01)

Definition at line 3956 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_DIVN_XTAL32M_MODE_Pos

#define CRG_TOP_CLK_CTRL_REG_DIVN_XTAL32M_MODE_Pos   (6UL)

CRG_TOP CLK_CTRL_REG: DIVN_XTAL32M_MODE (Bit 6)

Definition at line 3955 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_PLL_DIV2_Msk

#define CRG_TOP_CLK_CTRL_REG_PLL_DIV2_Msk   (0x20UL)

CRG_TOP CLK_CTRL_REG: PLL_DIV2 (Bitfield-Mask: 0x01)

Definition at line 3954 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_PLL_DIV2_Pos

#define CRG_TOP_CLK_CTRL_REG_PLL_DIV2_Pos   (5UL)

CRG_TOP CLK_CTRL_REG: PLL_DIV2 (Bit 5)

Definition at line 3953 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_32K_Msk

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_32K_Msk   (0x1000UL)

CRG_TOP CLK_CTRL_REG: RUNNING_AT_32K (Bitfield-Mask: 0x01)

Definition at line 3964 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_32K_Pos

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_32K_Pos   (12UL)

CRG_TOP CLK_CTRL_REG: RUNNING_AT_32K (Bit 12)

Definition at line 3963 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Msk   (0x8000UL)

CRG_TOP CLK_CTRL_REG: RUNNING_AT_PLL96M (Bitfield-Mask: 0x01)

Definition at line 3970 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Pos

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_PLL96M_Pos   (15UL)

CRG_TOP CLK_CTRL_REG: RUNNING_AT_PLL96M (Bit 15)

Definition at line 3969 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC16M_Msk

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC16M_Msk   (0x2000UL)

CRG_TOP CLK_CTRL_REG: RUNNING_AT_RC16M (Bitfield-Mask: 0x01)

Definition at line 3966 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC16M_Pos

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC16M_Pos   (13UL)

CRG_TOP CLK_CTRL_REG: RUNNING_AT_RC16M (Bit 13)

Definition at line 3965 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL16M_Msk

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL16M_Msk   (0x4000UL)

CRG_TOP CLK_CTRL_REG: RUNNING_AT_XTAL16M (Bitfield-Mask: 0x01)

Definition at line 3968 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL16M_Pos

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL16M_Pos   (14UL)

CRG_TOP CLK_CTRL_REG: RUNNING_AT_XTAL16M (Bit 14)

Definition at line 3967 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk

#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk   (0x3UL)

CRG_TOP CLK_CTRL_REG: SYS_CLK_SEL (Bitfield-Mask: 0x03)

Definition at line 3946 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos

#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos   (0UL)

CRG_TOP CLK_CTRL_REG: SYS_CLK_SEL (Bit 0)

Definition at line 3945 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk

#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Msk   (0x10UL)

CRG_TOP CLK_CTRL_REG: USB_CLK_SRC (Bitfield-Mask: 0x01)

Definition at line 3952 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Pos

#define CRG_TOP_CLK_CTRL_REG_USB_CLK_SRC_Pos   (4UL)

CRG_TOP CLK_CTRL_REG: USB_CLK_SRC (Bit 4)

Definition at line 3951 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_XTAL16M_DISABLE_Msk

#define CRG_TOP_CLK_CTRL_REG_XTAL16M_DISABLE_Msk   (0x4UL)

CRG_TOP CLK_CTRL_REG: XTAL16M_DISABLE (Bitfield-Mask: 0x01)

Definition at line 3948 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_XTAL16M_DISABLE_Pos

#define CRG_TOP_CLK_CTRL_REG_XTAL16M_DISABLE_Pos   (2UL)

CRG_TOP CLK_CTRL_REG: XTAL16M_DISABLE (Bit 2)

Definition at line 3947 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_XTAL32M_MODE_Msk

#define CRG_TOP_CLK_CTRL_REG_XTAL32M_MODE_Msk   (0x8UL)

CRG_TOP CLK_CTRL_REG: XTAL32M_MODE (Bitfield-Mask: 0x01)

Definition at line 3950 of file DA14680BA.h.

◆ CRG_TOP_CLK_CTRL_REG_XTAL32M_MODE_Pos

#define CRG_TOP_CLK_CTRL_REG_XTAL32M_MODE_Pos   (3UL)

CRG_TOP CLK_CTRL_REG: XTAL32M_MODE (Bit 3)

Definition at line 3949 of file DA14680BA.h.

◆ CRG_TOP_CLK_FREQ_TRIM_REG_COARSE_ADJ_Msk

#define CRG_TOP_CLK_FREQ_TRIM_REG_COARSE_ADJ_Msk   (0x700UL)

CRG_TOP CLK_FREQ_TRIM_REG: COARSE_ADJ (Bitfield-Mask: 0x07)

Definition at line 3926 of file DA14680BA.h.

◆ CRG_TOP_CLK_FREQ_TRIM_REG_COARSE_ADJ_Pos

#define CRG_TOP_CLK_FREQ_TRIM_REG_COARSE_ADJ_Pos   (8UL)

CRG_TOP CLK_FREQ_TRIM_REG: COARSE_ADJ (Bit 8)

Definition at line 3925 of file DA14680BA.h.

◆ CRG_TOP_CLK_FREQ_TRIM_REG_FINE_ADJ_Msk

#define CRG_TOP_CLK_FREQ_TRIM_REG_FINE_ADJ_Msk   (0xffUL)

CRG_TOP CLK_FREQ_TRIM_REG: FINE_ADJ (Bitfield-Mask: 0xff)

Definition at line 3924 of file DA14680BA.h.

◆ CRG_TOP_CLK_FREQ_TRIM_REG_FINE_ADJ_Pos

#define CRG_TOP_CLK_FREQ_TRIM_REG_FINE_ADJ_Pos   (0UL)

CRG_TOP CLK_FREQ_TRIM_REG: FINE_ADJ (Bit 0)

Definition at line 3923 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_BLE_DIV_Msk

#define CRG_TOP_CLK_RADIO_REG_BLE_DIV_Msk   (0x30UL)

CRG_TOP CLK_RADIO_REG: BLE_DIV (Bitfield-Mask: 0x03)

Definition at line 3934 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_BLE_DIV_Pos

#define CRG_TOP_CLK_RADIO_REG_BLE_DIV_Pos   (4UL)

CRG_TOP CLK_RADIO_REG: BLE_DIV (Bit 4)

Definition at line 3933 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_BLE_ENABLE_Msk

#define CRG_TOP_CLK_RADIO_REG_BLE_ENABLE_Msk   (0x80UL)

CRG_TOP CLK_RADIO_REG: BLE_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3938 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_BLE_ENABLE_Pos

#define CRG_TOP_CLK_RADIO_REG_BLE_ENABLE_Pos   (7UL)

CRG_TOP CLK_RADIO_REG: BLE_ENABLE (Bit 7)

Definition at line 3937 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_BLE_LP_RESET_Msk

#define CRG_TOP_CLK_RADIO_REG_BLE_LP_RESET_Msk   (0x40UL)

CRG_TOP CLK_RADIO_REG: BLE_LP_RESET (Bitfield-Mask: 0x01)

Definition at line 3936 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_BLE_LP_RESET_Pos

#define CRG_TOP_CLK_RADIO_REG_BLE_LP_RESET_Pos   (6UL)

CRG_TOP CLK_RADIO_REG: BLE_LP_RESET (Bit 6)

Definition at line 3935 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_FTDF_MAC_DIV_Msk

#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_DIV_Msk   (0x300UL)

CRG_TOP CLK_RADIO_REG: FTDF_MAC_DIV (Bitfield-Mask: 0x03)

Definition at line 3940 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_FTDF_MAC_DIV_Pos

#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_DIV_Pos   (8UL)

CRG_TOP CLK_RADIO_REG: FTDF_MAC_DIV (Bit 8)

Definition at line 3939 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_FTDF_MAC_ENABLE_Msk

#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_ENABLE_Msk   (0x800UL)

CRG_TOP CLK_RADIO_REG: FTDF_MAC_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3942 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_FTDF_MAC_ENABLE_Pos

#define CRG_TOP_CLK_RADIO_REG_FTDF_MAC_ENABLE_Pos   (11UL)

CRG_TOP CLK_RADIO_REG: FTDF_MAC_ENABLE (Bit 11)

Definition at line 3941 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_RFCU_DIV_Msk

#define CRG_TOP_CLK_RADIO_REG_RFCU_DIV_Msk   (0x3UL)

CRG_TOP CLK_RADIO_REG: RFCU_DIV (Bitfield-Mask: 0x03)

Definition at line 3930 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_RFCU_DIV_Pos

#define CRG_TOP_CLK_RADIO_REG_RFCU_DIV_Pos   (0UL)

CRG_TOP CLK_RADIO_REG: RFCU_DIV (Bit 0)

Definition at line 3929 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Msk

#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Msk   (0x8UL)

CRG_TOP CLK_RADIO_REG: RFCU_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3932 of file DA14680BA.h.

◆ CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos

#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos   (3UL)

CRG_TOP CLK_RADIO_REG: RFCU_ENABLE (Bit 3)

Definition at line 3931 of file DA14680BA.h.

◆ CRG_TOP_CLK_RCX20K_REG_RCX20K_BIAS_Msk

#define CRG_TOP_CLK_RCX20K_REG_RCX20K_BIAS_Msk   (0x300UL)

CRG_TOP CLK_RCX20K_REG: RCX20K_BIAS (Bitfield-Mask: 0x03)

Definition at line 4126 of file DA14680BA.h.

◆ CRG_TOP_CLK_RCX20K_REG_RCX20K_BIAS_Pos

#define CRG_TOP_CLK_RCX20K_REG_RCX20K_BIAS_Pos   (8UL)

CRG_TOP CLK_RCX20K_REG: RCX20K_BIAS (Bit 8)

Definition at line 4125 of file DA14680BA.h.

◆ CRG_TOP_CLK_RCX20K_REG_RCX20K_ENABLE_Msk

#define CRG_TOP_CLK_RCX20K_REG_RCX20K_ENABLE_Msk   (0x800UL)

CRG_TOP CLK_RCX20K_REG: RCX20K_ENABLE (Bitfield-Mask: 0x01)

Definition at line 4130 of file DA14680BA.h.

◆ CRG_TOP_CLK_RCX20K_REG_RCX20K_ENABLE_Pos

#define CRG_TOP_CLK_RCX20K_REG_RCX20K_ENABLE_Pos   (11UL)

CRG_TOP CLK_RCX20K_REG: RCX20K_ENABLE (Bit 11)

Definition at line 4129 of file DA14680BA.h.

◆ CRG_TOP_CLK_RCX20K_REG_RCX20K_LOWF_Msk

#define CRG_TOP_CLK_RCX20K_REG_RCX20K_LOWF_Msk   (0x400UL)

CRG_TOP CLK_RCX20K_REG: RCX20K_LOWF (Bitfield-Mask: 0x01)

Definition at line 4128 of file DA14680BA.h.

◆ CRG_TOP_CLK_RCX20K_REG_RCX20K_LOWF_Pos

#define CRG_TOP_CLK_RCX20K_REG_RCX20K_LOWF_Pos   (10UL)

CRG_TOP CLK_RCX20K_REG: RCX20K_LOWF (Bit 10)

Definition at line 4127 of file DA14680BA.h.

◆ CRG_TOP_CLK_RCX20K_REG_RCX20K_NTC_Msk

#define CRG_TOP_CLK_RCX20K_REG_RCX20K_NTC_Msk   (0xf0UL)

CRG_TOP CLK_RCX20K_REG: RCX20K_NTC (Bitfield-Mask: 0x0f)

Definition at line 4124 of file DA14680BA.h.

◆ CRG_TOP_CLK_RCX20K_REG_RCX20K_NTC_Pos

#define CRG_TOP_CLK_RCX20K_REG_RCX20K_NTC_Pos   (4UL)

CRG_TOP CLK_RCX20K_REG: RCX20K_NTC (Bit 4)

Definition at line 4123 of file DA14680BA.h.

◆ CRG_TOP_CLK_RCX20K_REG_RCX20K_TRIM_Msk

#define CRG_TOP_CLK_RCX20K_REG_RCX20K_TRIM_Msk   (0xfUL)

CRG_TOP CLK_RCX20K_REG: RCX20K_TRIM (Bitfield-Mask: 0x0f)

Definition at line 4122 of file DA14680BA.h.

◆ CRG_TOP_CLK_RCX20K_REG_RCX20K_TRIM_Pos

#define CRG_TOP_CLK_RCX20K_REG_RCX20K_TRIM_Pos   (0UL)

CRG_TOP CLK_RCX20K_REG: RCX20K_TRIM (Bit 0)

Definition at line 4121 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_BREATH_ENABLE_Msk

#define CRG_TOP_CLK_TMR_REG_BREATH_ENABLE_Msk   (0x1000UL)

CRG_TOP CLK_TMR_REG: BREATH_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3992 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_BREATH_ENABLE_Pos

#define CRG_TOP_CLK_TMR_REG_BREATH_ENABLE_Pos   (12UL)

CRG_TOP CLK_TMR_REG: BREATH_ENABLE (Bit 12)

Definition at line 3991 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_P06_TMR1_PWM_MODE_Msk

#define CRG_TOP_CLK_TMR_REG_P06_TMR1_PWM_MODE_Msk   (0x4000UL)

CRG_TOP CLK_TMR_REG: P06_TMR1_PWM_MODE (Bitfield-Mask: 0x01)

Definition at line 3996 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_P06_TMR1_PWM_MODE_Pos

#define CRG_TOP_CLK_TMR_REG_P06_TMR1_PWM_MODE_Pos   (14UL)

CRG_TOP CLK_TMR_REG: P06_TMR1_PWM_MODE (Bit 14)

Definition at line 3995 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Msk

#define CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Msk   (0x8UL)

CRG_TOP CLK_TMR_REG: TMR0_CLK_SEL (Bitfield-Mask: 0x01)

Definition at line 3978 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Pos

#define CRG_TOP_CLK_TMR_REG_TMR0_CLK_SEL_Pos   (3UL)

CRG_TOP CLK_TMR_REG: TMR0_CLK_SEL (Bit 3)

Definition at line 3977 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR0_DIV_Msk

#define CRG_TOP_CLK_TMR_REG_TMR0_DIV_Msk   (0x3UL)

CRG_TOP CLK_TMR_REG: TMR0_DIV (Bitfield-Mask: 0x03)

Definition at line 3974 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR0_DIV_Pos

#define CRG_TOP_CLK_TMR_REG_TMR0_DIV_Pos   (0UL)

CRG_TOP CLK_TMR_REG: TMR0_DIV (Bit 0)

Definition at line 3973 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Msk

#define CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Msk   (0x4UL)

CRG_TOP CLK_TMR_REG: TMR0_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3976 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Pos

#define CRG_TOP_CLK_TMR_REG_TMR0_ENABLE_Pos   (2UL)

CRG_TOP CLK_TMR_REG: TMR0_ENABLE (Bit 2)

Definition at line 3975 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR1_CLK_SEL_Msk

#define CRG_TOP_CLK_TMR_REG_TMR1_CLK_SEL_Msk   (0x80UL)

CRG_TOP CLK_TMR_REG: TMR1_CLK_SEL (Bitfield-Mask: 0x01)

Definition at line 3984 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR1_CLK_SEL_Pos

#define CRG_TOP_CLK_TMR_REG_TMR1_CLK_SEL_Pos   (7UL)

CRG_TOP CLK_TMR_REG: TMR1_CLK_SEL (Bit 7)

Definition at line 3983 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR1_DIV_Msk

#define CRG_TOP_CLK_TMR_REG_TMR1_DIV_Msk   (0x30UL)

CRG_TOP CLK_TMR_REG: TMR1_DIV (Bitfield-Mask: 0x03)

Definition at line 3980 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR1_DIV_Pos

#define CRG_TOP_CLK_TMR_REG_TMR1_DIV_Pos   (4UL)

CRG_TOP CLK_TMR_REG: TMR1_DIV (Bit 4)

Definition at line 3979 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR1_ENABLE_Msk

#define CRG_TOP_CLK_TMR_REG_TMR1_ENABLE_Msk   (0x40UL)

CRG_TOP CLK_TMR_REG: TMR1_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3982 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR1_ENABLE_Pos

#define CRG_TOP_CLK_TMR_REG_TMR1_ENABLE_Pos   (6UL)

CRG_TOP CLK_TMR_REG: TMR1_ENABLE (Bit 6)

Definition at line 3981 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR2_CLK_SEL_Msk

#define CRG_TOP_CLK_TMR_REG_TMR2_CLK_SEL_Msk   (0x800UL)

CRG_TOP CLK_TMR_REG: TMR2_CLK_SEL (Bitfield-Mask: 0x01)

Definition at line 3990 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR2_CLK_SEL_Pos

#define CRG_TOP_CLK_TMR_REG_TMR2_CLK_SEL_Pos   (11UL)

CRG_TOP CLK_TMR_REG: TMR2_CLK_SEL (Bit 11)

Definition at line 3989 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR2_DIV_Msk

#define CRG_TOP_CLK_TMR_REG_TMR2_DIV_Msk   (0x300UL)

CRG_TOP CLK_TMR_REG: TMR2_DIV (Bitfield-Mask: 0x03)

Definition at line 3986 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR2_DIV_Pos

#define CRG_TOP_CLK_TMR_REG_TMR2_DIV_Pos   (8UL)

CRG_TOP CLK_TMR_REG: TMR2_DIV (Bit 8)

Definition at line 3985 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR2_ENABLE_Msk

#define CRG_TOP_CLK_TMR_REG_TMR2_ENABLE_Msk   (0x400UL)

CRG_TOP CLK_TMR_REG: TMR2_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3988 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_TMR2_ENABLE_Pos

#define CRG_TOP_CLK_TMR_REG_TMR2_ENABLE_Pos   (10UL)

CRG_TOP CLK_TMR_REG: TMR2_ENABLE (Bit 10)

Definition at line 3987 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk

#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk   (0x2000UL)

CRG_TOP CLK_TMR_REG: WAKEUPCT_ENABLE (Bitfield-Mask: 0x01)

Definition at line 3994 of file DA14680BA.h.

◆ CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Pos

#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Pos   (13UL)

CRG_TOP CLK_TMR_REG: WAKEUPCT_ENABLE (Bit 13)

Definition at line 3993 of file DA14680BA.h.

◆ CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Msk

#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Msk   (0x1UL)

CRG_TOP DISCHARGE_RAIL_REG: RESET_V14 (Bitfield-Mask: 0x01)

Definition at line 4396 of file DA14680BA.h.

◆ CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Pos

#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V14_Pos   (0UL)

CRG_TOP DISCHARGE_RAIL_REG: RESET_V14 (Bit 0)

Definition at line 4395 of file DA14680BA.h.

◆ CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Msk

#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Msk   (0x2UL)

CRG_TOP DISCHARGE_RAIL_REG: RESET_V18 (Bitfield-Mask: 0x01)

Definition at line 4398 of file DA14680BA.h.

◆ CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Pos

#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18_Pos   (1UL)

CRG_TOP DISCHARGE_RAIL_REG: RESET_V18 (Bit 1)

Definition at line 4397 of file DA14680BA.h.

◆ CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Msk

#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Msk   (0x4UL)

CRG_TOP DISCHARGE_RAIL_REG: RESET_V18P (Bitfield-Mask: 0x01)

Definition at line 4400 of file DA14680BA.h.

◆ CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Pos

#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_V18P_Pos   (2UL)

CRG_TOP DISCHARGE_RAIL_REG: RESET_V18P (Bit 2)

Definition at line 4399 of file DA14680BA.h.

◆ CRG_TOP_FORCE_SLEEP_REG_FORCE_BLE_SLEEP_Msk

#define CRG_TOP_FORCE_SLEEP_REG_FORCE_BLE_SLEEP_Msk   (0x2UL)

CRG_TOP FORCE_SLEEP_REG: FORCE_BLE_SLEEP (Bitfield-Mask: 0x01)

Definition at line 4364 of file DA14680BA.h.

◆ CRG_TOP_FORCE_SLEEP_REG_FORCE_BLE_SLEEP_Pos

#define CRG_TOP_FORCE_SLEEP_REG_FORCE_BLE_SLEEP_Pos   (1UL)

CRG_TOP FORCE_SLEEP_REG: FORCE_BLE_SLEEP (Bit 1)

Definition at line 4363 of file DA14680BA.h.

◆ CRG_TOP_FORCE_SLEEP_REG_FORCE_FTDF_SLEEP_Msk

#define CRG_TOP_FORCE_SLEEP_REG_FORCE_FTDF_SLEEP_Msk   (0x1UL)

CRG_TOP FORCE_SLEEP_REG: FORCE_FTDF_SLEEP (Bitfield-Mask: 0x01)

Definition at line 4362 of file DA14680BA.h.

◆ CRG_TOP_FORCE_SLEEP_REG_FORCE_FTDF_SLEEP_Pos

#define CRG_TOP_FORCE_SLEEP_REG_FORCE_FTDF_SLEEP_Pos   (0UL)

CRG_TOP FORCE_SLEEP_REG: FORCE_FTDF_SLEEP (Bit 0)

Definition at line 4361 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_CORE_CURLIM_Msk

#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_CURLIM_Msk   (0x3UL)

CRG_TOP LDO_CTRL1_REG: LDO_CORE_CURLIM (Bitfield-Mask: 0x03)

Definition at line 4260 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_CORE_CURLIM_Pos

#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_CURLIM_Pos   (0UL)

CRG_TOP LDO_CTRL1_REG: LDO_CORE_CURLIM (Bit 0)

Definition at line 4259 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_CORE_SETVDD_Msk

#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_SETVDD_Msk   (0x700UL)

CRG_TOP LDO_CTRL1_REG: LDO_CORE_SETVDD (Bitfield-Mask: 0x07)

Definition at line 4268 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_CORE_SETVDD_Pos

#define CRG_TOP_LDO_CTRL1_REG_LDO_CORE_SETVDD_Pos   (8UL)

CRG_TOP LDO_CTRL1_REG: LDO_CORE_SETVDD (Bit 8)

Definition at line 4267 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_ENABLE_Msk

#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_ENABLE_Msk   (0x4000UL)

CRG_TOP LDO_CTRL1_REG: LDO_RADIO_ENABLE (Bitfield-Mask: 0x01)

Definition at line 4272 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_ENABLE_Pos

#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_ENABLE_Pos   (14UL)

CRG_TOP LDO_CTRL1_REG: LDO_RADIO_ENABLE (Bit 14)

Definition at line 4271 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_SETVDD_Msk

#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_SETVDD_Msk   (0x3800UL)

CRG_TOP LDO_CTRL1_REG: LDO_RADIO_SETVDD (Bitfield-Mask: 0x07)

Definition at line 4270 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_SETVDD_Pos

#define CRG_TOP_LDO_CTRL1_REG_LDO_RADIO_SETVDD_Pos   (11UL)

CRG_TOP LDO_CTRL1_REG: LDO_RADIO_SETVDD (Bit 11)

Definition at line 4269 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_USB_LEVEL_Msk

#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_USB_LEVEL_Msk   (0xc0UL)

CRG_TOP LDO_CTRL1_REG: LDO_SUPPLY_USB_LEVEL (Bitfield-Mask: 0x03)

Definition at line 4266 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_USB_LEVEL_Pos

#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_USB_LEVEL_Pos   (6UL)

CRG_TOP LDO_CTRL1_REG: LDO_SUPPLY_USB_LEVEL (Bit 6)

Definition at line 4265 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_VBAT_LEVEL_Msk

#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_VBAT_LEVEL_Msk   (0x30UL)

CRG_TOP LDO_CTRL1_REG: LDO_SUPPLY_VBAT_LEVEL (Bitfield-Mask: 0x03)

Definition at line 4264 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_VBAT_LEVEL_Pos

#define CRG_TOP_LDO_CTRL1_REG_LDO_SUPPLY_VBAT_LEVEL_Pos   (4UL)

CRG_TOP LDO_CTRL1_REG: LDO_SUPPLY_VBAT_LEVEL (Bit 4)

Definition at line 4263 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_VBAT_RET_LEVEL_Msk

#define CRG_TOP_LDO_CTRL1_REG_LDO_VBAT_RET_LEVEL_Msk   (0xcUL)

CRG_TOP LDO_CTRL1_REG: LDO_VBAT_RET_LEVEL (Bitfield-Mask: 0x03)

Definition at line 4262 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL1_REG_LDO_VBAT_RET_LEVEL_Pos

#define CRG_TOP_LDO_CTRL1_REG_LDO_VBAT_RET_LEVEL_Pos   (2UL)

CRG_TOP LDO_CTRL1_REG: LDO_VBAT_RET_LEVEL (Bit 2)

Definition at line 4261 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_1V2_ON_Msk

#define CRG_TOP_LDO_CTRL2_REG_LDO_1V2_ON_Msk   (0x1UL)

CRG_TOP LDO_CTRL2_REG: LDO_1V2_ON (Bitfield-Mask: 0x01)

Definition at line 4276 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_1V2_ON_Pos

#define CRG_TOP_LDO_CTRL2_REG_LDO_1V2_ON_Pos   (0UL)

CRG_TOP LDO_CTRL2_REG: LDO_1V2_ON (Bit 0)

Definition at line 4275 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_ON_Msk

#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_ON_Msk   (0x4UL)

CRG_TOP LDO_CTRL2_REG: LDO_1V8_FLASH_ON (Bitfield-Mask: 0x01)

Definition at line 4280 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_ON_Pos

#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_ON_Pos   (2UL)

CRG_TOP LDO_CTRL2_REG: LDO_1V8_FLASH_ON (Bit 2)

Definition at line 4279 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_RET_DISABLE_Msk

#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_RET_DISABLE_Msk   (0x20UL)

CRG_TOP LDO_CTRL2_REG: LDO_1V8_FLASH_RET_DISABLE (Bitfield-Mask: 0x01)

Definition at line 4286 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_RET_DISABLE_Pos

#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_FLASH_RET_DISABLE_Pos   (5UL)

CRG_TOP LDO_CTRL2_REG: LDO_1V8_FLASH_RET_DISABLE (Bit 5)

Definition at line 4285 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_ON_Msk

#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_ON_Msk   (0x8UL)

CRG_TOP LDO_CTRL2_REG: LDO_1V8_PA_ON (Bitfield-Mask: 0x01)

Definition at line 4282 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_ON_Pos

#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_ON_Pos   (3UL)

CRG_TOP LDO_CTRL2_REG: LDO_1V8_PA_ON (Bit 3)

Definition at line 4281 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_RET_DISABLE_Msk

#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_RET_DISABLE_Msk   (0x40UL)

CRG_TOP LDO_CTRL2_REG: LDO_1V8_PA_RET_DISABLE (Bitfield-Mask: 0x01)

Definition at line 4288 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_RET_DISABLE_Pos

#define CRG_TOP_LDO_CTRL2_REG_LDO_1V8_PA_RET_DISABLE_Pos   (6UL)

CRG_TOP LDO_CTRL2_REG: LDO_1V8_PA_RET_DISABLE (Bit 6)

Definition at line 4287 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_3V3_ON_Msk

#define CRG_TOP_LDO_CTRL2_REG_LDO_3V3_ON_Msk   (0x2UL)

CRG_TOP LDO_CTRL2_REG: LDO_3V3_ON (Bitfield-Mask: 0x01)

Definition at line 4278 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_3V3_ON_Pos

#define CRG_TOP_LDO_CTRL2_REG_LDO_3V3_ON_Pos   (1UL)

CRG_TOP LDO_CTRL2_REG: LDO_3V3_ON (Bit 1)

Definition at line 4277 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_VBAT_RET_DISABLE_Msk

#define CRG_TOP_LDO_CTRL2_REG_LDO_VBAT_RET_DISABLE_Msk   (0x10UL)

CRG_TOP LDO_CTRL2_REG: LDO_VBAT_RET_DISABLE (Bitfield-Mask: 0x01)

Definition at line 4284 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL2_REG_LDO_VBAT_RET_DISABLE_Pos

#define CRG_TOP_LDO_CTRL2_REG_LDO_VBAT_RET_DISABLE_Pos   (4UL)

CRG_TOP LDO_CTRL2_REG: LDO_VBAT_RET_DISABLE (Bit 4)

Definition at line 4283 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_ENABLE_Msk

#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_ENABLE_Msk   (0x4UL)

CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_ENABLE (Bitfield-Mask: 0x01)

Definition at line 4324 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_ENABLE_Pos

#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_ENABLE_Pos   (2UL)

CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_ENABLE (Bit 2)

Definition at line 4323 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_VREF_HOLD_Msk

#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_VREF_HOLD_Msk   (0x8UL)

CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_VREF_HOLD (Bitfield-Mask: 0x01)

Definition at line 4326 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_VREF_HOLD_Pos

#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_FLASH_RET_VREF_HOLD_Pos   (3UL)

CRG_TOP LDO_CTRL3_REG: LDO_1V8_FLASH_RET_VREF_HOLD (Bit 3)

Definition at line 4325 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_ENABLE_Msk

#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_ENABLE_Msk   (0x10UL)

CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_ENABLE (Bitfield-Mask: 0x01)

Definition at line 4328 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_ENABLE_Pos

#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_ENABLE_Pos   (4UL)

CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_ENABLE (Bit 4)

Definition at line 4327 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Msk

#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Msk   (0x20UL)

CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_VREF_HOLD (Bitfield-Mask: 0x01)

Definition at line 4330 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Pos

#define CRG_TOP_LDO_CTRL3_REG_LDO_1V8_PA_RET_VREF_HOLD_Pos   (5UL)

CRG_TOP LDO_CTRL3_REG: LDO_1V8_PA_RET_VREF_HOLD (Bit 5)

Definition at line 4329 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_ENABLE_Msk

#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_ENABLE_Msk   (0x1UL)

CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_ENABLE (Bitfield-Mask: 0x01)

Definition at line 4320 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_ENABLE_Pos

#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_ENABLE_Pos   (0UL)

CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_ENABLE (Bit 0)

Definition at line 4319 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_VREF_HOLD_Msk

#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_VREF_HOLD_Msk   (0x2UL)

CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_VREF_HOLD (Bitfield-Mask: 0x01)

Definition at line 4322 of file DA14680BA.h.

◆ CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_VREF_HOLD_Pos

#define CRG_TOP_LDO_CTRL3_REG_LDO_VBAT_RET_VREF_HOLD_Pos   (1UL)

CRG_TOP LDO_CTRL3_REG: LDO_VBAT_RET_VREF_HOLD (Bit 1)

Definition at line 4321 of file DA14680BA.h.

◆ CRG_TOP_LDOS_DISABLE_REG_LDOS_DISABLE_Msk

#define CRG_TOP_LDOS_DISABLE_REG_LDOS_DISABLE_Msk   (0x1UL)

CRG_TOP LDOS_DISABLE_REG: LDOS_DISABLE (Bitfield-Mask: 0x01)

Definition at line 4368 of file DA14680BA.h.

◆ CRG_TOP_LDOS_DISABLE_REG_LDOS_DISABLE_Pos

#define CRG_TOP_LDOS_DISABLE_REG_LDOS_DISABLE_Pos   (0UL)

CRG_TOP LDOS_DISABLE_REG: LDOS_DISABLE (Bit 0)

Definition at line 4367 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Msk

#define CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Msk   (0x4UL)

CRG_TOP PMU_CTRL_REG: BLE_SLEEP (Bitfield-Mask: 0x01)

Definition at line 4004 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Pos

#define CRG_TOP_PMU_CTRL_REG_BLE_SLEEP_Pos   (2UL)

CRG_TOP PMU_CTRL_REG: BLE_SLEEP (Bit 2)

Definition at line 4003 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Msk

#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Msk   (0x2000UL)

CRG_TOP PMU_CTRL_REG: ENABLE_CLKLESS (Bitfield-Mask: 0x01)

Definition at line 4016 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Pos

#define CRG_TOP_PMU_CTRL_REG_ENABLE_CLKLESS_Pos   (13UL)

CRG_TOP PMU_CTRL_REG: ENABLE_CLKLESS (Bit 13)

Definition at line 4015 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Msk

#define CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Msk   (0x8UL)

CRG_TOP PMU_CTRL_REG: FTDF_SLEEP (Bitfield-Mask: 0x01)

Definition at line 4006 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Pos

#define CRG_TOP_PMU_CTRL_REG_FTDF_SLEEP_Pos   (3UL)

CRG_TOP PMU_CTRL_REG: FTDF_SLEEP (Bit 3)

Definition at line 4005 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Msk

#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Msk   (0x10UL)

CRG_TOP PMU_CTRL_REG: MAP_BANDGAP_EN (Bitfield-Mask: 0x01)

Definition at line 4008 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Pos

#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Pos   (4UL)

CRG_TOP PMU_CTRL_REG: MAP_BANDGAP_EN (Bit 4)

Definition at line 4007 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_OTP_COPY_DIV_Msk

#define CRG_TOP_PMU_CTRL_REG_OTP_COPY_DIV_Msk   (0xc0UL)

CRG_TOP PMU_CTRL_REG: OTP_COPY_DIV (Bitfield-Mask: 0x03)

Definition at line 4012 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_OTP_COPY_DIV_Pos

#define CRG_TOP_PMU_CTRL_REG_OTP_COPY_DIV_Pos   (6UL)

CRG_TOP PMU_CTRL_REG: OTP_COPY_DIV (Bit 6)

Definition at line 4011 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk

#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk   (0x1UL)

CRG_TOP PMU_CTRL_REG: PERIPH_SLEEP (Bitfield-Mask: 0x01)

Definition at line 4000 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos

#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos   (0UL)

CRG_TOP PMU_CTRL_REG: PERIPH_SLEEP (Bit 0)

Definition at line 3999 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk

#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk   (0x2UL)

CRG_TOP PMU_CTRL_REG: RADIO_SLEEP (Bitfield-Mask: 0x01)

Definition at line 4002 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos

#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos   (1UL)

CRG_TOP PMU_CTRL_REG: RADIO_SLEEP (Bit 1)

Definition at line 4001 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Msk

#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Msk   (0x20UL)

CRG_TOP PMU_CTRL_REG: RESET_ON_WAKEUP (Bitfield-Mask: 0x01)

Definition at line 4010 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Pos

#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Pos   (5UL)

CRG_TOP PMU_CTRL_REG: RESET_ON_WAKEUP (Bit 5)

Definition at line 4009 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Msk

#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Msk   (0x4000UL)

CRG_TOP PMU_CTRL_REG: RETAIN_CACHE (Bitfield-Mask: 0x01)

Definition at line 4018 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Pos

#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Pos   (14UL)

CRG_TOP PMU_CTRL_REG: RETAIN_CACHE (Bit 14)

Definition at line 4017 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_RETAIN_ECCRAM_Msk

#define CRG_TOP_PMU_CTRL_REG_RETAIN_ECCRAM_Msk   (0x8000UL)

CRG_TOP PMU_CTRL_REG: RETAIN_ECCRAM (Bitfield-Mask: 0x01)

Definition at line 4020 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_RETAIN_ECCRAM_Pos

#define CRG_TOP_PMU_CTRL_REG_RETAIN_ECCRAM_Pos   (15UL)

CRG_TOP PMU_CTRL_REG: RETAIN_ECCRAM (Bit 15)

Definition at line 4019 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_RETAIN_RAM_Msk

#define CRG_TOP_PMU_CTRL_REG_RETAIN_RAM_Msk   (0x1f00UL)

CRG_TOP PMU_CTRL_REG: RETAIN_RAM (Bitfield-Mask: 0x1f)

Definition at line 4014 of file DA14680BA.h.

◆ CRG_TOP_PMU_CTRL_REG_RETAIN_RAM_Pos

#define CRG_TOP_PMU_CTRL_REG_RETAIN_RAM_Pos   (8UL)

CRG_TOP PMU_CTRL_REG: RETAIN_RAM (Bit 8)

Definition at line 4013 of file DA14680BA.h.

◆ CRG_TOP_PMU_RESET_RAIL_REG_RESET_V14_Msk

#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V14_Msk   (0x1UL)

CRG_TOP PMU_RESET_RAIL_REG: RESET_V14 (Bitfield-Mask: 0x01)

Definition at line 4388 of file DA14680BA.h.

◆ CRG_TOP_PMU_RESET_RAIL_REG_RESET_V14_Pos

#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V14_Pos   (0UL)

CRG_TOP PMU_RESET_RAIL_REG: RESET_V14 (Bit 0)

Definition at line 4387 of file DA14680BA.h.

◆ CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18_Msk

#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18_Msk   (0x2UL)

CRG_TOP PMU_RESET_RAIL_REG: RESET_V18 (Bitfield-Mask: 0x01)

Definition at line 4390 of file DA14680BA.h.

◆ CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18_Pos

#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18_Pos   (1UL)

CRG_TOP PMU_RESET_RAIL_REG: RESET_V18 (Bit 1)

Definition at line 4389 of file DA14680BA.h.

◆ CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18P_Msk

#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18P_Msk   (0x4UL)

CRG_TOP PMU_RESET_RAIL_REG: RESET_V18P (Bitfield-Mask: 0x01)

Definition at line 4392 of file DA14680BA.h.

◆ CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18P_Pos

#define CRG_TOP_PMU_RESET_RAIL_REG_RESET_V18P_Pos   (2UL)

CRG_TOP PMU_RESET_RAIL_REG: RESET_V18P (Bit 2)

Definition at line 4391 of file DA14680BA.h.

◆ CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Msk

#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Msk   (0x1000UL)

CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_ENABLE (Bitfield-Mask: 0x01)

Definition at line 4306 of file DA14680BA.h.

◆ CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Pos

#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_ENABLE_Pos   (12UL)

CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_ENABLE (Bit 12)

Definition at line 4305 of file DA14680BA.h.

◆ CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Msk

#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Msk   (0xf00UL)

CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_HYST_LOW (Bitfield-Mask: 0x0f)

Definition at line 4304 of file DA14680BA.h.

◆ CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Pos

#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_HYST_LOW_Pos   (8UL)

CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_HYST_LOW (Bit 8)

Definition at line 4303 of file DA14680BA.h.

◆ CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Msk

#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Msk   (0x2000UL)

CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_MASK_N (Bitfield-Mask: 0x01)

Definition at line 4308 of file DA14680BA.h.

◆ CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Pos

#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_MASK_N_Pos   (13UL)

CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_MASK_N (Bit 13)

Definition at line 4307 of file DA14680BA.h.

◆ CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Msk

#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Msk   (0xf0UL)

CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_HIGH (Bitfield-Mask: 0x0f)

Definition at line 4302 of file DA14680BA.h.

◆ CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Pos

#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_HIGH_Pos   (4UL)

CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_HIGH (Bit 4)

Definition at line 4301 of file DA14680BA.h.

◆ CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Msk

#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Msk   (0xfUL)

CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_LOW (Bitfield-Mask: 0x0f)

Definition at line 4300 of file DA14680BA.h.

◆ CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Pos

#define CRG_TOP_POR_VBAT_CTRL_REG_POR_VBAT_THRES_LOW_Pos   (0UL)

CRG_TOP POR_VBAT_CTRL_REG: POR_VBAT_THRES_LOW (Bit 0)

Definition at line 4299 of file DA14680BA.h.

◆ CRG_TOP_POWER_CTRL_REG_TRIM_NEWBAT_Msk

#define CRG_TOP_POWER_CTRL_REG_TRIM_NEWBAT_Msk   (0x7UL)

CRG_TOP POWER_CTRL_REG: TRIM_NEWBAT (Bitfield-Mask: 0x07)

Definition at line 4296 of file DA14680BA.h.

◆ CRG_TOP_POWER_CTRL_REG_TRIM_NEWBAT_Pos

#define CRG_TOP_POWER_CTRL_REG_TRIM_NEWBAT_Pos   (0UL)

CRG_TOP POWER_CTRL_REG: TRIM_NEWBAT (Bit 0)

Definition at line 4295 of file DA14680BA.h.

◆ CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk

#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk   (0x2UL)

CRG_TOP RESET_STAT_REG: HWRESET_STAT (Bitfield-Mask: 0x01)

Definition at line 4352 of file DA14680BA.h.

◆ CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos

#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos   (1UL)

CRG_TOP RESET_STAT_REG: HWRESET_STAT (Bit 1)

Definition at line 4351 of file DA14680BA.h.

◆ CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk

#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk   (0x1UL)

CRG_TOP RESET_STAT_REG: PORESET_STAT (Bitfield-Mask: 0x01)

Definition at line 4350 of file DA14680BA.h.

◆ CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos

#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos   (0UL)

CRG_TOP RESET_STAT_REG: PORESET_STAT (Bit 0)

Definition at line 4349 of file DA14680BA.h.

◆ CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk

#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk   (0x10UL)

CRG_TOP RESET_STAT_REG: SWD_HWRESET_STAT (Bitfield-Mask: 0x01)

Definition at line 4358 of file DA14680BA.h.

◆ CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos

#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos   (4UL)

CRG_TOP RESET_STAT_REG: SWD_HWRESET_STAT (Bit 4)

Definition at line 4357 of file DA14680BA.h.

◆ CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk

#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk   (0x4UL)

CRG_TOP RESET_STAT_REG: SWRESET_STAT (Bitfield-Mask: 0x01)

Definition at line 4354 of file DA14680BA.h.

◆ CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos

#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos   (2UL)

CRG_TOP RESET_STAT_REG: SWRESET_STAT (Bit 2)

Definition at line 4353 of file DA14680BA.h.

◆ CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk

#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk   (0x8UL)

CRG_TOP RESET_STAT_REG: WDOGRESET_STAT (Bitfield-Mask: 0x01)

Definition at line 4356 of file DA14680BA.h.

◆ CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Pos

#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Pos   (3UL)

CRG_TOP RESET_STAT_REG: WDOGRESET_STAT (Bit 3)

Definition at line 4355 of file DA14680BA.h.

◆ CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Msk

#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Msk   (0x2UL)

CRG_TOP SECURE_BOOT_REG: FORCE_DEBUGGER_OFF (Bitfield-Mask: 0x01)

Definition at line 4384 of file DA14680BA.h.

◆ CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Pos

#define CRG_TOP_SECURE_BOOT_REG_FORCE_DEBUGGER_OFF_Pos   (1UL)

CRG_TOP SECURE_BOOT_REG: FORCE_DEBUGGER_OFF (Bit 1)

Definition at line 4383 of file DA14680BA.h.

◆ CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Msk

#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Msk   (0x1UL)

CRG_TOP SECURE_BOOT_REG: SECURE_BOOT (Bitfield-Mask: 0x01)

Definition at line 4382 of file DA14680BA.h.

◆ CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Pos

#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Pos   (0UL)

CRG_TOP SECURE_BOOT_REG: SECURE_BOOT (Bit 0)

Definition at line 4381 of file DA14680BA.h.

◆ CRG_TOP_SLEEP_TIMER_REG_SLEEP_TIMER_Msk

#define CRG_TOP_SLEEP_TIMER_REG_SLEEP_TIMER_Msk   (0xffffUL)

CRG_TOP SLEEP_TIMER_REG: SLEEP_TIMER (Bitfield-Mask: 0xffff)

Definition at line 4292 of file DA14680BA.h.

◆ CRG_TOP_SLEEP_TIMER_REG_SLEEP_TIMER_Pos

#define CRG_TOP_SLEEP_TIMER_REG_SLEEP_TIMER_Pos   (0UL)

CRG_TOP SLEEP_TIMER_REG: SLEEP_TIMER (Bit 0)

Definition at line 4291 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_BANDGAP_OK_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_BANDGAP_OK_Msk   (0x1UL)

CRG_TOP STARTUP_STATUS_REG: SU_BANDGAP_OK (Bitfield-Mask: 0x01)

Definition at line 4178 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_BANDGAP_OK_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_BANDGAP_OK_Pos   (0UL)

CRG_TOP STARTUP_STATUS_REG: SU_BANDGAP_OK (Bit 0)

Definition at line 4177 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_BOD_STATUS_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_BOD_STATUS_Msk   (0xe000UL)

CRG_TOP STARTUP_STATUS_REG: SU_BOD_STATUS (Bitfield-Mask: 0x07)

Definition at line 4204 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_BOD_STATUS_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_BOD_STATUS_Pos   (13UL)

CRG_TOP STARTUP_STATUS_REG: SU_BOD_STATUS (Bit 13)

Definition at line 4203 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_FLASH_HIGH_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_FLASH_HIGH_Msk   (0x800UL)

CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_FLASH_HIGH (Bitfield-Mask: 0x01)

Definition at line 4200 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_FLASH_HIGH_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_FLASH_HIGH_Pos   (11UL)

CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_FLASH_HIGH (Bit 11)

Definition at line 4199 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_PA_HIGH_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_PA_HIGH_Msk   (0x400UL)

CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_PA_HIGH (Bitfield-Mask: 0x01)

Definition at line 4198 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_PA_HIGH_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_1V8_PA_HIGH_Pos   (10UL)

CRG_TOP STARTUP_STATUS_REG: SU_COMP_1V8_PA_HIGH (Bit 10)

Definition at line 4197 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_COMP_V33_HIGH_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_V33_HIGH_Msk   (0x80UL)

CRG_TOP STARTUP_STATUS_REG: SU_COMP_V33_HIGH (Bitfield-Mask: 0x01)

Definition at line 4192 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_COMP_V33_HIGH_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_V33_HIGH_Pos   (7UL)

CRG_TOP STARTUP_STATUS_REG: SU_COMP_V33_HIGH (Bit 7)

Definition at line 4191 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_HIGH_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_HIGH_Msk   (0x100UL)

CRG_TOP STARTUP_STATUS_REG: SU_COMP_VBUS_HIGH (Bitfield-Mask: 0x01)

Definition at line 4194 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_HIGH_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_HIGH_Pos   (8UL)

CRG_TOP STARTUP_STATUS_REG: SU_COMP_VBUS_HIGH (Bit 8)

Definition at line 4193 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_LOW_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_LOW_Msk   (0x200UL)

CRG_TOP STARTUP_STATUS_REG: SU_COMP_VBUS_LOW (Bitfield-Mask: 0x01)

Definition at line 4196 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_LOW_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VBUS_LOW_Pos   (9UL)

CRG_TOP STARTUP_STATUS_REG: SU_COMP_VBUS_LOW (Bit 9)

Definition at line 4195 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VDD_HIGH_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VDD_HIGH_Msk   (0x40UL)

CRG_TOP STARTUP_STATUS_REG: SU_COMP_VDD_HIGH (Bitfield-Mask: 0x01)

Definition at line 4190 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VDD_HIGH_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_COMP_VDD_HIGH_Pos   (6UL)

CRG_TOP STARTUP_STATUS_REG: SU_COMP_VDD_HIGH (Bit 6)

Definition at line 4189 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Msk   (0x1000UL)

CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_FLASH_OK (Bitfield-Mask: 0x01)

Definition at line 4202 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_FLASH_OK_Pos   (12UL)

CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_FLASH_OK (Bit 12)

Definition at line 4201 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_PA_OK_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_PA_OK_Msk   (0x20UL)

CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_PA_OK (Bitfield-Mask: 0x01)

Definition at line 4188 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_PA_OK_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_1V8_PA_OK_Pos   (5UL)

CRG_TOP STARTUP_STATUS_REG: SU_LDO_1V8_PA_OK (Bit 5)

Definition at line 4187 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_LDO_CORE_OK_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_CORE_OK_Msk   (0x10UL)

CRG_TOP STARTUP_STATUS_REG: SU_LDO_CORE_OK (Bitfield-Mask: 0x01)

Definition at line 4186 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_LDO_CORE_OK_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_CORE_OK_Pos   (4UL)

CRG_TOP STARTUP_STATUS_REG: SU_LDO_CORE_OK (Bit 4)

Definition at line 4185 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_LDO_SUPPLY_VBAT_OK_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_SUPPLY_VBAT_OK_Msk   (0x4UL)

CRG_TOP STARTUP_STATUS_REG: SU_LDO_SUPPLY_VBAT_OK (Bitfield-Mask: 0x01)

Definition at line 4182 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_LDO_SUPPLY_VBAT_OK_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_LDO_SUPPLY_VBAT_OK_Pos   (2UL)

CRG_TOP STARTUP_STATUS_REG: SU_LDO_SUPPLY_VBAT_OK (Bit 2)

Definition at line 4181 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_LOD_SUPPLY_USB_OK_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_LOD_SUPPLY_USB_OK_Msk   (0x8UL)

CRG_TOP STARTUP_STATUS_REG: SU_LOD_SUPPLY_USB_OK (Bitfield-Mask: 0x01)

Definition at line 4184 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_LOD_SUPPLY_USB_OK_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_LOD_SUPPLY_USB_OK_Pos   (3UL)

CRG_TOP STARTUP_STATUS_REG: SU_LOD_SUPPLY_USB_OK (Bit 3)

Definition at line 4183 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Msk

#define CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Msk   (0x2UL)

CRG_TOP STARTUP_STATUS_REG: SU_NEWBAT (Bitfield-Mask: 0x01)

Definition at line 4180 of file DA14680BA.h.

◆ CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Pos

#define CRG_TOP_STARTUP_STATUS_REG_SU_NEWBAT_Pos   (1UL)

CRG_TOP STARTUP_STATUS_REG: SU_NEWBAT (Bit 1)

Definition at line 4179 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk

#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk   (0x400UL)

CRG_TOP SYS_CTRL_REG: CACHERAM_MUX (Bitfield-Mask: 0x01)

Definition at line 4038 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Pos

#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Pos   (10UL)

CRG_TOP SYS_CTRL_REG: CACHERAM_MUX (Bit 10)

Definition at line 4037 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk

#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk   (0x80UL)

CRG_TOP SYS_CTRL_REG: DEBUGGER_ENABLE (Bitfield-Mask: 0x01)

Definition at line 4032 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Pos

#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Pos   (7UL)

CRG_TOP SYS_CTRL_REG: DEBUGGER_ENABLE (Bit 7)

Definition at line 4031 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_DEV_PHASE_Msk

#define CRG_TOP_SYS_CTRL_REG_DEV_PHASE_Msk   (0x800UL)

CRG_TOP SYS_CTRL_REG: DEV_PHASE (Bitfield-Mask: 0x01)

Definition at line 4040 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_DEV_PHASE_Pos

#define CRG_TOP_SYS_CTRL_REG_DEV_PHASE_Pos   (11UL)

CRG_TOP SYS_CTRL_REG: DEV_PHASE (Bit 11)

Definition at line 4039 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_DRA_OFF_Msk

#define CRG_TOP_SYS_CTRL_REG_DRA_OFF_Msk   (0x100UL)

CRG_TOP SYS_CTRL_REG: DRA_OFF (Bitfield-Mask: 0x01)

Definition at line 4034 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_DRA_OFF_Pos

#define CRG_TOP_SYS_CTRL_REG_DRA_OFF_Pos   (8UL)

CRG_TOP SYS_CTRL_REG: DRA_OFF (Bit 8)

Definition at line 4033 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_OTP_COPY_Msk

#define CRG_TOP_SYS_CTRL_REG_OTP_COPY_Msk   (0x2000UL)

CRG_TOP SYS_CTRL_REG: OTP_COPY (Bitfield-Mask: 0x01)

Definition at line 4044 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_OTP_COPY_Pos

#define CRG_TOP_SYS_CTRL_REG_OTP_COPY_Pos   (13UL)

CRG_TOP SYS_CTRL_REG: OTP_COPY (Bit 13)

Definition at line 4043 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_OTPC_RESET_REQ_Msk

#define CRG_TOP_SYS_CTRL_REG_OTPC_RESET_REQ_Msk   (0x40UL)

CRG_TOP SYS_CTRL_REG: OTPC_RESET_REQ (Bitfield-Mask: 0x01)

Definition at line 4030 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_OTPC_RESET_REQ_Pos

#define CRG_TOP_SYS_CTRL_REG_OTPC_RESET_REQ_Pos   (6UL)

CRG_TOP SYS_CTRL_REG: OTPC_RESET_REQ (Bit 6)

Definition at line 4029 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_PAD_LATCH_EN_Msk

#define CRG_TOP_SYS_CTRL_REG_PAD_LATCH_EN_Msk   (0x20UL)

CRG_TOP SYS_CTRL_REG: PAD_LATCH_EN (Bitfield-Mask: 0x01)

Definition at line 4028 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_PAD_LATCH_EN_Pos

#define CRG_TOP_SYS_CTRL_REG_PAD_LATCH_EN_Pos   (5UL)

CRG_TOP SYS_CTRL_REG: PAD_LATCH_EN (Bit 5)

Definition at line 4027 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Msk

#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Msk   (0x1000UL)

CRG_TOP SYS_CTRL_REG: QSPI_INIT (Bitfield-Mask: 0x01)

Definition at line 4042 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Pos

#define CRG_TOP_SYS_CTRL_REG_QSPI_INIT_Pos   (12UL)

CRG_TOP SYS_CTRL_REG: QSPI_INIT (Bit 12)

Definition at line 4041 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk

#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk   (0x7UL)

CRG_TOP SYS_CTRL_REG: REMAP_ADR0 (Bitfield-Mask: 0x07)

Definition at line 4024 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Pos

#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Pos   (0UL)

CRG_TOP SYS_CTRL_REG: REMAP_ADR0 (Bit 0)

Definition at line 4023 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk

#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk   (0x4000UL)

CRG_TOP SYS_CTRL_REG: REMAP_INTVECT (Bitfield-Mask: 0x01)

Definition at line 4046 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Pos

#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Pos   (14UL)

CRG_TOP SYS_CTRL_REG: REMAP_INTVECT (Bit 14)

Definition at line 4045 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_REMAP_RAMS_Msk

#define CRG_TOP_SYS_CTRL_REG_REMAP_RAMS_Msk   (0x18UL)

CRG_TOP SYS_CTRL_REG: REMAP_RAMS (Bitfield-Mask: 0x03)

Definition at line 4026 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_REMAP_RAMS_Pos

#define CRG_TOP_SYS_CTRL_REG_REMAP_RAMS_Pos   (3UL)

CRG_TOP SYS_CTRL_REG: REMAP_RAMS (Bit 3)

Definition at line 4025 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk

#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk   (0x8000UL)

CRG_TOP SYS_CTRL_REG: SW_RESET (Bitfield-Mask: 0x01)

Definition at line 4048 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_SW_RESET_Pos

#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Pos   (15UL)

CRG_TOP SYS_CTRL_REG: SW_RESET (Bit 15)

Definition at line 4047 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Msk

#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Msk   (0x200UL)

CRG_TOP SYS_CTRL_REG: TIMEOUT_DISABLE (Bitfield-Mask: 0x01)

Definition at line 4036 of file DA14680BA.h.

◆ CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Pos

#define CRG_TOP_SYS_CTRL_REG_TIMEOUT_DISABLE_Pos   (9UL)

CRG_TOP SYS_CTRL_REG: TIMEOUT_DISABLE (Bit 9)

Definition at line 4035 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_BLE_IS_DOWN_Msk

#define CRG_TOP_SYS_STAT_REG_BLE_IS_DOWN_Msk   (0x100UL)

CRG_TOP SYS_STAT_REG: BLE_IS_DOWN (Bitfield-Mask: 0x01)

Definition at line 4068 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_BLE_IS_DOWN_Pos

#define CRG_TOP_SYS_STAT_REG_BLE_IS_DOWN_Pos   (8UL)

CRG_TOP SYS_STAT_REG: BLE_IS_DOWN (Bit 8)

Definition at line 4067 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_BLE_IS_UP_Msk

#define CRG_TOP_SYS_STAT_REG_BLE_IS_UP_Msk   (0x200UL)

CRG_TOP SYS_STAT_REG: BLE_IS_UP (Bitfield-Mask: 0x01)

Definition at line 4070 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_BLE_IS_UP_Pos

#define CRG_TOP_SYS_STAT_REG_BLE_IS_UP_Pos   (9UL)

CRG_TOP SYS_STAT_REG: BLE_IS_UP (Bit 9)

Definition at line 4069 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk

#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk   (0x20UL)

CRG_TOP SYS_STAT_REG: DBG_IS_ACTIVE (Bitfield-Mask: 0x01)

Definition at line 4062 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Pos

#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Pos   (5UL)

CRG_TOP SYS_STAT_REG: DBG_IS_ACTIVE (Bit 5)

Definition at line 4061 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_FTDF_IS_DOWN_Msk

#define CRG_TOP_SYS_STAT_REG_FTDF_IS_DOWN_Msk   (0x400UL)

CRG_TOP SYS_STAT_REG: FTDF_IS_DOWN (Bitfield-Mask: 0x01)

Definition at line 4072 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_FTDF_IS_DOWN_Pos

#define CRG_TOP_SYS_STAT_REG_FTDF_IS_DOWN_Pos   (10UL)

CRG_TOP SYS_STAT_REG: FTDF_IS_DOWN (Bit 10)

Definition at line 4071 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_FTDF_IS_UP_Msk

#define CRG_TOP_SYS_STAT_REG_FTDF_IS_UP_Msk   (0x800UL)

CRG_TOP SYS_STAT_REG: FTDF_IS_UP (Bitfield-Mask: 0x01)

Definition at line 4074 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_FTDF_IS_UP_Pos

#define CRG_TOP_SYS_STAT_REG_FTDF_IS_UP_Pos   (11UL)

CRG_TOP SYS_STAT_REG: FTDF_IS_UP (Bit 11)

Definition at line 4073 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Msk

#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Msk   (0x4UL)

CRG_TOP SYS_STAT_REG: PER_IS_DOWN (Bitfield-Mask: 0x01)

Definition at line 4056 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Pos

#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Pos   (2UL)

CRG_TOP SYS_STAT_REG: PER_IS_DOWN (Bit 2)

Definition at line 4055 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_PER_IS_UP_Msk

#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Msk   (0x8UL)

CRG_TOP SYS_STAT_REG: PER_IS_UP (Bitfield-Mask: 0x01)

Definition at line 4058 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_PER_IS_UP_Pos

#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Pos   (3UL)

CRG_TOP SYS_STAT_REG: PER_IS_UP (Bit 3)

Definition at line 4057 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Msk

#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Msk   (0x1UL)

CRG_TOP SYS_STAT_REG: RAD_IS_DOWN (Bitfield-Mask: 0x01)

Definition at line 4052 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Pos

#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Pos   (0UL)

CRG_TOP SYS_STAT_REG: RAD_IS_DOWN (Bit 0)

Definition at line 4051 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Msk

#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Msk   (0x2UL)

CRG_TOP SYS_STAT_REG: RAD_IS_UP (Bitfield-Mask: 0x01)

Definition at line 4054 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Pos

#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Pos   (1UL)

CRG_TOP SYS_STAT_REG: RAD_IS_UP (Bit 1)

Definition at line 4053 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_XTAL16_SETTLE_READY_Msk

#define CRG_TOP_SYS_STAT_REG_XTAL16_SETTLE_READY_Msk   (0x80UL)

CRG_TOP SYS_STAT_REG: XTAL16_SETTLE_READY (Bitfield-Mask: 0x01)

Definition at line 4066 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_XTAL16_SETTLE_READY_Pos

#define CRG_TOP_SYS_STAT_REG_XTAL16_SETTLE_READY_Pos   (7UL)

CRG_TOP SYS_STAT_REG: XTAL16_SETTLE_READY (Bit 7)

Definition at line 4065 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_XTAL16_SW2_Msk

#define CRG_TOP_SYS_STAT_REG_XTAL16_SW2_Msk   (0x10UL)

CRG_TOP SYS_STAT_REG: XTAL16_SW2 (Bitfield-Mask: 0x01)

Definition at line 4060 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_XTAL16_SW2_Pos

#define CRG_TOP_SYS_STAT_REG_XTAL16_SW2_Pos   (4UL)

CRG_TOP SYS_STAT_REG: XTAL16_SW2 (Bit 4)

Definition at line 4059 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_XTAL16_TRIM_READY_Msk

#define CRG_TOP_SYS_STAT_REG_XTAL16_TRIM_READY_Msk   (0x40UL)

CRG_TOP SYS_STAT_REG: XTAL16_TRIM_READY (Bitfield-Mask: 0x01)

Definition at line 4064 of file DA14680BA.h.

◆ CRG_TOP_SYS_STAT_REG_XTAL16_TRIM_READY_Pos

#define CRG_TOP_SYS_STAT_REG_XTAL16_TRIM_READY_Pos   (6UL)

CRG_TOP SYS_STAT_REG: XTAL16_TRIM_READY (Bit 6)

Definition at line 4063 of file DA14680BA.h.

◆ CRG_TOP_TRIM_CTRL_REG_XTAL_COUNT_N_Msk

#define CRG_TOP_TRIM_CTRL_REG_XTAL_COUNT_N_Msk   (0x3fUL)

CRG_TOP TRIM_CTRL_REG: XTAL_COUNT_N (Bitfield-Mask: 0x3f)

Definition at line 4078 of file DA14680BA.h.

◆ CRG_TOP_TRIM_CTRL_REG_XTAL_COUNT_N_Pos

#define CRG_TOP_TRIM_CTRL_REG_XTAL_COUNT_N_Pos   (0UL)

CRG_TOP TRIM_CTRL_REG: XTAL_COUNT_N (Bit 0)

Definition at line 4077 of file DA14680BA.h.

◆ CRG_TOP_TRIM_CTRL_REG_XTAL_SETTLE_N_Msk

#define CRG_TOP_TRIM_CTRL_REG_XTAL_SETTLE_N_Msk   (0x3f00UL)

CRG_TOP TRIM_CTRL_REG: XTAL_SETTLE_N (Bitfield-Mask: 0x3f)

Definition at line 4082 of file DA14680BA.h.

◆ CRG_TOP_TRIM_CTRL_REG_XTAL_SETTLE_N_Pos

#define CRG_TOP_TRIM_CTRL_REG_XTAL_SETTLE_N_Pos   (8UL)

CRG_TOP TRIM_CTRL_REG: XTAL_SETTLE_N (Bit 8)

Definition at line 4081 of file DA14680BA.h.

◆ CRG_TOP_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Msk

#define CRG_TOP_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Msk   (0xc0UL)

CRG_TOP TRIM_CTRL_REG: XTAL_TRIM_SELECT (Bitfield-Mask: 0x03)

Definition at line 4080 of file DA14680BA.h.

◆ CRG_TOP_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Pos

#define CRG_TOP_TRIM_CTRL_REG_XTAL_TRIM_SELECT_Pos   (6UL)

CRG_TOP TRIM_CTRL_REG: XTAL_TRIM_SELECT (Bit 6)

Definition at line 4079 of file DA14680BA.h.

◆ CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Msk

#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Msk   (0xffffUL)

CRG_TOP VBUS_IRQ_CLEAR_REG: VBUS_IRQ_CLEAR (Bitfield-Mask: 0xffff)

Definition at line 4214 of file DA14680BA.h.

◆ CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Pos

#define CRG_TOP_VBUS_IRQ_CLEAR_REG_VBUS_IRQ_CLEAR_Pos   (0UL)

CRG_TOP VBUS_IRQ_CLEAR_REG: VBUS_IRQ_CLEAR (Bit 0)

Definition at line 4213 of file DA14680BA.h.

◆ CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk

#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Msk   (0x1UL)

CRG_TOP VBUS_IRQ_MASK_REG: VBUS_IRQ_EN_FALL (Bitfield-Mask: 0x01)

Definition at line 4208 of file DA14680BA.h.

◆ CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Pos

#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_FALL_Pos   (0UL)

CRG_TOP VBUS_IRQ_MASK_REG: VBUS_IRQ_EN_FALL (Bit 0)

Definition at line 4207 of file DA14680BA.h.

◆ CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk

#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Msk   (0x2UL)

CRG_TOP VBUS_IRQ_MASK_REG: VBUS_IRQ_EN_RISE (Bitfield-Mask: 0x01)

Definition at line 4210 of file DA14680BA.h.

◆ CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Pos

#define CRG_TOP_VBUS_IRQ_MASK_REG_VBUS_IRQ_EN_RISE_Pos   (1UL)

CRG_TOP VBUS_IRQ_MASK_REG: VBUS_IRQ_EN_RISE (Bit 1)

Definition at line 4209 of file DA14680BA.h.

◆ CRG_TOP_XTAL16M_RAMP_REG_COARSE_ADJ_Msk

#define CRG_TOP_XTAL16M_RAMP_REG_COARSE_ADJ_Msk   (0x700UL)

CRG_TOP XTAL16M_RAMP_REG: COARSE_ADJ (Bitfield-Mask: 0x07)

Definition at line 4342 of file DA14680BA.h.

◆ CRG_TOP_XTAL16M_RAMP_REG_COARSE_ADJ_Pos

#define CRG_TOP_XTAL16M_RAMP_REG_COARSE_ADJ_Pos   (8UL)

CRG_TOP XTAL16M_RAMP_REG: COARSE_ADJ (Bit 8)

Definition at line 4341 of file DA14680BA.h.

◆ CRG_TOP_XTAL16M_RAMP_REG_FINE_ADJ_Msk

#define CRG_TOP_XTAL16M_RAMP_REG_FINE_ADJ_Msk   (0xffUL)

CRG_TOP XTAL16M_RAMP_REG: FINE_ADJ (Bitfield-Mask: 0xff)

Definition at line 4340 of file DA14680BA.h.

◆ CRG_TOP_XTAL16M_RAMP_REG_FINE_ADJ_Pos

#define CRG_TOP_XTAL16M_RAMP_REG_FINE_ADJ_Pos   (0UL)

CRG_TOP XTAL16M_RAMP_REG: FINE_ADJ (Bit 0)

Definition at line 4339 of file DA14680BA.h.

◆ CRG_TOP_XTAL16M_START_REG_COARSE_ADJ_Msk

#define CRG_TOP_XTAL16M_START_REG_COARSE_ADJ_Msk   (0x700UL)

CRG_TOP XTAL16M_START_REG: COARSE_ADJ (Bitfield-Mask: 0x07)

Definition at line 4336 of file DA14680BA.h.

◆ CRG_TOP_XTAL16M_START_REG_COARSE_ADJ_Pos

#define CRG_TOP_XTAL16M_START_REG_COARSE_ADJ_Pos   (8UL)

CRG_TOP XTAL16M_START_REG: COARSE_ADJ (Bit 8)

Definition at line 4335 of file DA14680BA.h.

◆ CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Msk

#define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Msk   (0xffUL)

CRG_TOP XTAL16M_START_REG: FINE_ADJ (Bitfield-Mask: 0xff)

Definition at line 4334 of file DA14680BA.h.

◆ CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Pos

#define CRG_TOP_XTAL16M_START_REG_FINE_ADJ_Pos   (0UL)

CRG_TOP XTAL16M_START_REG: FINE_ADJ (Bit 0)

Definition at line 4333 of file DA14680BA.h.

◆ CRG_TOP_XTAL16M_TRSTAT_REG_XTAL16M_TRSTAT_Msk

#define CRG_TOP_XTAL16M_TRSTAT_REG_XTAL16M_TRSTAT_Msk   (0x7fffUL)

CRG_TOP XTAL16M_TRSTAT_REG: XTAL16M_TRSTAT (Bitfield-Mask: 0x7fff)

Definition at line 4346 of file DA14680BA.h.

◆ CRG_TOP_XTAL16M_TRSTAT_REG_XTAL16M_TRSTAT_Pos

#define CRG_TOP_XTAL16M_TRSTAT_REG_XTAL16M_TRSTAT_Pos   (0UL)

CRG_TOP XTAL16M_TRSTAT_REG: XTAL16M_TRSTAT (Bit 0)

Definition at line 4345 of file DA14680BA.h.

◆ CRG_TOP_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk

#define CRG_TOP_XTALRDY_CTRL_REG_XTALRDY_CNT_Msk   (0xffUL)

CRG_TOP XTALRDY_CTRL_REG: XTALRDY_CNT (Bitfield-Mask: 0xff)

Definition at line 4312 of file DA14680BA.h.

◆ CRG_TOP_XTALRDY_CTRL_REG_XTALRDY_CNT_Pos

#define CRG_TOP_XTALRDY_CTRL_REG_XTALRDY_CNT_Pos   (0UL)

CRG_TOP XTALRDY_CTRL_REG: XTALRDY_CNT (Bit 0)

Definition at line 4311 of file DA14680BA.h.

◆ CRG_TOP_XTALRDY_STAT_REG_XTALRDY_STAT_Msk

#define CRG_TOP_XTALRDY_STAT_REG_XTALRDY_STAT_Msk   (0xffUL)

CRG_TOP XTALRDY_STAT_REG: XTALRDY_STAT (Bitfield-Mask: 0xff)

Definition at line 4316 of file DA14680BA.h.

◆ CRG_TOP_XTALRDY_STAT_REG_XTALRDY_STAT_Pos

#define CRG_TOP_XTALRDY_STAT_REG_XTALRDY_STAT_Pos   (0UL)

CRG_TOP XTALRDY_STAT_REG: XTALRDY_STAT (Bit 0)

Definition at line 4315 of file DA14680BA.h.

◆ DCDC

#define DCDC   ((DCDC_Type *) DCDC_BASE)

Definition at line 12082 of file DA14680BA.h.

◆ DCDC_BASE

#define DCDC_BASE   0x50000080UL

Definition at line 12037 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_0_REG_DCDC_BROWNOUT_LV_MODE_Msk

#define DCDC_DCDC_CTRL_0_REG_DCDC_BROWNOUT_LV_MODE_Msk   (0x2000UL)

DCDC DCDC_CTRL_0_REG: DCDC_BROWNOUT_LV_MODE (Bitfield-Mask: 0x01)

Definition at line 4418 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_0_REG_DCDC_BROWNOUT_LV_MODE_Pos

#define DCDC_DCDC_CTRL_0_REG_DCDC_BROWNOUT_LV_MODE_Pos   (13UL)

DCDC DCDC_CTRL_0_REG: DCDC_BROWNOUT_LV_MODE (Bit 13)

Definition at line 4417 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_0_REG_DCDC_FAST_STARTUP_Msk

#define DCDC_DCDC_CTRL_0_REG_DCDC_FAST_STARTUP_Msk   (0x4000UL)

DCDC DCDC_CTRL_0_REG: DCDC_FAST_STARTUP (Bitfield-Mask: 0x01)

Definition at line 4420 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_0_REG_DCDC_FAST_STARTUP_Pos

#define DCDC_DCDC_CTRL_0_REG_DCDC_FAST_STARTUP_Pos   (14UL)

DCDC DCDC_CTRL_0_REG: DCDC_FAST_STARTUP (Bit 14)

Definition at line 4419 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_0_REG_DCDC_FW_ENABLE_Msk

#define DCDC_DCDC_CTRL_0_REG_DCDC_FW_ENABLE_Msk   (0x4UL)

DCDC DCDC_CTRL_0_REG: DCDC_FW_ENABLE (Bitfield-Mask: 0x01)

Definition at line 4412 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_0_REG_DCDC_FW_ENABLE_Pos

#define DCDC_DCDC_CTRL_0_REG_DCDC_FW_ENABLE_Pos   (2UL)

DCDC DCDC_CTRL_0_REG: DCDC_FW_ENABLE (Bit 2)

Definition at line 4411 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_0_REG_DCDC_IDLE_CLK_DIV_Msk

#define DCDC_DCDC_CTRL_0_REG_DCDC_IDLE_CLK_DIV_Msk   (0x1800UL)

DCDC DCDC_CTRL_0_REG: DCDC_IDLE_CLK_DIV (Bitfield-Mask: 0x03)

Definition at line 4416 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_0_REG_DCDC_IDLE_CLK_DIV_Pos

#define DCDC_DCDC_CTRL_0_REG_DCDC_IDLE_CLK_DIV_Pos   (11UL)

DCDC DCDC_CTRL_0_REG: DCDC_IDLE_CLK_DIV (Bit 11)

Definition at line 4415 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_0_REG_DCDC_MODE_Msk

#define DCDC_DCDC_CTRL_0_REG_DCDC_MODE_Msk   (0x3UL)

DCDC DCDC_CTRL_0_REG: DCDC_MODE (Bitfield-Mask: 0x03)

Definition at line 4410 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_0_REG_DCDC_MODE_Pos

#define DCDC_DCDC_CTRL_0_REG_DCDC_MODE_Pos   (0UL)

DCDC DCDC_CTRL_0_REG: DCDC_MODE (Bit 0)

Definition at line 4409 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_0_REG_DCDC_PRIORITY_Msk

#define DCDC_DCDC_CTRL_0_REG_DCDC_PRIORITY_Msk   (0x7f8UL)

DCDC DCDC_CTRL_0_REG: DCDC_PRIORITY (Bitfield-Mask: 0xff)

Definition at line 4414 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_0_REG_DCDC_PRIORITY_Pos

#define DCDC_DCDC_CTRL_0_REG_DCDC_PRIORITY_Pos   (3UL)

DCDC DCDC_CTRL_0_REG: DCDC_PRIORITY (Bit 3)

Definition at line 4413 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_1_REG_DCDC_GLOBAL_MAX_IDLE_TIME_Msk

#define DCDC_DCDC_CTRL_1_REG_DCDC_GLOBAL_MAX_IDLE_TIME_Msk   (0x7e0UL)

DCDC DCDC_CTRL_1_REG: DCDC_GLOBAL_MAX_IDLE_TIME (Bitfield-Mask: 0x3f)

Definition at line 4426 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_1_REG_DCDC_GLOBAL_MAX_IDLE_TIME_Pos

#define DCDC_DCDC_CTRL_1_REG_DCDC_GLOBAL_MAX_IDLE_TIME_Pos   (5UL)

DCDC DCDC_CTRL_1_REG: DCDC_GLOBAL_MAX_IDLE_TIME (Bit 5)

Definition at line 4425 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_1_REG_DCDC_STARTUP_DELAY_Msk

#define DCDC_DCDC_CTRL_1_REG_DCDC_STARTUP_DELAY_Msk   (0xf800UL)

DCDC DCDC_CTRL_1_REG: DCDC_STARTUP_DELAY (Bitfield-Mask: 0x1f)

Definition at line 4428 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_1_REG_DCDC_STARTUP_DELAY_Pos

#define DCDC_DCDC_CTRL_1_REG_DCDC_STARTUP_DELAY_Pos   (11UL)

DCDC DCDC_CTRL_1_REG: DCDC_STARTUP_DELAY (Bit 11)

Definition at line 4427 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_1_REG_DCDC_TIMEOUT_Msk

#define DCDC_DCDC_CTRL_1_REG_DCDC_TIMEOUT_Msk   (0x1fUL)

DCDC DCDC_CTRL_1_REG: DCDC_TIMEOUT (Bitfield-Mask: 0x1f)

Definition at line 4424 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_1_REG_DCDC_TIMEOUT_Pos

#define DCDC_DCDC_CTRL_1_REG_DCDC_TIMEOUT_Pos   (0UL)

DCDC DCDC_CTRL_1_REG: DCDC_TIMEOUT (Bit 0)

Definition at line 4423 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_2_REG_DCDC_HSGND_TRIM_Msk

#define DCDC_DCDC_CTRL_2_REG_DCDC_HSGND_TRIM_Msk   (0x7UL)

DCDC DCDC_CTRL_2_REG: DCDC_HSGND_TRIM (Bitfield-Mask: 0x07)

Definition at line 4432 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_2_REG_DCDC_HSGND_TRIM_Pos

#define DCDC_DCDC_CTRL_2_REG_DCDC_HSGND_TRIM_Pos   (0UL)

DCDC DCDC_CTRL_2_REG: DCDC_HSGND_TRIM (Bit 0)

Definition at line 4431 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_2_REG_DCDC_LSSUP_TRIM_Msk

#define DCDC_DCDC_CTRL_2_REG_DCDC_LSSUP_TRIM_Msk   (0x38UL)

DCDC DCDC_CTRL_2_REG: DCDC_LSSUP_TRIM (Bitfield-Mask: 0x07)

Definition at line 4434 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_2_REG_DCDC_LSSUP_TRIM_Pos

#define DCDC_DCDC_CTRL_2_REG_DCDC_LSSUP_TRIM_Pos   (3UL)

DCDC DCDC_CTRL_2_REG: DCDC_LSSUP_TRIM (Bit 3)

Definition at line 4433 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_RES_Msk

#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_RES_Msk   (0xf00UL)

DCDC DCDC_CTRL_2_REG: DCDC_TIMEOUT_IRQ_RES (Bitfield-Mask: 0x0f)

Definition at line 4438 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_RES_Pos

#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_RES_Pos   (8UL)

DCDC DCDC_CTRL_2_REG: DCDC_TIMEOUT_IRQ_RES (Bit 8)

Definition at line 4437 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_TRIG_Msk

#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_TRIG_Msk   (0xf000UL)

DCDC DCDC_CTRL_2_REG: DCDC_TIMEOUT_IRQ_TRIG (Bitfield-Mask: 0x0f)

Definition at line 4440 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_TRIG_Pos

#define DCDC_DCDC_CTRL_2_REG_DCDC_TIMEOUT_IRQ_TRIG_Pos   (12UL)

DCDC DCDC_CTRL_2_REG: DCDC_TIMEOUT_IRQ_TRIG (Bit 12)

Definition at line 4439 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_2_REG_DCDC_TUNE_Msk

#define DCDC_DCDC_CTRL_2_REG_DCDC_TUNE_Msk   (0xc0UL)

DCDC DCDC_CTRL_2_REG: DCDC_TUNE (Bitfield-Mask: 0x03)

Definition at line 4436 of file DA14680BA.h.

◆ DCDC_DCDC_CTRL_2_REG_DCDC_TUNE_Pos

#define DCDC_DCDC_CTRL_2_REG_DCDC_TUNE_Pos   (6UL)

DCDC DCDC_CTRL_2_REG: DCDC_TUNE (Bit 6)

Definition at line 4435 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_CLEAR_REG_DCDC_BROWN_OUT_IRQ_CLEAR_Msk

#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_BROWN_OUT_IRQ_CLEAR_Msk   (0x10UL)

DCDC DCDC_IRQ_CLEAR_REG: DCDC_BROWN_OUT_IRQ_CLEAR (Bitfield-Mask: 0x01)

Definition at line 4718 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_CLEAR_REG_DCDC_BROWN_OUT_IRQ_CLEAR_Pos

#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_BROWN_OUT_IRQ_CLEAR_Pos   (4UL)

DCDC DCDC_IRQ_CLEAR_REG: DCDC_BROWN_OUT_IRQ_CLEAR (Bit 4)

Definition at line 4717 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Msk

#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Msk   (0x1UL)

DCDC DCDC_IRQ_CLEAR_REG: DCDC_V14_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01)

Definition at line 4710 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Pos

#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V14_TIMEOUT_IRQ_CLEAR_Pos   (0UL)

DCDC DCDC_IRQ_CLEAR_REG: DCDC_V14_TIMEOUT_IRQ_CLEAR (Bit 0)

Definition at line 4709 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Msk

#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Msk   (0x2UL)

DCDC DCDC_IRQ_CLEAR_REG: DCDC_V18_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01)

Definition at line 4712 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Pos

#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18_TIMEOUT_IRQ_CLEAR_Pos   (1UL)

DCDC DCDC_IRQ_CLEAR_REG: DCDC_V18_TIMEOUT_IRQ_CLEAR (Bit 1)

Definition at line 4711 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Msk

#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Msk   (0x8UL)

DCDC DCDC_IRQ_CLEAR_REG: DCDC_V18P_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01)

Definition at line 4716 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Pos

#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_V18P_TIMEOUT_IRQ_CLEAR_Pos   (3UL)

DCDC DCDC_IRQ_CLEAR_REG: DCDC_V18P_TIMEOUT_IRQ_CLEAR (Bit 3)

Definition at line 4715 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Msk

#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Msk   (0x4UL)

DCDC DCDC_IRQ_CLEAR_REG: DCDC_VDD_TIMEOUT_IRQ_CLEAR (Bitfield-Mask: 0x01)

Definition at line 4714 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Pos

#define DCDC_DCDC_IRQ_CLEAR_REG_DCDC_VDD_TIMEOUT_IRQ_CLEAR_Pos   (2UL)

DCDC DCDC_IRQ_CLEAR_REG: DCDC_VDD_TIMEOUT_IRQ_CLEAR (Bit 2)

Definition at line 4713 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_MASK_REG_DCDC_BROWN_OUT_IRQ_MASK_Msk

#define DCDC_DCDC_IRQ_MASK_REG_DCDC_BROWN_OUT_IRQ_MASK_Msk   (0x10UL)

DCDC DCDC_IRQ_MASK_REG: DCDC_BROWN_OUT_IRQ_MASK (Bitfield-Mask: 0x01)

Definition at line 4730 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_MASK_REG_DCDC_BROWN_OUT_IRQ_MASK_Pos

#define DCDC_DCDC_IRQ_MASK_REG_DCDC_BROWN_OUT_IRQ_MASK_Pos   (4UL)

DCDC DCDC_IRQ_MASK_REG: DCDC_BROWN_OUT_IRQ_MASK (Bit 4)

Definition at line 4729 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Msk

#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Msk   (0x1UL)

DCDC DCDC_IRQ_MASK_REG: DCDC_V14_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01)

Definition at line 4722 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Pos

#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V14_TIMEOUT_IRQ_MASK_Pos   (0UL)

DCDC DCDC_IRQ_MASK_REG: DCDC_V14_TIMEOUT_IRQ_MASK (Bit 0)

Definition at line 4721 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Msk

#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Msk   (0x2UL)

DCDC DCDC_IRQ_MASK_REG: DCDC_V18_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01)

Definition at line 4724 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Pos

#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18_TIMEOUT_IRQ_MASK_Pos   (1UL)

DCDC DCDC_IRQ_MASK_REG: DCDC_V18_TIMEOUT_IRQ_MASK (Bit 1)

Definition at line 4723 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Msk

#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Msk   (0x8UL)

DCDC DCDC_IRQ_MASK_REG: DCDC_V18P_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01)

Definition at line 4728 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Pos

#define DCDC_DCDC_IRQ_MASK_REG_DCDC_V18P_TIMEOUT_IRQ_MASK_Pos   (3UL)

DCDC DCDC_IRQ_MASK_REG: DCDC_V18P_TIMEOUT_IRQ_MASK (Bit 3)

Definition at line 4727 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Msk

#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Msk   (0x4UL)

DCDC DCDC_IRQ_MASK_REG: DCDC_VDD_TIMEOUT_IRQ_MASK (Bitfield-Mask: 0x01)

Definition at line 4726 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Pos

#define DCDC_DCDC_IRQ_MASK_REG_DCDC_VDD_TIMEOUT_IRQ_MASK_Pos   (2UL)

DCDC DCDC_IRQ_MASK_REG: DCDC_VDD_TIMEOUT_IRQ_MASK (Bit 2)

Definition at line 4725 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_STATUS_REG_DCDC_BROWN_OUT_IRQ_STATUS_Msk

#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_BROWN_OUT_IRQ_STATUS_Msk   (0x10UL)

DCDC DCDC_IRQ_STATUS_REG: DCDC_BROWN_OUT_IRQ_STATUS (Bitfield-Mask: 0x01)

Definition at line 4706 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_STATUS_REG_DCDC_BROWN_OUT_IRQ_STATUS_Pos

#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_BROWN_OUT_IRQ_STATUS_Pos   (4UL)

DCDC DCDC_IRQ_STATUS_REG: DCDC_BROWN_OUT_IRQ_STATUS (Bit 4)

Definition at line 4705 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Msk

#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Msk   (0x1UL)

DCDC DCDC_IRQ_STATUS_REG: DCDC_V14_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01)

Definition at line 4698 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Pos

#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V14_TIMEOUT_IRQ_STATUS_Pos   (0UL)

DCDC DCDC_IRQ_STATUS_REG: DCDC_V14_TIMEOUT_IRQ_STATUS (Bit 0)

Definition at line 4697 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Msk

#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Msk   (0x2UL)

DCDC DCDC_IRQ_STATUS_REG: DCDC_V18_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01)

Definition at line 4700 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Pos

#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18_TIMEOUT_IRQ_STATUS_Pos   (1UL)

DCDC DCDC_IRQ_STATUS_REG: DCDC_V18_TIMEOUT_IRQ_STATUS (Bit 1)

Definition at line 4699 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Msk

#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Msk   (0x8UL)

DCDC DCDC_IRQ_STATUS_REG: DCDC_V18P_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01)

Definition at line 4704 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Pos

#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_V18P_TIMEOUT_IRQ_STATUS_Pos   (3UL)

DCDC DCDC_IRQ_STATUS_REG: DCDC_V18P_TIMEOUT_IRQ_STATUS (Bit 3)

Definition at line 4703 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Msk

#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Msk   (0x4UL)

DCDC DCDC_IRQ_STATUS_REG: DCDC_VDD_TIMEOUT_IRQ_STATUS (Bitfield-Mask: 0x01)

Definition at line 4702 of file DA14680BA.h.

◆ DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Pos

#define DCDC_DCDC_IRQ_STATUS_REG_DCDC_VDD_TIMEOUT_IRQ_STATUS_Pos   (2UL)

DCDC DCDC_IRQ_STATUS_REG: DCDC_VDD_TIMEOUT_IRQ_STATUS (Bit 2)

Definition at line 4701 of file DA14680BA.h.

◆ DCDC_DCDC_RET_0_REG_DCDC_V18P_CUR_LIM_RET_Msk

#define DCDC_DCDC_RET_0_REG_DCDC_V18P_CUR_LIM_RET_Msk   (0x1f00UL)

DCDC DCDC_RET_0_REG: DCDC_V18P_CUR_LIM_RET (Bitfield-Mask: 0x1f)

Definition at line 4536 of file DA14680BA.h.

◆ DCDC_DCDC_RET_0_REG_DCDC_V18P_CUR_LIM_RET_Pos

#define DCDC_DCDC_RET_0_REG_DCDC_V18P_CUR_LIM_RET_Pos   (8UL)

DCDC DCDC_RET_0_REG: DCDC_V18P_CUR_LIM_RET (Bit 8)

Definition at line 4535 of file DA14680BA.h.

◆ DCDC_DCDC_RET_0_REG_DCDC_V18P_RET_CYCLES_Msk

#define DCDC_DCDC_RET_0_REG_DCDC_V18P_RET_CYCLES_Msk   (0xe000UL)

DCDC DCDC_RET_0_REG: DCDC_V18P_RET_CYCLES (Bitfield-Mask: 0x07)

Definition at line 4538 of file DA14680BA.h.

◆ DCDC_DCDC_RET_0_REG_DCDC_V18P_RET_CYCLES_Pos

#define DCDC_DCDC_RET_0_REG_DCDC_V18P_RET_CYCLES_Pos   (13UL)

DCDC DCDC_RET_0_REG: DCDC_V18P_RET_CYCLES (Bit 13)

Definition at line 4537 of file DA14680BA.h.

◆ DCDC_DCDC_RET_0_REG_DCDC_VDD_CUR_LIM_RET_Msk

#define DCDC_DCDC_RET_0_REG_DCDC_VDD_CUR_LIM_RET_Msk   (0x1fUL)

DCDC DCDC_RET_0_REG: DCDC_VDD_CUR_LIM_RET (Bitfield-Mask: 0x1f)

Definition at line 4532 of file DA14680BA.h.

◆ DCDC_DCDC_RET_0_REG_DCDC_VDD_CUR_LIM_RET_Pos

#define DCDC_DCDC_RET_0_REG_DCDC_VDD_CUR_LIM_RET_Pos   (0UL)

DCDC DCDC_RET_0_REG: DCDC_VDD_CUR_LIM_RET (Bit 0)

Definition at line 4531 of file DA14680BA.h.

◆ DCDC_DCDC_RET_0_REG_DCDC_VDD_RET_CYCLES_Msk

#define DCDC_DCDC_RET_0_REG_DCDC_VDD_RET_CYCLES_Msk   (0xe0UL)

DCDC DCDC_RET_0_REG: DCDC_VDD_RET_CYCLES (Bitfield-Mask: 0x07)

Definition at line 4534 of file DA14680BA.h.

◆ DCDC_DCDC_RET_0_REG_DCDC_VDD_RET_CYCLES_Pos

#define DCDC_DCDC_RET_0_REG_DCDC_VDD_RET_CYCLES_Pos   (5UL)

DCDC DCDC_RET_0_REG: DCDC_VDD_RET_CYCLES (Bit 5)

Definition at line 4533 of file DA14680BA.h.

◆ DCDC_DCDC_RET_1_REG_DCDC_V14_CUR_LIM_RET_Msk

#define DCDC_DCDC_RET_1_REG_DCDC_V14_CUR_LIM_RET_Msk   (0x1fUL)

DCDC DCDC_RET_1_REG: DCDC_V14_CUR_LIM_RET (Bitfield-Mask: 0x1f)

Definition at line 4542 of file DA14680BA.h.

◆ DCDC_DCDC_RET_1_REG_DCDC_V14_CUR_LIM_RET_Pos

#define DCDC_DCDC_RET_1_REG_DCDC_V14_CUR_LIM_RET_Pos   (0UL)

DCDC DCDC_RET_1_REG: DCDC_V14_CUR_LIM_RET (Bit 0)

Definition at line 4541 of file DA14680BA.h.

◆ DCDC_DCDC_RET_1_REG_DCDC_V14_RET_CYCLES_Msk

#define DCDC_DCDC_RET_1_REG_DCDC_V14_RET_CYCLES_Msk   (0xe0UL)

DCDC DCDC_RET_1_REG: DCDC_V14_RET_CYCLES (Bitfield-Mask: 0x07)

Definition at line 4544 of file DA14680BA.h.

◆ DCDC_DCDC_RET_1_REG_DCDC_V14_RET_CYCLES_Pos

#define DCDC_DCDC_RET_1_REG_DCDC_V14_RET_CYCLES_Pos   (5UL)

DCDC DCDC_RET_1_REG: DCDC_V14_RET_CYCLES (Bit 5)

Definition at line 4543 of file DA14680BA.h.

◆ DCDC_DCDC_RET_1_REG_DCDC_V18_CUR_LIM_RET_Msk

#define DCDC_DCDC_RET_1_REG_DCDC_V18_CUR_LIM_RET_Msk   (0x1f00UL)

DCDC DCDC_RET_1_REG: DCDC_V18_CUR_LIM_RET (Bitfield-Mask: 0x1f)

Definition at line 4546 of file DA14680BA.h.

◆ DCDC_DCDC_RET_1_REG_DCDC_V18_CUR_LIM_RET_Pos

#define DCDC_DCDC_RET_1_REG_DCDC_V18_CUR_LIM_RET_Pos   (8UL)

DCDC DCDC_RET_1_REG: DCDC_V18_CUR_LIM_RET (Bit 8)

Definition at line 4545 of file DA14680BA.h.

◆ DCDC_DCDC_RET_1_REG_DCDC_V18_RET_CYCLES_Msk

#define DCDC_DCDC_RET_1_REG_DCDC_V18_RET_CYCLES_Msk   (0xe000UL)

DCDC DCDC_RET_1_REG: DCDC_V18_RET_CYCLES (Bitfield-Mask: 0x07)

Definition at line 4548 of file DA14680BA.h.

◆ DCDC_DCDC_RET_1_REG_DCDC_V18_RET_CYCLES_Pos

#define DCDC_DCDC_RET_1_REG_DCDC_V18_RET_CYCLES_Pos   (13UL)

DCDC DCDC_RET_1_REG: DCDC_V18_RET_CYCLES (Bit 13)

Definition at line 4547 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_0_Msk

#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_0_Msk   (0x7UL)

DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_0 (Bitfield-Mask: 0x07)

Definition at line 4596 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_0_Pos

#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_0_Pos   (0UL)

DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_0 (Bit 0)

Definition at line 4595 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_1_Msk

#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_1_Msk   (0x38UL)

DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_1 (Bitfield-Mask: 0x07)

Definition at line 4598 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_1_Pos

#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_1_Pos   (3UL)

DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_1 (Bit 3)

Definition at line 4597 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_2_Msk

#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_2_Msk   (0x1c0UL)

DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_2 (Bitfield-Mask: 0x07)

Definition at line 4600 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_2_Pos

#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_2_Pos   (6UL)

DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_2 (Bit 6)

Definition at line 4599 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_3_Msk

#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_3_Msk   (0xe00UL)

DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_3 (Bitfield-Mask: 0x07)

Definition at line 4602 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_3_Pos

#define DCDC_DCDC_STATUS_0_REG_DCDC_CHARGE_REG_3_Pos   (9UL)

DCDC DCDC_STATUS_0_REG: DCDC_CHARGE_REG_3 (Bit 9)

Definition at line 4601 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V14_AVAILABLE_Msk

#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_AVAILABLE_Msk   (0x100UL)

DCDC DCDC_STATUS_1_REG: DCDC_V14_AVAILABLE (Bitfield-Mask: 0x01)

Definition at line 4622 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V14_AVAILABLE_Pos

#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_AVAILABLE_Pos   (8UL)

DCDC DCDC_STATUS_1_REG: DCDC_V14_AVAILABLE (Bit 8)

Definition at line 4621 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V14_NOK_Msk

#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_NOK_Msk   (0x1UL)

DCDC DCDC_STATUS_1_REG: DCDC_V14_NOK (Bitfield-Mask: 0x01)

Definition at line 4606 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V14_NOK_Pos

#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_NOK_Pos   (0UL)

DCDC DCDC_STATUS_1_REG: DCDC_V14_NOK (Bit 0)

Definition at line 4605 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V14_OK_Msk

#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_OK_Msk   (0x10UL)

DCDC DCDC_STATUS_1_REG: DCDC_V14_OK (Bitfield-Mask: 0x01)

Definition at line 4614 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V14_OK_Pos

#define DCDC_DCDC_STATUS_1_REG_DCDC_V14_OK_Pos   (4UL)

DCDC DCDC_STATUS_1_REG: DCDC_V14_OK (Bit 4)

Definition at line 4613 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V18_AVAILABLE_Msk

#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_AVAILABLE_Msk   (0x200UL)

DCDC DCDC_STATUS_1_REG: DCDC_V18_AVAILABLE (Bitfield-Mask: 0x01)

Definition at line 4624 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V18_AVAILABLE_Pos

#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_AVAILABLE_Pos   (9UL)

DCDC DCDC_STATUS_1_REG: DCDC_V18_AVAILABLE (Bit 9)

Definition at line 4623 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V18_NOK_Msk

#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_NOK_Msk   (0x2UL)

DCDC DCDC_STATUS_1_REG: DCDC_V18_NOK (Bitfield-Mask: 0x01)

Definition at line 4608 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V18_NOK_Pos

#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_NOK_Pos   (1UL)

DCDC DCDC_STATUS_1_REG: DCDC_V18_NOK (Bit 1)

Definition at line 4607 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V18_OK_Msk

#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_OK_Msk   (0x20UL)

DCDC DCDC_STATUS_1_REG: DCDC_V18_OK (Bitfield-Mask: 0x01)

Definition at line 4616 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V18_OK_Pos

#define DCDC_DCDC_STATUS_1_REG_DCDC_V18_OK_Pos   (5UL)

DCDC DCDC_STATUS_1_REG: DCDC_V18_OK (Bit 5)

Definition at line 4615 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V18P_AVAILABLE_Msk

#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_AVAILABLE_Msk   (0x800UL)

DCDC DCDC_STATUS_1_REG: DCDC_V18P_AVAILABLE (Bitfield-Mask: 0x01)

Definition at line 4628 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V18P_AVAILABLE_Pos

#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_AVAILABLE_Pos   (11UL)

DCDC DCDC_STATUS_1_REG: DCDC_V18P_AVAILABLE (Bit 11)

Definition at line 4627 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V18P_NOK_Msk

#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_NOK_Msk   (0x8UL)

DCDC DCDC_STATUS_1_REG: DCDC_V18P_NOK (Bitfield-Mask: 0x01)

Definition at line 4612 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V18P_NOK_Pos

#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_NOK_Pos   (3UL)

DCDC DCDC_STATUS_1_REG: DCDC_V18P_NOK (Bit 3)

Definition at line 4611 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V18P_OK_Msk

#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_OK_Msk   (0x80UL)

DCDC DCDC_STATUS_1_REG: DCDC_V18P_OK (Bitfield-Mask: 0x01)

Definition at line 4620 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_V18P_OK_Pos

#define DCDC_DCDC_STATUS_1_REG_DCDC_V18P_OK_Pos   (7UL)

DCDC DCDC_STATUS_1_REG: DCDC_V18P_OK (Bit 7)

Definition at line 4619 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_VDD_AVAILABLE_Msk

#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_AVAILABLE_Msk   (0x400UL)

DCDC DCDC_STATUS_1_REG: DCDC_VDD_AVAILABLE (Bitfield-Mask: 0x01)

Definition at line 4626 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_VDD_AVAILABLE_Pos

#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_AVAILABLE_Pos   (10UL)

DCDC DCDC_STATUS_1_REG: DCDC_VDD_AVAILABLE (Bit 10)

Definition at line 4625 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_VDD_NOK_Msk

#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_NOK_Msk   (0x4UL)

DCDC DCDC_STATUS_1_REG: DCDC_VDD_NOK (Bitfield-Mask: 0x01)

Definition at line 4610 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_VDD_NOK_Pos

#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_NOK_Pos   (2UL)

DCDC DCDC_STATUS_1_REG: DCDC_VDD_NOK (Bit 2)

Definition at line 4609 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_VDD_OK_Msk

#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_OK_Msk   (0x40UL)

DCDC DCDC_STATUS_1_REG: DCDC_VDD_OK (Bitfield-Mask: 0x01)

Definition at line 4618 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_1_REG_DCDC_VDD_OK_Pos

#define DCDC_DCDC_STATUS_1_REG_DCDC_VDD_OK_Pos   (6UL)

DCDC DCDC_STATUS_1_REG: DCDC_VDD_OK (Bit 6)

Definition at line 4617 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_Msk

#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_Msk   (0x1UL)

DCDC DCDC_STATUS_2_REG: DCDC_N_COMP (Bitfield-Mask: 0x01)

Definition at line 4632 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_N_Msk

#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_N_Msk   (0x4UL)

DCDC DCDC_STATUS_2_REG: DCDC_N_COMP_N (Bitfield-Mask: 0x01)

Definition at line 4636 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_N_Pos

#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_N_Pos   (2UL)

DCDC DCDC_STATUS_2_REG: DCDC_N_COMP_N (Bit 2)

Definition at line 4635 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_P_Msk

#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_P_Msk   (0x8UL)

DCDC DCDC_STATUS_2_REG: DCDC_N_COMP_P (Bitfield-Mask: 0x01)

Definition at line 4638 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_P_Pos

#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_P_Pos   (3UL)

DCDC DCDC_STATUS_2_REG: DCDC_N_COMP_P (Bit 3)

Definition at line 4637 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_Pos

#define DCDC_DCDC_STATUS_2_REG_DCDC_N_COMP_Pos   (0UL)

DCDC DCDC_STATUS_2_REG: DCDC_N_COMP (Bit 0)

Definition at line 4631 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_NSW_STATE_Msk

#define DCDC_DCDC_STATUS_2_REG_DCDC_NSW_STATE_Msk   (0x80UL)

DCDC DCDC_STATUS_2_REG: DCDC_NSW_STATE (Bitfield-Mask: 0x01)

Definition at line 4646 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_NSW_STATE_Pos

#define DCDC_DCDC_STATUS_2_REG_DCDC_NSW_STATE_Pos   (7UL)

DCDC DCDC_STATUS_2_REG: DCDC_NSW_STATE (Bit 7)

Definition at line 4645 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_Msk

#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_Msk   (0x2UL)

DCDC DCDC_STATUS_2_REG: DCDC_P_COMP (Bitfield-Mask: 0x01)

Definition at line 4634 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_N_Msk

#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_N_Msk   (0x10UL)

DCDC DCDC_STATUS_2_REG: DCDC_P_COMP_N (Bitfield-Mask: 0x01)

Definition at line 4640 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_N_Pos

#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_N_Pos   (4UL)

DCDC DCDC_STATUS_2_REG: DCDC_P_COMP_N (Bit 4)

Definition at line 4639 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_P_Msk

#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_P_Msk   (0x20UL)

DCDC DCDC_STATUS_2_REG: DCDC_P_COMP_P (Bitfield-Mask: 0x01)

Definition at line 4642 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_P_Pos

#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_P_Pos   (5UL)

DCDC DCDC_STATUS_2_REG: DCDC_P_COMP_P (Bit 5)

Definition at line 4641 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_Pos

#define DCDC_DCDC_STATUS_2_REG_DCDC_P_COMP_Pos   (1UL)

DCDC DCDC_STATUS_2_REG: DCDC_P_COMP (Bit 1)

Definition at line 4633 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_PSW_STATE_Msk

#define DCDC_DCDC_STATUS_2_REG_DCDC_PSW_STATE_Msk   (0x40UL)

DCDC DCDC_STATUS_2_REG: DCDC_PSW_STATE (Bitfield-Mask: 0x01)

Definition at line 4644 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_PSW_STATE_Pos

#define DCDC_DCDC_STATUS_2_REG_DCDC_PSW_STATE_Pos   (6UL)

DCDC DCDC_STATUS_2_REG: DCDC_PSW_STATE (Bit 6)

Definition at line 4643 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_V14_SW_STATE_Msk

#define DCDC_DCDC_STATUS_2_REG_DCDC_V14_SW_STATE_Msk   (0x100UL)

DCDC DCDC_STATUS_2_REG: DCDC_V14_SW_STATE (Bitfield-Mask: 0x01)

Definition at line 4648 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_V14_SW_STATE_Pos

#define DCDC_DCDC_STATUS_2_REG_DCDC_V14_SW_STATE_Pos   (8UL)

DCDC DCDC_STATUS_2_REG: DCDC_V14_SW_STATE (Bit 8)

Definition at line 4647 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_V18_SW_STATE_Msk

#define DCDC_DCDC_STATUS_2_REG_DCDC_V18_SW_STATE_Msk   (0x200UL)

DCDC DCDC_STATUS_2_REG: DCDC_V18_SW_STATE (Bitfield-Mask: 0x01)

Definition at line 4650 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_V18_SW_STATE_Pos

#define DCDC_DCDC_STATUS_2_REG_DCDC_V18_SW_STATE_Pos   (9UL)

DCDC DCDC_STATUS_2_REG: DCDC_V18_SW_STATE (Bit 9)

Definition at line 4649 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_V18P_SW_STATE_Msk

#define DCDC_DCDC_STATUS_2_REG_DCDC_V18P_SW_STATE_Msk   (0x800UL)

DCDC DCDC_STATUS_2_REG: DCDC_V18P_SW_STATE (Bitfield-Mask: 0x01)

Definition at line 4654 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_V18P_SW_STATE_Pos

#define DCDC_DCDC_STATUS_2_REG_DCDC_V18P_SW_STATE_Pos   (11UL)

DCDC DCDC_STATUS_2_REG: DCDC_V18P_SW_STATE (Bit 11)

Definition at line 4653 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_VDD_SW_STATE_Msk

#define DCDC_DCDC_STATUS_2_REG_DCDC_VDD_SW_STATE_Msk   (0x400UL)

DCDC DCDC_STATUS_2_REG: DCDC_VDD_SW_STATE (Bitfield-Mask: 0x01)

Definition at line 4652 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_2_REG_DCDC_VDD_SW_STATE_Pos

#define DCDC_DCDC_STATUS_2_REG_DCDC_VDD_SW_STATE_Pos   (10UL)

DCDC DCDC_STATUS_2_REG: DCDC_VDD_SW_STATE (Bit 10)

Definition at line 4651 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_V18P_Msk

#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_V18P_Msk   (0x3e0UL)

DCDC DCDC_STATUS_3_REG: DCDC_I_LIM_V18P (Bitfield-Mask: 0x1f)

Definition at line 4660 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_V18P_Pos

#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_V18P_Pos   (5UL)

DCDC DCDC_STATUS_3_REG: DCDC_I_LIM_V18P (Bit 5)

Definition at line 4659 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_VDD_Msk

#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_VDD_Msk   (0x1fUL)

DCDC DCDC_STATUS_3_REG: DCDC_I_LIM_VDD (Bitfield-Mask: 0x1f)

Definition at line 4658 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_VDD_Pos

#define DCDC_DCDC_STATUS_3_REG_DCDC_I_LIM_VDD_Pos   (0UL)

DCDC DCDC_STATUS_3_REG: DCDC_I_LIM_VDD (Bit 0)

Definition at line 4657 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_3_REG_DCDC_LV_MODE_Msk

#define DCDC_DCDC_STATUS_3_REG_DCDC_LV_MODE_Msk   (0x400UL)

DCDC DCDC_STATUS_3_REG: DCDC_LV_MODE (Bitfield-Mask: 0x01)

Definition at line 4662 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_3_REG_DCDC_LV_MODE_Pos

#define DCDC_DCDC_STATUS_3_REG_DCDC_LV_MODE_Pos   (10UL)

DCDC DCDC_STATUS_3_REG: DCDC_LV_MODE (Bit 10)

Definition at line 4661 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_3_REG_DCDC_STARTUP_COMPLETE_Msk

#define DCDC_DCDC_STATUS_3_REG_DCDC_STARTUP_COMPLETE_Msk   (0x800UL)

DCDC DCDC_STATUS_3_REG: DCDC_STARTUP_COMPLETE (Bitfield-Mask: 0x01)

Definition at line 4664 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_3_REG_DCDC_STARTUP_COMPLETE_Pos

#define DCDC_DCDC_STATUS_3_REG_DCDC_STARTUP_COMPLETE_Pos   (11UL)

DCDC DCDC_STATUS_3_REG: DCDC_STARTUP_COMPLETE (Bit 11)

Definition at line 4663 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V14_Msk

#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V14_Msk   (0x1fUL)

DCDC DCDC_STATUS_4_REG: DCDC_I_LIM_V14 (Bitfield-Mask: 0x1f)

Definition at line 4668 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V14_Pos

#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V14_Pos   (0UL)

DCDC DCDC_STATUS_4_REG: DCDC_I_LIM_V14 (Bit 0)

Definition at line 4667 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V18_Msk

#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V18_Msk   (0x3e0UL)

DCDC DCDC_STATUS_4_REG: DCDC_I_LIM_V18 (Bitfield-Mask: 0x1f)

Definition at line 4670 of file DA14680BA.h.

◆ DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V18_Pos

#define DCDC_DCDC_STATUS_4_REG_DCDC_I_LIM_V18_Pos   (5UL)

DCDC DCDC_STATUS_4_REG: DCDC_I_LIM_V18 (Bit 5)

Definition at line 4669 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_ANA_TEST_Msk

#define DCDC_DCDC_TEST_0_REG_DCDC_ANA_TEST_Msk   (0x700UL)

DCDC DCDC_TEST_0_REG: DCDC_ANA_TEST (Bitfield-Mask: 0x07)

Definition at line 4578 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_ANA_TEST_Pos

#define DCDC_DCDC_TEST_0_REG_DCDC_ANA_TEST_Pos   (8UL)

DCDC DCDC_TEST_0_REG: DCDC_ANA_TEST (Bit 8)

Definition at line 4577 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_COMP_CLK_Msk

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_COMP_CLK_Msk   (0x8000UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_COMP_CLK (Bitfield-Mask: 0x01)

Definition at line 4584 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_COMP_CLK_Pos

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_COMP_CLK_Pos   (15UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_COMP_CLK (Bit 15)

Definition at line 4583 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_CURRENT_Msk

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_CURRENT_Msk   (0x4000UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_CURRENT (Bitfield-Mask: 0x01)

Definition at line 4582 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_CURRENT_Pos

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_CURRENT_Pos   (14UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_CURRENT (Bit 14)

Definition at line 4581 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_FW_Msk

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_FW_Msk   (0x4UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_FW (Bitfield-Mask: 0x01)

Definition at line 4566 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_FW_Pos

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_FW_Pos   (2UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_FW (Bit 2)

Definition at line 4565 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_IDLE_Msk

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_IDLE_Msk   (0x80UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_IDLE (Bitfield-Mask: 0x01)

Definition at line 4576 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_IDLE_Pos

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_IDLE_Pos   (7UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_IDLE (Bit 7)

Definition at line 4575 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_NSW_Msk

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_NSW_Msk   (0x2UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_NSW (Bitfield-Mask: 0x01)

Definition at line 4564 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_NSW_Pos

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_NSW_Pos   (1UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_NSW (Bit 1)

Definition at line 4563 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_PSW_Msk

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_PSW_Msk   (0x1UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_PSW (Bitfield-Mask: 0x01)

Definition at line 4562 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_PSW_Pos

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_PSW_Pos   (0UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_PSW (Bit 0)

Definition at line 4561 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V14_Msk

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V14_Msk   (0x8UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_V14 (Bitfield-Mask: 0x01)

Definition at line 4568 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V14_Pos

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V14_Pos   (3UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_V14 (Bit 3)

Definition at line 4567 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18_Msk

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18_Msk   (0x10UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_V18 (Bitfield-Mask: 0x01)

Definition at line 4570 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18_Pos

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18_Pos   (4UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_V18 (Bit 4)

Definition at line 4569 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18P_Msk

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18P_Msk   (0x40UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_V18P (Bitfield-Mask: 0x01)

Definition at line 4574 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18P_Pos

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_V18P_Pos   (6UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_V18P (Bit 6)

Definition at line 4573 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_VDD_Msk

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_VDD_Msk   (0x20UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_VDD (Bitfield-Mask: 0x01)

Definition at line 4572 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_FORCE_VDD_Pos

#define DCDC_DCDC_TEST_0_REG_DCDC_FORCE_VDD_Pos   (5UL)

DCDC DCDC_TEST_0_REG: DCDC_FORCE_VDD (Bit 5)

Definition at line 4571 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_OUTPUT_MONITOR_Msk

#define DCDC_DCDC_TEST_0_REG_DCDC_OUTPUT_MONITOR_Msk   (0x3800UL)

DCDC DCDC_TEST_0_REG: DCDC_OUTPUT_MONITOR (Bitfield-Mask: 0x07)

Definition at line 4580 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_0_REG_DCDC_OUTPUT_MONITOR_Pos

#define DCDC_DCDC_TEST_0_REG_DCDC_OUTPUT_MONITOR_Pos   (11UL)

DCDC DCDC_TEST_0_REG: DCDC_OUTPUT_MONITOR (Bit 11)

Definition at line 4579 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_1_REG_DCDC_COMP_CLK_Msk

#define DCDC_DCDC_TEST_1_REG_DCDC_COMP_CLK_Msk   (0x1e00UL)

DCDC DCDC_TEST_1_REG: DCDC_COMP_CLK (Bitfield-Mask: 0x0f)

Definition at line 4592 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_1_REG_DCDC_COMP_CLK_Pos

#define DCDC_DCDC_TEST_1_REG_DCDC_COMP_CLK_Pos   (9UL)

DCDC DCDC_TEST_1_REG: DCDC_COMP_CLK (Bit 9)

Definition at line 4591 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_1_REG_DCDC_TEST_CURRENT_Msk

#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_CURRENT_Msk   (0x1f0UL)

DCDC DCDC_TEST_1_REG: DCDC_TEST_CURRENT (Bitfield-Mask: 0x1f)

Definition at line 4590 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_1_REG_DCDC_TEST_CURRENT_Pos

#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_CURRENT_Pos   (4UL)

DCDC DCDC_TEST_1_REG: DCDC_TEST_CURRENT (Bit 4)

Definition at line 4589 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_1_REG_DCDC_TEST_REG_Msk

#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_REG_Msk   (0xfUL)

DCDC DCDC_TEST_1_REG: DCDC_TEST_REG (Bitfield-Mask: 0x0f)

Definition at line 4588 of file DA14680BA.h.

◆ DCDC_DCDC_TEST_1_REG_DCDC_TEST_REG_Pos

#define DCDC_DCDC_TEST_1_REG_DCDC_TEST_REG_Pos   (0UL)

DCDC DCDC_TEST_1_REG: DCDC_TEST_REG (Bit 0)

Definition at line 4587 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_N_Msk

#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_N_Msk   (0x3fUL)

DCDC DCDC_TRIM_0_REG: DCDC_V14_TRIM_N (Bitfield-Mask: 0x3f)

Definition at line 4674 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_N_Pos

#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_N_Pos   (0UL)

DCDC DCDC_TRIM_0_REG: DCDC_V14_TRIM_N (Bit 0)

Definition at line 4673 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_P_Msk

#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_P_Msk   (0xfc0UL)

DCDC DCDC_TRIM_0_REG: DCDC_V14_TRIM_P (Bitfield-Mask: 0x3f)

Definition at line 4676 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_P_Pos

#define DCDC_DCDC_TRIM_0_REG_DCDC_V14_TRIM_P_Pos   (6UL)

DCDC DCDC_TRIM_0_REG: DCDC_V14_TRIM_P (Bit 6)

Definition at line 4675 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_N_Msk

#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_N_Msk   (0x3fUL)

DCDC DCDC_TRIM_1_REG: DCDC_V18_TRIM_N (Bitfield-Mask: 0x3f)

Definition at line 4680 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_N_Pos

#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_N_Pos   (0UL)

DCDC DCDC_TRIM_1_REG: DCDC_V18_TRIM_N (Bit 0)

Definition at line 4679 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_P_Msk

#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_P_Msk   (0xfc0UL)

DCDC DCDC_TRIM_1_REG: DCDC_V18_TRIM_P (Bitfield-Mask: 0x3f)

Definition at line 4682 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_P_Pos

#define DCDC_DCDC_TRIM_1_REG_DCDC_V18_TRIM_P_Pos   (6UL)

DCDC DCDC_TRIM_1_REG: DCDC_V18_TRIM_P (Bit 6)

Definition at line 4681 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_N_Msk

#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_N_Msk   (0x3fUL)

DCDC DCDC_TRIM_2_REG: DCDC_VDD_TRIM_N (Bitfield-Mask: 0x3f)

Definition at line 4686 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_N_Pos

#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_N_Pos   (0UL)

DCDC DCDC_TRIM_2_REG: DCDC_VDD_TRIM_N (Bit 0)

Definition at line 4685 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_P_Msk

#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_P_Msk   (0xfc0UL)

DCDC DCDC_TRIM_2_REG: DCDC_VDD_TRIM_P (Bitfield-Mask: 0x3f)

Definition at line 4688 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_P_Pos

#define DCDC_DCDC_TRIM_2_REG_DCDC_VDD_TRIM_P_Pos   (6UL)

DCDC DCDC_TRIM_2_REG: DCDC_VDD_TRIM_P (Bit 6)

Definition at line 4687 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_N_Msk

#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_N_Msk   (0x3fUL)

DCDC DCDC_TRIM_3_REG: DCDC_V18P_TRIM_N (Bitfield-Mask: 0x3f)

Definition at line 4692 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_N_Pos

#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_N_Pos   (0UL)

DCDC DCDC_TRIM_3_REG: DCDC_V18P_TRIM_N (Bit 0)

Definition at line 4691 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_P_Msk

#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_P_Msk   (0xfc0UL)

DCDC DCDC_TRIM_3_REG: DCDC_V18P_TRIM_P (Bitfield-Mask: 0x3f)

Definition at line 4694 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_P_Pos

#define DCDC_DCDC_TRIM_3_REG_DCDC_V18P_TRIM_P_Pos   (6UL)

DCDC DCDC_TRIM_3_REG: DCDC_V18P_TRIM_P (Bit 6)

Definition at line 4693 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_REG_DCDC_N_COMP_MAN_TRIM_Msk

#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_MAN_TRIM_Msk   (0x40UL)

DCDC DCDC_TRIM_REG: DCDC_N_COMP_MAN_TRIM (Bitfield-Mask: 0x01)

Definition at line 4554 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_REG_DCDC_N_COMP_MAN_TRIM_Pos

#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_MAN_TRIM_Pos   (6UL)

DCDC DCDC_TRIM_REG: DCDC_N_COMP_MAN_TRIM (Bit 6)

Definition at line 4553 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_REG_DCDC_N_COMP_TRIM_Msk

#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_TRIM_Msk   (0x3fUL)

DCDC DCDC_TRIM_REG: DCDC_N_COMP_TRIM (Bitfield-Mask: 0x3f)

Definition at line 4552 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_REG_DCDC_N_COMP_TRIM_Pos

#define DCDC_DCDC_TRIM_REG_DCDC_N_COMP_TRIM_Pos   (0UL)

DCDC DCDC_TRIM_REG: DCDC_N_COMP_TRIM (Bit 0)

Definition at line 4551 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_REG_DCDC_P_COMP_MAN_TRIM_Msk

#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_MAN_TRIM_Msk   (0x2000UL)

DCDC DCDC_TRIM_REG: DCDC_P_COMP_MAN_TRIM (Bitfield-Mask: 0x01)

Definition at line 4558 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_REG_DCDC_P_COMP_MAN_TRIM_Pos

#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_MAN_TRIM_Pos   (13UL)

DCDC DCDC_TRIM_REG: DCDC_P_COMP_MAN_TRIM (Bit 13)

Definition at line 4557 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_REG_DCDC_P_COMP_TRIM_Msk

#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_TRIM_Msk   (0x1f80UL)

DCDC DCDC_TRIM_REG: DCDC_P_COMP_TRIM (Bitfield-Mask: 0x3f)

Definition at line 4556 of file DA14680BA.h.

◆ DCDC_DCDC_TRIM_REG_DCDC_P_COMP_TRIM_Pos

#define DCDC_DCDC_TRIM_REG_DCDC_P_COMP_TRIM_Pos   (7UL)

DCDC DCDC_TRIM_REG: DCDC_P_COMP_TRIM (Bit 7)

Definition at line 4555 of file DA14680BA.h.

◆ DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MAX_HV_Msk

#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MAX_HV_Msk   (0x3e0UL)

DCDC DCDC_V14_0_REG: DCDC_V14_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f)

Definition at line 4446 of file DA14680BA.h.

◆ DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MAX_HV_Pos

#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MAX_HV_Pos   (5UL)

DCDC DCDC_V14_0_REG: DCDC_V14_CUR_LIM_MAX_HV (Bit 5)

Definition at line 4445 of file DA14680BA.h.

◆ DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MIN_Msk

#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MIN_Msk   (0x1fUL)

DCDC DCDC_V14_0_REG: DCDC_V14_CUR_LIM_MIN (Bitfield-Mask: 0x1f)

Definition at line 4444 of file DA14680BA.h.

◆ DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MIN_Pos

#define DCDC_DCDC_V14_0_REG_DCDC_V14_CUR_LIM_MIN_Pos   (0UL)

DCDC DCDC_V14_0_REG: DCDC_V14_CUR_LIM_MIN (Bit 0)

Definition at line 4443 of file DA14680BA.h.

◆ DCDC_DCDC_V14_0_REG_DCDC_V14_FAST_RAMPING_Msk

#define DCDC_DCDC_V14_0_REG_DCDC_V14_FAST_RAMPING_Msk   (0x8000UL)

DCDC DCDC_V14_0_REG: DCDC_V14_FAST_RAMPING (Bitfield-Mask: 0x01)

Definition at line 4450 of file DA14680BA.h.

◆ DCDC_DCDC_V14_0_REG_DCDC_V14_FAST_RAMPING_Pos

#define DCDC_DCDC_V14_0_REG_DCDC_V14_FAST_RAMPING_Pos   (15UL)

DCDC DCDC_V14_0_REG: DCDC_V14_FAST_RAMPING (Bit 15)

Definition at line 4449 of file DA14680BA.h.

◆ DCDC_DCDC_V14_0_REG_DCDC_V14_VOLTAGE_Msk

#define DCDC_DCDC_V14_0_REG_DCDC_V14_VOLTAGE_Msk   (0x7c00UL)

DCDC DCDC_V14_0_REG: DCDC_V14_VOLTAGE (Bitfield-Mask: 0x1f)

Definition at line 4448 of file DA14680BA.h.

◆ DCDC_DCDC_V14_0_REG_DCDC_V14_VOLTAGE_Pos

#define DCDC_DCDC_V14_0_REG_DCDC_V14_VOLTAGE_Pos   (10UL)

DCDC DCDC_V14_0_REG: DCDC_V14_VOLTAGE (Bit 10)

Definition at line 4447 of file DA14680BA.h.

◆ DCDC_DCDC_V14_1_REG_DCDC_V14_CUR_LIM_MAX_LV_Msk

#define DCDC_DCDC_V14_1_REG_DCDC_V14_CUR_LIM_MAX_LV_Msk   (0x3c00UL)

DCDC DCDC_V14_1_REG: DCDC_V14_CUR_LIM_MAX_LV (Bitfield-Mask: 0x0f)

Definition at line 4458 of file DA14680BA.h.

◆ DCDC_DCDC_V14_1_REG_DCDC_V14_CUR_LIM_MAX_LV_Pos

#define DCDC_DCDC_V14_1_REG_DCDC_V14_CUR_LIM_MAX_LV_Pos   (10UL)

DCDC DCDC_V14_1_REG: DCDC_V14_CUR_LIM_MAX_LV (Bit 10)

Definition at line 4457 of file DA14680BA.h.

◆ DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_HV_Msk

#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_HV_Msk   (0x8000UL)

DCDC DCDC_V14_1_REG: DCDC_V14_ENABLE_HV (Bitfield-Mask: 0x01)

Definition at line 4462 of file DA14680BA.h.

◆ DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_HV_Pos

#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_HV_Pos   (15UL)

DCDC DCDC_V14_1_REG: DCDC_V14_ENABLE_HV (Bit 15)

Definition at line 4461 of file DA14680BA.h.

◆ DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_LV_Msk

#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_LV_Msk   (0x4000UL)

DCDC DCDC_V14_1_REG: DCDC_V14_ENABLE_LV (Bitfield-Mask: 0x01)

Definition at line 4460 of file DA14680BA.h.

◆ DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_LV_Pos

#define DCDC_DCDC_V14_1_REG_DCDC_V14_ENABLE_LV_Pos   (14UL)

DCDC DCDC_V14_1_REG: DCDC_V14_ENABLE_LV (Bit 14)

Definition at line 4459 of file DA14680BA.h.

◆ DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_HYST_Msk

#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_HYST_Msk   (0x3e0UL)

DCDC DCDC_V14_1_REG: DCDC_V14_IDLE_HYST (Bitfield-Mask: 0x1f)

Definition at line 4456 of file DA14680BA.h.

◆ DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_HYST_Pos

#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_HYST_Pos   (5UL)

DCDC DCDC_V14_1_REG: DCDC_V14_IDLE_HYST (Bit 5)

Definition at line 4455 of file DA14680BA.h.

◆ DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_MIN_Msk

#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_MIN_Msk   (0x1fUL)

DCDC DCDC_V14_1_REG: DCDC_V14_IDLE_MIN (Bitfield-Mask: 0x1f)

Definition at line 4454 of file DA14680BA.h.

◆ DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_MIN_Pos

#define DCDC_DCDC_V14_1_REG_DCDC_V14_IDLE_MIN_Pos   (0UL)

DCDC DCDC_V14_1_REG: DCDC_V14_IDLE_MIN (Bit 0)

Definition at line 4453 of file DA14680BA.h.

◆ DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MAX_HV_Msk

#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MAX_HV_Msk   (0x3e0UL)

DCDC DCDC_V18_0_REG: DCDC_V18_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f)

Definition at line 4468 of file DA14680BA.h.

◆ DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MAX_HV_Pos

#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MAX_HV_Pos   (5UL)

DCDC DCDC_V18_0_REG: DCDC_V18_CUR_LIM_MAX_HV (Bit 5)

Definition at line 4467 of file DA14680BA.h.

◆ DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MIN_Msk

#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MIN_Msk   (0x1fUL)

DCDC DCDC_V18_0_REG: DCDC_V18_CUR_LIM_MIN (Bitfield-Mask: 0x1f)

Definition at line 4466 of file DA14680BA.h.

◆ DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MIN_Pos

#define DCDC_DCDC_V18_0_REG_DCDC_V18_CUR_LIM_MIN_Pos   (0UL)

DCDC DCDC_V18_0_REG: DCDC_V18_CUR_LIM_MIN (Bit 0)

Definition at line 4465 of file DA14680BA.h.

◆ DCDC_DCDC_V18_0_REG_DCDC_V18_FAST_RAMPING_Msk

#define DCDC_DCDC_V18_0_REG_DCDC_V18_FAST_RAMPING_Msk   (0x8000UL)

DCDC DCDC_V18_0_REG: DCDC_V18_FAST_RAMPING (Bitfield-Mask: 0x01)

Definition at line 4472 of file DA14680BA.h.

◆ DCDC_DCDC_V18_0_REG_DCDC_V18_FAST_RAMPING_Pos

#define DCDC_DCDC_V18_0_REG_DCDC_V18_FAST_RAMPING_Pos   (15UL)

DCDC DCDC_V18_0_REG: DCDC_V18_FAST_RAMPING (Bit 15)

Definition at line 4471 of file DA14680BA.h.

◆ DCDC_DCDC_V18_0_REG_DCDC_V18_VOLTAGE_Msk

#define DCDC_DCDC_V18_0_REG_DCDC_V18_VOLTAGE_Msk   (0x7c00UL)

DCDC DCDC_V18_0_REG: DCDC_V18_VOLTAGE (Bitfield-Mask: 0x1f)

Definition at line 4470 of file DA14680BA.h.

◆ DCDC_DCDC_V18_0_REG_DCDC_V18_VOLTAGE_Pos

#define DCDC_DCDC_V18_0_REG_DCDC_V18_VOLTAGE_Pos   (10UL)

DCDC DCDC_V18_0_REG: DCDC_V18_VOLTAGE (Bit 10)

Definition at line 4469 of file DA14680BA.h.

◆ DCDC_DCDC_V18_1_REG_DCDC_V18_CUR_LIM_MAX_LV_Msk

#define DCDC_DCDC_V18_1_REG_DCDC_V18_CUR_LIM_MAX_LV_Msk   (0x3c00UL)

DCDC DCDC_V18_1_REG: DCDC_V18_CUR_LIM_MAX_LV (Bitfield-Mask: 0x0f)

Definition at line 4480 of file DA14680BA.h.

◆ DCDC_DCDC_V18_1_REG_DCDC_V18_CUR_LIM_MAX_LV_Pos

#define DCDC_DCDC_V18_1_REG_DCDC_V18_CUR_LIM_MAX_LV_Pos   (10UL)

DCDC DCDC_V18_1_REG: DCDC_V18_CUR_LIM_MAX_LV (Bit 10)

Definition at line 4479 of file DA14680BA.h.

◆ DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_HV_Msk

#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_HV_Msk   (0x8000UL)

DCDC DCDC_V18_1_REG: DCDC_V18_ENABLE_HV (Bitfield-Mask: 0x01)

Definition at line 4484 of file DA14680BA.h.

◆ DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_HV_Pos

#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_HV_Pos   (15UL)

DCDC DCDC_V18_1_REG: DCDC_V18_ENABLE_HV (Bit 15)

Definition at line 4483 of file DA14680BA.h.

◆ DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_LV_Msk

#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_LV_Msk   (0x4000UL)

DCDC DCDC_V18_1_REG: DCDC_V18_ENABLE_LV (Bitfield-Mask: 0x01)

Definition at line 4482 of file DA14680BA.h.

◆ DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_LV_Pos

#define DCDC_DCDC_V18_1_REG_DCDC_V18_ENABLE_LV_Pos   (14UL)

DCDC DCDC_V18_1_REG: DCDC_V18_ENABLE_LV (Bit 14)

Definition at line 4481 of file DA14680BA.h.

◆ DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_HYST_Msk

#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_HYST_Msk   (0x3e0UL)

DCDC DCDC_V18_1_REG: DCDC_V18_IDLE_HYST (Bitfield-Mask: 0x1f)

Definition at line 4478 of file DA14680BA.h.

◆ DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_HYST_Pos

#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_HYST_Pos   (5UL)

DCDC DCDC_V18_1_REG: DCDC_V18_IDLE_HYST (Bit 5)

Definition at line 4477 of file DA14680BA.h.

◆ DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_MIN_Msk

#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_MIN_Msk   (0x1fUL)

DCDC DCDC_V18_1_REG: DCDC_V18_IDLE_MIN (Bitfield-Mask: 0x1f)

Definition at line 4476 of file DA14680BA.h.

◆ DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_MIN_Pos

#define DCDC_DCDC_V18_1_REG_DCDC_V18_IDLE_MIN_Pos   (0UL)

DCDC DCDC_V18_1_REG: DCDC_V18_IDLE_MIN (Bit 0)

Definition at line 4475 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MAX_HV_Msk

#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MAX_HV_Msk   (0x3e0UL)

DCDC DCDC_V18P_0_REG: DCDC_V18P_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f)

Definition at line 4512 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MAX_HV_Pos

#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MAX_HV_Pos   (5UL)

DCDC DCDC_V18P_0_REG: DCDC_V18P_CUR_LIM_MAX_HV (Bit 5)

Definition at line 4511 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MIN_Msk

#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MIN_Msk   (0x1fUL)

DCDC DCDC_V18P_0_REG: DCDC_V18P_CUR_LIM_MIN (Bitfield-Mask: 0x1f)

Definition at line 4510 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MIN_Pos

#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_CUR_LIM_MIN_Pos   (0UL)

DCDC DCDC_V18P_0_REG: DCDC_V18P_CUR_LIM_MIN (Bit 0)

Definition at line 4509 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_0_REG_DCDC_V18P_FAST_RAMPING_Msk

#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_FAST_RAMPING_Msk   (0x8000UL)

DCDC DCDC_V18P_0_REG: DCDC_V18P_FAST_RAMPING (Bitfield-Mask: 0x01)

Definition at line 4516 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_0_REG_DCDC_V18P_FAST_RAMPING_Pos

#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_FAST_RAMPING_Pos   (15UL)

DCDC DCDC_V18P_0_REG: DCDC_V18P_FAST_RAMPING (Bit 15)

Definition at line 4515 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_0_REG_DCDC_V18P_VOLTAGE_Msk

#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_VOLTAGE_Msk   (0x7c00UL)

DCDC DCDC_V18P_0_REG: DCDC_V18P_VOLTAGE (Bitfield-Mask: 0x1f)

Definition at line 4514 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_0_REG_DCDC_V18P_VOLTAGE_Pos

#define DCDC_DCDC_V18P_0_REG_DCDC_V18P_VOLTAGE_Pos   (10UL)

DCDC DCDC_V18P_0_REG: DCDC_V18P_VOLTAGE (Bit 10)

Definition at line 4513 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_1_REG_DCDC_V18P_CUR_LIM_MAX_LV_Msk

#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_CUR_LIM_MAX_LV_Msk   (0x3c00UL)

DCDC DCDC_V18P_1_REG: DCDC_V18P_CUR_LIM_MAX_LV (Bitfield-Mask: 0x0f)

Definition at line 4524 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_1_REG_DCDC_V18P_CUR_LIM_MAX_LV_Pos

#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_CUR_LIM_MAX_LV_Pos   (10UL)

DCDC DCDC_V18P_1_REG: DCDC_V18P_CUR_LIM_MAX_LV (Bit 10)

Definition at line 4523 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_HV_Msk

#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_HV_Msk   (0x8000UL)

DCDC DCDC_V18P_1_REG: DCDC_V18P_ENABLE_HV (Bitfield-Mask: 0x01)

Definition at line 4528 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_HV_Pos

#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_HV_Pos   (15UL)

DCDC DCDC_V18P_1_REG: DCDC_V18P_ENABLE_HV (Bit 15)

Definition at line 4527 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_LV_Msk

#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_LV_Msk   (0x4000UL)

DCDC DCDC_V18P_1_REG: DCDC_V18P_ENABLE_LV (Bitfield-Mask: 0x01)

Definition at line 4526 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_LV_Pos

#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_ENABLE_LV_Pos   (14UL)

DCDC DCDC_V18P_1_REG: DCDC_V18P_ENABLE_LV (Bit 14)

Definition at line 4525 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_HYST_Msk

#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_HYST_Msk   (0x3e0UL)

DCDC DCDC_V18P_1_REG: DCDC_V18P_IDLE_HYST (Bitfield-Mask: 0x1f)

Definition at line 4522 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_HYST_Pos

#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_HYST_Pos   (5UL)

DCDC DCDC_V18P_1_REG: DCDC_V18P_IDLE_HYST (Bit 5)

Definition at line 4521 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_MIN_Msk

#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_MIN_Msk   (0x1fUL)

DCDC DCDC_V18P_1_REG: DCDC_V18P_IDLE_MIN (Bitfield-Mask: 0x1f)

Definition at line 4520 of file DA14680BA.h.

◆ DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_MIN_Pos

#define DCDC_DCDC_V18P_1_REG_DCDC_V18P_IDLE_MIN_Pos   (0UL)

DCDC DCDC_V18P_1_REG: DCDC_V18P_IDLE_MIN (Bit 0)

Definition at line 4519 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MAX_HV_Msk

#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MAX_HV_Msk   (0x3e0UL)

DCDC DCDC_VDD_0_REG: DCDC_VDD_CUR_LIM_MAX_HV (Bitfield-Mask: 0x1f)

Definition at line 4490 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MAX_HV_Pos

#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MAX_HV_Pos   (5UL)

DCDC DCDC_VDD_0_REG: DCDC_VDD_CUR_LIM_MAX_HV (Bit 5)

Definition at line 4489 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MIN_Msk

#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MIN_Msk   (0x1fUL)

DCDC DCDC_VDD_0_REG: DCDC_VDD_CUR_LIM_MIN (Bitfield-Mask: 0x1f)

Definition at line 4488 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MIN_Pos

#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_CUR_LIM_MIN_Pos   (0UL)

DCDC DCDC_VDD_0_REG: DCDC_VDD_CUR_LIM_MIN (Bit 0)

Definition at line 4487 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_0_REG_DCDC_VDD_FAST_RAMPING_Msk

#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_FAST_RAMPING_Msk   (0x8000UL)

DCDC DCDC_VDD_0_REG: DCDC_VDD_FAST_RAMPING (Bitfield-Mask: 0x01)

Definition at line 4494 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_0_REG_DCDC_VDD_FAST_RAMPING_Pos

#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_FAST_RAMPING_Pos   (15UL)

DCDC DCDC_VDD_0_REG: DCDC_VDD_FAST_RAMPING (Bit 15)

Definition at line 4493 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_0_REG_DCDC_VDD_VOLTAGE_Msk

#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_VOLTAGE_Msk   (0x7c00UL)

DCDC DCDC_VDD_0_REG: DCDC_VDD_VOLTAGE (Bitfield-Mask: 0x1f)

Definition at line 4492 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_0_REG_DCDC_VDD_VOLTAGE_Pos

#define DCDC_DCDC_VDD_0_REG_DCDC_VDD_VOLTAGE_Pos   (10UL)

DCDC DCDC_VDD_0_REG: DCDC_VDD_VOLTAGE (Bit 10)

Definition at line 4491 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_1_REG_DCDC_VDD_CUR_LIM_MAX_LV_Msk

#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_CUR_LIM_MAX_LV_Msk   (0x3c00UL)

DCDC DCDC_VDD_1_REG: DCDC_VDD_CUR_LIM_MAX_LV (Bitfield-Mask: 0x0f)

Definition at line 4502 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_1_REG_DCDC_VDD_CUR_LIM_MAX_LV_Pos

#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_CUR_LIM_MAX_LV_Pos   (10UL)

DCDC DCDC_VDD_1_REG: DCDC_VDD_CUR_LIM_MAX_LV (Bit 10)

Definition at line 4501 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_HV_Msk

#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_HV_Msk   (0x8000UL)

DCDC DCDC_VDD_1_REG: DCDC_VDD_ENABLE_HV (Bitfield-Mask: 0x01)

Definition at line 4506 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_HV_Pos

#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_HV_Pos   (15UL)

DCDC DCDC_VDD_1_REG: DCDC_VDD_ENABLE_HV (Bit 15)

Definition at line 4505 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_LV_Msk

#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_LV_Msk   (0x4000UL)

DCDC DCDC_VDD_1_REG: DCDC_VDD_ENABLE_LV (Bitfield-Mask: 0x01)

Definition at line 4504 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_LV_Pos

#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_ENABLE_LV_Pos   (14UL)

DCDC DCDC_VDD_1_REG: DCDC_VDD_ENABLE_LV (Bit 14)

Definition at line 4503 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_HYST_Msk

#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_HYST_Msk   (0x3e0UL)

DCDC DCDC_VDD_1_REG: DCDC_VDD_IDLE_HYST (Bitfield-Mask: 0x1f)

Definition at line 4500 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_HYST_Pos

#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_HYST_Pos   (5UL)

DCDC DCDC_VDD_1_REG: DCDC_VDD_IDLE_HYST (Bit 5)

Definition at line 4499 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_MIN_Msk

#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_MIN_Msk   (0x1fUL)

DCDC DCDC_VDD_1_REG: DCDC_VDD_IDLE_MIN (Bitfield-Mask: 0x1f)

Definition at line 4498 of file DA14680BA.h.

◆ DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_MIN_Pos

#define DCDC_DCDC_VDD_1_REG_DCDC_VDD_IDLE_MIN_Pos   (0UL)

DCDC DCDC_VDD_1_REG: DCDC_VDD_IDLE_MIN (Bit 0)

Definition at line 4497 of file DA14680BA.h.

◆ DEM

#define DEM   ((DEM_Type *) DEM_BASE)

Definition at line 12083 of file DA14680BA.h.

◆ DEM_BASE

#define DEM_BASE   0x50002E00UL

Definition at line 12038 of file DA14680BA.h.

◆ DEM_RF_AFC_CTRL_REG_AFC_MODE_Msk

#define DEM_RF_AFC_CTRL_REG_AFC_MODE_Msk   (0xfUL)

DEM RF_AFC_CTRL_REG: AFC_MODE (Bitfield-Mask: 0x0f)

Definition at line 4850 of file DA14680BA.h.

◆ DEM_RF_AFC_CTRL_REG_AFC_MODE_Pos

#define DEM_RF_AFC_CTRL_REG_AFC_MODE_Pos   (0UL)

DEM RF_AFC_CTRL_REG: AFC_MODE (Bit 0)

Definition at line 4849 of file DA14680BA.h.

◆ DEM_RF_AFC_CTRL_REG_APD_MODE_Msk

#define DEM_RF_AFC_CTRL_REG_APD_MODE_Msk   (0x1c00UL)

DEM RF_AFC_CTRL_REG: APD_MODE (Bitfield-Mask: 0x07)

Definition at line 4858 of file DA14680BA.h.

◆ DEM_RF_AFC_CTRL_REG_APD_MODE_Pos

#define DEM_RF_AFC_CTRL_REG_APD_MODE_Pos   (10UL)

DEM RF_AFC_CTRL_REG: APD_MODE (Bit 10)

Definition at line 4857 of file DA14680BA.h.

◆ DEM_RF_AFC_CTRL_REG_PAD_MODE_Msk

#define DEM_RF_AFC_CTRL_REG_PAD_MODE_Msk   (0x300UL)

DEM RF_AFC_CTRL_REG: PAD_MODE (Bitfield-Mask: 0x03)

Definition at line 4856 of file DA14680BA.h.

◆ DEM_RF_AFC_CTRL_REG_PAD_MODE_Pos

#define DEM_RF_AFC_CTRL_REG_PAD_MODE_Pos   (8UL)

DEM RF_AFC_CTRL_REG: PAD_MODE (Bit 8)

Definition at line 4855 of file DA14680BA.h.

◆ DEM_RF_AFC_CTRL_REG_POLE1_Msk

#define DEM_RF_AFC_CTRL_REG_POLE1_Msk   (0x30UL)

DEM RF_AFC_CTRL_REG: POLE1 (Bitfield-Mask: 0x03)

Definition at line 4852 of file DA14680BA.h.

◆ DEM_RF_AFC_CTRL_REG_POLE1_Pos

#define DEM_RF_AFC_CTRL_REG_POLE1_Pos   (4UL)

DEM RF_AFC_CTRL_REG: POLE1 (Bit 4)

Definition at line 4851 of file DA14680BA.h.

◆ DEM_RF_AFC_CTRL_REG_POLE2_Msk

#define DEM_RF_AFC_CTRL_REG_POLE2_Msk   (0xc0UL)

DEM RF_AFC_CTRL_REG: POLE2 (Bitfield-Mask: 0x03)

Definition at line 4854 of file DA14680BA.h.

◆ DEM_RF_AFC_CTRL_REG_POLE2_Pos

#define DEM_RF_AFC_CTRL_REG_POLE2_Pos   (6UL)

DEM RF_AFC_CTRL_REG: POLE2 (Bit 6)

Definition at line 4853 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL1_REG_AGC_MODE_Msk

#define DEM_RF_AGC_CTRL1_REG_AGC_MODE_Msk   (0xc000UL)

DEM RF_AGC_CTRL1_REG: AGC_MODE (Bitfield-Mask: 0x03)

Definition at line 4834 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL1_REG_AGC_MODE_Pos

#define DEM_RF_AGC_CTRL1_REG_AGC_MODE_Pos   (14UL)

DEM RF_AGC_CTRL1_REG: AGC_MODE (Bit 14)

Definition at line 4833 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL1_REG_AGC_TH_HIGH_Msk

#define DEM_RF_AGC_CTRL1_REG_AGC_TH_HIGH_Msk   (0x3f80UL)

DEM RF_AGC_CTRL1_REG: AGC_TH_HIGH (Bitfield-Mask: 0x7f)

Definition at line 4832 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL1_REG_AGC_TH_HIGH_Pos

#define DEM_RF_AGC_CTRL1_REG_AGC_TH_HIGH_Pos   (7UL)

DEM RF_AGC_CTRL1_REG: AGC_TH_HIGH (Bit 7)

Definition at line 4831 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL1_REG_AGC_TH_LOW_Msk

#define DEM_RF_AGC_CTRL1_REG_AGC_TH_LOW_Msk   (0x7fUL)

DEM RF_AGC_CTRL1_REG: AGC_TH_LOW (Bitfield-Mask: 0x7f)

Definition at line 4830 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL1_REG_AGC_TH_LOW_Pos

#define DEM_RF_AGC_CTRL1_REG_AGC_TH_LOW_Pos   (0UL)

DEM RF_AGC_CTRL1_REG: AGC_TH_LOW (Bit 0)

Definition at line 4829 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL2_REG_AGCSETTING_SEL_Msk

#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_SEL_Msk   (0x80UL)

DEM RF_AGC_CTRL2_REG: AGCSETTING_SEL (Bitfield-Mask: 0x01)

Definition at line 4842 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL2_REG_AGCSETTING_SEL_Pos

#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_SEL_Pos   (7UL)

DEM RF_AGC_CTRL2_REG: AGCSETTING_SEL (Bit 7)

Definition at line 4841 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL2_REG_AGCSETTING_WR_Msk

#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_WR_Msk   (0xf00UL)

DEM RF_AGC_CTRL2_REG: AGCSETTING_WR (Bitfield-Mask: 0x0f)

Definition at line 4844 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL2_REG_AGCSETTING_WR_Pos

#define DEM_RF_AGC_CTRL2_REG_AGCSETTING_WR_Pos   (8UL)

DEM RF_AGC_CTRL2_REG: AGCSETTING_WR (Bit 8)

Definition at line 4843 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL2_REG_EN_FRZ_GAIN_Msk

#define DEM_RF_AGC_CTRL2_REG_EN_FRZ_GAIN_Msk   (0x40UL)

DEM RF_AGC_CTRL2_REG: EN_FRZ_GAIN (Bitfield-Mask: 0x01)

Definition at line 4840 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL2_REG_EN_FRZ_GAIN_Pos

#define DEM_RF_AGC_CTRL2_REG_EN_FRZ_GAIN_Pos   (6UL)

DEM RF_AGC_CTRL2_REG: EN_FRZ_GAIN (Bit 6)

Definition at line 4839 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL2_REG_RSSI_TH_Msk

#define DEM_RF_AGC_CTRL2_REG_RSSI_TH_Msk   (0x3fUL)

DEM RF_AGC_CTRL2_REG: RSSI_TH (Bitfield-Mask: 0x3f)

Definition at line 4838 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL2_REG_RSSI_TH_Pos

#define DEM_RF_AGC_CTRL2_REG_RSSI_TH_Pos   (0UL)

DEM RF_AGC_CTRL2_REG: RSSI_TH (Bit 0)

Definition at line 4837 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL2_REG_SLOW_AGC_Msk

#define DEM_RF_AGC_CTRL2_REG_SLOW_AGC_Msk   (0x1000UL)

DEM RF_AGC_CTRL2_REG: SLOW_AGC (Bitfield-Mask: 0x01)

Definition at line 4846 of file DA14680BA.h.

◆ DEM_RF_AGC_CTRL2_REG_SLOW_AGC_Pos

#define DEM_RF_AGC_CTRL2_REG_SLOW_AGC_Pos   (12UL)

DEM RF_AGC_CTRL2_REG: SLOW_AGC (Bit 12)

Definition at line 4845 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_01_REG_LNA_GAIN0_Msk

#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN0_Msk   (0xc0UL)

DEM RF_AGC_LUT_01_REG: LNA_GAIN0 (Bitfield-Mask: 0x03)

Definition at line 4764 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_01_REG_LNA_GAIN0_Pos

#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN0_Pos   (6UL)

DEM RF_AGC_LUT_01_REG: LNA_GAIN0 (Bit 6)

Definition at line 4763 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_01_REG_LNA_GAIN1_Msk

#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN1_Msk   (0xc000UL)

DEM RF_AGC_LUT_01_REG: LNA_GAIN1 (Bitfield-Mask: 0x03)

Definition at line 4770 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_01_REG_LNA_GAIN1_Pos

#define DEM_RF_AGC_LUT_01_REG_LNA_GAIN1_Pos   (14UL)

DEM RF_AGC_LUT_01_REG: LNA_GAIN1 (Bit 14)

Definition at line 4769 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_01_REG_VGA1_GAIN0_Msk

#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN0_Msk   (0x38UL)

DEM RF_AGC_LUT_01_REG: VGA1_GAIN0 (Bitfield-Mask: 0x07)

Definition at line 4762 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_01_REG_VGA1_GAIN0_Pos

#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN0_Pos   (3UL)

DEM RF_AGC_LUT_01_REG: VGA1_GAIN0 (Bit 3)

Definition at line 4761 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_01_REG_VGA1_GAIN1_Msk

#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN1_Msk   (0x3800UL)

DEM RF_AGC_LUT_01_REG: VGA1_GAIN1 (Bitfield-Mask: 0x07)

Definition at line 4768 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_01_REG_VGA1_GAIN1_Pos

#define DEM_RF_AGC_LUT_01_REG_VGA1_GAIN1_Pos   (11UL)

DEM RF_AGC_LUT_01_REG: VGA1_GAIN1 (Bit 11)

Definition at line 4767 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_01_REG_VGA2_GAIN0_Msk

#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN0_Msk   (0x7UL)

DEM RF_AGC_LUT_01_REG: VGA2_GAIN0 (Bitfield-Mask: 0x07)

Definition at line 4760 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_01_REG_VGA2_GAIN0_Pos

#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN0_Pos   (0UL)

DEM RF_AGC_LUT_01_REG: VGA2_GAIN0 (Bit 0)

Definition at line 4759 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_01_REG_VGA2_GAIN1_Msk

#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN1_Msk   (0x700UL)

DEM RF_AGC_LUT_01_REG: VGA2_GAIN1 (Bitfield-Mask: 0x07)

Definition at line 4766 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_01_REG_VGA2_GAIN1_Pos

#define DEM_RF_AGC_LUT_01_REG_VGA2_GAIN1_Pos   (8UL)

DEM RF_AGC_LUT_01_REG: VGA2_GAIN1 (Bit 8)

Definition at line 4765 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_23_REG_LNA_GAIN2_Msk

#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN2_Msk   (0xc0UL)

DEM RF_AGC_LUT_23_REG: LNA_GAIN2 (Bitfield-Mask: 0x03)

Definition at line 4778 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_23_REG_LNA_GAIN2_Pos

#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN2_Pos   (6UL)

DEM RF_AGC_LUT_23_REG: LNA_GAIN2 (Bit 6)

Definition at line 4777 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_23_REG_LNA_GAIN3_Msk

#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN3_Msk   (0xc000UL)

DEM RF_AGC_LUT_23_REG: LNA_GAIN3 (Bitfield-Mask: 0x03)

Definition at line 4784 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_23_REG_LNA_GAIN3_Pos

#define DEM_RF_AGC_LUT_23_REG_LNA_GAIN3_Pos   (14UL)

DEM RF_AGC_LUT_23_REG: LNA_GAIN3 (Bit 14)

Definition at line 4783 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_23_REG_VGA1_GAIN2_Msk

#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN2_Msk   (0x38UL)

DEM RF_AGC_LUT_23_REG: VGA1_GAIN2 (Bitfield-Mask: 0x07)

Definition at line 4776 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_23_REG_VGA1_GAIN2_Pos

#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN2_Pos   (3UL)

DEM RF_AGC_LUT_23_REG: VGA1_GAIN2 (Bit 3)

Definition at line 4775 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_23_REG_VGA1_GAIN3_Msk

#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN3_Msk   (0x3800UL)

DEM RF_AGC_LUT_23_REG: VGA1_GAIN3 (Bitfield-Mask: 0x07)

Definition at line 4782 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_23_REG_VGA1_GAIN3_Pos

#define DEM_RF_AGC_LUT_23_REG_VGA1_GAIN3_Pos   (11UL)

DEM RF_AGC_LUT_23_REG: VGA1_GAIN3 (Bit 11)

Definition at line 4781 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_23_REG_VGA2_GAIN2_Msk

#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN2_Msk   (0x7UL)

DEM RF_AGC_LUT_23_REG: VGA2_GAIN2 (Bitfield-Mask: 0x07)

Definition at line 4774 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_23_REG_VGA2_GAIN2_Pos

#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN2_Pos   (0UL)

DEM RF_AGC_LUT_23_REG: VGA2_GAIN2 (Bit 0)

Definition at line 4773 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_23_REG_VGA2_GAIN3_Msk

#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN3_Msk   (0x700UL)

DEM RF_AGC_LUT_23_REG: VGA2_GAIN3 (Bitfield-Mask: 0x07)

Definition at line 4780 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_23_REG_VGA2_GAIN3_Pos

#define DEM_RF_AGC_LUT_23_REG_VGA2_GAIN3_Pos   (8UL)

DEM RF_AGC_LUT_23_REG: VGA2_GAIN3 (Bit 8)

Definition at line 4779 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_45_REG_LNA_GAIN4_Msk

#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN4_Msk   (0xc0UL)

DEM RF_AGC_LUT_45_REG: LNA_GAIN4 (Bitfield-Mask: 0x03)

Definition at line 4792 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_45_REG_LNA_GAIN4_Pos

#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN4_Pos   (6UL)

DEM RF_AGC_LUT_45_REG: LNA_GAIN4 (Bit 6)

Definition at line 4791 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_45_REG_LNA_GAIN5_Msk

#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN5_Msk   (0xc000UL)

DEM RF_AGC_LUT_45_REG: LNA_GAIN5 (Bitfield-Mask: 0x03)

Definition at line 4798 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_45_REG_LNA_GAIN5_Pos

#define DEM_RF_AGC_LUT_45_REG_LNA_GAIN5_Pos   (14UL)

DEM RF_AGC_LUT_45_REG: LNA_GAIN5 (Bit 14)

Definition at line 4797 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_45_REG_VGA1_GAIN4_Msk

#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN4_Msk   (0x38UL)

DEM RF_AGC_LUT_45_REG: VGA1_GAIN4 (Bitfield-Mask: 0x07)

Definition at line 4790 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_45_REG_VGA1_GAIN4_Pos

#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN4_Pos   (3UL)

DEM RF_AGC_LUT_45_REG: VGA1_GAIN4 (Bit 3)

Definition at line 4789 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_45_REG_VGA1_GAIN5_Msk

#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN5_Msk   (0x3800UL)

DEM RF_AGC_LUT_45_REG: VGA1_GAIN5 (Bitfield-Mask: 0x07)

Definition at line 4796 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_45_REG_VGA1_GAIN5_Pos

#define DEM_RF_AGC_LUT_45_REG_VGA1_GAIN5_Pos   (11UL)

DEM RF_AGC_LUT_45_REG: VGA1_GAIN5 (Bit 11)

Definition at line 4795 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_45_REG_VGA2_GAIN4_Msk

#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN4_Msk   (0x7UL)

DEM RF_AGC_LUT_45_REG: VGA2_GAIN4 (Bitfield-Mask: 0x07)

Definition at line 4788 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_45_REG_VGA2_GAIN4_Pos

#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN4_Pos   (0UL)

DEM RF_AGC_LUT_45_REG: VGA2_GAIN4 (Bit 0)

Definition at line 4787 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_45_REG_VGA2_GAIN5_Msk

#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN5_Msk   (0x700UL)

DEM RF_AGC_LUT_45_REG: VGA2_GAIN5 (Bitfield-Mask: 0x07)

Definition at line 4794 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_45_REG_VGA2_GAIN5_Pos

#define DEM_RF_AGC_LUT_45_REG_VGA2_GAIN5_Pos   (8UL)

DEM RF_AGC_LUT_45_REG: VGA2_GAIN5 (Bit 8)

Definition at line 4793 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_67_REG_LNA_GAIN6_Msk

#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN6_Msk   (0xc0UL)

DEM RF_AGC_LUT_67_REG: LNA_GAIN6 (Bitfield-Mask: 0x03)

Definition at line 4806 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_67_REG_LNA_GAIN6_Pos

#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN6_Pos   (6UL)

DEM RF_AGC_LUT_67_REG: LNA_GAIN6 (Bit 6)

Definition at line 4805 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_67_REG_LNA_GAIN7_Msk

#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN7_Msk   (0xc000UL)

DEM RF_AGC_LUT_67_REG: LNA_GAIN7 (Bitfield-Mask: 0x03)

Definition at line 4812 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_67_REG_LNA_GAIN7_Pos

#define DEM_RF_AGC_LUT_67_REG_LNA_GAIN7_Pos   (14UL)

DEM RF_AGC_LUT_67_REG: LNA_GAIN7 (Bit 14)

Definition at line 4811 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_67_REG_VGA1_GAIN6_Msk

#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN6_Msk   (0x38UL)

DEM RF_AGC_LUT_67_REG: VGA1_GAIN6 (Bitfield-Mask: 0x07)

Definition at line 4804 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_67_REG_VGA1_GAIN6_Pos

#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN6_Pos   (3UL)

DEM RF_AGC_LUT_67_REG: VGA1_GAIN6 (Bit 3)

Definition at line 4803 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_67_REG_VGA1_GAIN7_Msk

#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN7_Msk   (0x3800UL)

DEM RF_AGC_LUT_67_REG: VGA1_GAIN7 (Bitfield-Mask: 0x07)

Definition at line 4810 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_67_REG_VGA1_GAIN7_Pos

#define DEM_RF_AGC_LUT_67_REG_VGA1_GAIN7_Pos   (11UL)

DEM RF_AGC_LUT_67_REG: VGA1_GAIN7 (Bit 11)

Definition at line 4809 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_67_REG_VGA2_GAIN6_Msk

#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN6_Msk   (0x7UL)

DEM RF_AGC_LUT_67_REG: VGA2_GAIN6 (Bitfield-Mask: 0x07)

Definition at line 4802 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_67_REG_VGA2_GAIN6_Pos

#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN6_Pos   (0UL)

DEM RF_AGC_LUT_67_REG: VGA2_GAIN6 (Bit 0)

Definition at line 4801 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_67_REG_VGA2_GAIN7_Msk

#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN7_Msk   (0x700UL)

DEM RF_AGC_LUT_67_REG: VGA2_GAIN7 (Bitfield-Mask: 0x07)

Definition at line 4808 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_67_REG_VGA2_GAIN7_Pos

#define DEM_RF_AGC_LUT_67_REG_VGA2_GAIN7_Pos   (8UL)

DEM RF_AGC_LUT_67_REG: VGA2_GAIN7 (Bit 8)

Definition at line 4807 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_89_REG_LNA_GAIN8_Msk

#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN8_Msk   (0xc0UL)

DEM RF_AGC_LUT_89_REG: LNA_GAIN8 (Bitfield-Mask: 0x03)

Definition at line 4820 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_89_REG_LNA_GAIN8_Pos

#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN8_Pos   (6UL)

DEM RF_AGC_LUT_89_REG: LNA_GAIN8 (Bit 6)

Definition at line 4819 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_89_REG_LNA_GAIN9_Msk

#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN9_Msk   (0xc000UL)

DEM RF_AGC_LUT_89_REG: LNA_GAIN9 (Bitfield-Mask: 0x03)

Definition at line 4826 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_89_REG_LNA_GAIN9_Pos

#define DEM_RF_AGC_LUT_89_REG_LNA_GAIN9_Pos   (14UL)

DEM RF_AGC_LUT_89_REG: LNA_GAIN9 (Bit 14)

Definition at line 4825 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_89_REG_VGA1_GAIN8_Msk

#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN8_Msk   (0x38UL)

DEM RF_AGC_LUT_89_REG: VGA1_GAIN8 (Bitfield-Mask: 0x07)

Definition at line 4818 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_89_REG_VGA1_GAIN8_Pos

#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN8_Pos   (3UL)

DEM RF_AGC_LUT_89_REG: VGA1_GAIN8 (Bit 3)

Definition at line 4817 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_89_REG_VGA1_GAIN9_Msk

#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN9_Msk   (0x3800UL)

DEM RF_AGC_LUT_89_REG: VGA1_GAIN9 (Bitfield-Mask: 0x07)

Definition at line 4824 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_89_REG_VGA1_GAIN9_Pos

#define DEM_RF_AGC_LUT_89_REG_VGA1_GAIN9_Pos   (11UL)

DEM RF_AGC_LUT_89_REG: VGA1_GAIN9 (Bit 11)

Definition at line 4823 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_89_REG_VGA2_GAIN8_Msk

#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN8_Msk   (0x7UL)

DEM RF_AGC_LUT_89_REG: VGA2_GAIN8 (Bitfield-Mask: 0x07)

Definition at line 4816 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_89_REG_VGA2_GAIN8_Pos

#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN8_Pos   (0UL)

DEM RF_AGC_LUT_89_REG: VGA2_GAIN8 (Bit 0)

Definition at line 4815 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_89_REG_VGA2_GAIN9_Msk

#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN9_Msk   (0x700UL)

DEM RF_AGC_LUT_89_REG: VGA2_GAIN9 (Bitfield-Mask: 0x07)

Definition at line 4822 of file DA14680BA.h.

◆ DEM_RF_AGC_LUT_89_REG_VGA2_GAIN9_Pos

#define DEM_RF_AGC_LUT_89_REG_VGA2_GAIN9_Pos   (8UL)

DEM RF_AGC_LUT_89_REG: VGA2_GAIN9 (Bit 8)

Definition at line 4821 of file DA14680BA.h.

◆ DEM_RF_AGC_RESULT_REG_AFC_RD_Msk

#define DEM_RF_AGC_RESULT_REG_AFC_RD_Msk   (0xffUL)

DEM RF_AGC_RESULT_REG: AFC_RD (Bitfield-Mask: 0xff)

Definition at line 4900 of file DA14680BA.h.

◆ DEM_RF_AGC_RESULT_REG_AFC_RD_Pos

#define DEM_RF_AGC_RESULT_REG_AFC_RD_Pos   (0UL)

DEM RF_AGC_RESULT_REG: AFC_RD (Bit 0)

Definition at line 4899 of file DA14680BA.h.

◆ DEM_RF_AGC_RESULT_REG_AGCSETTING_RD_Msk

#define DEM_RF_AGC_RESULT_REG_AGCSETTING_RD_Msk   (0xf00UL)

DEM RF_AGC_RESULT_REG: AGCSETTING_RD (Bitfield-Mask: 0x0f)

Definition at line 4902 of file DA14680BA.h.

◆ DEM_RF_AGC_RESULT_REG_AGCSETTING_RD_Pos

#define DEM_RF_AGC_RESULT_REG_AGCSETTING_RD_Pos   (8UL)

DEM RF_AGC_RESULT_REG: AGCSETTING_RD (Bit 8)

Definition at line 4901 of file DA14680BA.h.

◆ DEM_RF_CCA_RSSITH_REG_CCA_RSSITH_Msk

#define DEM_RF_CCA_RSSITH_REG_CCA_RSSITH_Msk   (0x1fffUL)

DEM RF_CCA_RSSITH_REG: CCA_RSSITH (Bitfield-Mask: 0x1fff)

Definition at line 5052 of file DA14680BA.h.

◆ DEM_RF_CCA_RSSITH_REG_CCA_RSSITH_Pos

#define DEM_RF_CCA_RSSITH_REG_CCA_RSSITH_Pos   (0UL)

DEM RF_CCA_RSSITH_REG: CCA_RSSITH (Bit 0)

Definition at line 5051 of file DA14680BA.h.

◆ DEM_RF_CCA_RSSITH_REG_SIGDET_TIMEOUT_LEN_Msk

#define DEM_RF_CCA_RSSITH_REG_SIGDET_TIMEOUT_LEN_Msk   (0xe000UL)

DEM RF_CCA_RSSITH_REG: SIGDET_TIMEOUT_LEN (Bitfield-Mask: 0x07)

Definition at line 5054 of file DA14680BA.h.

◆ DEM_RF_CCA_RSSITH_REG_SIGDET_TIMEOUT_LEN_Pos

#define DEM_RF_CCA_RSSITH_REG_SIGDET_TIMEOUT_LEN_Pos   (13UL)

DEM RF_CCA_RSSITH_REG: SIGDET_TIMEOUT_LEN (Bit 13)

Definition at line 5053 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_I_WR_Msk

#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_I_WR_Msk   (0xffUL)

DEM RF_DC_OFFSET_CTRL1_REG: DCOFFSET_I_WR (Bitfield-Mask: 0xff)

Definition at line 4862 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_I_WR_Pos

#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_I_WR_Pos   (0UL)

DEM RF_DC_OFFSET_CTRL1_REG: DCOFFSET_I_WR (Bit 0)

Definition at line 4861 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_Q_WR_Msk

#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_Q_WR_Msk   (0xff00UL)

DEM RF_DC_OFFSET_CTRL1_REG: DCOFFSET_Q_WR (Bitfield-Mask: 0xff)

Definition at line 4864 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_Q_WR_Pos

#define DEM_RF_DC_OFFSET_CTRL1_REG_DCOFFSET_Q_WR_Pos   (8UL)

DEM RF_DC_OFFSET_CTRL1_REG: DCOFFSET_Q_WR (Bit 8)

Definition at line 4863 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCNGAIN_Msk

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNGAIN_Msk   (0x180UL)

DEM RF_DC_OFFSET_CTRL2_REG: DCNGAIN (Bitfield-Mask: 0x03)

Definition at line 4876 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCNGAIN_Pos

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNGAIN_Pos   (7UL)

DEM RF_DC_OFFSET_CTRL2_REG: DCNGAIN (Bit 7)

Definition at line 4875 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCNSTEP_Msk

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNSTEP_Msk   (0x70UL)

DEM RF_DC_OFFSET_CTRL2_REG: DCNSTEP (Bitfield-Mask: 0x07)

Definition at line 4874 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCNSTEP_Pos

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCNSTEP_Pos   (4UL)

DEM RF_DC_OFFSET_CTRL2_REG: DCNSTEP (Bit 4)

Definition at line 4873 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCOFFSET_SEL_Msk

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCOFFSET_SEL_Msk   (0x1UL)

DEM RF_DC_OFFSET_CTRL2_REG: DCOFFSET_SEL (Bitfield-Mask: 0x01)

Definition at line 4868 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCOFFSET_SEL_Pos

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCOFFSET_SEL_Pos   (0UL)

DEM RF_DC_OFFSET_CTRL2_REG: DCOFFSET_SEL (Bit 0)

Definition at line 4867 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_EN_Msk

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_EN_Msk   (0x2UL)

DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_EN (Bitfield-Mask: 0x01)

Definition at line 4870 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_EN_Pos

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_EN_Pos   (1UL)

DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_EN (Bit 1)

Definition at line 4869 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_INIT_Msk

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_INIT_Msk   (0x200UL)

DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_INIT (Bitfield-Mask: 0x01)

Definition at line 4878 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_INIT_Pos

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPARCAL_INIT_Pos   (9UL)

DEM RF_DC_OFFSET_CTRL2_REG: DCPARCAL_INIT (Bit 9)

Definition at line 4877 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCPOLE_Msk

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPOLE_Msk   (0xcUL)

DEM RF_DC_OFFSET_CTRL2_REG: DCPOLE (Bitfield-Mask: 0x03)

Definition at line 4872 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCPOLE_Pos

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCPOLE_Pos   (2UL)

DEM RF_DC_OFFSET_CTRL2_REG: DCPOLE (Bit 2)

Definition at line 4871 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCVGA1SCALE_EN_Msk

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCVGA1SCALE_EN_Msk   (0x400UL)

DEM RF_DC_OFFSET_CTRL2_REG: DCVGA1SCALE_EN (Bitfield-Mask: 0x01)

Definition at line 4880 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL2_REG_DCVGA1SCALE_EN_Pos

#define DEM_RF_DC_OFFSET_CTRL2_REG_DCVGA1SCALE_EN_Pos   (10UL)

DEM RF_DC_OFFSET_CTRL2_REG: DCVGA1SCALE_EN (Bit 10)

Definition at line 4879 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_I_Msk

#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_I_Msk   (0xffUL)

DEM RF_DC_OFFSET_CTRL3_REG: DCBETA_I (Bitfield-Mask: 0xff)

Definition at line 4884 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_I_Pos

#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_I_Pos   (0UL)

DEM RF_DC_OFFSET_CTRL3_REG: DCBETA_I (Bit 0)

Definition at line 4883 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_Q_Msk

#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_Q_Msk   (0xff00UL)

DEM RF_DC_OFFSET_CTRL3_REG: DCBETA_Q (Bitfield-Mask: 0xff)

Definition at line 4886 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_Q_Pos

#define DEM_RF_DC_OFFSET_CTRL3_REG_DCBETA_Q_Pos   (8UL)

DEM RF_DC_OFFSET_CTRL3_REG: DCBETA_Q (Bit 8)

Definition at line 4885 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL0_Msk

#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL0_Msk   (0xfUL)

DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL0 (Bitfield-Mask: 0x0f)

Definition at line 4890 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL0_Pos

#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL0_Pos   (0UL)

DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL0 (Bit 0)

Definition at line 4889 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL1_Msk

#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL1_Msk   (0xf0UL)

DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL1 (Bitfield-Mask: 0x0f)

Definition at line 4892 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL1_Pos

#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL1_Pos   (4UL)

DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL1 (Bit 4)

Definition at line 4891 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL2_Msk

#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL2_Msk   (0xf00UL)

DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL2 (Bitfield-Mask: 0x0f)

Definition at line 4894 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL2_Pos

#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL2_Pos   (8UL)

DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL2 (Bit 8)

Definition at line 4893 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL3_Msk

#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL3_Msk   (0xf000UL)

DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL3 (Bitfield-Mask: 0x0f)

Definition at line 4896 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL3_Pos

#define DEM_RF_DC_OFFSET_CTRL4_REG_DCAGCSETTING_FULL3_Pos   (12UL)

DEM RF_DC_OFFSET_CTRL4_REG: DCAGCSETTING_FULL3 (Bit 12)

Definition at line 4895 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_I_RD_Msk

#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_I_RD_Msk   (0xffUL)

DEM RF_DC_OFFSET_RESULT_REG: DCOFFSET_I_RD (Bitfield-Mask: 0xff)

Definition at line 4912 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_I_RD_Pos

#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_I_RD_Pos   (0UL)

DEM RF_DC_OFFSET_RESULT_REG: DCOFFSET_I_RD (Bit 0)

Definition at line 4911 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_Q_RD_Msk

#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_Q_RD_Msk   (0xff00UL)

DEM RF_DC_OFFSET_RESULT_REG: DCOFFSET_Q_RD (Bitfield-Mask: 0xff)

Definition at line 4914 of file DA14680BA.h.

◆ DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_Q_RD_Pos

#define DEM_RF_DC_OFFSET_RESULT_REG_DCOFFSET_Q_RD_Pos   (8UL)

DEM RF_DC_OFFSET_RESULT_REG: DCOFFSET_Q_RD (Bit 8)

Definition at line 4913 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_BLE_DDC_EN_Msk

#define DEM_RF_DEM_CTRL_REG_BLE_DDC_EN_Msk   (0x80UL)

DEM RF_DEM_CTRL_REG: BLE_DDC_EN (Bitfield-Mask: 0x01)

Definition at line 4748 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_BLE_DDC_EN_Pos

#define DEM_RF_DEM_CTRL_REG_BLE_DDC_EN_Pos   (7UL)

DEM RF_DEM_CTRL_REG: BLE_DDC_EN (Bit 7)

Definition at line 4747 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_CFE_DOUBLE_EN_Msk

#define DEM_RF_DEM_CTRL_REG_CFE_DOUBLE_EN_Msk   (0x200UL)

DEM RF_DEM_CTRL_REG: CFE_DOUBLE_EN (Bitfield-Mask: 0x01)

Definition at line 4752 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_CFE_DOUBLE_EN_Pos

#define DEM_RF_DEM_CTRL_REG_CFE_DOUBLE_EN_Pos   (9UL)

DEM RF_DEM_CTRL_REG: CFE_DOUBLE_EN (Bit 9)

Definition at line 4751 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_CFE_MEDIAN_EN_Msk

#define DEM_RF_DEM_CTRL_REG_CFE_MEDIAN_EN_Msk   (0x400UL)

DEM RF_DEM_CTRL_REG: CFE_MEDIAN_EN (Bitfield-Mask: 0x01)

Definition at line 4754 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_CFE_MEDIAN_EN_Pos

#define DEM_RF_DEM_CTRL_REG_CFE_MEDIAN_EN_Pos   (10UL)

DEM RF_DEM_CTRL_REG: CFE_MEDIAN_EN (Bit 10)

Definition at line 4753 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_CFE_PPOLE_Msk

#define DEM_RF_DEM_CTRL_REG_CFE_PPOLE_Msk   (0x3800UL)

DEM RF_DEM_CTRL_REG: CFE_PPOLE (Bitfield-Mask: 0x07)

Definition at line 4756 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_CFE_PPOLE_Pos

#define DEM_RF_DEM_CTRL_REG_CFE_PPOLE_Pos   (11UL)

DEM RF_DEM_CTRL_REG: CFE_PPOLE (Bit 11)

Definition at line 4755 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_DEM_HSI_POL_Msk

#define DEM_RF_DEM_CTRL_REG_DEM_HSI_POL_Msk   (0x2UL)

DEM RF_DEM_CTRL_REG: DEM_HSI_POL (Bitfield-Mask: 0x01)

Definition at line 4742 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_DEM_HSI_POL_Pos

#define DEM_RF_DEM_CTRL_REG_DEM_HSI_POL_Pos   (1UL)

DEM RF_DEM_CTRL_REG: DEM_HSI_POL (Bit 1)

Definition at line 4741 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_EQUAL_EN_Msk

#define DEM_RF_DEM_CTRL_REG_EQUAL_EN_Msk   (0x40UL)

DEM RF_DEM_CTRL_REG: EQUAL_EN (Bitfield-Mask: 0x01)

Definition at line 4746 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_EQUAL_EN_Pos

#define DEM_RF_DEM_CTRL_REG_EQUAL_EN_Pos   (6UL)

DEM RF_DEM_CTRL_REG: EQUAL_EN (Bit 6)

Definition at line 4745 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_IQCORR_EN_Msk

#define DEM_RF_DEM_CTRL_REG_IQCORR_EN_Msk   (0x100UL)

DEM RF_DEM_CTRL_REG: IQCORR_EN (Bitfield-Mask: 0x01)

Definition at line 4750 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_IQCORR_EN_Pos

#define DEM_RF_DEM_CTRL_REG_IQCORR_EN_Pos   (8UL)

DEM RF_DEM_CTRL_REG: IQCORR_EN (Bit 8)

Definition at line 4749 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_MATCH0101_TH_Msk

#define DEM_RF_DEM_CTRL_REG_MATCH0101_TH_Msk   (0x3cUL)

DEM RF_DEM_CTRL_REG: MATCH0101_TH (Bitfield-Mask: 0x0f)

Definition at line 4744 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_MATCH0101_TH_Pos

#define DEM_RF_DEM_CTRL_REG_MATCH0101_TH_Pos   (2UL)

DEM RF_DEM_CTRL_REG: MATCH0101_TH (Bit 2)

Definition at line 4743 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_RXDATA_INV_Msk

#define DEM_RF_DEM_CTRL_REG_RXDATA_INV_Msk   (0x1UL)

DEM RF_DEM_CTRL_REG: RXDATA_INV (Bitfield-Mask: 0x01)

Definition at line 4740 of file DA14680BA.h.

◆ DEM_RF_DEM_CTRL_REG_RXDATA_INV_Pos

#define DEM_RF_DEM_CTRL_REG_RXDATA_INV_Pos   (0UL)

DEM RF_DEM_CTRL_REG: RXDATA_INV (Bit 0)

Definition at line 4739 of file DA14680BA.h.

◆ DEM_RF_DEM_IQCORRECT_REG_IQCORR_ALPHA_Msk

#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_ALPHA_Msk   (0xff00UL)

DEM RF_DEM_IQCORRECT_REG: IQCORR_ALPHA (Bitfield-Mask: 0xff)

Definition at line 5022 of file DA14680BA.h.

◆ DEM_RF_DEM_IQCORRECT_REG_IQCORR_ALPHA_Pos

#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_ALPHA_Pos   (8UL)

DEM RF_DEM_IQCORRECT_REG: IQCORR_ALPHA (Bit 8)

Definition at line 5021 of file DA14680BA.h.

◆ DEM_RF_DEM_IQCORRECT_REG_IQCORR_BETA_Msk

#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_BETA_Msk   (0xffUL)

DEM RF_DEM_IQCORRECT_REG: IQCORR_BETA (Bitfield-Mask: 0xff)

Definition at line 5020 of file DA14680BA.h.

◆ DEM_RF_DEM_IQCORRECT_REG_IQCORR_BETA_Pos

#define DEM_RF_DEM_IQCORRECT_REG_IQCORR_BETA_Pos   (0UL)

DEM RF_DEM_IQCORRECT_REG: IQCORR_BETA (Bit 0)

Definition at line 5019 of file DA14680BA.h.

◆ DEM_RF_DEM_TESTMODE_REG_DEM_TESTMODE_Msk

#define DEM_RF_DEM_TESTMODE_REG_DEM_TESTMODE_Msk   (0x3ffUL)

DEM RF_DEM_TESTMODE_REG: DEM_TESTMODE (Bitfield-Mask: 0x3ff)

Definition at line 5016 of file DA14680BA.h.

◆ DEM_RF_DEM_TESTMODE_REG_DEM_TESTMODE_Pos

#define DEM_RF_DEM_TESTMODE_REG_DEM_TESTMODE_Pos   (0UL)

DEM RF_DEM_TESTMODE_REG: DEM_TESTMODE (Bit 0)

Definition at line 5015 of file DA14680BA.h.

◆ DEM_RF_FSSS_I_RESULT_REG_FSSS_I_RD_Msk

#define DEM_RF_FSSS_I_RESULT_REG_FSSS_I_RD_Msk   (0xffffUL)

DEM RF_FSSS_I_RESULT_REG: FSSS_I_RD (Bitfield-Mask: 0xffff)

Definition at line 5040 of file DA14680BA.h.

◆ DEM_RF_FSSS_I_RESULT_REG_FSSS_I_RD_Pos

#define DEM_RF_FSSS_I_RESULT_REG_FSSS_I_RD_Pos   (0UL)

DEM RF_FSSS_I_RESULT_REG: FSSS_I_RD (Bit 0)

Definition at line 5039 of file DA14680BA.h.

◆ DEM_RF_FSSS_MAG_RESULT_REG_FSSS_MAG_RD_Msk

#define DEM_RF_FSSS_MAG_RESULT_REG_FSSS_MAG_RD_Msk   (0xffffUL)

DEM RF_FSSS_MAG_RESULT_REG: FSSS_MAG_RD (Bitfield-Mask: 0xffff)

Definition at line 5048 of file DA14680BA.h.

◆ DEM_RF_FSSS_MAG_RESULT_REG_FSSS_MAG_RD_Pos

#define DEM_RF_FSSS_MAG_RESULT_REG_FSSS_MAG_RD_Pos   (0UL)

DEM RF_FSSS_MAG_RESULT_REG: FSSS_MAG_RD (Bit 0)

Definition at line 5047 of file DA14680BA.h.

◆ DEM_RF_FSSS_Q_RESULT_REG_FSSS_Q_RD_Msk

#define DEM_RF_FSSS_Q_RESULT_REG_FSSS_Q_RD_Msk   (0xffffUL)

DEM RF_FSSS_Q_RESULT_REG: FSSS_Q_RD (Bitfield-Mask: 0xffff)

Definition at line 5044 of file DA14680BA.h.

◆ DEM_RF_FSSS_Q_RESULT_REG_FSSS_Q_RD_Pos

#define DEM_RF_FSSS_Q_RESULT_REG_FSSS_Q_RD_Pos   (0UL)

DEM RF_FSSS_Q_RESULT_REG: FSSS_Q_RD (Bit 0)

Definition at line 5043 of file DA14680BA.h.

◆ DEM_RF_FTDF_COBI_HIGH_REG_COBI_Msk

#define DEM_RF_FTDF_COBI_HIGH_REG_COBI_Msk   (0xffffUL)

DEM RF_FTDF_COBI_HIGH_REG: COBI (Bitfield-Mask: 0xffff)

Definition at line 5012 of file DA14680BA.h.

◆ DEM_RF_FTDF_COBI_HIGH_REG_COBI_Pos

#define DEM_RF_FTDF_COBI_HIGH_REG_COBI_Pos   (0UL)

DEM RF_FTDF_COBI_HIGH_REG: COBI (Bit 0)

Definition at line 5011 of file DA14680BA.h.

◆ DEM_RF_FTDF_COBI_LOW_REG_COBI_Msk

#define DEM_RF_FTDF_COBI_LOW_REG_COBI_Msk   (0xffffUL)

DEM RF_FTDF_COBI_LOW_REG: COBI (Bitfield-Mask: 0xffff)

Definition at line 5008 of file DA14680BA.h.

◆ DEM_RF_FTDF_COBI_LOW_REG_COBI_Pos

#define DEM_RF_FTDF_COBI_LOW_REG_COBI_Pos   (0UL)

DEM RF_FTDF_COBI_LOW_REG: COBI (Bit 0)

Definition at line 5007 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL1_REG_CFE_BIAS_Msk

#define DEM_RF_FTDF_CTRL1_REG_CFE_BIAS_Msk   (0x3ffUL)

DEM RF_FTDF_CTRL1_REG: CFE_BIAS (Bitfield-Mask: 0x3ff)

Definition at line 4928 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL1_REG_CFE_BIAS_Pos

#define DEM_RF_FTDF_CTRL1_REG_CFE_BIAS_Pos   (0UL)

DEM RF_FTDF_CTRL1_REG: CFE_BIAS (Bit 0)

Definition at line 4927 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL1_REG_CFE_MODE_Msk

#define DEM_RF_FTDF_CTRL1_REG_CFE_MODE_Msk   (0xc00UL)

DEM RF_FTDF_CTRL1_REG: CFE_MODE (Bitfield-Mask: 0x03)

Definition at line 4930 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL1_REG_CFE_MODE_Pos

#define DEM_RF_FTDF_CTRL1_REG_CFE_MODE_Pos   (10UL)

DEM RF_FTDF_CTRL1_REG: CFE_MODE (Bit 10)

Definition at line 4929 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL1_REG_CFE_NSTEP_Msk

#define DEM_RF_FTDF_CTRL1_REG_CFE_NSTEP_Msk   (0x3000UL)

DEM RF_FTDF_CTRL1_REG: CFE_NSTEP (Bitfield-Mask: 0x03)

Definition at line 4932 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL1_REG_CFE_NSTEP_Pos

#define DEM_RF_FTDF_CTRL1_REG_CFE_NSTEP_Pos   (12UL)

DEM RF_FTDF_CTRL1_REG: CFE_NSTEP (Bit 12)

Definition at line 4931 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL1_REG_CHSEL_FILT_MODE2_Msk

#define DEM_RF_FTDF_CTRL1_REG_CHSEL_FILT_MODE2_Msk   (0xc000UL)

DEM RF_FTDF_CTRL1_REG: CHSEL_FILT_MODE2 (Bitfield-Mask: 0x03)

Definition at line 4934 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL1_REG_CHSEL_FILT_MODE2_Pos

#define DEM_RF_FTDF_CTRL1_REG_CHSEL_FILT_MODE2_Pos   (14UL)

DEM RF_FTDF_CTRL1_REG: CHSEL_FILT_MODE2 (Bit 14)

Definition at line 4933 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL2_REG_CORRTH_Msk

#define DEM_RF_FTDF_CTRL2_REG_CORRTH_Msk   (0x3fUL)

DEM RF_FTDF_CTRL2_REG: CORRTH (Bitfield-Mask: 0x3f)

Definition at line 4938 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL2_REG_CORRTH_Pos

#define DEM_RF_FTDF_CTRL2_REG_CORRTH_Pos   (0UL)

DEM RF_FTDF_CTRL2_REG: CORRTH (Bit 0)

Definition at line 4937 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL2_REG_NORM_EN_Msk

#define DEM_RF_FTDF_CTRL2_REG_NORM_EN_Msk   (0x40UL)

DEM RF_FTDF_CTRL2_REG: NORM_EN (Bitfield-Mask: 0x01)

Definition at line 4940 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL2_REG_NORM_EN_Pos

#define DEM_RF_FTDF_CTRL2_REG_NORM_EN_Pos   (6UL)

DEM RF_FTDF_CTRL2_REG: NORM_EN (Bit 6)

Definition at line 4939 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL2_REG_PD_MODE_Msk

#define DEM_RF_FTDF_CTRL2_REG_PD_MODE_Msk   (0x80UL)

DEM RF_FTDF_CTRL2_REG: PD_MODE (Bitfield-Mask: 0x01)

Definition at line 4942 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL2_REG_PD_MODE_Pos

#define DEM_RF_FTDF_CTRL2_REG_PD_MODE_Pos   (7UL)

DEM RF_FTDF_CTRL2_REG: PD_MODE (Bit 7)

Definition at line 4941 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL2_REG_PD_NPEAK_Msk

#define DEM_RF_FTDF_CTRL2_REG_PD_NPEAK_Msk   (0x700UL)

DEM RF_FTDF_CTRL2_REG: PD_NPEAK (Bitfield-Mask: 0x07)

Definition at line 4944 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL2_REG_PD_NPEAK_Pos

#define DEM_RF_FTDF_CTRL2_REG_PD_NPEAK_Pos   (8UL)

DEM RF_FTDF_CTRL2_REG: PD_NPEAK (Bit 8)

Definition at line 4943 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL2_REG_PD_NWIN_Msk

#define DEM_RF_FTDF_CTRL2_REG_PD_NWIN_Msk   (0x3800UL)

DEM RF_FTDF_CTRL2_REG: PD_NWIN (Bitfield-Mask: 0x07)

Definition at line 4946 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL2_REG_PD_NWIN_Pos

#define DEM_RF_FTDF_CTRL2_REG_PD_NWIN_Pos   (11UL)

DEM RF_FTDF_CTRL2_REG: PD_NWIN (Bit 11)

Definition at line 4945 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL2_REG_PD_OFFSET_Msk

#define DEM_RF_FTDF_CTRL2_REG_PD_OFFSET_Msk   (0xc000UL)

DEM RF_FTDF_CTRL2_REG: PD_OFFSET (Bitfield-Mask: 0x03)

Definition at line 4948 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL2_REG_PD_OFFSET_Pos

#define DEM_RF_FTDF_CTRL2_REG_PD_OFFSET_Pos   (14UL)

DEM RF_FTDF_CTRL2_REG: PD_OFFSET (Bit 14)

Definition at line 4947 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL3_REG_CHSEL_FILT_MODE1_Msk

#define DEM_RF_FTDF_CTRL3_REG_CHSEL_FILT_MODE1_Msk   (0x3000UL)

DEM RF_FTDF_CTRL3_REG: CHSEL_FILT_MODE1 (Bitfield-Mask: 0x03)

Definition at line 4960 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL3_REG_CHSEL_FILT_MODE1_Pos

#define DEM_RF_FTDF_CTRL3_REG_CHSEL_FILT_MODE1_Pos   (12UL)

DEM RF_FTDF_CTRL3_REG: CHSEL_FILT_MODE1 (Bit 12)

Definition at line 4959 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL3_REG_DS_OFFSET_Msk

#define DEM_RF_FTDF_CTRL3_REG_DS_OFFSET_Msk   (0xc000UL)

DEM RF_FTDF_CTRL3_REG: DS_OFFSET (Bitfield-Mask: 0x03)

Definition at line 4962 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL3_REG_DS_OFFSET_Pos

#define DEM_RF_FTDF_CTRL3_REG_DS_OFFSET_Pos   (14UL)

DEM RF_FTDF_CTRL3_REG: DS_OFFSET (Bit 14)

Definition at line 4961 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL3_REG_FIF_Msk

#define DEM_RF_FTDF_CTRL3_REG_FIF_Msk   (0x1ffUL)

DEM RF_FTDF_CTRL3_REG: FIF (Bitfield-Mask: 0x1ff)

Definition at line 4952 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL3_REG_FIF_Pos

#define DEM_RF_FTDF_CTRL3_REG_FIF_Pos   (0UL)

DEM RF_FTDF_CTRL3_REG: FIF (Bit 0)

Definition at line 4951 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL3_REG_FTDF_DDC_EN_Msk

#define DEM_RF_FTDF_CTRL3_REG_FTDF_DDC_EN_Msk   (0x200UL)

DEM RF_FTDF_CTRL3_REG: FTDF_DDC_EN (Bitfield-Mask: 0x01)

Definition at line 4954 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL3_REG_FTDF_DDC_EN_Pos

#define DEM_RF_FTDF_CTRL3_REG_FTDF_DDC_EN_Pos   (9UL)

DEM RF_FTDF_CTRL3_REG: FTDF_DDC_EN (Bit 9)

Definition at line 4953 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL3_REG_MATCH_FILT_EN_Msk

#define DEM_RF_FTDF_CTRL3_REG_MATCH_FILT_EN_Msk   (0x400UL)

DEM RF_FTDF_CTRL3_REG: MATCH_FILT_EN (Bitfield-Mask: 0x01)

Definition at line 4956 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL3_REG_MATCH_FILT_EN_Pos

#define DEM_RF_FTDF_CTRL3_REG_MATCH_FILT_EN_Pos   (10UL)

DEM RF_FTDF_CTRL3_REG: MATCH_FILT_EN (Bit 10)

Definition at line 4955 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL3_REG_TIMING_CORR_EN_Msk

#define DEM_RF_FTDF_CTRL3_REG_TIMING_CORR_EN_Msk   (0x800UL)

DEM RF_FTDF_CTRL3_REG: TIMING_CORR_EN (Bitfield-Mask: 0x01)

Definition at line 4958 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL3_REG_TIMING_CORR_EN_Pos

#define DEM_RF_FTDF_CTRL3_REG_TIMING_CORR_EN_Pos   (11UL)

DEM RF_FTDF_CTRL3_REG: TIMING_CORR_EN (Bit 11)

Definition at line 4957 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_CCA_MODE_Msk

#define DEM_RF_FTDF_CTRL4_REG_CCA_MODE_Msk   (0x4000UL)

DEM RF_FTDF_CTRL4_REG: CCA_MODE (Bitfield-Mask: 0x01)

Definition at line 4980 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_CCA_MODE_Pos

#define DEM_RF_FTDF_CTRL4_REG_CCA_MODE_Pos   (14UL)

DEM RF_FTDF_CTRL4_REG: CCA_MODE (Bit 14)

Definition at line 4979 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_FTDF_HSI_POL_Msk

#define DEM_RF_FTDF_CTRL4_REG_FTDF_HSI_POL_Msk   (0x2000UL)

DEM RF_FTDF_CTRL4_REG: FTDF_HSI_POL (Bitfield-Mask: 0x01)

Definition at line 4978 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_FTDF_HSI_POL_Pos

#define DEM_RF_FTDF_CTRL4_REG_FTDF_HSI_POL_Pos   (13UL)

DEM RF_FTDF_CTRL4_REG: FTDF_HSI_POL (Bit 13)

Definition at line 4977 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_LQI_CORRTH_EN_Msk

#define DEM_RF_FTDF_CTRL4_REG_LQI_CORRTH_EN_Msk   (0x400UL)

DEM RF_FTDF_CTRL4_REG: LQI_CORRTH_EN (Bitfield-Mask: 0x01)

Definition at line 4974 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_LQI_CORRTH_EN_Pos

#define DEM_RF_FTDF_CTRL4_REG_LQI_CORRTH_EN_Pos   (10UL)

DEM RF_FTDF_CTRL4_REG: LQI_CORRTH_EN (Bit 10)

Definition at line 4973 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_LQI_PREAMBLE_EN_Msk

#define DEM_RF_FTDF_CTRL4_REG_LQI_PREAMBLE_EN_Msk   (0x100UL)

DEM RF_FTDF_CTRL4_REG: LQI_PREAMBLE_EN (Bitfield-Mask: 0x01)

Definition at line 4970 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_LQI_PREAMBLE_EN_Pos

#define DEM_RF_FTDF_CTRL4_REG_LQI_PREAMBLE_EN_Pos   (8UL)

DEM RF_FTDF_CTRL4_REG: LQI_PREAMBLE_EN (Bit 8)

Definition at line 4969 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_LQI_SCALE_Msk

#define DEM_RF_FTDF_CTRL4_REG_LQI_SCALE_Msk   (0x1800UL)

DEM RF_FTDF_CTRL4_REG: LQI_SCALE (Bitfield-Mask: 0x03)

Definition at line 4976 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_LQI_SCALE_Pos

#define DEM_RF_FTDF_CTRL4_REG_LQI_SCALE_Pos   (11UL)

DEM RF_FTDF_CTRL4_REG: LQI_SCALE (Bit 11)

Definition at line 4975 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_LQI_SYMBOL_EN_Msk

#define DEM_RF_FTDF_CTRL4_REG_LQI_SYMBOL_EN_Msk   (0x200UL)

DEM RF_FTDF_CTRL4_REG: LQI_SYMBOL_EN (Bitfield-Mask: 0x01)

Definition at line 4972 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_LQI_SYMBOL_EN_Pos

#define DEM_RF_FTDF_CTRL4_REG_LQI_SYMBOL_EN_Pos   (9UL)

DEM RF_FTDF_CTRL4_REG: LQI_SYMBOL_EN (Bit 9)

Definition at line 4971 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_SFD0_Msk

#define DEM_RF_FTDF_CTRL4_REG_SFD0_Msk   (0xfUL)

DEM RF_FTDF_CTRL4_REG: SFD0 (Bitfield-Mask: 0x0f)

Definition at line 4966 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_SFD0_Pos

#define DEM_RF_FTDF_CTRL4_REG_SFD0_Pos   (0UL)

DEM RF_FTDF_CTRL4_REG: SFD0 (Bit 0)

Definition at line 4965 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_SFD1_Msk

#define DEM_RF_FTDF_CTRL4_REG_SFD1_Msk   (0xf0UL)

DEM RF_FTDF_CTRL4_REG: SFD1 (Bitfield-Mask: 0x0f)

Definition at line 4968 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_SFD1_Pos

#define DEM_RF_FTDF_CTRL4_REG_SFD1_Pos   (4UL)

DEM RF_FTDF_CTRL4_REG: SFD1 (Bit 4)

Definition at line 4967 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_SO_FTDF_SEL_Msk

#define DEM_RF_FTDF_CTRL4_REG_SO_FTDF_SEL_Msk   (0x8000UL)

DEM RF_FTDF_CTRL4_REG: SO_FTDF_SEL (Bitfield-Mask: 0x01)

Definition at line 4982 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL4_REG_SO_FTDF_SEL_Pos

#define DEM_RF_FTDF_CTRL4_REG_SO_FTDF_SEL_Pos   (15UL)

DEM RF_FTDF_CTRL4_REG: SO_FTDF_SEL (Bit 15)

Definition at line 4981 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL5_REG_DS_OFFSET_SEL_Msk

#define DEM_RF_FTDF_CTRL5_REG_DS_OFFSET_SEL_Msk   (0x8000UL)

DEM RF_FTDF_CTRL5_REG: DS_OFFSET_SEL (Bitfield-Mask: 0x01)

Definition at line 5004 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL5_REG_DS_OFFSET_SEL_Pos

#define DEM_RF_FTDF_CTRL5_REG_DS_OFFSET_SEL_Pos   (15UL)

DEM RF_FTDF_CTRL5_REG: DS_OFFSET_SEL (Bit 15)

Definition at line 5003 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL5_REG_FSSS_CLEAR_Msk

#define DEM_RF_FTDF_CTRL5_REG_FSSS_CLEAR_Msk   (0x4000UL)

DEM RF_FTDF_CTRL5_REG: FSSS_CLEAR (Bitfield-Mask: 0x01)

Definition at line 5002 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL5_REG_FSSS_CLEAR_Pos

#define DEM_RF_FTDF_CTRL5_REG_FSSS_CLEAR_Pos   (14UL)

DEM RF_FTDF_CTRL5_REG: FSSS_CLEAR (Bit 14)

Definition at line 5001 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL5_REG_FTDF_DDC_INV_Msk

#define DEM_RF_FTDF_CTRL5_REG_FTDF_DDC_INV_Msk   (0x2000UL)

DEM RF_FTDF_CTRL5_REG: FTDF_DDC_INV (Bitfield-Mask: 0x01)

Definition at line 5000 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL5_REG_FTDF_DDC_INV_Pos

#define DEM_RF_FTDF_CTRL5_REG_FTDF_DDC_INV_Pos   (13UL)

DEM RF_FTDF_CTRL5_REG: FTDF_DDC_INV (Bit 13)

Definition at line 4999 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL5_REG_RSSITH_Msk

#define DEM_RF_FTDF_CTRL5_REG_RSSITH_Msk   (0x1fffUL)

DEM RF_FTDF_CTRL5_REG: RSSITH (Bitfield-Mask: 0x1fff)

Definition at line 4998 of file DA14680BA.h.

◆ DEM_RF_FTDF_CTRL5_REG_RSSITH_Pos

#define DEM_RF_FTDF_CTRL5_REG_RSSITH_Pos   (0UL)

DEM RF_FTDF_CTRL5_REG: RSSITH (Bit 0)

Definition at line 4997 of file DA14680BA.h.

◆ DEM_RF_FTDF_LOOP_GAIN_DS_REG_KI_LF_DS_Msk

#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KI_LF_DS_Msk   (0xff00UL)

DEM RF_FTDF_LOOP_GAIN_DS_REG: KI_LF_DS (Bitfield-Mask: 0xff)

Definition at line 4994 of file DA14680BA.h.

◆ DEM_RF_FTDF_LOOP_GAIN_DS_REG_KI_LF_DS_Pos

#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KI_LF_DS_Pos   (8UL)

DEM RF_FTDF_LOOP_GAIN_DS_REG: KI_LF_DS (Bit 8)

Definition at line 4993 of file DA14680BA.h.

◆ DEM_RF_FTDF_LOOP_GAIN_DS_REG_KP_LF_DS_Msk

#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KP_LF_DS_Msk   (0xffUL)

DEM RF_FTDF_LOOP_GAIN_DS_REG: KP_LF_DS (Bitfield-Mask: 0xff)

Definition at line 4992 of file DA14680BA.h.

◆ DEM_RF_FTDF_LOOP_GAIN_DS_REG_KP_LF_DS_Pos

#define DEM_RF_FTDF_LOOP_GAIN_DS_REG_KP_LF_DS_Pos   (0UL)

DEM RF_FTDF_LOOP_GAIN_DS_REG: KP_LF_DS (Bit 0)

Definition at line 4991 of file DA14680BA.h.

◆ DEM_RF_FTDF_LOOP_GAIN_PD_REG_KI_LF_PD_Msk

#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KI_LF_PD_Msk   (0xff00UL)

DEM RF_FTDF_LOOP_GAIN_PD_REG: KI_LF_PD (Bitfield-Mask: 0xff)

Definition at line 4988 of file DA14680BA.h.

◆ DEM_RF_FTDF_LOOP_GAIN_PD_REG_KI_LF_PD_Pos

#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KI_LF_PD_Pos   (8UL)

DEM RF_FTDF_LOOP_GAIN_PD_REG: KI_LF_PD (Bit 8)

Definition at line 4987 of file DA14680BA.h.

◆ DEM_RF_FTDF_LOOP_GAIN_PD_REG_KP_LF_PD_Msk

#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KP_LF_PD_Msk   (0xffUL)

DEM RF_FTDF_LOOP_GAIN_PD_REG: KP_LF_PD (Bitfield-Mask: 0xff)

Definition at line 4986 of file DA14680BA.h.

◆ DEM_RF_FTDF_LOOP_GAIN_PD_REG_KP_LF_PD_Pos

#define DEM_RF_FTDF_LOOP_GAIN_PD_REG_KP_LF_PD_Pos   (0UL)

DEM RF_FTDF_LOOP_GAIN_PD_REG: KP_LF_PD (Bit 0)

Definition at line 4985 of file DA14680BA.h.

◆ DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DELAY_Msk

#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DELAY_Msk   (0x6000UL)

DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DELAY (Bitfield-Mask: 0x03)

Definition at line 5068 of file DA14680BA.h.

◆ DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DELAY_Pos

#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DELAY_Pos   (13UL)

DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DELAY (Bit 13)

Definition at line 5067 of file DA14680BA.h.

◆ DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DIFF_Msk

#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DIFF_Msk   (0x100UL)

DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DIFF (Bitfield-Mask: 0x01)

Definition at line 5062 of file DA14680BA.h.

◆ DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DIFF_Pos

#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_DIFF_Pos   (8UL)

DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_DIFF (Bit 8)

Definition at line 5061 of file DA14680BA.h.

◆ DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_MODE_Msk

#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_MODE_Msk   (0x3UL)

DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_MODE (Bitfield-Mask: 0x03)

Definition at line 5058 of file DA14680BA.h.

◆ DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_MODE_Pos

#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_MODE_Pos   (0UL)

DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_MODE (Bit 0)

Definition at line 5057 of file DA14680BA.h.

◆ DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR1_Msk

#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR1_Msk   (0x1800UL)

DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR1 (Bitfield-Mask: 0x03)

Definition at line 5066 of file DA14680BA.h.

◆ DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR1_Pos

#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR1_Pos   (11UL)

DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR1 (Bit 11)

Definition at line 5065 of file DA14680BA.h.

◆ DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR2_Msk

#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR2_Msk   (0x600UL)

DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR2 (Bitfield-Mask: 0x03)

Definition at line 5064 of file DA14680BA.h.

◆ DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR2_Pos

#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_SFACTOR2_Pos   (9UL)

DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_SFACTOR2 (Bit 9)

Definition at line 5063 of file DA14680BA.h.

◆ DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_THRESHOLD_Msk

#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_THRESHOLD_Msk   (0xfcUL)

DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_THRESHOLD (Bitfield-Mask: 0x3f)

Definition at line 5060 of file DA14680BA.h.

◆ DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_THRESHOLD_Pos

#define DEM_RF_FTDF_SIGDET_CTRL_REG_SIGDET_THRESHOLD_Pos   (2UL)

DEM RF_FTDF_SIGDET_CTRL_REG: SIGDET_THRESHOLD (Bit 2)

Definition at line 5059 of file DA14680BA.h.

◆ DEM_RF_PAD_CNT_CTRL_REG_PAD_CLEAR_COUNT_Msk

#define DEM_RF_PAD_CNT_CTRL_REG_PAD_CLEAR_COUNT_Msk   (0x4000UL)

DEM RF_PAD_CNT_CTRL_REG: PAD_CLEAR_COUNT (Bitfield-Mask: 0x01)

Definition at line 5030 of file DA14680BA.h.

◆ DEM_RF_PAD_CNT_CTRL_REG_PAD_CLEAR_COUNT_Pos

#define DEM_RF_PAD_CNT_CTRL_REG_PAD_CLEAR_COUNT_Pos   (14UL)

DEM RF_PAD_CNT_CTRL_REG: PAD_CLEAR_COUNT (Bit 14)

Definition at line 5029 of file DA14680BA.h.

◆ DEM_RF_PAD_CNT_CTRL_REG_PAD_NEG_LIMIT_Msk

#define DEM_RF_PAD_CNT_CTRL_REG_PAD_NEG_LIMIT_Msk   (0x3f80UL)

DEM RF_PAD_CNT_CTRL_REG: PAD_NEG_LIMIT (Bitfield-Mask: 0x7f)

Definition at line 5028 of file DA14680BA.h.

◆ DEM_RF_PAD_CNT_CTRL_REG_PAD_NEG_LIMIT_Pos

#define DEM_RF_PAD_CNT_CTRL_REG_PAD_NEG_LIMIT_Pos   (7UL)

DEM RF_PAD_CNT_CTRL_REG: PAD_NEG_LIMIT (Bit 7)

Definition at line 5027 of file DA14680BA.h.

◆ DEM_RF_PAD_CNT_CTRL_REG_PAD_POS_LIMIT_Msk

#define DEM_RF_PAD_CNT_CTRL_REG_PAD_POS_LIMIT_Msk   (0x7fUL)

DEM RF_PAD_CNT_CTRL_REG: PAD_POS_LIMIT (Bitfield-Mask: 0x7f)

Definition at line 5026 of file DA14680BA.h.

◆ DEM_RF_PAD_CNT_CTRL_REG_PAD_POS_LIMIT_Pos

#define DEM_RF_PAD_CNT_CTRL_REG_PAD_POS_LIMIT_Pos   (0UL)

DEM RF_PAD_CNT_CTRL_REG: PAD_POS_LIMIT (Bit 0)

Definition at line 5025 of file DA14680BA.h.

◆ DEM_RF_PAD_CNT_RESULT_REG_PAD_NEG_CNT_RD_Msk

#define DEM_RF_PAD_CNT_RESULT_REG_PAD_NEG_CNT_RD_Msk   (0xff00UL)

DEM RF_PAD_CNT_RESULT_REG: PAD_NEG_CNT_RD (Bitfield-Mask: 0xff)

Definition at line 5036 of file DA14680BA.h.

◆ DEM_RF_PAD_CNT_RESULT_REG_PAD_NEG_CNT_RD_Pos

#define DEM_RF_PAD_CNT_RESULT_REG_PAD_NEG_CNT_RD_Pos   (8UL)

DEM RF_PAD_CNT_RESULT_REG: PAD_NEG_CNT_RD (Bit 8)

Definition at line 5035 of file DA14680BA.h.

◆ DEM_RF_PAD_CNT_RESULT_REG_PAD_POS_CNT_RD_Msk

#define DEM_RF_PAD_CNT_RESULT_REG_PAD_POS_CNT_RD_Msk   (0xffUL)

DEM RF_PAD_CNT_RESULT_REG: PAD_POS_CNT_RD (Bitfield-Mask: 0xff)

Definition at line 5034 of file DA14680BA.h.

◆ DEM_RF_PAD_CNT_RESULT_REG_PAD_POS_CNT_RD_Pos

#define DEM_RF_PAD_CNT_RESULT_REG_PAD_POS_CNT_RD_Pos   (0UL)

DEM RF_PAD_CNT_RESULT_REG: PAD_POS_CNT_RD (Bit 0)

Definition at line 5033 of file DA14680BA.h.

◆ DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP00_Msk

#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP00_Msk   (0xf000UL)

DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP00 (Bitfield-Mask: 0x0f)

Definition at line 4924 of file DA14680BA.h.

◆ DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP00_Pos

#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP00_Pos   (12UL)

DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP00 (Bit 12)

Definition at line 4923 of file DA14680BA.h.

◆ DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP01_Msk

#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP01_Msk   (0xfUL)

DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP01 (Bitfield-Mask: 0x0f)

Definition at line 4918 of file DA14680BA.h.

◆ DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP01_Pos

#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP01_Pos   (0UL)

DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP01 (Bit 0)

Definition at line 4917 of file DA14680BA.h.

◆ DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP10_Msk

#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP10_Msk   (0xf0UL)

DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP10 (Bitfield-Mask: 0x0f)

Definition at line 4920 of file DA14680BA.h.

◆ DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP10_Pos

#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP10_Pos   (4UL)

DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP10 (Bit 4)

Definition at line 4919 of file DA14680BA.h.

◆ DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP11_Msk

#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP11_Msk   (0xf00UL)

DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP11 (Bitfield-Mask: 0x0f)

Definition at line 4922 of file DA14680BA.h.

◆ DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP11_Pos

#define DEM_RF_RSSI_COMP_CTRL_REG_RSSI_COMP11_Pos   (8UL)

DEM RF_RSSI_COMP_CTRL_REG: RSSI_COMP11 (Bit 8)

Definition at line 4921 of file DA14680BA.h.

◆ DEM_RF_RSSI_RESULT_REG_RSSI_AVG_RD_Msk

#define DEM_RF_RSSI_RESULT_REG_RSSI_AVG_RD_Msk   (0xffc0UL)

DEM RF_RSSI_RESULT_REG: RSSI_AVG_RD (Bitfield-Mask: 0x3ff)

Definition at line 4908 of file DA14680BA.h.

◆ DEM_RF_RSSI_RESULT_REG_RSSI_AVG_RD_Pos

#define DEM_RF_RSSI_RESULT_REG_RSSI_AVG_RD_Pos   (6UL)

DEM RF_RSSI_RESULT_REG: RSSI_AVG_RD (Bit 6)

Definition at line 4907 of file DA14680BA.h.

◆ DEM_RF_RSSI_RESULT_REG_RSSI_PH_RD_Msk

#define DEM_RF_RSSI_RESULT_REG_RSSI_PH_RD_Msk   (0x3fUL)

DEM RF_RSSI_RESULT_REG: RSSI_PH_RD (Bitfield-Mask: 0x3f)

Definition at line 4906 of file DA14680BA.h.

◆ DEM_RF_RSSI_RESULT_REG_RSSI_PH_RD_Pos

#define DEM_RF_RSSI_RESULT_REG_RSSI_PH_RD_Pos   (0UL)

DEM RF_RSSI_RESULT_REG: RSSI_PH_RD (Bit 0)

Definition at line 4905 of file DA14680BA.h.

◆ DMA

#define DMA   ((DMA_Type *) DMA_BASE)

Definition at line 12084 of file DA14680BA.h.

◆ DMA_BASE

#define DMA_BASE   0x50003500UL

Definition at line 12039 of file DA14680BA.h.

◆ DMA_DMA0_A_STARTH_REG_DMA0_A_STARTH_Msk

#define DMA_DMA0_A_STARTH_REG_DMA0_A_STARTH_Msk   (0xffffUL)

DMA DMA0_A_STARTH_REG: DMA0_A_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5082 of file DA14680BA.h.

◆ DMA_DMA0_A_STARTH_REG_DMA0_A_STARTH_Pos

#define DMA_DMA0_A_STARTH_REG_DMA0_A_STARTH_Pos   (0UL)

DMA DMA0_A_STARTH_REG: DMA0_A_STARTH (Bit 0)

Definition at line 5081 of file DA14680BA.h.

◆ DMA_DMA0_A_STARTL_REG_DMA0_A_STARTL_Msk

#define DMA_DMA0_A_STARTL_REG_DMA0_A_STARTL_Msk   (0xffffUL)

DMA DMA0_A_STARTL_REG: DMA0_A_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5078 of file DA14680BA.h.

◆ DMA_DMA0_A_STARTL_REG_DMA0_A_STARTL_Pos

#define DMA_DMA0_A_STARTL_REG_DMA0_A_STARTL_Pos   (0UL)

DMA DMA0_A_STARTL_REG: DMA0_A_STARTL (Bit 0)

Definition at line 5077 of file DA14680BA.h.

◆ DMA_DMA0_B_STARTH_REG_DMA0_B_STARTH_Msk

#define DMA_DMA0_B_STARTH_REG_DMA0_B_STARTH_Msk   (0xffffUL)

DMA DMA0_B_STARTH_REG: DMA0_B_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5090 of file DA14680BA.h.

◆ DMA_DMA0_B_STARTH_REG_DMA0_B_STARTH_Pos

#define DMA_DMA0_B_STARTH_REG_DMA0_B_STARTH_Pos   (0UL)

DMA DMA0_B_STARTH_REG: DMA0_B_STARTH (Bit 0)

Definition at line 5089 of file DA14680BA.h.

◆ DMA_DMA0_B_STARTL_REG_DMA0_B_STARTL_Msk

#define DMA_DMA0_B_STARTL_REG_DMA0_B_STARTL_Msk   (0xffffUL)

DMA DMA0_B_STARTL_REG: DMA0_B_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5086 of file DA14680BA.h.

◆ DMA_DMA0_B_STARTL_REG_DMA0_B_STARTL_Pos

#define DMA_DMA0_B_STARTL_REG_DMA0_B_STARTL_Pos   (0UL)

DMA DMA0_B_STARTL_REG: DMA0_B_STARTL (Bit 0)

Definition at line 5085 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_AINC_Msk

#define DMA_DMA0_CTRL_REG_AINC_Msk   (0x40UL)

DMA DMA0_CTRL_REG: AINC (Bitfield-Mask: 0x01)

Definition at line 5112 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_AINC_Pos

#define DMA_DMA0_CTRL_REG_AINC_Pos   (6UL)

DMA DMA0_CTRL_REG: AINC (Bit 6)

Definition at line 5111 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_BINC_Msk

#define DMA_DMA0_CTRL_REG_BINC_Msk   (0x20UL)

DMA DMA0_CTRL_REG: BINC (Bitfield-Mask: 0x01)

Definition at line 5110 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_BINC_Pos

#define DMA_DMA0_CTRL_REG_BINC_Pos   (5UL)

DMA DMA0_CTRL_REG: BINC (Bit 5)

Definition at line 5109 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_BW_Msk

#define DMA_DMA0_CTRL_REG_BW_Msk   (0x6UL)

DMA DMA0_CTRL_REG: BW (Bitfield-Mask: 0x03)

Definition at line 5104 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_BW_Pos

#define DMA_DMA0_CTRL_REG_BW_Pos   (1UL)

DMA DMA0_CTRL_REG: BW (Bit 1)

Definition at line 5103 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA0_CTRL_REG_CIRCULAR_Msk   (0x80UL)

DMA DMA0_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)

Definition at line 5114 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA0_CTRL_REG_CIRCULAR_Pos   (7UL)

DMA DMA0_CTRL_REG: CIRCULAR (Bit 7)

Definition at line 5113 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA0_CTRL_REG_DMA_IDLE_Msk   (0x800UL)

DMA DMA0_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)

Definition at line 5118 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA0_CTRL_REG_DMA_IDLE_Pos   (11UL)

DMA DMA0_CTRL_REG: DMA_IDLE (Bit 11)

Definition at line 5117 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA0_CTRL_REG_DMA_INIT_Msk   (0x1000UL)

DMA DMA0_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)

Definition at line 5120 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA0_CTRL_REG_DMA_INIT_Pos   (12UL)

DMA DMA0_CTRL_REG: DMA_INIT (Bit 12)

Definition at line 5119 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_DMA_ON_Msk

#define DMA_DMA0_CTRL_REG_DMA_ON_Msk   (0x1UL)

DMA DMA0_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)

Definition at line 5102 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_DMA_ON_Pos

#define DMA_DMA0_CTRL_REG_DMA_ON_Pos   (0UL)

DMA DMA0_CTRL_REG: DMA_ON (Bit 0)

Definition at line 5101 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA0_CTRL_REG_DMA_PRIO_Msk   (0x700UL)

DMA DMA0_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)

Definition at line 5116 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA0_CTRL_REG_DMA_PRIO_Pos   (8UL)

DMA DMA0_CTRL_REG: DMA_PRIO (Bit 8)

Definition at line 5115 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA0_CTRL_REG_DREQ_MODE_Msk   (0x10UL)

DMA DMA0_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)

Definition at line 5108 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA0_CTRL_REG_DREQ_MODE_Pos   (4UL)

DMA DMA0_CTRL_REG: DREQ_MODE (Bit 4)

Definition at line 5107 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_IRQ_ENABLE_Msk

#define DMA_DMA0_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)

DMA DMA0_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)

Definition at line 5106 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_IRQ_ENABLE_Pos

#define DMA_DMA0_CTRL_REG_IRQ_ENABLE_Pos   (3UL)

DMA DMA0_CTRL_REG: IRQ_ENABLE (Bit 3)

Definition at line 5105 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA0_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)

DMA DMA0_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)

Definition at line 5122 of file DA14680BA.h.

◆ DMA_DMA0_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA0_CTRL_REG_REQ_SENSE_Pos   (13UL)

DMA DMA0_CTRL_REG: REQ_SENSE (Bit 13)

Definition at line 5121 of file DA14680BA.h.

◆ DMA_DMA0_IDX_REG_DMA0_IDX_Msk

#define DMA_DMA0_IDX_REG_DMA0_IDX_Msk   (0xffffUL)

DMA DMA0_IDX_REG: DMA0_IDX (Bitfield-Mask: 0xffff)

Definition at line 5126 of file DA14680BA.h.

◆ DMA_DMA0_IDX_REG_DMA0_IDX_Pos

#define DMA_DMA0_IDX_REG_DMA0_IDX_Pos   (0UL)

DMA DMA0_IDX_REG: DMA0_IDX (Bit 0)

Definition at line 5125 of file DA14680BA.h.

◆ DMA_DMA0_INT_REG_DMA0_INT_Msk

#define DMA_DMA0_INT_REG_DMA0_INT_Msk   (0xffffUL)

DMA DMA0_INT_REG: DMA0_INT (Bitfield-Mask: 0xffff)

Definition at line 5094 of file DA14680BA.h.

◆ DMA_DMA0_INT_REG_DMA0_INT_Pos

#define DMA_DMA0_INT_REG_DMA0_INT_Pos   (0UL)

DMA DMA0_INT_REG: DMA0_INT (Bit 0)

Definition at line 5093 of file DA14680BA.h.

◆ DMA_DMA0_LEN_REG_DMA0_LEN_Msk

#define DMA_DMA0_LEN_REG_DMA0_LEN_Msk   (0xffffUL)

DMA DMA0_LEN_REG: DMA0_LEN (Bitfield-Mask: 0xffff)

Definition at line 5098 of file DA14680BA.h.

◆ DMA_DMA0_LEN_REG_DMA0_LEN_Pos

#define DMA_DMA0_LEN_REG_DMA0_LEN_Pos   (0UL)

DMA DMA0_LEN_REG: DMA0_LEN (Bit 0)

Definition at line 5097 of file DA14680BA.h.

◆ DMA_DMA1_A_STARTH_REG_DMA1_A_STARTH_Msk

#define DMA_DMA1_A_STARTH_REG_DMA1_A_STARTH_Msk   (0xffffUL)

DMA DMA1_A_STARTH_REG: DMA1_A_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5134 of file DA14680BA.h.

◆ DMA_DMA1_A_STARTH_REG_DMA1_A_STARTH_Pos

#define DMA_DMA1_A_STARTH_REG_DMA1_A_STARTH_Pos   (0UL)

DMA DMA1_A_STARTH_REG: DMA1_A_STARTH (Bit 0)

Definition at line 5133 of file DA14680BA.h.

◆ DMA_DMA1_A_STARTL_REG_DMA1_A_STARTL_Msk

#define DMA_DMA1_A_STARTL_REG_DMA1_A_STARTL_Msk   (0xffffUL)

DMA DMA1_A_STARTL_REG: DMA1_A_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5130 of file DA14680BA.h.

◆ DMA_DMA1_A_STARTL_REG_DMA1_A_STARTL_Pos

#define DMA_DMA1_A_STARTL_REG_DMA1_A_STARTL_Pos   (0UL)

DMA DMA1_A_STARTL_REG: DMA1_A_STARTL (Bit 0)

Definition at line 5129 of file DA14680BA.h.

◆ DMA_DMA1_B_STARTH_REG_DMA1_B_STARTH_Msk

#define DMA_DMA1_B_STARTH_REG_DMA1_B_STARTH_Msk   (0xffffUL)

DMA DMA1_B_STARTH_REG: DMA1_B_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5142 of file DA14680BA.h.

◆ DMA_DMA1_B_STARTH_REG_DMA1_B_STARTH_Pos

#define DMA_DMA1_B_STARTH_REG_DMA1_B_STARTH_Pos   (0UL)

DMA DMA1_B_STARTH_REG: DMA1_B_STARTH (Bit 0)

Definition at line 5141 of file DA14680BA.h.

◆ DMA_DMA1_B_STARTL_REG_DMA1_B_STARTL_Msk

#define DMA_DMA1_B_STARTL_REG_DMA1_B_STARTL_Msk   (0xffffUL)

DMA DMA1_B_STARTL_REG: DMA1_B_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5138 of file DA14680BA.h.

◆ DMA_DMA1_B_STARTL_REG_DMA1_B_STARTL_Pos

#define DMA_DMA1_B_STARTL_REG_DMA1_B_STARTL_Pos   (0UL)

DMA DMA1_B_STARTL_REG: DMA1_B_STARTL (Bit 0)

Definition at line 5137 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_AINC_Msk

#define DMA_DMA1_CTRL_REG_AINC_Msk   (0x40UL)

DMA DMA1_CTRL_REG: AINC (Bitfield-Mask: 0x01)

Definition at line 5164 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_AINC_Pos

#define DMA_DMA1_CTRL_REG_AINC_Pos   (6UL)

DMA DMA1_CTRL_REG: AINC (Bit 6)

Definition at line 5163 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_BINC_Msk

#define DMA_DMA1_CTRL_REG_BINC_Msk   (0x20UL)

DMA DMA1_CTRL_REG: BINC (Bitfield-Mask: 0x01)

Definition at line 5162 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_BINC_Pos

#define DMA_DMA1_CTRL_REG_BINC_Pos   (5UL)

DMA DMA1_CTRL_REG: BINC (Bit 5)

Definition at line 5161 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_BW_Msk

#define DMA_DMA1_CTRL_REG_BW_Msk   (0x6UL)

DMA DMA1_CTRL_REG: BW (Bitfield-Mask: 0x03)

Definition at line 5156 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_BW_Pos

#define DMA_DMA1_CTRL_REG_BW_Pos   (1UL)

DMA DMA1_CTRL_REG: BW (Bit 1)

Definition at line 5155 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA1_CTRL_REG_CIRCULAR_Msk   (0x80UL)

DMA DMA1_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)

Definition at line 5166 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA1_CTRL_REG_CIRCULAR_Pos   (7UL)

DMA DMA1_CTRL_REG: CIRCULAR (Bit 7)

Definition at line 5165 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA1_CTRL_REG_DMA_IDLE_Msk   (0x800UL)

DMA DMA1_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)

Definition at line 5170 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA1_CTRL_REG_DMA_IDLE_Pos   (11UL)

DMA DMA1_CTRL_REG: DMA_IDLE (Bit 11)

Definition at line 5169 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA1_CTRL_REG_DMA_INIT_Msk   (0x1000UL)

DMA DMA1_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)

Definition at line 5172 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA1_CTRL_REG_DMA_INIT_Pos   (12UL)

DMA DMA1_CTRL_REG: DMA_INIT (Bit 12)

Definition at line 5171 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_DMA_ON_Msk

#define DMA_DMA1_CTRL_REG_DMA_ON_Msk   (0x1UL)

DMA DMA1_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)

Definition at line 5154 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_DMA_ON_Pos

#define DMA_DMA1_CTRL_REG_DMA_ON_Pos   (0UL)

DMA DMA1_CTRL_REG: DMA_ON (Bit 0)

Definition at line 5153 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA1_CTRL_REG_DMA_PRIO_Msk   (0x700UL)

DMA DMA1_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)

Definition at line 5168 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA1_CTRL_REG_DMA_PRIO_Pos   (8UL)

DMA DMA1_CTRL_REG: DMA_PRIO (Bit 8)

Definition at line 5167 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA1_CTRL_REG_DREQ_MODE_Msk   (0x10UL)

DMA DMA1_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)

Definition at line 5160 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA1_CTRL_REG_DREQ_MODE_Pos   (4UL)

DMA DMA1_CTRL_REG: DREQ_MODE (Bit 4)

Definition at line 5159 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_IRQ_ENABLE_Msk

#define DMA_DMA1_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)

DMA DMA1_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)

Definition at line 5158 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_IRQ_ENABLE_Pos

#define DMA_DMA1_CTRL_REG_IRQ_ENABLE_Pos   (3UL)

DMA DMA1_CTRL_REG: IRQ_ENABLE (Bit 3)

Definition at line 5157 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA1_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)

DMA DMA1_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)

Definition at line 5174 of file DA14680BA.h.

◆ DMA_DMA1_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA1_CTRL_REG_REQ_SENSE_Pos   (13UL)

DMA DMA1_CTRL_REG: REQ_SENSE (Bit 13)

Definition at line 5173 of file DA14680BA.h.

◆ DMA_DMA1_IDX_REG_DMA1_IDX_Msk

#define DMA_DMA1_IDX_REG_DMA1_IDX_Msk   (0xffffUL)

DMA DMA1_IDX_REG: DMA1_IDX (Bitfield-Mask: 0xffff)

Definition at line 5178 of file DA14680BA.h.

◆ DMA_DMA1_IDX_REG_DMA1_IDX_Pos

#define DMA_DMA1_IDX_REG_DMA1_IDX_Pos   (0UL)

DMA DMA1_IDX_REG: DMA1_IDX (Bit 0)

Definition at line 5177 of file DA14680BA.h.

◆ DMA_DMA1_INT_REG_DMA1_INT_Msk

#define DMA_DMA1_INT_REG_DMA1_INT_Msk   (0xffffUL)

DMA DMA1_INT_REG: DMA1_INT (Bitfield-Mask: 0xffff)

Definition at line 5146 of file DA14680BA.h.

◆ DMA_DMA1_INT_REG_DMA1_INT_Pos

#define DMA_DMA1_INT_REG_DMA1_INT_Pos   (0UL)

DMA DMA1_INT_REG: DMA1_INT (Bit 0)

Definition at line 5145 of file DA14680BA.h.

◆ DMA_DMA1_LEN_REG_DMA1_LEN_Msk

#define DMA_DMA1_LEN_REG_DMA1_LEN_Msk   (0xffffUL)

DMA DMA1_LEN_REG: DMA1_LEN (Bitfield-Mask: 0xffff)

Definition at line 5150 of file DA14680BA.h.

◆ DMA_DMA1_LEN_REG_DMA1_LEN_Pos

#define DMA_DMA1_LEN_REG_DMA1_LEN_Pos   (0UL)

DMA DMA1_LEN_REG: DMA1_LEN (Bit 0)

Definition at line 5149 of file DA14680BA.h.

◆ DMA_DMA2_A_STARTH_REG_DMA2_A_STARTH_Msk

#define DMA_DMA2_A_STARTH_REG_DMA2_A_STARTH_Msk   (0xffffUL)

DMA DMA2_A_STARTH_REG: DMA2_A_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5186 of file DA14680BA.h.

◆ DMA_DMA2_A_STARTH_REG_DMA2_A_STARTH_Pos

#define DMA_DMA2_A_STARTH_REG_DMA2_A_STARTH_Pos   (0UL)

DMA DMA2_A_STARTH_REG: DMA2_A_STARTH (Bit 0)

Definition at line 5185 of file DA14680BA.h.

◆ DMA_DMA2_A_STARTL_REG_DMA2_A_STARTL_Msk

#define DMA_DMA2_A_STARTL_REG_DMA2_A_STARTL_Msk   (0xffffUL)

DMA DMA2_A_STARTL_REG: DMA2_A_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5182 of file DA14680BA.h.

◆ DMA_DMA2_A_STARTL_REG_DMA2_A_STARTL_Pos

#define DMA_DMA2_A_STARTL_REG_DMA2_A_STARTL_Pos   (0UL)

DMA DMA2_A_STARTL_REG: DMA2_A_STARTL (Bit 0)

Definition at line 5181 of file DA14680BA.h.

◆ DMA_DMA2_B_STARTH_REG_DMA2_B_STARTH_Msk

#define DMA_DMA2_B_STARTH_REG_DMA2_B_STARTH_Msk   (0xffffUL)

DMA DMA2_B_STARTH_REG: DMA2_B_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5194 of file DA14680BA.h.

◆ DMA_DMA2_B_STARTH_REG_DMA2_B_STARTH_Pos

#define DMA_DMA2_B_STARTH_REG_DMA2_B_STARTH_Pos   (0UL)

DMA DMA2_B_STARTH_REG: DMA2_B_STARTH (Bit 0)

Definition at line 5193 of file DA14680BA.h.

◆ DMA_DMA2_B_STARTL_REG_DMA2_B_STARTL_Msk

#define DMA_DMA2_B_STARTL_REG_DMA2_B_STARTL_Msk   (0xffffUL)

DMA DMA2_B_STARTL_REG: DMA2_B_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5190 of file DA14680BA.h.

◆ DMA_DMA2_B_STARTL_REG_DMA2_B_STARTL_Pos

#define DMA_DMA2_B_STARTL_REG_DMA2_B_STARTL_Pos   (0UL)

DMA DMA2_B_STARTL_REG: DMA2_B_STARTL (Bit 0)

Definition at line 5189 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_AINC_Msk

#define DMA_DMA2_CTRL_REG_AINC_Msk   (0x40UL)

DMA DMA2_CTRL_REG: AINC (Bitfield-Mask: 0x01)

Definition at line 5216 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_AINC_Pos

#define DMA_DMA2_CTRL_REG_AINC_Pos   (6UL)

DMA DMA2_CTRL_REG: AINC (Bit 6)

Definition at line 5215 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_BINC_Msk

#define DMA_DMA2_CTRL_REG_BINC_Msk   (0x20UL)

DMA DMA2_CTRL_REG: BINC (Bitfield-Mask: 0x01)

Definition at line 5214 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_BINC_Pos

#define DMA_DMA2_CTRL_REG_BINC_Pos   (5UL)

DMA DMA2_CTRL_REG: BINC (Bit 5)

Definition at line 5213 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_BW_Msk

#define DMA_DMA2_CTRL_REG_BW_Msk   (0x6UL)

DMA DMA2_CTRL_REG: BW (Bitfield-Mask: 0x03)

Definition at line 5208 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_BW_Pos

#define DMA_DMA2_CTRL_REG_BW_Pos   (1UL)

DMA DMA2_CTRL_REG: BW (Bit 1)

Definition at line 5207 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA2_CTRL_REG_CIRCULAR_Msk   (0x80UL)

DMA DMA2_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)

Definition at line 5218 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA2_CTRL_REG_CIRCULAR_Pos   (7UL)

DMA DMA2_CTRL_REG: CIRCULAR (Bit 7)

Definition at line 5217 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA2_CTRL_REG_DMA_IDLE_Msk   (0x800UL)

DMA DMA2_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)

Definition at line 5222 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA2_CTRL_REG_DMA_IDLE_Pos   (11UL)

DMA DMA2_CTRL_REG: DMA_IDLE (Bit 11)

Definition at line 5221 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA2_CTRL_REG_DMA_INIT_Msk   (0x1000UL)

DMA DMA2_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)

Definition at line 5224 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA2_CTRL_REG_DMA_INIT_Pos   (12UL)

DMA DMA2_CTRL_REG: DMA_INIT (Bit 12)

Definition at line 5223 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_DMA_ON_Msk

#define DMA_DMA2_CTRL_REG_DMA_ON_Msk   (0x1UL)

DMA DMA2_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)

Definition at line 5206 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_DMA_ON_Pos

#define DMA_DMA2_CTRL_REG_DMA_ON_Pos   (0UL)

DMA DMA2_CTRL_REG: DMA_ON (Bit 0)

Definition at line 5205 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA2_CTRL_REG_DMA_PRIO_Msk   (0x700UL)

DMA DMA2_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)

Definition at line 5220 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA2_CTRL_REG_DMA_PRIO_Pos   (8UL)

DMA DMA2_CTRL_REG: DMA_PRIO (Bit 8)

Definition at line 5219 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA2_CTRL_REG_DREQ_MODE_Msk   (0x10UL)

DMA DMA2_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)

Definition at line 5212 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA2_CTRL_REG_DREQ_MODE_Pos   (4UL)

DMA DMA2_CTRL_REG: DREQ_MODE (Bit 4)

Definition at line 5211 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_IRQ_ENABLE_Msk

#define DMA_DMA2_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)

DMA DMA2_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)

Definition at line 5210 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_IRQ_ENABLE_Pos

#define DMA_DMA2_CTRL_REG_IRQ_ENABLE_Pos   (3UL)

DMA DMA2_CTRL_REG: IRQ_ENABLE (Bit 3)

Definition at line 5209 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA2_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)

DMA DMA2_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)

Definition at line 5226 of file DA14680BA.h.

◆ DMA_DMA2_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA2_CTRL_REG_REQ_SENSE_Pos   (13UL)

DMA DMA2_CTRL_REG: REQ_SENSE (Bit 13)

Definition at line 5225 of file DA14680BA.h.

◆ DMA_DMA2_IDX_REG_DMA2_IDX_Msk

#define DMA_DMA2_IDX_REG_DMA2_IDX_Msk   (0xffffUL)

DMA DMA2_IDX_REG: DMA2_IDX (Bitfield-Mask: 0xffff)

Definition at line 5230 of file DA14680BA.h.

◆ DMA_DMA2_IDX_REG_DMA2_IDX_Pos

#define DMA_DMA2_IDX_REG_DMA2_IDX_Pos   (0UL)

DMA DMA2_IDX_REG: DMA2_IDX (Bit 0)

Definition at line 5229 of file DA14680BA.h.

◆ DMA_DMA2_INT_REG_DMA2_INT_Msk

#define DMA_DMA2_INT_REG_DMA2_INT_Msk   (0xffffUL)

DMA DMA2_INT_REG: DMA2_INT (Bitfield-Mask: 0xffff)

Definition at line 5198 of file DA14680BA.h.

◆ DMA_DMA2_INT_REG_DMA2_INT_Pos

#define DMA_DMA2_INT_REG_DMA2_INT_Pos   (0UL)

DMA DMA2_INT_REG: DMA2_INT (Bit 0)

Definition at line 5197 of file DA14680BA.h.

◆ DMA_DMA2_LEN_REG_DMA2_LEN_Msk

#define DMA_DMA2_LEN_REG_DMA2_LEN_Msk   (0xffffUL)

DMA DMA2_LEN_REG: DMA2_LEN (Bitfield-Mask: 0xffff)

Definition at line 5202 of file DA14680BA.h.

◆ DMA_DMA2_LEN_REG_DMA2_LEN_Pos

#define DMA_DMA2_LEN_REG_DMA2_LEN_Pos   (0UL)

DMA DMA2_LEN_REG: DMA2_LEN (Bit 0)

Definition at line 5201 of file DA14680BA.h.

◆ DMA_DMA3_A_STARTH_REG_DMA3_A_STARTH_Msk

#define DMA_DMA3_A_STARTH_REG_DMA3_A_STARTH_Msk   (0xffffUL)

DMA DMA3_A_STARTH_REG: DMA3_A_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5238 of file DA14680BA.h.

◆ DMA_DMA3_A_STARTH_REG_DMA3_A_STARTH_Pos

#define DMA_DMA3_A_STARTH_REG_DMA3_A_STARTH_Pos   (0UL)

DMA DMA3_A_STARTH_REG: DMA3_A_STARTH (Bit 0)

Definition at line 5237 of file DA14680BA.h.

◆ DMA_DMA3_A_STARTL_REG_DMA3_A_STARTL_Msk

#define DMA_DMA3_A_STARTL_REG_DMA3_A_STARTL_Msk   (0xffffUL)

DMA DMA3_A_STARTL_REG: DMA3_A_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5234 of file DA14680BA.h.

◆ DMA_DMA3_A_STARTL_REG_DMA3_A_STARTL_Pos

#define DMA_DMA3_A_STARTL_REG_DMA3_A_STARTL_Pos   (0UL)

DMA DMA3_A_STARTL_REG: DMA3_A_STARTL (Bit 0)

Definition at line 5233 of file DA14680BA.h.

◆ DMA_DMA3_B_STARTH_REG_DMA3_B_STARTH_Msk

#define DMA_DMA3_B_STARTH_REG_DMA3_B_STARTH_Msk   (0xffffUL)

DMA DMA3_B_STARTH_REG: DMA3_B_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5246 of file DA14680BA.h.

◆ DMA_DMA3_B_STARTH_REG_DMA3_B_STARTH_Pos

#define DMA_DMA3_B_STARTH_REG_DMA3_B_STARTH_Pos   (0UL)

DMA DMA3_B_STARTH_REG: DMA3_B_STARTH (Bit 0)

Definition at line 5245 of file DA14680BA.h.

◆ DMA_DMA3_B_STARTL_REG_DMA3_B_STARTL_Msk

#define DMA_DMA3_B_STARTL_REG_DMA3_B_STARTL_Msk   (0xffffUL)

DMA DMA3_B_STARTL_REG: DMA3_B_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5242 of file DA14680BA.h.

◆ DMA_DMA3_B_STARTL_REG_DMA3_B_STARTL_Pos

#define DMA_DMA3_B_STARTL_REG_DMA3_B_STARTL_Pos   (0UL)

DMA DMA3_B_STARTL_REG: DMA3_B_STARTL (Bit 0)

Definition at line 5241 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_AINC_Msk

#define DMA_DMA3_CTRL_REG_AINC_Msk   (0x40UL)

DMA DMA3_CTRL_REG: AINC (Bitfield-Mask: 0x01)

Definition at line 5268 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_AINC_Pos

#define DMA_DMA3_CTRL_REG_AINC_Pos   (6UL)

DMA DMA3_CTRL_REG: AINC (Bit 6)

Definition at line 5267 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_BINC_Msk

#define DMA_DMA3_CTRL_REG_BINC_Msk   (0x20UL)

DMA DMA3_CTRL_REG: BINC (Bitfield-Mask: 0x01)

Definition at line 5266 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_BINC_Pos

#define DMA_DMA3_CTRL_REG_BINC_Pos   (5UL)

DMA DMA3_CTRL_REG: BINC (Bit 5)

Definition at line 5265 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_BW_Msk

#define DMA_DMA3_CTRL_REG_BW_Msk   (0x6UL)

DMA DMA3_CTRL_REG: BW (Bitfield-Mask: 0x03)

Definition at line 5260 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_BW_Pos

#define DMA_DMA3_CTRL_REG_BW_Pos   (1UL)

DMA DMA3_CTRL_REG: BW (Bit 1)

Definition at line 5259 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA3_CTRL_REG_CIRCULAR_Msk   (0x80UL)

DMA DMA3_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)

Definition at line 5270 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA3_CTRL_REG_CIRCULAR_Pos   (7UL)

DMA DMA3_CTRL_REG: CIRCULAR (Bit 7)

Definition at line 5269 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA3_CTRL_REG_DMA_IDLE_Msk   (0x800UL)

DMA DMA3_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)

Definition at line 5274 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA3_CTRL_REG_DMA_IDLE_Pos   (11UL)

DMA DMA3_CTRL_REG: DMA_IDLE (Bit 11)

Definition at line 5273 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA3_CTRL_REG_DMA_INIT_Msk   (0x1000UL)

DMA DMA3_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)

Definition at line 5276 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA3_CTRL_REG_DMA_INIT_Pos   (12UL)

DMA DMA3_CTRL_REG: DMA_INIT (Bit 12)

Definition at line 5275 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_DMA_ON_Msk

#define DMA_DMA3_CTRL_REG_DMA_ON_Msk   (0x1UL)

DMA DMA3_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)

Definition at line 5258 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_DMA_ON_Pos

#define DMA_DMA3_CTRL_REG_DMA_ON_Pos   (0UL)

DMA DMA3_CTRL_REG: DMA_ON (Bit 0)

Definition at line 5257 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA3_CTRL_REG_DMA_PRIO_Msk   (0x700UL)

DMA DMA3_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)

Definition at line 5272 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA3_CTRL_REG_DMA_PRIO_Pos   (8UL)

DMA DMA3_CTRL_REG: DMA_PRIO (Bit 8)

Definition at line 5271 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA3_CTRL_REG_DREQ_MODE_Msk   (0x10UL)

DMA DMA3_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)

Definition at line 5264 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA3_CTRL_REG_DREQ_MODE_Pos   (4UL)

DMA DMA3_CTRL_REG: DREQ_MODE (Bit 4)

Definition at line 5263 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_IRQ_ENABLE_Msk

#define DMA_DMA3_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)

DMA DMA3_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)

Definition at line 5262 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_IRQ_ENABLE_Pos

#define DMA_DMA3_CTRL_REG_IRQ_ENABLE_Pos   (3UL)

DMA DMA3_CTRL_REG: IRQ_ENABLE (Bit 3)

Definition at line 5261 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA3_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)

DMA DMA3_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)

Definition at line 5278 of file DA14680BA.h.

◆ DMA_DMA3_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA3_CTRL_REG_REQ_SENSE_Pos   (13UL)

DMA DMA3_CTRL_REG: REQ_SENSE (Bit 13)

Definition at line 5277 of file DA14680BA.h.

◆ DMA_DMA3_IDX_REG_DMA3_IDX_Msk

#define DMA_DMA3_IDX_REG_DMA3_IDX_Msk   (0xffffUL)

DMA DMA3_IDX_REG: DMA3_IDX (Bitfield-Mask: 0xffff)

Definition at line 5282 of file DA14680BA.h.

◆ DMA_DMA3_IDX_REG_DMA3_IDX_Pos

#define DMA_DMA3_IDX_REG_DMA3_IDX_Pos   (0UL)

DMA DMA3_IDX_REG: DMA3_IDX (Bit 0)

Definition at line 5281 of file DA14680BA.h.

◆ DMA_DMA3_INT_REG_DMA3_INT_Msk

#define DMA_DMA3_INT_REG_DMA3_INT_Msk   (0xffffUL)

DMA DMA3_INT_REG: DMA3_INT (Bitfield-Mask: 0xffff)

Definition at line 5250 of file DA14680BA.h.

◆ DMA_DMA3_INT_REG_DMA3_INT_Pos

#define DMA_DMA3_INT_REG_DMA3_INT_Pos   (0UL)

DMA DMA3_INT_REG: DMA3_INT (Bit 0)

Definition at line 5249 of file DA14680BA.h.

◆ DMA_DMA3_LEN_REG_DMA3_LEN_Msk

#define DMA_DMA3_LEN_REG_DMA3_LEN_Msk   (0xffffUL)

DMA DMA3_LEN_REG: DMA3_LEN (Bitfield-Mask: 0xffff)

Definition at line 5254 of file DA14680BA.h.

◆ DMA_DMA3_LEN_REG_DMA3_LEN_Pos

#define DMA_DMA3_LEN_REG_DMA3_LEN_Pos   (0UL)

DMA DMA3_LEN_REG: DMA3_LEN (Bit 0)

Definition at line 5253 of file DA14680BA.h.

◆ DMA_DMA4_A_STARTH_REG_DMA4_A_STARTH_Msk

#define DMA_DMA4_A_STARTH_REG_DMA4_A_STARTH_Msk   (0xffffUL)

DMA DMA4_A_STARTH_REG: DMA4_A_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5290 of file DA14680BA.h.

◆ DMA_DMA4_A_STARTH_REG_DMA4_A_STARTH_Pos

#define DMA_DMA4_A_STARTH_REG_DMA4_A_STARTH_Pos   (0UL)

DMA DMA4_A_STARTH_REG: DMA4_A_STARTH (Bit 0)

Definition at line 5289 of file DA14680BA.h.

◆ DMA_DMA4_A_STARTL_REG_DMA4_A_STARTL_Msk

#define DMA_DMA4_A_STARTL_REG_DMA4_A_STARTL_Msk   (0xffffUL)

DMA DMA4_A_STARTL_REG: DMA4_A_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5286 of file DA14680BA.h.

◆ DMA_DMA4_A_STARTL_REG_DMA4_A_STARTL_Pos

#define DMA_DMA4_A_STARTL_REG_DMA4_A_STARTL_Pos   (0UL)

DMA DMA4_A_STARTL_REG: DMA4_A_STARTL (Bit 0)

Definition at line 5285 of file DA14680BA.h.

◆ DMA_DMA4_B_STARTH_REG_DMA4_B_STARTH_Msk

#define DMA_DMA4_B_STARTH_REG_DMA4_B_STARTH_Msk   (0xffffUL)

DMA DMA4_B_STARTH_REG: DMA4_B_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5298 of file DA14680BA.h.

◆ DMA_DMA4_B_STARTH_REG_DMA4_B_STARTH_Pos

#define DMA_DMA4_B_STARTH_REG_DMA4_B_STARTH_Pos   (0UL)

DMA DMA4_B_STARTH_REG: DMA4_B_STARTH (Bit 0)

Definition at line 5297 of file DA14680BA.h.

◆ DMA_DMA4_B_STARTL_REG_DMA4_B_STARTL_Msk

#define DMA_DMA4_B_STARTL_REG_DMA4_B_STARTL_Msk   (0xffffUL)

DMA DMA4_B_STARTL_REG: DMA4_B_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5294 of file DA14680BA.h.

◆ DMA_DMA4_B_STARTL_REG_DMA4_B_STARTL_Pos

#define DMA_DMA4_B_STARTL_REG_DMA4_B_STARTL_Pos   (0UL)

DMA DMA4_B_STARTL_REG: DMA4_B_STARTL (Bit 0)

Definition at line 5293 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_AINC_Msk

#define DMA_DMA4_CTRL_REG_AINC_Msk   (0x40UL)

DMA DMA4_CTRL_REG: AINC (Bitfield-Mask: 0x01)

Definition at line 5320 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_AINC_Pos

#define DMA_DMA4_CTRL_REG_AINC_Pos   (6UL)

DMA DMA4_CTRL_REG: AINC (Bit 6)

Definition at line 5319 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_BINC_Msk

#define DMA_DMA4_CTRL_REG_BINC_Msk   (0x20UL)

DMA DMA4_CTRL_REG: BINC (Bitfield-Mask: 0x01)

Definition at line 5318 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_BINC_Pos

#define DMA_DMA4_CTRL_REG_BINC_Pos   (5UL)

DMA DMA4_CTRL_REG: BINC (Bit 5)

Definition at line 5317 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_BW_Msk

#define DMA_DMA4_CTRL_REG_BW_Msk   (0x6UL)

DMA DMA4_CTRL_REG: BW (Bitfield-Mask: 0x03)

Definition at line 5312 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_BW_Pos

#define DMA_DMA4_CTRL_REG_BW_Pos   (1UL)

DMA DMA4_CTRL_REG: BW (Bit 1)

Definition at line 5311 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA4_CTRL_REG_CIRCULAR_Msk   (0x80UL)

DMA DMA4_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)

Definition at line 5322 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA4_CTRL_REG_CIRCULAR_Pos   (7UL)

DMA DMA4_CTRL_REG: CIRCULAR (Bit 7)

Definition at line 5321 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA4_CTRL_REG_DMA_IDLE_Msk   (0x800UL)

DMA DMA4_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)

Definition at line 5326 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA4_CTRL_REG_DMA_IDLE_Pos   (11UL)

DMA DMA4_CTRL_REG: DMA_IDLE (Bit 11)

Definition at line 5325 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA4_CTRL_REG_DMA_INIT_Msk   (0x1000UL)

DMA DMA4_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)

Definition at line 5328 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA4_CTRL_REG_DMA_INIT_Pos   (12UL)

DMA DMA4_CTRL_REG: DMA_INIT (Bit 12)

Definition at line 5327 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_DMA_ON_Msk

#define DMA_DMA4_CTRL_REG_DMA_ON_Msk   (0x1UL)

DMA DMA4_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)

Definition at line 5310 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_DMA_ON_Pos

#define DMA_DMA4_CTRL_REG_DMA_ON_Pos   (0UL)

DMA DMA4_CTRL_REG: DMA_ON (Bit 0)

Definition at line 5309 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA4_CTRL_REG_DMA_PRIO_Msk   (0x700UL)

DMA DMA4_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)

Definition at line 5324 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA4_CTRL_REG_DMA_PRIO_Pos   (8UL)

DMA DMA4_CTRL_REG: DMA_PRIO (Bit 8)

Definition at line 5323 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA4_CTRL_REG_DREQ_MODE_Msk   (0x10UL)

DMA DMA4_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)

Definition at line 5316 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA4_CTRL_REG_DREQ_MODE_Pos   (4UL)

DMA DMA4_CTRL_REG: DREQ_MODE (Bit 4)

Definition at line 5315 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_IRQ_ENABLE_Msk

#define DMA_DMA4_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)

DMA DMA4_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)

Definition at line 5314 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_IRQ_ENABLE_Pos

#define DMA_DMA4_CTRL_REG_IRQ_ENABLE_Pos   (3UL)

DMA DMA4_CTRL_REG: IRQ_ENABLE (Bit 3)

Definition at line 5313 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA4_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)

DMA DMA4_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)

Definition at line 5330 of file DA14680BA.h.

◆ DMA_DMA4_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA4_CTRL_REG_REQ_SENSE_Pos   (13UL)

DMA DMA4_CTRL_REG: REQ_SENSE (Bit 13)

Definition at line 5329 of file DA14680BA.h.

◆ DMA_DMA4_IDX_REG_DMA4_IDX_Msk

#define DMA_DMA4_IDX_REG_DMA4_IDX_Msk   (0xffffUL)

DMA DMA4_IDX_REG: DMA4_IDX (Bitfield-Mask: 0xffff)

Definition at line 5334 of file DA14680BA.h.

◆ DMA_DMA4_IDX_REG_DMA4_IDX_Pos

#define DMA_DMA4_IDX_REG_DMA4_IDX_Pos   (0UL)

DMA DMA4_IDX_REG: DMA4_IDX (Bit 0)

Definition at line 5333 of file DA14680BA.h.

◆ DMA_DMA4_INT_REG_DMA4_INT_Msk

#define DMA_DMA4_INT_REG_DMA4_INT_Msk   (0xffffUL)

DMA DMA4_INT_REG: DMA4_INT (Bitfield-Mask: 0xffff)

Definition at line 5302 of file DA14680BA.h.

◆ DMA_DMA4_INT_REG_DMA4_INT_Pos

#define DMA_DMA4_INT_REG_DMA4_INT_Pos   (0UL)

DMA DMA4_INT_REG: DMA4_INT (Bit 0)

Definition at line 5301 of file DA14680BA.h.

◆ DMA_DMA4_LEN_REG_DMA4_LEN_Msk

#define DMA_DMA4_LEN_REG_DMA4_LEN_Msk   (0xffffUL)

DMA DMA4_LEN_REG: DMA4_LEN (Bitfield-Mask: 0xffff)

Definition at line 5306 of file DA14680BA.h.

◆ DMA_DMA4_LEN_REG_DMA4_LEN_Pos

#define DMA_DMA4_LEN_REG_DMA4_LEN_Pos   (0UL)

DMA DMA4_LEN_REG: DMA4_LEN (Bit 0)

Definition at line 5305 of file DA14680BA.h.

◆ DMA_DMA5_A_STARTH_REG_DMA5_A_STARTH_Msk

#define DMA_DMA5_A_STARTH_REG_DMA5_A_STARTH_Msk   (0xffffUL)

DMA DMA5_A_STARTH_REG: DMA5_A_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5342 of file DA14680BA.h.

◆ DMA_DMA5_A_STARTH_REG_DMA5_A_STARTH_Pos

#define DMA_DMA5_A_STARTH_REG_DMA5_A_STARTH_Pos   (0UL)

DMA DMA5_A_STARTH_REG: DMA5_A_STARTH (Bit 0)

Definition at line 5341 of file DA14680BA.h.

◆ DMA_DMA5_A_STARTL_REG_DMA5_A_STARTL_Msk

#define DMA_DMA5_A_STARTL_REG_DMA5_A_STARTL_Msk   (0xffffUL)

DMA DMA5_A_STARTL_REG: DMA5_A_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5338 of file DA14680BA.h.

◆ DMA_DMA5_A_STARTL_REG_DMA5_A_STARTL_Pos

#define DMA_DMA5_A_STARTL_REG_DMA5_A_STARTL_Pos   (0UL)

DMA DMA5_A_STARTL_REG: DMA5_A_STARTL (Bit 0)

Definition at line 5337 of file DA14680BA.h.

◆ DMA_DMA5_B_STARTH_REG_DMA5_B_STARTH_Msk

#define DMA_DMA5_B_STARTH_REG_DMA5_B_STARTH_Msk   (0xffffUL)

DMA DMA5_B_STARTH_REG: DMA5_B_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5350 of file DA14680BA.h.

◆ DMA_DMA5_B_STARTH_REG_DMA5_B_STARTH_Pos

#define DMA_DMA5_B_STARTH_REG_DMA5_B_STARTH_Pos   (0UL)

DMA DMA5_B_STARTH_REG: DMA5_B_STARTH (Bit 0)

Definition at line 5349 of file DA14680BA.h.

◆ DMA_DMA5_B_STARTL_REG_DMA5_B_STARTL_Msk

#define DMA_DMA5_B_STARTL_REG_DMA5_B_STARTL_Msk   (0xffffUL)

DMA DMA5_B_STARTL_REG: DMA5_B_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5346 of file DA14680BA.h.

◆ DMA_DMA5_B_STARTL_REG_DMA5_B_STARTL_Pos

#define DMA_DMA5_B_STARTL_REG_DMA5_B_STARTL_Pos   (0UL)

DMA DMA5_B_STARTL_REG: DMA5_B_STARTL (Bit 0)

Definition at line 5345 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_AINC_Msk

#define DMA_DMA5_CTRL_REG_AINC_Msk   (0x40UL)

DMA DMA5_CTRL_REG: AINC (Bitfield-Mask: 0x01)

Definition at line 5372 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_AINC_Pos

#define DMA_DMA5_CTRL_REG_AINC_Pos   (6UL)

DMA DMA5_CTRL_REG: AINC (Bit 6)

Definition at line 5371 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_BINC_Msk

#define DMA_DMA5_CTRL_REG_BINC_Msk   (0x20UL)

DMA DMA5_CTRL_REG: BINC (Bitfield-Mask: 0x01)

Definition at line 5370 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_BINC_Pos

#define DMA_DMA5_CTRL_REG_BINC_Pos   (5UL)

DMA DMA5_CTRL_REG: BINC (Bit 5)

Definition at line 5369 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_BW_Msk

#define DMA_DMA5_CTRL_REG_BW_Msk   (0x6UL)

DMA DMA5_CTRL_REG: BW (Bitfield-Mask: 0x03)

Definition at line 5364 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_BW_Pos

#define DMA_DMA5_CTRL_REG_BW_Pos   (1UL)

DMA DMA5_CTRL_REG: BW (Bit 1)

Definition at line 5363 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA5_CTRL_REG_CIRCULAR_Msk   (0x80UL)

DMA DMA5_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)

Definition at line 5374 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA5_CTRL_REG_CIRCULAR_Pos   (7UL)

DMA DMA5_CTRL_REG: CIRCULAR (Bit 7)

Definition at line 5373 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA5_CTRL_REG_DMA_IDLE_Msk   (0x800UL)

DMA DMA5_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)

Definition at line 5378 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA5_CTRL_REG_DMA_IDLE_Pos   (11UL)

DMA DMA5_CTRL_REG: DMA_IDLE (Bit 11)

Definition at line 5377 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA5_CTRL_REG_DMA_INIT_Msk   (0x1000UL)

DMA DMA5_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)

Definition at line 5380 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA5_CTRL_REG_DMA_INIT_Pos   (12UL)

DMA DMA5_CTRL_REG: DMA_INIT (Bit 12)

Definition at line 5379 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_DMA_ON_Msk

#define DMA_DMA5_CTRL_REG_DMA_ON_Msk   (0x1UL)

DMA DMA5_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)

Definition at line 5362 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_DMA_ON_Pos

#define DMA_DMA5_CTRL_REG_DMA_ON_Pos   (0UL)

DMA DMA5_CTRL_REG: DMA_ON (Bit 0)

Definition at line 5361 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA5_CTRL_REG_DMA_PRIO_Msk   (0x700UL)

DMA DMA5_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)

Definition at line 5376 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA5_CTRL_REG_DMA_PRIO_Pos   (8UL)

DMA DMA5_CTRL_REG: DMA_PRIO (Bit 8)

Definition at line 5375 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA5_CTRL_REG_DREQ_MODE_Msk   (0x10UL)

DMA DMA5_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)

Definition at line 5368 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA5_CTRL_REG_DREQ_MODE_Pos   (4UL)

DMA DMA5_CTRL_REG: DREQ_MODE (Bit 4)

Definition at line 5367 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_IRQ_ENABLE_Msk

#define DMA_DMA5_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)

DMA DMA5_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)

Definition at line 5366 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_IRQ_ENABLE_Pos

#define DMA_DMA5_CTRL_REG_IRQ_ENABLE_Pos   (3UL)

DMA DMA5_CTRL_REG: IRQ_ENABLE (Bit 3)

Definition at line 5365 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA5_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)

DMA DMA5_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)

Definition at line 5382 of file DA14680BA.h.

◆ DMA_DMA5_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA5_CTRL_REG_REQ_SENSE_Pos   (13UL)

DMA DMA5_CTRL_REG: REQ_SENSE (Bit 13)

Definition at line 5381 of file DA14680BA.h.

◆ DMA_DMA5_IDX_REG_DMA5_IDX_Msk

#define DMA_DMA5_IDX_REG_DMA5_IDX_Msk   (0xffffUL)

DMA DMA5_IDX_REG: DMA5_IDX (Bitfield-Mask: 0xffff)

Definition at line 5386 of file DA14680BA.h.

◆ DMA_DMA5_IDX_REG_DMA5_IDX_Pos

#define DMA_DMA5_IDX_REG_DMA5_IDX_Pos   (0UL)

DMA DMA5_IDX_REG: DMA5_IDX (Bit 0)

Definition at line 5385 of file DA14680BA.h.

◆ DMA_DMA5_INT_REG_DMA5_INT_Msk

#define DMA_DMA5_INT_REG_DMA5_INT_Msk   (0xffffUL)

DMA DMA5_INT_REG: DMA5_INT (Bitfield-Mask: 0xffff)

Definition at line 5354 of file DA14680BA.h.

◆ DMA_DMA5_INT_REG_DMA5_INT_Pos

#define DMA_DMA5_INT_REG_DMA5_INT_Pos   (0UL)

DMA DMA5_INT_REG: DMA5_INT (Bit 0)

Definition at line 5353 of file DA14680BA.h.

◆ DMA_DMA5_LEN_REG_DMA5_LEN_Msk

#define DMA_DMA5_LEN_REG_DMA5_LEN_Msk   (0xffffUL)

DMA DMA5_LEN_REG: DMA5_LEN (Bitfield-Mask: 0xffff)

Definition at line 5358 of file DA14680BA.h.

◆ DMA_DMA5_LEN_REG_DMA5_LEN_Pos

#define DMA_DMA5_LEN_REG_DMA5_LEN_Pos   (0UL)

DMA DMA5_LEN_REG: DMA5_LEN (Bit 0)

Definition at line 5357 of file DA14680BA.h.

◆ DMA_DMA6_A_STARTH_REG_DMA6_A_STARTH_Msk

#define DMA_DMA6_A_STARTH_REG_DMA6_A_STARTH_Msk   (0xffffUL)

DMA DMA6_A_STARTH_REG: DMA6_A_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5394 of file DA14680BA.h.

◆ DMA_DMA6_A_STARTH_REG_DMA6_A_STARTH_Pos

#define DMA_DMA6_A_STARTH_REG_DMA6_A_STARTH_Pos   (0UL)

DMA DMA6_A_STARTH_REG: DMA6_A_STARTH (Bit 0)

Definition at line 5393 of file DA14680BA.h.

◆ DMA_DMA6_A_STARTL_REG_DMA6_A_STARTL_Msk

#define DMA_DMA6_A_STARTL_REG_DMA6_A_STARTL_Msk   (0xffffUL)

DMA DMA6_A_STARTL_REG: DMA6_A_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5390 of file DA14680BA.h.

◆ DMA_DMA6_A_STARTL_REG_DMA6_A_STARTL_Pos

#define DMA_DMA6_A_STARTL_REG_DMA6_A_STARTL_Pos   (0UL)

DMA DMA6_A_STARTL_REG: DMA6_A_STARTL (Bit 0)

Definition at line 5389 of file DA14680BA.h.

◆ DMA_DMA6_B_STARTH_REG_DMA6_B_STARTH_Msk

#define DMA_DMA6_B_STARTH_REG_DMA6_B_STARTH_Msk   (0xffffUL)

DMA DMA6_B_STARTH_REG: DMA6_B_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5402 of file DA14680BA.h.

◆ DMA_DMA6_B_STARTH_REG_DMA6_B_STARTH_Pos

#define DMA_DMA6_B_STARTH_REG_DMA6_B_STARTH_Pos   (0UL)

DMA DMA6_B_STARTH_REG: DMA6_B_STARTH (Bit 0)

Definition at line 5401 of file DA14680BA.h.

◆ DMA_DMA6_B_STARTL_REG_DMA6_B_STARTL_Msk

#define DMA_DMA6_B_STARTL_REG_DMA6_B_STARTL_Msk   (0xffffUL)

DMA DMA6_B_STARTL_REG: DMA6_B_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5398 of file DA14680BA.h.

◆ DMA_DMA6_B_STARTL_REG_DMA6_B_STARTL_Pos

#define DMA_DMA6_B_STARTL_REG_DMA6_B_STARTL_Pos   (0UL)

DMA DMA6_B_STARTL_REG: DMA6_B_STARTL (Bit 0)

Definition at line 5397 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_AINC_Msk

#define DMA_DMA6_CTRL_REG_AINC_Msk   (0x40UL)

DMA DMA6_CTRL_REG: AINC (Bitfield-Mask: 0x01)

Definition at line 5424 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_AINC_Pos

#define DMA_DMA6_CTRL_REG_AINC_Pos   (6UL)

DMA DMA6_CTRL_REG: AINC (Bit 6)

Definition at line 5423 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_BINC_Msk

#define DMA_DMA6_CTRL_REG_BINC_Msk   (0x20UL)

DMA DMA6_CTRL_REG: BINC (Bitfield-Mask: 0x01)

Definition at line 5422 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_BINC_Pos

#define DMA_DMA6_CTRL_REG_BINC_Pos   (5UL)

DMA DMA6_CTRL_REG: BINC (Bit 5)

Definition at line 5421 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_BW_Msk

#define DMA_DMA6_CTRL_REG_BW_Msk   (0x6UL)

DMA DMA6_CTRL_REG: BW (Bitfield-Mask: 0x03)

Definition at line 5416 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_BW_Pos

#define DMA_DMA6_CTRL_REG_BW_Pos   (1UL)

DMA DMA6_CTRL_REG: BW (Bit 1)

Definition at line 5415 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA6_CTRL_REG_CIRCULAR_Msk   (0x80UL)

DMA DMA6_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)

Definition at line 5426 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA6_CTRL_REG_CIRCULAR_Pos   (7UL)

DMA DMA6_CTRL_REG: CIRCULAR (Bit 7)

Definition at line 5425 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA6_CTRL_REG_DMA_IDLE_Msk   (0x800UL)

DMA DMA6_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)

Definition at line 5430 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA6_CTRL_REG_DMA_IDLE_Pos   (11UL)

DMA DMA6_CTRL_REG: DMA_IDLE (Bit 11)

Definition at line 5429 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA6_CTRL_REG_DMA_INIT_Msk   (0x1000UL)

DMA DMA6_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)

Definition at line 5432 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA6_CTRL_REG_DMA_INIT_Pos   (12UL)

DMA DMA6_CTRL_REG: DMA_INIT (Bit 12)

Definition at line 5431 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_DMA_ON_Msk

#define DMA_DMA6_CTRL_REG_DMA_ON_Msk   (0x1UL)

DMA DMA6_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)

Definition at line 5414 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_DMA_ON_Pos

#define DMA_DMA6_CTRL_REG_DMA_ON_Pos   (0UL)

DMA DMA6_CTRL_REG: DMA_ON (Bit 0)

Definition at line 5413 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA6_CTRL_REG_DMA_PRIO_Msk   (0x700UL)

DMA DMA6_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)

Definition at line 5428 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA6_CTRL_REG_DMA_PRIO_Pos   (8UL)

DMA DMA6_CTRL_REG: DMA_PRIO (Bit 8)

Definition at line 5427 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA6_CTRL_REG_DREQ_MODE_Msk   (0x10UL)

DMA DMA6_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)

Definition at line 5420 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA6_CTRL_REG_DREQ_MODE_Pos   (4UL)

DMA DMA6_CTRL_REG: DREQ_MODE (Bit 4)

Definition at line 5419 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_IRQ_ENABLE_Msk

#define DMA_DMA6_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)

DMA DMA6_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)

Definition at line 5418 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_IRQ_ENABLE_Pos

#define DMA_DMA6_CTRL_REG_IRQ_ENABLE_Pos   (3UL)

DMA DMA6_CTRL_REG: IRQ_ENABLE (Bit 3)

Definition at line 5417 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA6_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)

DMA DMA6_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)

Definition at line 5434 of file DA14680BA.h.

◆ DMA_DMA6_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA6_CTRL_REG_REQ_SENSE_Pos   (13UL)

DMA DMA6_CTRL_REG: REQ_SENSE (Bit 13)

Definition at line 5433 of file DA14680BA.h.

◆ DMA_DMA6_IDX_REG_DMA6_IDX_Msk

#define DMA_DMA6_IDX_REG_DMA6_IDX_Msk   (0xffffUL)

DMA DMA6_IDX_REG: DMA6_IDX (Bitfield-Mask: 0xffff)

Definition at line 5438 of file DA14680BA.h.

◆ DMA_DMA6_IDX_REG_DMA6_IDX_Pos

#define DMA_DMA6_IDX_REG_DMA6_IDX_Pos   (0UL)

DMA DMA6_IDX_REG: DMA6_IDX (Bit 0)

Definition at line 5437 of file DA14680BA.h.

◆ DMA_DMA6_INT_REG_DMA6_INT_Msk

#define DMA_DMA6_INT_REG_DMA6_INT_Msk   (0xffffUL)

DMA DMA6_INT_REG: DMA6_INT (Bitfield-Mask: 0xffff)

Definition at line 5406 of file DA14680BA.h.

◆ DMA_DMA6_INT_REG_DMA6_INT_Pos

#define DMA_DMA6_INT_REG_DMA6_INT_Pos   (0UL)

DMA DMA6_INT_REG: DMA6_INT (Bit 0)

Definition at line 5405 of file DA14680BA.h.

◆ DMA_DMA6_LEN_REG_DMA6_LEN_Msk

#define DMA_DMA6_LEN_REG_DMA6_LEN_Msk   (0xffffUL)

DMA DMA6_LEN_REG: DMA6_LEN (Bitfield-Mask: 0xffff)

Definition at line 5410 of file DA14680BA.h.

◆ DMA_DMA6_LEN_REG_DMA6_LEN_Pos

#define DMA_DMA6_LEN_REG_DMA6_LEN_Pos   (0UL)

DMA DMA6_LEN_REG: DMA6_LEN (Bit 0)

Definition at line 5409 of file DA14680BA.h.

◆ DMA_DMA7_A_STARTH_REG_DMA7_A_STARTH_Msk

#define DMA_DMA7_A_STARTH_REG_DMA7_A_STARTH_Msk   (0xffffUL)

DMA DMA7_A_STARTH_REG: DMA7_A_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5446 of file DA14680BA.h.

◆ DMA_DMA7_A_STARTH_REG_DMA7_A_STARTH_Pos

#define DMA_DMA7_A_STARTH_REG_DMA7_A_STARTH_Pos   (0UL)

DMA DMA7_A_STARTH_REG: DMA7_A_STARTH (Bit 0)

Definition at line 5445 of file DA14680BA.h.

◆ DMA_DMA7_A_STARTL_REG_DMA7_A_STARTL_Msk

#define DMA_DMA7_A_STARTL_REG_DMA7_A_STARTL_Msk   (0xffffUL)

DMA DMA7_A_STARTL_REG: DMA7_A_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5442 of file DA14680BA.h.

◆ DMA_DMA7_A_STARTL_REG_DMA7_A_STARTL_Pos

#define DMA_DMA7_A_STARTL_REG_DMA7_A_STARTL_Pos   (0UL)

DMA DMA7_A_STARTL_REG: DMA7_A_STARTL (Bit 0)

Definition at line 5441 of file DA14680BA.h.

◆ DMA_DMA7_B_STARTH_REG_DMA7_B_STARTH_Msk

#define DMA_DMA7_B_STARTH_REG_DMA7_B_STARTH_Msk   (0xffffUL)

DMA DMA7_B_STARTH_REG: DMA7_B_STARTH (Bitfield-Mask: 0xffff)

Definition at line 5454 of file DA14680BA.h.

◆ DMA_DMA7_B_STARTH_REG_DMA7_B_STARTH_Pos

#define DMA_DMA7_B_STARTH_REG_DMA7_B_STARTH_Pos   (0UL)

DMA DMA7_B_STARTH_REG: DMA7_B_STARTH (Bit 0)

Definition at line 5453 of file DA14680BA.h.

◆ DMA_DMA7_B_STARTL_REG_DMA7_B_STARTL_Msk

#define DMA_DMA7_B_STARTL_REG_DMA7_B_STARTL_Msk   (0xffffUL)

DMA DMA7_B_STARTL_REG: DMA7_B_STARTL (Bitfield-Mask: 0xffff)

Definition at line 5450 of file DA14680BA.h.

◆ DMA_DMA7_B_STARTL_REG_DMA7_B_STARTL_Pos

#define DMA_DMA7_B_STARTL_REG_DMA7_B_STARTL_Pos   (0UL)

DMA DMA7_B_STARTL_REG: DMA7_B_STARTL (Bit 0)

Definition at line 5449 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_AINC_Msk

#define DMA_DMA7_CTRL_REG_AINC_Msk   (0x40UL)

DMA DMA7_CTRL_REG: AINC (Bitfield-Mask: 0x01)

Definition at line 5476 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_AINC_Pos

#define DMA_DMA7_CTRL_REG_AINC_Pos   (6UL)

DMA DMA7_CTRL_REG: AINC (Bit 6)

Definition at line 5475 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_BINC_Msk

#define DMA_DMA7_CTRL_REG_BINC_Msk   (0x20UL)

DMA DMA7_CTRL_REG: BINC (Bitfield-Mask: 0x01)

Definition at line 5474 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_BINC_Pos

#define DMA_DMA7_CTRL_REG_BINC_Pos   (5UL)

DMA DMA7_CTRL_REG: BINC (Bit 5)

Definition at line 5473 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_BW_Msk

#define DMA_DMA7_CTRL_REG_BW_Msk   (0x6UL)

DMA DMA7_CTRL_REG: BW (Bitfield-Mask: 0x03)

Definition at line 5468 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_BW_Pos

#define DMA_DMA7_CTRL_REG_BW_Pos   (1UL)

DMA DMA7_CTRL_REG: BW (Bit 1)

Definition at line 5467 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA7_CTRL_REG_CIRCULAR_Msk   (0x80UL)

DMA DMA7_CTRL_REG: CIRCULAR (Bitfield-Mask: 0x01)

Definition at line 5478 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA7_CTRL_REG_CIRCULAR_Pos   (7UL)

DMA DMA7_CTRL_REG: CIRCULAR (Bit 7)

Definition at line 5477 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA7_CTRL_REG_DMA_IDLE_Msk   (0x800UL)

DMA DMA7_CTRL_REG: DMA_IDLE (Bitfield-Mask: 0x01)

Definition at line 5482 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA7_CTRL_REG_DMA_IDLE_Pos   (11UL)

DMA DMA7_CTRL_REG: DMA_IDLE (Bit 11)

Definition at line 5481 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA7_CTRL_REG_DMA_INIT_Msk   (0x1000UL)

DMA DMA7_CTRL_REG: DMA_INIT (Bitfield-Mask: 0x01)

Definition at line 5484 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA7_CTRL_REG_DMA_INIT_Pos   (12UL)

DMA DMA7_CTRL_REG: DMA_INIT (Bit 12)

Definition at line 5483 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_DMA_ON_Msk

#define DMA_DMA7_CTRL_REG_DMA_ON_Msk   (0x1UL)

DMA DMA7_CTRL_REG: DMA_ON (Bitfield-Mask: 0x01)

Definition at line 5466 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_DMA_ON_Pos

#define DMA_DMA7_CTRL_REG_DMA_ON_Pos   (0UL)

DMA DMA7_CTRL_REG: DMA_ON (Bit 0)

Definition at line 5465 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA7_CTRL_REG_DMA_PRIO_Msk   (0x700UL)

DMA DMA7_CTRL_REG: DMA_PRIO (Bitfield-Mask: 0x07)

Definition at line 5480 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA7_CTRL_REG_DMA_PRIO_Pos   (8UL)

DMA DMA7_CTRL_REG: DMA_PRIO (Bit 8)

Definition at line 5479 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA7_CTRL_REG_DREQ_MODE_Msk   (0x10UL)

DMA DMA7_CTRL_REG: DREQ_MODE (Bitfield-Mask: 0x01)

Definition at line 5472 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA7_CTRL_REG_DREQ_MODE_Pos   (4UL)

DMA DMA7_CTRL_REG: DREQ_MODE (Bit 4)

Definition at line 5471 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_IRQ_ENABLE_Msk

#define DMA_DMA7_CTRL_REG_IRQ_ENABLE_Msk   (0x8UL)

DMA DMA7_CTRL_REG: IRQ_ENABLE (Bitfield-Mask: 0x01)

Definition at line 5470 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_IRQ_ENABLE_Pos

#define DMA_DMA7_CTRL_REG_IRQ_ENABLE_Pos   (3UL)

DMA DMA7_CTRL_REG: IRQ_ENABLE (Bit 3)

Definition at line 5469 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA7_CTRL_REG_REQ_SENSE_Msk   (0x2000UL)

DMA DMA7_CTRL_REG: REQ_SENSE (Bitfield-Mask: 0x01)

Definition at line 5486 of file DA14680BA.h.

◆ DMA_DMA7_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA7_CTRL_REG_REQ_SENSE_Pos   (13UL)

DMA DMA7_CTRL_REG: REQ_SENSE (Bit 13)

Definition at line 5485 of file DA14680BA.h.

◆ DMA_DMA7_IDX_REG_DMA7_IDX_Msk

#define DMA_DMA7_IDX_REG_DMA7_IDX_Msk   (0xffffUL)

DMA DMA7_IDX_REG: DMA7_IDX (Bitfield-Mask: 0xffff)

Definition at line 5490 of file DA14680BA.h.

◆ DMA_DMA7_IDX_REG_DMA7_IDX_Pos

#define DMA_DMA7_IDX_REG_DMA7_IDX_Pos   (0UL)

DMA DMA7_IDX_REG: DMA7_IDX (Bit 0)

Definition at line 5489 of file DA14680BA.h.

◆ DMA_DMA7_INT_REG_DMA7_INT_Msk

#define DMA_DMA7_INT_REG_DMA7_INT_Msk   (0xffffUL)

DMA DMA7_INT_REG: DMA7_INT (Bitfield-Mask: 0xffff)

Definition at line 5458 of file DA14680BA.h.

◆ DMA_DMA7_INT_REG_DMA7_INT_Pos

#define DMA_DMA7_INT_REG_DMA7_INT_Pos   (0UL)

DMA DMA7_INT_REG: DMA7_INT (Bit 0)

Definition at line 5457 of file DA14680BA.h.

◆ DMA_DMA7_LEN_REG_DMA7_LEN_Msk

#define DMA_DMA7_LEN_REG_DMA7_LEN_Msk   (0xffffUL)

DMA DMA7_LEN_REG: DMA7_LEN (Bitfield-Mask: 0xffff)

Definition at line 5462 of file DA14680BA.h.

◆ DMA_DMA7_LEN_REG_DMA7_LEN_Pos

#define DMA_DMA7_LEN_REG_DMA7_LEN_Pos   (0UL)

DMA DMA7_LEN_REG: DMA7_LEN (Bit 0)

Definition at line 5461 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Msk   (0x1UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH0 (Bitfield-Mask: 0x01)

Definition at line 5522 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Pos   (0UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH0 (Bit 0)

Definition at line 5521 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Msk   (0x2UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH1 (Bitfield-Mask: 0x01)

Definition at line 5524 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Pos   (1UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH1 (Bit 1)

Definition at line 5523 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Msk   (0x4UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH2 (Bitfield-Mask: 0x01)

Definition at line 5526 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Pos   (2UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH2 (Bit 2)

Definition at line 5525 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Msk   (0x8UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH3 (Bitfield-Mask: 0x01)

Definition at line 5528 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Pos   (3UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH3 (Bit 3)

Definition at line 5527 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Msk   (0x10UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH4 (Bitfield-Mask: 0x01)

Definition at line 5530 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Pos   (4UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH4 (Bit 4)

Definition at line 5529 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Msk   (0x20UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH5 (Bitfield-Mask: 0x01)

Definition at line 5532 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Pos   (5UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH5 (Bit 5)

Definition at line 5531 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Msk   (0x40UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH6 (Bitfield-Mask: 0x01)

Definition at line 5534 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH6_Pos   (6UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH6 (Bit 6)

Definition at line 5533 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Msk   (0x80UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH7 (Bitfield-Mask: 0x01)

Definition at line 5536 of file DA14680BA.h.

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH7_Pos   (7UL)

DMA DMA_CLEAR_INT_REG: DMA_RST_IRQ_CH7 (Bit 7)

Definition at line 5535 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Msk   (0x1UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH0 (Bitfield-Mask: 0x01)

Definition at line 5504 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Pos   (0UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH0 (Bit 0)

Definition at line 5503 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Msk   (0x2UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH1 (Bitfield-Mask: 0x01)

Definition at line 5506 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Pos   (1UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH1 (Bit 1)

Definition at line 5505 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Msk   (0x4UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH2 (Bitfield-Mask: 0x01)

Definition at line 5508 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Pos   (2UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH2 (Bit 2)

Definition at line 5507 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Msk   (0x8UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH3 (Bitfield-Mask: 0x01)

Definition at line 5510 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Pos   (3UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH3 (Bit 3)

Definition at line 5509 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Msk   (0x10UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH4 (Bitfield-Mask: 0x01)

Definition at line 5512 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Pos   (4UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH4 (Bit 4)

Definition at line 5511 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Msk   (0x20UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH5 (Bitfield-Mask: 0x01)

Definition at line 5514 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Pos   (5UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH5 (Bit 5)

Definition at line 5513 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Msk   (0x40UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH6 (Bitfield-Mask: 0x01)

Definition at line 5516 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH6_Pos   (6UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH6 (Bit 6)

Definition at line 5515 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Msk   (0x80UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH7 (Bitfield-Mask: 0x01)

Definition at line 5518 of file DA14680BA.h.

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH7_Pos   (7UL)

DMA DMA_INT_STATUS_REG: DMA_IRQ_CH7 (Bit 7)

Definition at line 5517 of file DA14680BA.h.

◆ DMA_DMA_REQ_MUX_REG_DMA01_SEL_Msk

#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Msk   (0xfUL)

DMA DMA_REQ_MUX_REG: DMA01_SEL (Bitfield-Mask: 0x0f)

Definition at line 5494 of file DA14680BA.h.

◆ DMA_DMA_REQ_MUX_REG_DMA01_SEL_Pos

#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Pos   (0UL)

DMA DMA_REQ_MUX_REG: DMA01_SEL (Bit 0)

Definition at line 5493 of file DA14680BA.h.

◆ DMA_DMA_REQ_MUX_REG_DMA23_SEL_Msk

#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Msk   (0xf0UL)

DMA DMA_REQ_MUX_REG: DMA23_SEL (Bitfield-Mask: 0x0f)

Definition at line 5496 of file DA14680BA.h.

◆ DMA_DMA_REQ_MUX_REG_DMA23_SEL_Pos

#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Pos   (4UL)

DMA DMA_REQ_MUX_REG: DMA23_SEL (Bit 4)

Definition at line 5495 of file DA14680BA.h.

◆ DMA_DMA_REQ_MUX_REG_DMA45_SEL_Msk

#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Msk   (0xf00UL)

DMA DMA_REQ_MUX_REG: DMA45_SEL (Bitfield-Mask: 0x0f)

Definition at line 5498 of file DA14680BA.h.

◆ DMA_DMA_REQ_MUX_REG_DMA45_SEL_Pos

#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Pos   (8UL)

DMA DMA_REQ_MUX_REG: DMA45_SEL (Bit 8)

Definition at line 5497 of file DA14680BA.h.

◆ DMA_DMA_REQ_MUX_REG_DMA67_SEL_Msk

#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Msk   (0xf000UL)

DMA DMA_REQ_MUX_REG: DMA67_SEL (Bitfield-Mask: 0x0f)

Definition at line 5500 of file DA14680BA.h.

◆ DMA_DMA_REQ_MUX_REG_DMA67_SEL_Pos

#define DMA_DMA_REQ_MUX_REG_DMA67_SEL_Pos   (12UL)

DMA DMA_REQ_MUX_REG: DMA67_SEL (Bit 12)

Definition at line 5499 of file DA14680BA.h.

◆ ECC

#define ECC   ((ECC_Type *) ECC_BASE)

Definition at line 12085 of file DA14680BA.h.

◆ ECC_BASE

#define ECC_BASE   0x50006000UL

Definition at line 12040 of file DA14680BA.h.

◆ ECC_ECC_COMMAND_REG_ECC_CalcR2_Msk

#define ECC_ECC_COMMAND_REG_ECC_CalcR2_Msk   (0x80000000UL)

ECC ECC_COMMAND_REG: ECC_CalcR2 (Bitfield-Mask: 0x01)

Definition at line 5564 of file DA14680BA.h.

◆ ECC_ECC_COMMAND_REG_ECC_CalcR2_Pos

#define ECC_ECC_COMMAND_REG_ECC_CalcR2_Pos   (31UL)

ECC ECC_COMMAND_REG: ECC_CalcR2 (Bit 31)

Definition at line 5563 of file DA14680BA.h.

◆ ECC_ECC_COMMAND_REG_ECC_Field_Msk

#define ECC_ECC_COMMAND_REG_ECC_Field_Msk   (0x80UL)

ECC ECC_COMMAND_REG: ECC_Field (Bitfield-Mask: 0x01)

Definition at line 5556 of file DA14680BA.h.

◆ ECC_ECC_COMMAND_REG_ECC_Field_Pos

#define ECC_ECC_COMMAND_REG_ECC_Field_Pos   (7UL)

ECC ECC_COMMAND_REG: ECC_Field (Bit 7)

Definition at line 5555 of file DA14680BA.h.

◆ ECC_ECC_COMMAND_REG_ECC_SignA_Msk

#define ECC_ECC_COMMAND_REG_ECC_SignA_Msk   (0x20000000UL)

ECC ECC_COMMAND_REG: ECC_SignA (Bitfield-Mask: 0x01)

Definition at line 5560 of file DA14680BA.h.

◆ ECC_ECC_COMMAND_REG_ECC_SignA_Pos

#define ECC_ECC_COMMAND_REG_ECC_SignA_Pos   (29UL)

ECC ECC_COMMAND_REG: ECC_SignA (Bit 29)

Definition at line 5559 of file DA14680BA.h.

◆ ECC_ECC_COMMAND_REG_ECC_SignB_Msk

#define ECC_ECC_COMMAND_REG_ECC_SignB_Msk   (0x40000000UL)

ECC ECC_COMMAND_REG: ECC_SignB (Bitfield-Mask: 0x01)

Definition at line 5562 of file DA14680BA.h.

◆ ECC_ECC_COMMAND_REG_ECC_SignB_Pos

#define ECC_ECC_COMMAND_REG_ECC_SignB_Pos   (30UL)

ECC ECC_COMMAND_REG: ECC_SignB (Bit 30)

Definition at line 5561 of file DA14680BA.h.

◆ ECC_ECC_COMMAND_REG_ECC_SizeOfOperands_Msk

#define ECC_ECC_COMMAND_REG_ECC_SizeOfOperands_Msk   (0xff00UL)

ECC ECC_COMMAND_REG: ECC_SizeOfOperands (Bitfield-Mask: 0xff)

Definition at line 5558 of file DA14680BA.h.

◆ ECC_ECC_COMMAND_REG_ECC_SizeOfOperands_Pos

#define ECC_ECC_COMMAND_REG_ECC_SizeOfOperands_Pos   (8UL)

ECC ECC_COMMAND_REG: ECC_SizeOfOperands (Bit 8)

Definition at line 5557 of file DA14680BA.h.

◆ ECC_ECC_COMMAND_REG_ECC_TypeOperation_Msk

#define ECC_ECC_COMMAND_REG_ECC_TypeOperation_Msk   (0x7fUL)

ECC ECC_COMMAND_REG: ECC_TypeOperation (Bitfield-Mask: 0x7f)

Definition at line 5554 of file DA14680BA.h.

◆ ECC_ECC_COMMAND_REG_ECC_TypeOperation_Pos

#define ECC_ECC_COMMAND_REG_ECC_TypeOperation_Pos   (0UL)

ECC ECC_COMMAND_REG: ECC_TypeOperation (Bit 0)

Definition at line 5553 of file DA14680BA.h.

◆ ECC_ECC_CONFIG_REG_ECC_OpPtrA_Msk

#define ECC_ECC_CONFIG_REG_ECC_OpPtrA_Msk   (0x1fUL)

ECC ECC_CONFIG_REG: ECC_OpPtrA (Bitfield-Mask: 0x1f)

Definition at line 5546 of file DA14680BA.h.

◆ ECC_ECC_CONFIG_REG_ECC_OpPtrA_Pos

#define ECC_ECC_CONFIG_REG_ECC_OpPtrA_Pos   (0UL)

ECC ECC_CONFIG_REG: ECC_OpPtrA (Bit 0)

Definition at line 5545 of file DA14680BA.h.

◆ ECC_ECC_CONFIG_REG_ECC_OpPtrB_Msk

#define ECC_ECC_CONFIG_REG_ECC_OpPtrB_Msk   (0x1f00UL)

ECC ECC_CONFIG_REG: ECC_OpPtrB (Bitfield-Mask: 0x1f)

Definition at line 5548 of file DA14680BA.h.

◆ ECC_ECC_CONFIG_REG_ECC_OpPtrB_Pos

#define ECC_ECC_CONFIG_REG_ECC_OpPtrB_Pos   (8UL)

ECC ECC_CONFIG_REG: ECC_OpPtrB (Bit 8)

Definition at line 5547 of file DA14680BA.h.

◆ ECC_ECC_CONFIG_REG_ECC_OpPtrC_Msk

#define ECC_ECC_CONFIG_REG_ECC_OpPtrC_Msk   (0x1f0000UL)

ECC ECC_CONFIG_REG: ECC_OpPtrC (Bitfield-Mask: 0x1f)

Definition at line 5550 of file DA14680BA.h.

◆ ECC_ECC_CONFIG_REG_ECC_OpPtrC_Pos

#define ECC_ECC_CONFIG_REG_ECC_OpPtrC_Pos   (16UL)

ECC ECC_CONFIG_REG: ECC_OpPtrC (Bit 16)

Definition at line 5549 of file DA14680BA.h.

◆ ECC_ECC_CONTROL_REG_ECC_Start_Msk

#define ECC_ECC_CONTROL_REG_ECC_Start_Msk   (0x1UL)

ECC ECC_CONTROL_REG: ECC_Start (Bitfield-Mask: 0x01)

Definition at line 5568 of file DA14680BA.h.

◆ ECC_ECC_CONTROL_REG_ECC_Start_Pos

#define ECC_ECC_CONTROL_REG_ECC_Start_Pos   (0UL)

ECC ECC_CONTROL_REG: ECC_Start (Bit 0)

Definition at line 5567 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Busy_Msk

#define ECC_ECC_STATUS_REG_ECC_Busy_Msk   (0x10000UL)

ECC ECC_STATUS_REG: ECC_Busy (Bitfield-Mask: 0x01)

Definition at line 5590 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Busy_Pos

#define ECC_ECC_STATUS_REG_ECC_Busy_Pos   (16UL)

ECC ECC_STATUS_REG: ECC_Busy (Bit 16)

Definition at line 5589 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Couple_NotValid_Msk

#define ECC_ECC_STATUS_REG_ECC_Couple_NotValid_Msk   (0x40UL)

ECC ECC_STATUS_REG: ECC_Couple_NotValid (Bitfield-Mask: 0x01)

Definition at line 5578 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Couple_NotValid_Pos

#define ECC_ECC_STATUS_REG_ECC_Couple_NotValid_Pos   (6UL)

ECC ECC_STATUS_REG: ECC_Couple_NotValid (Bit 6)

Definition at line 5577 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Fail_Address_Msk

#define ECC_ECC_STATUS_REG_ECC_Fail_Address_Msk   (0xfUL)

ECC ECC_STATUS_REG: ECC_Fail_Address (Bitfield-Mask: 0x0f)

Definition at line 5572 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Fail_Address_Pos

#define ECC_ECC_STATUS_REG_ECC_Fail_Address_Pos   (0UL)

ECC ECC_STATUS_REG: ECC_Fail_Address (Bit 0)

Definition at line 5571 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_NotInvertible_Msk

#define ECC_ECC_STATUS_REG_ECC_NotInvertible_Msk   (0x800UL)

ECC ECC_STATUS_REG: ECC_NotInvertible (Bitfield-Mask: 0x01)

Definition at line 5586 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_NotInvertible_Pos

#define ECC_ECC_STATUS_REG_ECC_NotInvertible_Pos   (11UL)

ECC ECC_STATUS_REG: ECC_NotInvertible (Bit 11)

Definition at line 5585 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Param_AB_NotValid_Msk

#define ECC_ECC_STATUS_REG_ECC_Param_AB_NotValid_Msk   (0x400UL)

ECC ECC_STATUS_REG: ECC_Param_AB_NotValid (Bitfield-Mask: 0x01)

Definition at line 5584 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Param_AB_NotValid_Pos

#define ECC_ECC_STATUS_REG_ECC_Param_AB_NotValid_Pos   (10UL)

ECC ECC_STATUS_REG: ECC_Param_AB_NotValid (Bit 10)

Definition at line 5583 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Param_n_NotValid_Msk

#define ECC_ECC_STATUS_REG_ECC_Param_n_NotValid_Msk   (0x80UL)

ECC ECC_STATUS_REG: ECC_Param_n_NotValid (Bitfield-Mask: 0x01)

Definition at line 5580 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Param_n_NotValid_Pos

#define ECC_ECC_STATUS_REG_ECC_Param_n_NotValid_Pos   (7UL)

ECC ECC_STATUS_REG: ECC_Param_n_NotValid (Bit 7)

Definition at line 5579 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Point_Px_AtInfinity_Msk

#define ECC_ECC_STATUS_REG_ECC_Point_Px_AtInfinity_Msk   (0x20UL)

ECC ECC_STATUS_REG: ECC_Point_Px_AtInfinity (Bitfield-Mask: 0x01)

Definition at line 5576 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Point_Px_AtInfinity_Pos

#define ECC_ECC_STATUS_REG_ECC_Point_Px_AtInfinity_Pos   (5UL)

ECC ECC_STATUS_REG: ECC_Point_Px_AtInfinity (Bit 5)

Definition at line 5575 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Point_Px_NotOnCurve_Msk

#define ECC_ECC_STATUS_REG_ECC_Point_Px_NotOnCurve_Msk   (0x10UL)

ECC ECC_STATUS_REG: ECC_Point_Px_NotOnCurve (Bitfield-Mask: 0x01)

Definition at line 5574 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Point_Px_NotOnCurve_Pos

#define ECC_ECC_STATUS_REG_ECC_Point_Px_NotOnCurve_Pos   (4UL)

ECC ECC_STATUS_REG: ECC_Point_Px_NotOnCurve (Bit 4)

Definition at line 5573 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_PrimalityTestResult_Msk

#define ECC_ECC_STATUS_REG_ECC_PrimalityTestResult_Msk   (0x1000UL)

ECC ECC_STATUS_REG: ECC_PrimalityTestResult (Bitfield-Mask: 0x01)

Definition at line 5588 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_PrimalityTestResult_Pos

#define ECC_ECC_STATUS_REG_ECC_PrimalityTestResult_Pos   (12UL)

ECC ECC_STATUS_REG: ECC_PrimalityTestResult (Bit 12)

Definition at line 5587 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Signature_NotValid_Msk

#define ECC_ECC_STATUS_REG_ECC_Signature_NotValid_Msk   (0x200UL)

ECC ECC_STATUS_REG: ECC_Signature_NotValid (Bitfield-Mask: 0x01)

Definition at line 5582 of file DA14680BA.h.

◆ ECC_ECC_STATUS_REG_ECC_Signature_NotValid_Pos

#define ECC_ECC_STATUS_REG_ECC_Signature_NotValid_Pos   (9UL)

ECC ECC_STATUS_REG: ECC_Signature_NotValid (Bit 9)

Definition at line 5581 of file DA14680BA.h.

◆ ECC_ECC_VERSION_REG_ECC_HVN_Msk

#define ECC_ECC_VERSION_REG_ECC_HVN_Msk   (0xff00UL)

ECC ECC_VERSION_REG: ECC_HVN (Bitfield-Mask: 0xff)

Definition at line 5596 of file DA14680BA.h.

◆ ECC_ECC_VERSION_REG_ECC_HVN_Pos

#define ECC_ECC_VERSION_REG_ECC_HVN_Pos   (8UL)

ECC ECC_VERSION_REG: ECC_HVN (Bit 8)

Definition at line 5595 of file DA14680BA.h.

◆ ECC_ECC_VERSION_REG_ECC_SVN_Msk

#define ECC_ECC_VERSION_REG_ECC_SVN_Msk   (0xffUL)

ECC ECC_VERSION_REG: ECC_SVN (Bitfield-Mask: 0xff)

Definition at line 5594 of file DA14680BA.h.

◆ ECC_ECC_VERSION_REG_ECC_SVN_Pos

#define ECC_ECC_VERSION_REG_ECC_SVN_Pos   (0UL)

ECC ECC_VERSION_REG: ECC_SVN (Bit 0)

Definition at line 5593 of file DA14680BA.h.

◆ FTDF

#define FTDF   ((FTDF_Type *) FTDF_BASE)

Definition at line 12086 of file DA14680BA.h.

◆ FTDF_BASE

#define FTDF_BASE   0x40080000UL

Definition at line 12041 of file DA14680BA.h.

◆ FTDF_FTDF_BUILDTIME_0_REG_BUILDTIME_Msk

#define FTDF_FTDF_BUILDTIME_0_REG_BUILDTIME_Msk   (0xffffffffUL)

FTDF FTDF_BUILDTIME_0_REG: BUILDTIME (Bitfield-Mask: 0xffffffff)

Definition at line 5998 of file DA14680BA.h.

◆ FTDF_FTDF_BUILDTIME_0_REG_BUILDTIME_Pos

#define FTDF_FTDF_BUILDTIME_0_REG_BUILDTIME_Pos   (0UL)

FTDF FTDF_BUILDTIME_0_REG: BUILDTIME (Bit 0)

Definition at line 5997 of file DA14680BA.h.

◆ FTDF_FTDF_BUILDTIME_1_REG_BUILDTIME_Msk

#define FTDF_FTDF_BUILDTIME_1_REG_BUILDTIME_Msk   (0xffffffffUL)

FTDF FTDF_BUILDTIME_1_REG: BUILDTIME (Bitfield-Mask: 0xffffffff)

Definition at line 6002 of file DA14680BA.h.

◆ FTDF_FTDF_BUILDTIME_1_REG_BUILDTIME_Pos

#define FTDF_FTDF_BUILDTIME_1_REG_BUILDTIME_Pos   (0UL)

FTDF FTDF_BUILDTIME_1_REG: BUILDTIME (Bit 0)

Definition at line 6001 of file DA14680BA.h.

◆ FTDF_FTDF_BUILDTIME_2_REG_BUILDTIME_Msk

#define FTDF_FTDF_BUILDTIME_2_REG_BUILDTIME_Msk   (0xffffffffUL)

FTDF FTDF_BUILDTIME_2_REG: BUILDTIME (Bitfield-Mask: 0xffffffff)

Definition at line 6006 of file DA14680BA.h.

◆ FTDF_FTDF_BUILDTIME_2_REG_BUILDTIME_Pos

#define FTDF_FTDF_BUILDTIME_2_REG_BUILDTIME_Pos   (0UL)

FTDF FTDF_BUILDTIME_2_REG: BUILDTIME (Bit 0)

Definition at line 6005 of file DA14680BA.h.

◆ FTDF_FTDF_BUILDTIME_3_REG_BUILDTIME_Msk

#define FTDF_FTDF_BUILDTIME_3_REG_BUILDTIME_Msk   (0xffffffffUL)

FTDF FTDF_BUILDTIME_3_REG: BUILDTIME (Bitfield-Mask: 0xffffffff)

Definition at line 6010 of file DA14680BA.h.

◆ FTDF_FTDF_BUILDTIME_3_REG_BUILDTIME_Pos

#define FTDF_FTDF_BUILDTIME_3_REG_BUILDTIME_Pos   (0UL)

FTDF FTDF_BUILDTIME_3_REG: BUILDTIME (Bit 0)

Definition at line 6009 of file DA14680BA.h.

◆ FTDF_FTDF_DEBUGCONTROL_REG_DBG_RX_INPUT_Msk

#define FTDF_FTDF_DEBUGCONTROL_REG_DBG_RX_INPUT_Msk   (0x100UL)

FTDF FTDF_DEBUGCONTROL_REG: DBG_RX_INPUT (Bitfield-Mask: 0x01)

Definition at line 6608 of file DA14680BA.h.

◆ FTDF_FTDF_DEBUGCONTROL_REG_DBG_RX_INPUT_Pos

#define FTDF_FTDF_DEBUGCONTROL_REG_DBG_RX_INPUT_Pos   (8UL)

FTDF FTDF_DEBUGCONTROL_REG: DBG_RX_INPUT (Bit 8)

Definition at line 6607 of file DA14680BA.h.

◆ FTDF_FTDF_EVENTCURRVAL_REG_EVENTCURRVAL_Msk

#define FTDF_FTDF_EVENTCURRVAL_REG_EVENTCURRVAL_Msk   (0x1ffffffUL)

FTDF FTDF_EVENTCURRVAL_REG: EVENTCURRVAL (Bitfield-Mask: 0x1ffffff)

Definition at line 6124 of file DA14680BA.h.

◆ FTDF_FTDF_EVENTCURRVAL_REG_EVENTCURRVAL_Pos

#define FTDF_FTDF_EVENTCURRVAL_REG_EVENTCURRVAL_Pos   (0UL)

FTDF FTDF_EVENTCURRVAL_REG: EVENTCURRVAL (Bit 0)

Definition at line 6123 of file DA14680BA.h.

◆ FTDF_FTDF_FTDF_CE_REG_FTDF_CE_Msk

#define FTDF_FTDF_FTDF_CE_REG_FTDF_CE_Msk   (0x3fUL)

FTDF FTDF_FTDF_CE_REG: FTDF_CE (Bitfield-Mask: 0x3f)

Definition at line 6528 of file DA14680BA.h.

◆ FTDF_FTDF_FTDF_CE_REG_FTDF_CE_Pos

#define FTDF_FTDF_FTDF_CE_REG_FTDF_CE_Pos   (0UL)

FTDF FTDF_FTDF_CE_REG: FTDF_CE (Bit 0)

Definition at line 6527 of file DA14680BA.h.

◆ FTDF_FTDF_FTDF_CM_REG_FTDF_CM_Msk

#define FTDF_FTDF_FTDF_CM_REG_FTDF_CM_Msk   (0x3fUL)

FTDF FTDF_FTDF_CM_REG: FTDF_CM (Bitfield-Mask: 0x3f)

Definition at line 6532 of file DA14680BA.h.

◆ FTDF_FTDF_FTDF_CM_REG_FTDF_CM_Pos

#define FTDF_FTDF_FTDF_CM_REG_FTDF_CM_Pos   (0UL)

FTDF FTDF_FTDF_CM_REG: FTDF_CM (Bit 0)

Definition at line 6531 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_0_REG_ISPANCOORDINATOR_Msk

#define FTDF_FTDF_GLOB_CONTROL_0_REG_ISPANCOORDINATOR_Msk   (0x2UL)

FTDF FTDF_GLOB_CONTROL_0_REG: ISPANCOORDINATOR (Bitfield-Mask: 0x01)

Definition at line 6014 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_0_REG_ISPANCOORDINATOR_Pos

#define FTDF_FTDF_GLOB_CONTROL_0_REG_ISPANCOORDINATOR_Pos   (1UL)

FTDF FTDF_GLOB_CONTROL_0_REG: ISPANCOORDINATOR (Bit 1)

Definition at line 6013 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_0_REG_MACLEENABLED_Msk

#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACLEENABLED_Msk   (0x20000UL)

FTDF FTDF_GLOB_CONTROL_0_REG: MACLEENABLED (Bitfield-Mask: 0x01)

Definition at line 6022 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_0_REG_MACLEENABLED_Pos

#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACLEENABLED_Pos   (17UL)

FTDF FTDF_GLOB_CONTROL_0_REG: MACLEENABLED (Bit 17)

Definition at line 6021 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_0_REG_MACSIMPLEADDRESS_Msk

#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACSIMPLEADDRESS_Msk   (0xff00UL)

FTDF FTDF_GLOB_CONTROL_0_REG: MACSIMPLEADDRESS (Bitfield-Mask: 0xff)

Definition at line 6020 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_0_REG_MACSIMPLEADDRESS_Pos

#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACSIMPLEADDRESS_Pos   (8UL)

FTDF FTDF_GLOB_CONTROL_0_REG: MACSIMPLEADDRESS (Bit 8)

Definition at line 6019 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_0_REG_MACTSCHENABLED_Msk

#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACTSCHENABLED_Msk   (0x40000UL)

FTDF FTDF_GLOB_CONTROL_0_REG: MACTSCHENABLED (Bitfield-Mask: 0x01)

Definition at line 6024 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_0_REG_MACTSCHENABLED_Pos

#define FTDF_FTDF_GLOB_CONTROL_0_REG_MACTSCHENABLED_Pos   (18UL)

FTDF FTDF_GLOB_CONTROL_0_REG: MACTSCHENABLED (Bit 18)

Definition at line 6023 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_0_REG_RX_DMA_REQ_Msk

#define FTDF_FTDF_GLOB_CONTROL_0_REG_RX_DMA_REQ_Msk   (0x4UL)

FTDF FTDF_GLOB_CONTROL_0_REG: RX_DMA_REQ (Bitfield-Mask: 0x01)

Definition at line 6016 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_0_REG_RX_DMA_REQ_Pos

#define FTDF_FTDF_GLOB_CONTROL_0_REG_RX_DMA_REQ_Pos   (2UL)

FTDF FTDF_GLOB_CONTROL_0_REG: RX_DMA_REQ (Bit 2)

Definition at line 6015 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_0_REG_TX_DMA_REQ_Msk

#define FTDF_FTDF_GLOB_CONTROL_0_REG_TX_DMA_REQ_Msk   (0x8UL)

FTDF FTDF_GLOB_CONTROL_0_REG: TX_DMA_REQ (Bitfield-Mask: 0x01)

Definition at line 6018 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_0_REG_TX_DMA_REQ_Pos

#define FTDF_FTDF_GLOB_CONTROL_0_REG_TX_DMA_REQ_Pos   (3UL)

FTDF FTDF_GLOB_CONTROL_0_REG: TX_DMA_REQ (Bit 3)

Definition at line 6017 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_1_REG_MACPANID_Msk

#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACPANID_Msk   (0xffffUL)

FTDF FTDF_GLOB_CONTROL_1_REG: MACPANID (Bitfield-Mask: 0xffff)

Definition at line 6028 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_1_REG_MACPANID_Pos

#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACPANID_Pos   (0UL)

FTDF FTDF_GLOB_CONTROL_1_REG: MACPANID (Bit 0)

Definition at line 6027 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_1_REG_MACSHORTADDRESS_Msk

#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACSHORTADDRESS_Msk   (0xffff0000UL)

FTDF FTDF_GLOB_CONTROL_1_REG: MACSHORTADDRESS (Bitfield-Mask: 0xffff)

Definition at line 6030 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_1_REG_MACSHORTADDRESS_Pos

#define FTDF_FTDF_GLOB_CONTROL_1_REG_MACSHORTADDRESS_Pos   (16UL)

FTDF FTDF_GLOB_CONTROL_1_REG: MACSHORTADDRESS (Bit 16)

Definition at line 6029 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_2_REG_AEXTENDEDADDRESS_L_Msk

#define FTDF_FTDF_GLOB_CONTROL_2_REG_AEXTENDEDADDRESS_L_Msk   (0xffffffffUL)

FTDF FTDF_GLOB_CONTROL_2_REG: AEXTENDEDADDRESS_L (Bitfield-Mask: 0xffffffff)

Definition at line 6034 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_2_REG_AEXTENDEDADDRESS_L_Pos

#define FTDF_FTDF_GLOB_CONTROL_2_REG_AEXTENDEDADDRESS_L_Pos   (0UL)

FTDF FTDF_GLOB_CONTROL_2_REG: AEXTENDEDADDRESS_L (Bit 0)

Definition at line 6033 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_3_REG_AEXTENDEDADDRESS_H_Msk

#define FTDF_FTDF_GLOB_CONTROL_3_REG_AEXTENDEDADDRESS_H_Msk   (0xffffffffUL)

FTDF FTDF_GLOB_CONTROL_3_REG: AEXTENDEDADDRESS_H (Bitfield-Mask: 0xffffffff)

Definition at line 6038 of file DA14680BA.h.

◆ FTDF_FTDF_GLOB_CONTROL_3_REG_AEXTENDEDADDRESS_H_Pos

#define FTDF_FTDF_GLOB_CONTROL_3_REG_AEXTENDEDADDRESS_H_Pos   (0UL)

FTDF FTDF_GLOB_CONTROL_3_REG: AEXTENDEDADDRESS_H (Bit 0)

Definition at line 6037 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_0_REG_KEEP_PHY_EN_Msk

#define FTDF_FTDF_LMAC_CONTROL_0_REG_KEEP_PHY_EN_Msk   (0x80000000UL)

FTDF FTDF_LMAC_CONTROL_0_REG: KEEP_PHY_EN (Bitfield-Mask: 0x01)

Definition at line 6048 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_0_REG_KEEP_PHY_EN_Pos

#define FTDF_FTDF_LMAC_CONTROL_0_REG_KEEP_PHY_EN_Pos   (31UL)

FTDF FTDF_LMAC_CONTROL_0_REG: KEEP_PHY_EN (Bit 31)

Definition at line 6047 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_RX_Msk

#define FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_RX_Msk   (0x78000000UL)

FTDF FTDF_LMAC_CONTROL_0_REG: PTI_RX (Bitfield-Mask: 0x0f)

Definition at line 6046 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_RX_Pos

#define FTDF_FTDF_LMAC_CONTROL_0_REG_PTI_RX_Pos   (27UL)

FTDF FTDF_LMAC_CONTROL_0_REG: PTI_RX (Bit 27)

Definition at line 6045 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_0_REG_RXALWAYSON_Msk

#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXALWAYSON_Msk   (0x2000000UL)

FTDF FTDF_LMAC_CONTROL_0_REG: RXALWAYSON (Bitfield-Mask: 0x01)

Definition at line 6044 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_0_REG_RXALWAYSON_Pos

#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXALWAYSON_Pos   (25UL)

FTDF FTDF_LMAC_CONTROL_0_REG: RXALWAYSON (Bit 25)

Definition at line 6043 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_0_REG_RXONDURATION_Msk

#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXONDURATION_Msk   (0x1fffffeUL)

FTDF FTDF_LMAC_CONTROL_0_REG: RXONDURATION (Bitfield-Mask: 0xffffff)

Definition at line 6042 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_0_REG_RXONDURATION_Pos

#define FTDF_FTDF_LMAC_CONTROL_0_REG_RXONDURATION_Pos   (1UL)

FTDF FTDF_LMAC_CONTROL_0_REG: RXONDURATION (Bit 1)

Definition at line 6041 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_10_REG_MACCSLMARGINRZ_Msk

#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACCSLMARGINRZ_Msk   (0xf0000UL)

FTDF FTDF_LMAC_CONTROL_10_REG: MACCSLMARGINRZ (Bitfield-Mask: 0x0f)

Definition at line 6294 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_10_REG_MACCSLMARGINRZ_Pos

#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACCSLMARGINRZ_Pos   (16UL)

FTDF FTDF_LMAC_CONTROL_10_REG: MACCSLMARGINRZ (Bit 16)

Definition at line 6293 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_10_REG_MACRZZEROVAL_Msk

#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACRZZEROVAL_Msk   (0xf0000000UL)

FTDF FTDF_LMAC_CONTROL_10_REG: MACRZZEROVAL (Bitfield-Mask: 0x0f)

Definition at line 6296 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_10_REG_MACRZZEROVAL_Pos

#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACRZZEROVAL_Pos   (28UL)

FTDF FTDF_LMAC_CONTROL_10_REG: MACRZZEROVAL (Bit 28)

Definition at line 6295 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_10_REG_MACWURZCORRECTION_Msk

#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACWURZCORRECTION_Msk   (0xffUL)

FTDF FTDF_LMAC_CONTROL_10_REG: MACWURZCORRECTION (Bitfield-Mask: 0xff)

Definition at line 6292 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_10_REG_MACWURZCORRECTION_Pos

#define FTDF_FTDF_LMAC_CONTROL_10_REG_MACWURZCORRECTION_Pos   (0UL)

FTDF FTDF_LMAC_CONTROL_10_REG: MACWURZCORRECTION (Bit 0)

Definition at line 6291 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_BO_THRESHOLD_Msk

#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_BO_THRESHOLD_Msk   (0xff000000UL)

FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_BO_THRESHOLD (Bitfield-Mask: 0xff)

Definition at line 6178 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_BO_THRESHOLD_Pos

#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_BO_THRESHOLD_Pos   (24UL)

FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_BO_THRESHOLD (Bit 24)

Definition at line 6177 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_NB_VAL_Msk

#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_NB_VAL_Msk   (0xe0000UL)

FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_NB_VAL (Bitfield-Mask: 0x07)

Definition at line 6176 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_NB_VAL_Pos

#define FTDF_FTDF_LMAC_CONTROL_11_REG_CSMA_CA_NB_VAL_Pos   (17UL)

FTDF FTDF_LMAC_CONTROL_11_REG: CSMA_CA_NB_VAL (Bit 17)

Definition at line 6175 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_11_REG_MACDISCARXOFFTORZ_Msk

#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACDISCARXOFFTORZ_Msk   (0x10000UL)

FTDF FTDF_LMAC_CONTROL_11_REG: MACDISCARXOFFTORZ (Bitfield-Mask: 0x01)

Definition at line 6174 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_11_REG_MACDISCARXOFFTORZ_Pos

#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACDISCARXOFFTORZ_Pos   (16UL)

FTDF FTDF_LMAC_CONTROL_11_REG: MACDISCARXOFFTORZ (Bit 16)

Definition at line 6173 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_11_REG_MACRXTOTALCYCLETIME_Msk

#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACRXTOTALCYCLETIME_Msk   (0xffffUL)

FTDF FTDF_LMAC_CONTROL_11_REG: MACRXTOTALCYCLETIME (Bitfield-Mask: 0xffff)

Definition at line 6172 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_11_REG_MACRXTOTALCYCLETIME_Pos

#define FTDF_FTDF_LMAC_CONTROL_11_REG_MACRXTOTALCYCLETIME_Pos   (0UL)

FTDF FTDF_LMAC_CONTROL_11_REG: MACRXTOTALCYCLETIME (Bit 0)

Definition at line 6171 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CALCAP_Msk

#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CALCAP_Msk   (0xf00UL)

FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_CALCAP (Bitfield-Mask: 0x0f)

Definition at line 6068 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CALCAP_Pos

#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CALCAP_Pos   (8UL)

FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_CALCAP (Bit 8)

Definition at line 6067 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CN_Msk

#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CN_Msk   (0xf0UL)

FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_CN (Bitfield-Mask: 0x0f)

Definition at line 6066 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CN_Pos

#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_CN_Pos   (4UL)

FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_CN (Bit 4)

Definition at line 6065 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_DEM_PTI_Msk

#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_DEM_PTI_Msk   (0xfUL)

FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_DEM_PTI (Bitfield-Mask: 0x0f)

Definition at line 6064 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_DEM_PTI_Pos

#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_DEM_PTI_Pos   (0UL)

FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_DEM_PTI (Bit 0)

Definition at line 6063 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_HSI_Msk

#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_HSI_Msk   (0x8000UL)

FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_HSI (Bitfield-Mask: 0x01)

Definition at line 6072 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_HSI_Pos

#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_HSI_Pos   (15UL)

FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_HSI (Bit 15)

Definition at line 6071 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_RF_GPIO_PINS_Msk

#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_RF_GPIO_PINS_Msk   (0x7000UL)

FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07)

Definition at line 6070 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_RF_GPIO_PINS_Pos

#define FTDF_FTDF_LMAC_CONTROL_1_REG_PHYRXATTR_RF_GPIO_PINS_Pos   (12UL)

FTDF FTDF_LMAC_CONTROL_1_REG: PHYRXATTR_RF_GPIO_PINS (Bit 12)

Definition at line 6069 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANDURATION_Msk

#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANDURATION_Msk   (0xffffff00UL)

FTDF FTDF_LMAC_CONTROL_2_REG: EDSCANDURATION (Bitfield-Mask: 0xffffff)

Definition at line 6078 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANDURATION_Pos

#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANDURATION_Pos   (8UL)

FTDF FTDF_LMAC_CONTROL_2_REG: EDSCANDURATION (Bit 8)

Definition at line 6077 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANENABLE_Msk

#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANENABLE_Msk   (0x1UL)

FTDF FTDF_LMAC_CONTROL_2_REG: EDSCANENABLE (Bitfield-Mask: 0x01)

Definition at line 6076 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANENABLE_Pos

#define FTDF_FTDF_LMAC_CONTROL_2_REG_EDSCANENABLE_Pos   (0UL)

FTDF FTDF_LMAC_CONTROL_2_REG: EDSCANENABLE (Bit 0)

Definition at line 6075 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_3_REG_ADDR_TAB_MATCH_FP_VALUE_Msk

#define FTDF_FTDF_LMAC_CONTROL_3_REG_ADDR_TAB_MATCH_FP_VALUE_Msk   (0x1000000UL)

FTDF FTDF_LMAC_CONTROL_3_REG: ADDR_TAB_MATCH_FP_VALUE (Bitfield-Mask: 0x01)

Definition at line 6086 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_3_REG_ADDR_TAB_MATCH_FP_VALUE_Pos

#define FTDF_FTDF_LMAC_CONTROL_3_REG_ADDR_TAB_MATCH_FP_VALUE_Pos   (24UL)

FTDF FTDF_LMAC_CONTROL_3_REG: ADDR_TAB_MATCH_FP_VALUE (Bit 24)

Definition at line 6085 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_3_REG_CCAIDLEWAIT_Msk

#define FTDF_FTDF_LMAC_CONTROL_3_REG_CCAIDLEWAIT_Msk   (0xff0000UL)

FTDF FTDF_LMAC_CONTROL_3_REG: CCAIDLEWAIT (Bitfield-Mask: 0xff)

Definition at line 6084 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_3_REG_CCAIDLEWAIT_Pos

#define FTDF_FTDF_LMAC_CONTROL_3_REG_CCAIDLEWAIT_Pos   (16UL)

FTDF FTDF_LMAC_CONTROL_3_REG: CCAIDLEWAIT (Bit 16)

Definition at line 6083 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_3_REG_FP_FORCE_VALUE_Msk

#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_FORCE_VALUE_Msk   (0x4000000UL)

FTDF FTDF_LMAC_CONTROL_3_REG: FP_FORCE_VALUE (Bitfield-Mask: 0x01)

Definition at line 6090 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_3_REG_FP_FORCE_VALUE_Pos

#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_FORCE_VALUE_Pos   (26UL)

FTDF FTDF_LMAC_CONTROL_3_REG: FP_FORCE_VALUE (Bit 26)

Definition at line 6089 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_3_REG_FP_OVERRIDE_Msk

#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_OVERRIDE_Msk   (0x2000000UL)

FTDF FTDF_LMAC_CONTROL_3_REG: FP_OVERRIDE (Bitfield-Mask: 0x01)

Definition at line 6088 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_3_REG_FP_OVERRIDE_Pos

#define FTDF_FTDF_LMAC_CONTROL_3_REG_FP_OVERRIDE_Pos   (25UL)

FTDF FTDF_LMAC_CONTROL_3_REG: FP_OVERRIDE (Bit 25)

Definition at line 6087 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_3_REG_FTDF_LPDP_ENABLE_Msk

#define FTDF_FTDF_LMAC_CONTROL_3_REG_FTDF_LPDP_ENABLE_Msk   (0x8000000UL)

FTDF FTDF_LMAC_CONTROL_3_REG: FTDF_LPDP_ENABLE (Bitfield-Mask: 0x01)

Definition at line 6092 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_3_REG_FTDF_LPDP_ENABLE_Pos

#define FTDF_FTDF_LMAC_CONTROL_3_REG_FTDF_LPDP_ENABLE_Pos   (27UL)

FTDF FTDF_LMAC_CONTROL_3_REG: FTDF_LPDP_ENABLE (Bit 27)

Definition at line 6091 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_3_REG_MACMAXFRAMETOTALWAITTIME_Msk

#define FTDF_FTDF_LMAC_CONTROL_3_REG_MACMAXFRAMETOTALWAITTIME_Msk   (0xffffUL)

FTDF FTDF_LMAC_CONTROL_3_REG: MACMAXFRAMETOTALWAITTIME (Bitfield-Mask: 0xffff)

Definition at line 6082 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_3_REG_MACMAXFRAMETOTALWAITTIME_Pos

#define FTDF_FTDF_LMAC_CONTROL_3_REG_MACMAXFRAMETOTALWAITTIME_Pos   (0UL)

FTDF FTDF_LMAC_CONTROL_3_REG: MACMAXFRAMETOTALWAITTIME (Bit 0)

Definition at line 6081 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CALCAP_Msk

#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CALCAP_Msk   (0xf000000UL)

FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_CALCAP (Bitfield-Mask: 0x0f)

Definition at line 6140 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CALCAP_Pos

#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CALCAP_Pos   (24UL)

FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_CALCAP (Bit 24)

Definition at line 6139 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CN_Msk

#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CN_Msk   (0xf00000UL)

FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_CN (Bitfield-Mask: 0x0f)

Definition at line 6138 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CN_Pos

#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_CN_Pos   (20UL)

FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_CN (Bit 20)

Definition at line 6137 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_DEM_PTI_Msk

#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_DEM_PTI_Msk   (0xf0000UL)

FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_DEM_PTI (Bitfield-Mask: 0x0f)

Definition at line 6136 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_DEM_PTI_Pos

#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_DEM_PTI_Pos   (16UL)

FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_DEM_PTI (Bit 16)

Definition at line 6135 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_HSI_Msk

#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_HSI_Msk   (0x80000000UL)

FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_HSI (Bitfield-Mask: 0x01)

Definition at line 6144 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_HSI_Pos

#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_HSI_Pos   (31UL)

FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_HSI (Bit 31)

Definition at line 6143 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_RF_GPIO_PINS_Msk

#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_RF_GPIO_PINS_Msk   (0x70000000UL)

FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07)

Definition at line 6142 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_RF_GPIO_PINS_Pos

#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYACKATTR_RF_GPIO_PINS_Pos   (28UL)

FTDF FTDF_LMAC_CONTROL_4_REG: PHYACKATTR_RF_GPIO_PINS (Bit 28)

Definition at line 6141 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_PHYSLEEPWAIT_Msk

#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYSLEEPWAIT_Msk   (0xffUL)

FTDF FTDF_LMAC_CONTROL_4_REG: PHYSLEEPWAIT (Bitfield-Mask: 0xff)

Definition at line 6132 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_PHYSLEEPWAIT_Pos

#define FTDF_FTDF_LMAC_CONTROL_4_REG_PHYSLEEPWAIT_Pos   (0UL)

FTDF FTDF_LMAC_CONTROL_4_REG: PHYSLEEPWAIT (Bit 0)

Definition at line 6131 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_RXPIPEPROPDELAY_Msk

#define FTDF_FTDF_LMAC_CONTROL_4_REG_RXPIPEPROPDELAY_Msk   (0xff00UL)

FTDF FTDF_LMAC_CONTROL_4_REG: RXPIPEPROPDELAY (Bitfield-Mask: 0xff)

Definition at line 6134 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_4_REG_RXPIPEPROPDELAY_Pos

#define FTDF_FTDF_LMAC_CONTROL_4_REG_RXPIPEPROPDELAY_Pos   (8UL)

FTDF FTDF_LMAC_CONTROL_4_REG: RXPIPEPROPDELAY (Bit 8)

Definition at line 6133 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_ACK_RESPONSE_DELAY_Msk

#define FTDF_FTDF_LMAC_CONTROL_5_REG_ACK_RESPONSE_DELAY_Msk   (0xffUL)

FTDF FTDF_LMAC_CONTROL_5_REG: ACK_RESPONSE_DELAY (Bitfield-Mask: 0xff)

Definition at line 6148 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_ACK_RESPONSE_DELAY_Pos

#define FTDF_FTDF_LMAC_CONTROL_5_REG_ACK_RESPONSE_DELAY_Pos   (0UL)

FTDF FTDF_LMAC_CONTROL_5_REG: ACK_RESPONSE_DELAY (Bit 0)

Definition at line 6147 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_CCASTATWAIT_Msk

#define FTDF_FTDF_LMAC_CONTROL_5_REG_CCASTATWAIT_Msk   (0xf00UL)

FTDF FTDF_LMAC_CONTROL_5_REG: CCASTATWAIT (Bitfield-Mask: 0x0f)

Definition at line 6150 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_CCASTATWAIT_Pos

#define FTDF_FTDF_LMAC_CONTROL_5_REG_CCASTATWAIT_Pos   (8UL)

FTDF FTDF_LMAC_CONTROL_5_REG: CCASTATWAIT (Bit 8)

Definition at line 6149 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CALCAP_Msk

#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CALCAP_Msk   (0xf000000UL)

FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_CALCAP (Bitfield-Mask: 0x0f)

Definition at line 6156 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CALCAP_Pos

#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CALCAP_Pos   (24UL)

FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_CALCAP (Bit 24)

Definition at line 6155 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CN_Msk

#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CN_Msk   (0xf00000UL)

FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_CN (Bitfield-Mask: 0x0f)

Definition at line 6154 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CN_Pos

#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_CN_Pos   (20UL)

FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_CN (Bit 20)

Definition at line 6153 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_DEM_PTI_Msk

#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_DEM_PTI_Msk   (0xf0000UL)

FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_DEM_PTI (Bitfield-Mask: 0x0f)

Definition at line 6152 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_DEM_PTI_Pos

#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_DEM_PTI_Pos   (16UL)

FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_DEM_PTI (Bit 16)

Definition at line 6151 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_HSI_Msk

#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_HSI_Msk   (0x80000000UL)

FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_HSI (Bitfield-Mask: 0x01)

Definition at line 6160 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_HSI_Pos

#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_HSI_Pos   (31UL)

FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_HSI (Bit 31)

Definition at line 6159 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_RF_GPIO_PINS_Msk

#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_RF_GPIO_PINS_Msk   (0x70000000UL)

FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07)

Definition at line 6158 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_RF_GPIO_PINS_Pos

#define FTDF_FTDF_LMAC_CONTROL_5_REG_PHYCSMACAATTR_RF_GPIO_PINS_Pos   (28UL)

FTDF FTDF_LMAC_CONTROL_5_REG: PHYCSMACAATTR_RF_GPIO_PINS (Bit 28)

Definition at line 6157 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_6_REG_LIFSPERIOD_Msk

#define FTDF_FTDF_LMAC_CONTROL_6_REG_LIFSPERIOD_Msk   (0xffUL)

FTDF FTDF_LMAC_CONTROL_6_REG: LIFSPERIOD (Bitfield-Mask: 0xff)

Definition at line 6164 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_6_REG_LIFSPERIOD_Pos

#define FTDF_FTDF_LMAC_CONTROL_6_REG_LIFSPERIOD_Pos   (0UL)

FTDF FTDF_LMAC_CONTROL_6_REG: LIFSPERIOD (Bit 0)

Definition at line 6163 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_6_REG_SIFSPERIOD_Msk

#define FTDF_FTDF_LMAC_CONTROL_6_REG_SIFSPERIOD_Msk   (0xff00UL)

FTDF FTDF_LMAC_CONTROL_6_REG: SIFSPERIOD (Bitfield-Mask: 0xff)

Definition at line 6166 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_6_REG_SIFSPERIOD_Pos

#define FTDF_FTDF_LMAC_CONTROL_6_REG_SIFSPERIOD_Pos   (8UL)

FTDF FTDF_LMAC_CONTROL_6_REG: SIFSPERIOD (Bit 8)

Definition at line 6165 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_6_REG_WUIFSPERIOD_Msk

#define FTDF_FTDF_LMAC_CONTROL_6_REG_WUIFSPERIOD_Msk   (0xff0000UL)

FTDF FTDF_LMAC_CONTROL_6_REG: WUIFSPERIOD (Bitfield-Mask: 0xff)

Definition at line 6168 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_6_REG_WUIFSPERIOD_Pos

#define FTDF_FTDF_LMAC_CONTROL_6_REG_WUIFSPERIOD_Pos   (16UL)

FTDF FTDF_LMAC_CONTROL_6_REG: WUIFSPERIOD (Bit 16)

Definition at line 6167 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_7_REG_MACCSLSAMPLEPERIOD_Msk

#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACCSLSAMPLEPERIOD_Msk   (0xffff0000UL)

FTDF FTDF_LMAC_CONTROL_7_REG: MACCSLSAMPLEPERIOD (Bitfield-Mask: 0xffff)

Definition at line 6278 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_7_REG_MACCSLSAMPLEPERIOD_Pos

#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACCSLSAMPLEPERIOD_Pos   (16UL)

FTDF FTDF_LMAC_CONTROL_7_REG: MACCSLSAMPLEPERIOD (Bit 16)

Definition at line 6277 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_7_REG_MACWUPERIOD_Msk

#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACWUPERIOD_Msk   (0xffffUL)

FTDF FTDF_LMAC_CONTROL_7_REG: MACWUPERIOD (Bitfield-Mask: 0xffff)

Definition at line 6276 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_7_REG_MACWUPERIOD_Pos

#define FTDF_FTDF_LMAC_CONTROL_7_REG_MACWUPERIOD_Pos   (0UL)

FTDF FTDF_LMAC_CONTROL_7_REG: MACWUPERIOD (Bit 0)

Definition at line 6275 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_8_REG_MACCSLSTARTSAMPLETIME_Msk

#define FTDF_FTDF_LMAC_CONTROL_8_REG_MACCSLSTARTSAMPLETIME_Msk   (0xffffffffUL)

FTDF FTDF_LMAC_CONTROL_8_REG: MACCSLSTARTSAMPLETIME (Bitfield-Mask: 0xffffffff)

Definition at line 6282 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_8_REG_MACCSLSTARTSAMPLETIME_Pos

#define FTDF_FTDF_LMAC_CONTROL_8_REG_MACCSLSTARTSAMPLETIME_Pos   (0UL)

FTDF FTDF_LMAC_CONTROL_8_REG: MACCSLSTARTSAMPLETIME (Bit 0)

Definition at line 6281 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLDATAPERIOD_Msk

#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLDATAPERIOD_Msk   (0xffffUL)

FTDF FTDF_LMAC_CONTROL_9_REG: MACCSLDATAPERIOD (Bitfield-Mask: 0xffff)

Definition at line 6286 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLDATAPERIOD_Pos

#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLDATAPERIOD_Pos   (0UL)

FTDF FTDF_LMAC_CONTROL_9_REG: MACCSLDATAPERIOD (Bit 0)

Definition at line 6285 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLFRAMEPENDINGWAITT_Msk

#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLFRAMEPENDINGWAITT_Msk   (0xffff0000UL)

FTDF FTDF_LMAC_CONTROL_9_REG: MACCSLFRAMEPENDINGWAITT (Bitfield-Mask: 0xffff)

Definition at line 6288 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLFRAMEPENDINGWAITT_Pos

#define FTDF_FTDF_LMAC_CONTROL_9_REG_MACCSLFRAMEPENDINGWAITT_Pos   (16UL)

FTDF FTDF_LMAC_CONTROL_9_REG: MACCSLFRAMEPENDINGWAITT (Bit 16)

Definition at line 6287 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_DELTA_REG_GETGENERATORVAL_E_Msk

#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_GETGENERATORVAL_E_Msk   (0x20UL)

FTDF FTDF_LMAC_CONTROL_DELTA_REG: GETGENERATORVAL_E (Bitfield-Mask: 0x01)

Definition at line 6190 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_DELTA_REG_GETGENERATORVAL_E_Pos

#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_GETGENERATORVAL_E_Pos   (5UL)

FTDF FTDF_LMAC_CONTROL_DELTA_REG: GETGENERATORVAL_E (Bit 5)

Definition at line 6189 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_DELTA_REG_LMACREADY4SLEEP_D_Msk

#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_LMACREADY4SLEEP_D_Msk   (0x2UL)

FTDF FTDF_LMAC_CONTROL_DELTA_REG: LMACREADY4SLEEP_D (Bitfield-Mask: 0x01)

Definition at line 6182 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_DELTA_REG_LMACREADY4SLEEP_D_Pos

#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_LMACREADY4SLEEP_D_Pos   (1UL)

FTDF FTDF_LMAC_CONTROL_DELTA_REG: LMACREADY4SLEEP_D (Bit 1)

Definition at line 6181 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIME2THR_E_Msk

#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIME2THR_E_Msk   (0x10UL)

FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYMBOLTIME2THR_E (Bitfield-Mask: 0x01)

Definition at line 6188 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIME2THR_E_Pos

#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIME2THR_E_Pos   (4UL)

FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYMBOLTIME2THR_E (Bit 4)

Definition at line 6187 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIMETHR_E_Msk

#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIMETHR_E_Msk   (0x8UL)

FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYMBOLTIMETHR_E (Bitfield-Mask: 0x01)

Definition at line 6186 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIMETHR_E_Pos

#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYMBOLTIMETHR_E_Pos   (3UL)

FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYMBOLTIMETHR_E (Bit 3)

Definition at line 6185 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYNCTIMESTAMP_E_Msk

#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYNCTIMESTAMP_E_Msk   (0x4UL)

FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYNCTIMESTAMP_E (Bitfield-Mask: 0x01)

Definition at line 6184 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYNCTIMESTAMP_E_Pos

#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_SYNCTIMESTAMP_E_Pos   (2UL)

FTDF FTDF_LMAC_CONTROL_DELTA_REG: SYNCTIMESTAMP_E (Bit 2)

Definition at line 6183 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_DELTA_REG_WAKEUPTIMERENABLESTATUS_D_Msk

#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_WAKEUPTIMERENABLESTATUS_D_Msk   (0x40UL)

FTDF FTDF_LMAC_CONTROL_DELTA_REG: WAKEUPTIMERENABLESTATUS_D (Bitfield-Mask: 0x01)

Definition at line 6192 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_DELTA_REG_WAKEUPTIMERENABLESTATUS_D_Pos

#define FTDF_FTDF_LMAC_CONTROL_DELTA_REG_WAKEUPTIMERENABLESTATUS_D_Pos   (6UL)

FTDF FTDF_LMAC_CONTROL_DELTA_REG: WAKEUPTIMERENABLESTATUS_D (Bit 6)

Definition at line 6191 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_MASK_REG_GETGENERATORVAL_M_Msk

#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_GETGENERATORVAL_M_Msk   (0x20UL)

FTDF FTDF_LMAC_CONTROL_MASK_REG: GETGENERATORVAL_M (Bitfield-Mask: 0x01)

Definition at line 6212 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_MASK_REG_GETGENERATORVAL_M_Pos

#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_GETGENERATORVAL_M_Pos   (5UL)

FTDF FTDF_LMAC_CONTROL_MASK_REG: GETGENERATORVAL_M (Bit 5)

Definition at line 6211 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_MASK_REG_LMACREADY4SLEEP_M_Msk

#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_LMACREADY4SLEEP_M_Msk   (0x2UL)

FTDF FTDF_LMAC_CONTROL_MASK_REG: LMACREADY4SLEEP_M (Bitfield-Mask: 0x01)

Definition at line 6204 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_MASK_REG_LMACREADY4SLEEP_M_Pos

#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_LMACREADY4SLEEP_M_Pos   (1UL)

FTDF FTDF_LMAC_CONTROL_MASK_REG: LMACREADY4SLEEP_M (Bit 1)

Definition at line 6203 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIME2THR_M_Msk

#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIME2THR_M_Msk   (0x10UL)

FTDF FTDF_LMAC_CONTROL_MASK_REG: SYMBOLTIME2THR_M (Bitfield-Mask: 0x01)

Definition at line 6210 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIME2THR_M_Pos

#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIME2THR_M_Pos   (4UL)

FTDF FTDF_LMAC_CONTROL_MASK_REG: SYMBOLTIME2THR_M (Bit 4)

Definition at line 6209 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIMETHR_M_Msk

#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIMETHR_M_Msk   (0x8UL)

FTDF FTDF_LMAC_CONTROL_MASK_REG: SYMBOLTIMETHR_M (Bitfield-Mask: 0x01)

Definition at line 6208 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIMETHR_M_Pos

#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYMBOLTIMETHR_M_Pos   (3UL)

FTDF FTDF_LMAC_CONTROL_MASK_REG: SYMBOLTIMETHR_M (Bit 3)

Definition at line 6207 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYNCTIMESTAMP_M_Msk

#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYNCTIMESTAMP_M_Msk   (0x4UL)

FTDF FTDF_LMAC_CONTROL_MASK_REG: SYNCTIMESTAMP_M (Bitfield-Mask: 0x01)

Definition at line 6206 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYNCTIMESTAMP_M_Pos

#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_SYNCTIMESTAMP_M_Pos   (2UL)

FTDF FTDF_LMAC_CONTROL_MASK_REG: SYNCTIMESTAMP_M (Bit 2)

Definition at line 6205 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_MASK_REG_WAKEUPTIMERENABLESTATUS_M_Msk

#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_WAKEUPTIMERENABLESTATUS_M_Msk   (0x40UL)

FTDF FTDF_LMAC_CONTROL_MASK_REG: WAKEUPTIMERENABLESTATUS_M (Bitfield-Mask: 0x01)

Definition at line 6214 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_MASK_REG_WAKEUPTIMERENABLESTATUS_M_Pos

#define FTDF_FTDF_LMAC_CONTROL_MASK_REG_WAKEUPTIMERENABLESTATUS_M_Pos   (6UL)

FTDF FTDF_LMAC_CONTROL_MASK_REG: WAKEUPTIMERENABLESTATUS_M (Bit 6)

Definition at line 6213 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_CLEAR_Msk

#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_CLEAR_Msk   (0x10UL)

FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_CLEAR (Bitfield-Mask: 0x01)

Definition at line 6104 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_CLEAR_Pos

#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_CLEAR_Pos   (4UL)

FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_CLEAR (Bit 4)

Definition at line 6103 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_SET_Msk

#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_SET_Msk   (0x8UL)

FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_SET (Bitfield-Mask: 0x01)

Definition at line 6102 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_SET_Pos

#define FTDF_FTDF_LMAC_CONTROL_OS_REG_CSMA_CA_RESUME_SET_Pos   (3UL)

FTDF FTDF_LMAC_CONTROL_OS_REG: CSMA_CA_RESUME_SET (Bit 3)

Definition at line 6101 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_OS_REG_GETGENERATORVAL_Msk

#define FTDF_FTDF_LMAC_CONTROL_OS_REG_GETGENERATORVAL_Msk   (0x1UL)

FTDF FTDF_LMAC_CONTROL_OS_REG: GETGENERATORVAL (Bitfield-Mask: 0x01)

Definition at line 6096 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_OS_REG_GETGENERATORVAL_Pos

#define FTDF_FTDF_LMAC_CONTROL_OS_REG_GETGENERATORVAL_Pos   (0UL)

FTDF FTDF_LMAC_CONTROL_OS_REG: GETGENERATORVAL (Bit 0)

Definition at line 6095 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_OS_REG_RXENABLE_Msk

#define FTDF_FTDF_LMAC_CONTROL_OS_REG_RXENABLE_Msk   (0x2UL)

FTDF FTDF_LMAC_CONTROL_OS_REG: RXENABLE (Bitfield-Mask: 0x01)

Definition at line 6098 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_OS_REG_RXENABLE_Pos

#define FTDF_FTDF_LMAC_CONTROL_OS_REG_RXENABLE_Pos   (1UL)

FTDF FTDF_LMAC_CONTROL_OS_REG: RXENABLE (Bit 1)

Definition at line 6097 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_OS_REG_SINGLECCA_Msk

#define FTDF_FTDF_LMAC_CONTROL_OS_REG_SINGLECCA_Msk   (0x4UL)

FTDF FTDF_LMAC_CONTROL_OS_REG: SINGLECCA (Bitfield-Mask: 0x01)

Definition at line 6100 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_OS_REG_SINGLECCA_Pos

#define FTDF_FTDF_LMAC_CONTROL_OS_REG_SINGLECCA_Pos   (2UL)

FTDF FTDF_LMAC_CONTROL_OS_REG: SINGLECCA (Bit 2)

Definition at line 6099 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CCASTAT_Msk

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CCASTAT_Msk   (0x4UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: CCASTAT (Bitfield-Mask: 0x01)

Definition at line 6110 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CCASTAT_Pos

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CCASTAT_Pos   (2UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: CCASTAT (Bit 2)

Definition at line 6109 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_BO_STAT_Msk

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_BO_STAT_Msk   (0xff000000UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_BO_STAT (Bitfield-Mask: 0xff)

Definition at line 6120 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_BO_STAT_Pos

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_BO_STAT_Pos   (24UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_BO_STAT (Bit 24)

Definition at line 6119 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_NB_STAT_Msk

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_NB_STAT_Msk   (0x70000UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_NB_STAT (Bitfield-Mask: 0x07)

Definition at line 6116 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_NB_STAT_Pos

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_NB_STAT_Pos   (16UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_NB_STAT (Bit 16)

Definition at line 6115 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_RESUME_STAT_Msk

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_RESUME_STAT_Msk   (0x80000UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_RESUME_STAT (Bitfield-Mask: 0x01)

Definition at line 6118 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_RESUME_STAT_Pos

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_CSMA_CA_RESUME_STAT_Pos   (19UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: CSMA_CA_RESUME_STAT (Bit 19)

Definition at line 6117 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_EDSCANVALUE_Msk

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_EDSCANVALUE_Msk   (0xff00UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: EDSCANVALUE (Bitfield-Mask: 0xff)

Definition at line 6114 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_EDSCANVALUE_Pos

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_EDSCANVALUE_Pos   (8UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: EDSCANVALUE (Bit 8)

Definition at line 6113 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_LMACREADY4SLEEP_Msk

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_LMACREADY4SLEEP_Msk   (0x2UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: LMACREADY4SLEEP (Bitfield-Mask: 0x01)

Definition at line 6108 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_LMACREADY4SLEEP_Pos

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_LMACREADY4SLEEP_Pos   (1UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: LMACREADY4SLEEP (Bit 1)

Definition at line 6107 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_WAKEUPTIMERENABLESTATUS_Msk

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_WAKEUPTIMERENABLESTATUS_Msk   (0x40UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: WAKEUPTIMERENABLESTATUS (Bitfield-Mask: 0x01)

Definition at line 6112 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_CONTROL_STATUS_REG_WAKEUPTIMERENABLESTATUS_Pos

#define FTDF_FTDF_LMAC_CONTROL_STATUS_REG_WAKEUPTIMERENABLESTATUS_Pos   (6UL)

FTDF FTDF_LMAC_CONTROL_STATUS_REG: WAKEUPTIMERENABLESTATUS (Bit 6)

Definition at line 6111 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_EVENT_REG_CCASTAT_E_Msk

#define FTDF_FTDF_LMAC_EVENT_REG_CCASTAT_E_Msk   (0x2UL)

FTDF FTDF_LMAC_EVENT_REG: CCASTAT_E (Bitfield-Mask: 0x01)

Definition at line 6220 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_EVENT_REG_CCASTAT_E_Pos

#define FTDF_FTDF_LMAC_EVENT_REG_CCASTAT_E_Pos   (1UL)

FTDF FTDF_LMAC_EVENT_REG: CCASTAT_E (Bit 1)

Definition at line 6219 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_EVENT_REG_CSMA_CA_BO_THR_E_Msk

#define FTDF_FTDF_LMAC_EVENT_REG_CSMA_CA_BO_THR_E_Msk   (0x8UL)

FTDF FTDF_LMAC_EVENT_REG: CSMA_CA_BO_THR_E (Bitfield-Mask: 0x01)

Definition at line 6224 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_EVENT_REG_CSMA_CA_BO_THR_E_Pos

#define FTDF_FTDF_LMAC_EVENT_REG_CSMA_CA_BO_THR_E_Pos   (3UL)

FTDF FTDF_LMAC_EVENT_REG: CSMA_CA_BO_THR_E (Bit 3)

Definition at line 6223 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_EVENT_REG_EDSCANREADY_E_Msk

#define FTDF_FTDF_LMAC_EVENT_REG_EDSCANREADY_E_Msk   (0x1UL)

FTDF FTDF_LMAC_EVENT_REG: EDSCANREADY_E (Bitfield-Mask: 0x01)

Definition at line 6218 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_EVENT_REG_EDSCANREADY_E_Pos

#define FTDF_FTDF_LMAC_EVENT_REG_EDSCANREADY_E_Pos   (0UL)

FTDF FTDF_LMAC_EVENT_REG: EDSCANREADY_E (Bit 0)

Definition at line 6217 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_EVENT_REG_RXTIMEREXPIRED_E_Msk

#define FTDF_FTDF_LMAC_EVENT_REG_RXTIMEREXPIRED_E_Msk   (0x4UL)

FTDF FTDF_LMAC_EVENT_REG: RXTIMEREXPIRED_E (Bitfield-Mask: 0x01)

Definition at line 6222 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_EVENT_REG_RXTIMEREXPIRED_E_Pos

#define FTDF_FTDF_LMAC_EVENT_REG_RXTIMEREXPIRED_E_Pos   (2UL)

FTDF FTDF_LMAC_EVENT_REG: RXTIMEREXPIRED_E (Bit 2)

Definition at line 6221 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_ED_REQUEST_Msk

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_ED_REQUEST_Msk   (0x20UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_ED_REQUEST (Bitfield-Mask: 0x01)

Definition at line 6248 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_ED_REQUEST_Pos

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_ED_REQUEST_Pos   (5UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_ED_REQUEST (Bit 5)

Definition at line 6247 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_MODE_Msk

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_MODE_Msk   (0x1UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_MODE (Bitfield-Mask: 0x01)

Definition at line 6238 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_MODE_Pos

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_MODE_Pos   (0UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_MODE (Bit 0)

Definition at line 6237 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CALCAP_Msk

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CALCAP_Msk   (0xf000000UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_CALCAP (Bitfield-Mask: 0x0f)

Definition at line 6258 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CALCAP_Pos

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CALCAP_Pos   (24UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_CALCAP (Bit 24)

Definition at line 6257 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CN_Msk

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CN_Msk   (0xf00000UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_CN (Bitfield-Mask: 0x0f)

Definition at line 6256 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CN_Pos

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_CN_Pos   (20UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_CN (Bit 20)

Definition at line 6255 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_DEM_PTI_Msk

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_DEM_PTI_Msk   (0xf0000UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_DEM_PTI (Bitfield-Mask: 0x0f)

Definition at line 6254 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_DEM_PTI_Pos

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_DEM_PTI_Pos   (16UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_DEM_PTI (Bit 16)

Definition at line 6253 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_HSI_Msk

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_HSI_Msk   (0x80000000UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_HSI (Bitfield-Mask: 0x01)

Definition at line 6262 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_HSI_Pos

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_HSI_Pos   (31UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_HSI (Bit 31)

Definition at line 6261 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS_Msk

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS_Msk   (0x70000000UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07)

Definition at line 6260 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS_Pos

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS_Pos   (28UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS (Bit 28)

Definition at line 6259 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_EN_Msk

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_EN_Msk   (0x2UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_EN (Bitfield-Mask: 0x01)

Definition at line 6240 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_EN_Pos

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PHY_EN_Pos   (1UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PHY_EN (Bit 1)

Definition at line 6239 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PTI_Msk

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PTI_Msk   (0xf00UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PTI (Bitfield-Mask: 0x0f)

Definition at line 6252 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PTI_Pos

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_PTI_Pos   (8UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_PTI (Bit 8)

Definition at line 6251 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_EN_Msk

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_EN_Msk   (0x8UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_RX_EN (Bitfield-Mask: 0x01)

Definition at line 6244 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_EN_Pos

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_EN_Pos   (3UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_RX_EN (Bit 3)

Definition at line 6243 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_PIPE_EN_Msk

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_PIPE_EN_Msk   (0x10UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_RX_PIPE_EN (Bitfield-Mask: 0x01)

Definition at line 6246 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_PIPE_EN_Pos

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_RX_PIPE_EN_Pos   (4UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_RX_PIPE_EN (Bit 4)

Definition at line 6245 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_EN_Msk

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_EN_Msk   (0x4UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_TX_EN (Bitfield-Mask: 0x01)

Definition at line 6242 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_EN_Pos

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_EN_Pos   (2UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_TX_EN (Bit 2)

Definition at line 6241 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_FRM_NR_Msk

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_FRM_NR_Msk   (0xc0UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_TX_FRM_NR (Bitfield-Mask: 0x03)

Definition at line 6250 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_FRM_NR_Pos

#define FTDF_FTDF_LMAC_MANUAL_1_REG_LMAC_MANUAL_TX_FRM_NR_Pos   (6UL)

FTDF FTDF_LMAC_MANUAL_1_REG: LMAC_MANUAL_TX_FRM_NR (Bit 6)

Definition at line 6249 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_OS_REG_LMAC_MANUAL_TX_START_Msk

#define FTDF_FTDF_LMAC_MANUAL_OS_REG_LMAC_MANUAL_TX_START_Msk   (0x1UL)

FTDF FTDF_LMAC_MANUAL_OS_REG: LMAC_MANUAL_TX_START (Bitfield-Mask: 0x01)

Definition at line 6266 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_OS_REG_LMAC_MANUAL_TX_START_Pos

#define FTDF_FTDF_LMAC_MANUAL_OS_REG_LMAC_MANUAL_TX_START_Pos   (0UL)

FTDF FTDF_LMAC_MANUAL_OS_REG: LMAC_MANUAL_TX_START (Bit 0)

Definition at line 6265 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_CCA_STAT_Msk

#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_CCA_STAT_Msk   (0x1UL)

FTDF FTDF_LMAC_MANUAL_STATUS_REG: LMAC_MANUAL_CCA_STAT (Bitfield-Mask: 0x01)

Definition at line 6270 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_CCA_STAT_Pos

#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_CCA_STAT_Pos   (0UL)

FTDF FTDF_LMAC_MANUAL_STATUS_REG: LMAC_MANUAL_CCA_STAT (Bit 0)

Definition at line 6269 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_ED_STAT_Msk

#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_ED_STAT_Msk   (0xff00UL)

FTDF FTDF_LMAC_MANUAL_STATUS_REG: LMAC_MANUAL_ED_STAT (Bitfield-Mask: 0xff)

Definition at line 6272 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_ED_STAT_Pos

#define FTDF_FTDF_LMAC_MANUAL_STATUS_REG_LMAC_MANUAL_ED_STAT_Pos   (8UL)

FTDF FTDF_LMAC_MANUAL_STATUS_REG: LMAC_MANUAL_ED_STAT (Bit 8)

Definition at line 6271 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MASK_REG_CCASTAT_M_Msk

#define FTDF_FTDF_LMAC_MASK_REG_CCASTAT_M_Msk   (0x2UL)

FTDF FTDF_LMAC_MASK_REG: CCASTAT_M (Bitfield-Mask: 0x01)

Definition at line 6230 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MASK_REG_CCASTAT_M_Pos

#define FTDF_FTDF_LMAC_MASK_REG_CCASTAT_M_Pos   (1UL)

FTDF FTDF_LMAC_MASK_REG: CCASTAT_M (Bit 1)

Definition at line 6229 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MASK_REG_CSMA_CA_BO_THR_M_Msk

#define FTDF_FTDF_LMAC_MASK_REG_CSMA_CA_BO_THR_M_Msk   (0x8UL)

FTDF FTDF_LMAC_MASK_REG: CSMA_CA_BO_THR_M (Bitfield-Mask: 0x01)

Definition at line 6234 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MASK_REG_CSMA_CA_BO_THR_M_Pos

#define FTDF_FTDF_LMAC_MASK_REG_CSMA_CA_BO_THR_M_Pos   (3UL)

FTDF FTDF_LMAC_MASK_REG: CSMA_CA_BO_THR_M (Bit 3)

Definition at line 6233 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MASK_REG_EDSCANREADY_M_Msk

#define FTDF_FTDF_LMAC_MASK_REG_EDSCANREADY_M_Msk   (0x1UL)

FTDF FTDF_LMAC_MASK_REG: EDSCANREADY_M (Bitfield-Mask: 0x01)

Definition at line 6228 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MASK_REG_EDSCANREADY_M_Pos

#define FTDF_FTDF_LMAC_MASK_REG_EDSCANREADY_M_Pos   (0UL)

FTDF FTDF_LMAC_MASK_REG: EDSCANREADY_M (Bit 0)

Definition at line 6227 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MASK_REG_RXTIMEREXPIRED_M_Msk

#define FTDF_FTDF_LMAC_MASK_REG_RXTIMEREXPIRED_M_Msk   (0x4UL)

FTDF FTDF_LMAC_MASK_REG: RXTIMEREXPIRED_M (Bitfield-Mask: 0x01)

Definition at line 6232 of file DA14680BA.h.

◆ FTDF_FTDF_LMAC_MASK_REG_RXTIMEREXPIRED_M_Pos

#define FTDF_FTDF_LMAC_MASK_REG_RXTIMEREXPIRED_M_Pos   (2UL)

FTDF FTDF_LMAC_MASK_REG: RXTIMEREXPIRED_M (Bit 2)

Definition at line 6231 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACGLOBRESET_COUNT_Msk

#define FTDF_FTDF_LMACRESET_REG_LMACGLOBRESET_COUNT_Msk   (0x10000UL)

FTDF FTDF_LMACRESET_REG: LMACGLOBRESET_COUNT (Bitfield-Mask: 0x01)

Definition at line 6590 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACGLOBRESET_COUNT_Pos

#define FTDF_FTDF_LMACRESET_REG_LMACGLOBRESET_COUNT_Pos   (16UL)

FTDF FTDF_LMACRESET_REG: LMACGLOBRESET_COUNT (Bit 16)

Definition at line 6589 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_AHB_Msk

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_AHB_Msk   (0x8UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_AHB (Bitfield-Mask: 0x01)

Definition at line 6578 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_AHB_Pos

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_AHB_Pos   (3UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_AHB (Bit 3)

Definition at line 6577 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_CONTROL_Msk

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_CONTROL_Msk   (0x1UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_CONTROL (Bitfield-Mask: 0x01)

Definition at line 6572 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_CONTROL_Pos

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_CONTROL_Pos   (0UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_CONTROL (Bit 0)

Definition at line 6571 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_COUNT_Msk

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_COUNT_Msk   (0x200UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_COUNT (Bitfield-Mask: 0x01)

Definition at line 6586 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_COUNT_Pos

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_COUNT_Pos   (9UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_COUNT (Bit 9)

Definition at line 6585 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_OREG_Msk

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_OREG_Msk   (0x10UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_OREG (Bitfield-Mask: 0x01)

Definition at line 6580 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_OREG_Pos

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_OREG_Pos   (4UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_OREG (Bit 4)

Definition at line 6579 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_RX_Msk

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_RX_Msk   (0x2UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_RX (Bitfield-Mask: 0x01)

Definition at line 6574 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_RX_Pos

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_RX_Pos   (1UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_RX (Bit 1)

Definition at line 6573 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_SEC_Msk

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_SEC_Msk   (0x80UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_SEC (Bitfield-Mask: 0x01)

Definition at line 6584 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_SEC_Pos

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_SEC_Pos   (7UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_SEC (Bit 7)

Definition at line 6583 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_TIMCTRL_Msk

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TIMCTRL_Msk   (0x400UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_TIMCTRL (Bitfield-Mask: 0x01)

Definition at line 6588 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_TIMCTRL_Pos

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TIMCTRL_Pos   (10UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_TIMCTRL (Bit 10)

Definition at line 6587 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_TSTIM_Msk

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TSTIM_Msk   (0x40UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_TSTIM (Bitfield-Mask: 0x01)

Definition at line 6582 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_TSTIM_Pos

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TSTIM_Pos   (6UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_TSTIM (Bit 6)

Definition at line 6581 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_TX_Msk

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TX_Msk   (0x4UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_TX (Bitfield-Mask: 0x01)

Definition at line 6576 of file DA14680BA.h.

◆ FTDF_FTDF_LMACRESET_REG_LMACRESET_TX_Pos

#define FTDF_FTDF_LMACRESET_REG_LMACRESET_TX_Pos   (2UL)

FTDF FTDF_LMACRESET_REG: LMACRESET_TX (Bit 2)

Definition at line 6575 of file DA14680BA.h.

◆ FTDF_FTDF_LONG_ADDR_0_0_REG_EXP_SA_L_Msk

#define FTDF_FTDF_LONG_ADDR_0_0_REG_EXP_SA_L_Msk   (0xffffffffUL)

FTDF FTDF_LONG_ADDR_0_0_REG: EXP_SA_L (Bitfield-Mask: 0xffffffff)

Definition at line 6720 of file DA14680BA.h.

◆ FTDF_FTDF_LONG_ADDR_0_0_REG_EXP_SA_L_Pos

#define FTDF_FTDF_LONG_ADDR_0_0_REG_EXP_SA_L_Pos   (0UL)

FTDF FTDF_LONG_ADDR_0_0_REG: EXP_SA_L (Bit 0)

Definition at line 6719 of file DA14680BA.h.

◆ FTDF_FTDF_LONG_ADDR_1_0_REG_EXP_SA_H_Msk

#define FTDF_FTDF_LONG_ADDR_1_0_REG_EXP_SA_H_Msk   (0xffffffffUL)

FTDF FTDF_LONG_ADDR_1_0_REG: EXP_SA_H (Bitfield-Mask: 0xffffffff)

Definition at line 6724 of file DA14680BA.h.

◆ FTDF_FTDF_LONG_ADDR_1_0_REG_EXP_SA_H_Pos

#define FTDF_FTDF_LONG_ADDR_1_0_REG_EXP_SA_H_Pos   (0UL)

FTDF FTDF_LONG_ADDR_1_0_REG: EXP_SA_H (Bit 0)

Definition at line 6723 of file DA14680BA.h.

◆ FTDF_FTDF_MACACKWAITDURATION_REG_MACACKWAITDURATION_Msk

#define FTDF_FTDF_MACACKWAITDURATION_REG_MACACKWAITDURATION_Msk   (0xffUL)

FTDF FTDF_MACACKWAITDURATION_REG: MACACKWAITDURATION (Bitfield-Mask: 0xff)

Definition at line 6056 of file DA14680BA.h.

◆ FTDF_FTDF_MACACKWAITDURATION_REG_MACACKWAITDURATION_Pos

#define FTDF_FTDF_MACACKWAITDURATION_REG_MACACKWAITDURATION_Pos   (0UL)

FTDF FTDF_MACACKWAITDURATION_REG: MACACKWAITDURATION (Bit 0)

Definition at line 6055 of file DA14680BA.h.

◆ FTDF_FTDF_MACENHACKWAITDURATION_REG_MACENHACKWAITDURATION_Msk

#define FTDF_FTDF_MACENHACKWAITDURATION_REG_MACENHACKWAITDURATION_Msk   (0xffffUL)

FTDF FTDF_MACENHACKWAITDURATION_REG: MACENHACKWAITDURATION (Bitfield-Mask: 0xffff)

Definition at line 6060 of file DA14680BA.h.

◆ FTDF_FTDF_MACENHACKWAITDURATION_REG_MACENHACKWAITDURATION_Pos

#define FTDF_FTDF_MACENHACKWAITDURATION_REG_MACENHACKWAITDURATION_Pos   (0UL)

FTDF FTDF_MACENHACKWAITDURATION_REG: MACENHACKWAITDURATION (Bit 0)

Definition at line 6059 of file DA14680BA.h.

◆ FTDF_FTDF_MACFCSERRORCOUNT_REG_MACFCSERRORCOUNT_Msk

#define FTDF_FTDF_MACFCSERRORCOUNT_REG_MACFCSERRORCOUNT_Msk   (0xffffffffUL)

FTDF FTDF_MACFCSERRORCOUNT_REG: MACFCSERRORCOUNT (Bitfield-Mask: 0xffffffff)

Definition at line 6568 of file DA14680BA.h.

◆ FTDF_FTDF_MACFCSERRORCOUNT_REG_MACFCSERRORCOUNT_Pos

#define FTDF_FTDF_MACFCSERRORCOUNT_REG_MACFCSERRORCOUNT_Pos   (0UL)

FTDF FTDF_MACFCSERRORCOUNT_REG: MACFCSERRORCOUNT (Bit 0)

Definition at line 6567 of file DA14680BA.h.

◆ FTDF_FTDF_MACRXADDRFAILFRMCNT_REG_MACRXADDRFAILFRMCNT_Msk

#define FTDF_FTDF_MACRXADDRFAILFRMCNT_REG_MACRXADDRFAILFRMCNT_Msk   (0xffffffffUL)

FTDF FTDF_MACRXADDRFAILFRMCNT_REG: MACRXADDRFAILFRMCNT (Bitfield-Mask: 0xffffffff)

Definition at line 6556 of file DA14680BA.h.

◆ FTDF_FTDF_MACRXADDRFAILFRMCNT_REG_MACRXADDRFAILFRMCNT_Pos

#define FTDF_FTDF_MACRXADDRFAILFRMCNT_REG_MACRXADDRFAILFRMCNT_Pos   (0UL)

FTDF FTDF_MACRXADDRFAILFRMCNT_REG: MACRXADDRFAILFRMCNT (Bit 0)

Definition at line 6555 of file DA14680BA.h.

◆ FTDF_FTDF_MACRXSTDACKFRMOKCNT_REG_MACRXSTDACKFRMOKCNT_Msk

#define FTDF_FTDF_MACRXSTDACKFRMOKCNT_REG_MACRXSTDACKFRMOKCNT_Msk   (0xffffffffUL)

FTDF FTDF_MACRXSTDACKFRMOKCNT_REG: MACRXSTDACKFRMOKCNT (Bitfield-Mask: 0xffffffff)

Definition at line 6552 of file DA14680BA.h.

◆ FTDF_FTDF_MACRXSTDACKFRMOKCNT_REG_MACRXSTDACKFRMOKCNT_Pos

#define FTDF_FTDF_MACRXSTDACKFRMOKCNT_REG_MACRXSTDACKFRMOKCNT_Pos   (0UL)

FTDF FTDF_MACRXSTDACKFRMOKCNT_REG: MACRXSTDACKFRMOKCNT (Bit 0)

Definition at line 6551 of file DA14680BA.h.

◆ FTDF_FTDF_MACRXUNSUPFRMCNT_REG_MACRXUNSUPFRMCNT_Msk

#define FTDF_FTDF_MACRXUNSUPFRMCNT_REG_MACRXUNSUPFRMCNT_Msk   (0xffffffffUL)

FTDF FTDF_MACRXUNSUPFRMCNT_REG: MACRXUNSUPFRMCNT (Bitfield-Mask: 0xffffffff)

Definition at line 6560 of file DA14680BA.h.

◆ FTDF_FTDF_MACRXUNSUPFRMCNT_REG_MACRXUNSUPFRMCNT_Pos

#define FTDF_FTDF_MACRXUNSUPFRMCNT_REG_MACRXUNSUPFRMCNT_Pos   (0UL)

FTDF FTDF_MACRXUNSUPFRMCNT_REG: MACRXUNSUPFRMCNT (Bit 0)

Definition at line 6559 of file DA14680BA.h.

◆ FTDF_FTDF_MACTSTXACKDELAYVAL_REG_MACTSTXACKDELAYVAL_Msk

#define FTDF_FTDF_MACTSTXACKDELAYVAL_REG_MACTSTXACKDELAYVAL_Msk   (0xffffUL)

FTDF FTDF_MACTSTXACKDELAYVAL_REG: MACTSTXACKDELAYVAL (Bitfield-Mask: 0xffff)

Definition at line 6200 of file DA14680BA.h.

◆ FTDF_FTDF_MACTSTXACKDELAYVAL_REG_MACTSTXACKDELAYVAL_Pos

#define FTDF_FTDF_MACTSTXACKDELAYVAL_REG_MACTSTXACKDELAYVAL_Pos   (0UL)

FTDF FTDF_MACTSTXACKDELAYVAL_REG: MACTSTXACKDELAYVAL (Bit 0)

Definition at line 6199 of file DA14680BA.h.

◆ FTDF_FTDF_MACTXSTDACKFRMCNT_REG_MACTXSTDACKFRMCNT_Msk

#define FTDF_FTDF_MACTXSTDACKFRMCNT_REG_MACTXSTDACKFRMCNT_Msk   (0xffffffffUL)

FTDF FTDF_MACTXSTDACKFRMCNT_REG: MACTXSTDACKFRMCNT (Bitfield-Mask: 0xffffffff)

Definition at line 6548 of file DA14680BA.h.

◆ FTDF_FTDF_MACTXSTDACKFRMCNT_REG_MACTXSTDACKFRMCNT_Pos

#define FTDF_FTDF_MACTXSTDACKFRMCNT_REG_MACTXSTDACKFRMCNT_Pos   (0UL)

FTDF FTDF_MACTXSTDACKFRMCNT_REG: MACTXSTDACKFRMCNT (Bit 0)

Definition at line 6547 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_0_Msk

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_0_Msk   (0x7UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_0 (Bitfield-Mask: 0x07)

Definition at line 6386 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_0_Pos

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_0_Pos   (0UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_0 (Bit 0)

Definition at line 6385 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_1_Msk

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_1_Msk   (0x70UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_1 (Bitfield-Mask: 0x07)

Definition at line 6388 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_1_Pos

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_1_Pos   (4UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_1 (Bit 4)

Definition at line 6387 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_2_Msk

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_2_Msk   (0x700UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_2 (Bitfield-Mask: 0x07)

Definition at line 6390 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_2_Pos

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_2_Pos   (8UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_2 (Bit 8)

Definition at line 6389 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_3_Msk

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_3_Msk   (0x7000UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_3 (Bitfield-Mask: 0x07)

Definition at line 6392 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_3_Pos

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_3_Pos   (12UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_3 (Bit 12)

Definition at line 6391 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_4_Msk

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_4_Msk   (0x70000UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_4 (Bitfield-Mask: 0x07)

Definition at line 6394 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_4_Pos

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_4_Pos   (16UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_4 (Bit 16)

Definition at line 6393 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_5_Msk

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_5_Msk   (0x700000UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_5 (Bitfield-Mask: 0x07)

Definition at line 6396 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_5_Pos

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_5_Pos   (20UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_5 (Bit 20)

Definition at line 6395 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_6_Msk

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_6_Msk   (0x7000000UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_6 (Bitfield-Mask: 0x07)

Definition at line 6398 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_6_Pos

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_6_Pos   (24UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_6 (Bit 24)

Definition at line 6397 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_7_Msk

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_7_Msk   (0x70000000UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_7 (Bitfield-Mask: 0x07)

Definition at line 6400 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_7_Pos

#define FTDF_FTDF_PHY_PARAMETERS_0_REG_RXBITPOS_7_Pos   (28UL)

FTDF FTDF_PHY_PARAMETERS_0_REG: RXBITPOS_7 (Bit 28)

Definition at line 6399 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_0_Msk

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_0_Msk   (0x7UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_0 (Bitfield-Mask: 0x07)

Definition at line 6404 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_0_Pos

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_0_Pos   (0UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_0 (Bit 0)

Definition at line 6403 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_1_Msk

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_1_Msk   (0x70UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_1 (Bitfield-Mask: 0x07)

Definition at line 6406 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_1_Pos

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_1_Pos   (4UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_1 (Bit 4)

Definition at line 6405 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_2_Msk

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_2_Msk   (0x700UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_2 (Bitfield-Mask: 0x07)

Definition at line 6408 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_2_Pos

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_2_Pos   (8UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_2 (Bit 8)

Definition at line 6407 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_3_Msk

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_3_Msk   (0x7000UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_3 (Bitfield-Mask: 0x07)

Definition at line 6410 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_3_Pos

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_3_Pos   (12UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_3 (Bit 12)

Definition at line 6409 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_4_Msk

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_4_Msk   (0x70000UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_4 (Bitfield-Mask: 0x07)

Definition at line 6412 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_4_Pos

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_4_Pos   (16UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_4 (Bit 16)

Definition at line 6411 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_5_Msk

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_5_Msk   (0x700000UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_5 (Bitfield-Mask: 0x07)

Definition at line 6414 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_5_Pos

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_5_Pos   (20UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_5 (Bit 20)

Definition at line 6413 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_6_Msk

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_6_Msk   (0x7000000UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_6 (Bitfield-Mask: 0x07)

Definition at line 6416 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_6_Pos

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_6_Pos   (24UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_6 (Bit 24)

Definition at line 6415 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_7_Msk

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_7_Msk   (0x70000000UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_7 (Bitfield-Mask: 0x07)

Definition at line 6418 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_7_Pos

#define FTDF_FTDF_PHY_PARAMETERS_1_REG_TXBITPOS_7_Pos   (28UL)

FTDF FTDF_PHY_PARAMETERS_1_REG: TXBITPOS_7 (Bit 28)

Definition at line 6417 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTRXWAIT_Msk

#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTRXWAIT_Msk   (0xff000000UL)

FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTRXWAIT (Bitfield-Mask: 0xff)

Definition at line 6428 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTRXWAIT_Pos

#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTRXWAIT_Pos   (24UL)

FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTRXWAIT (Bit 24)

Definition at line 6427 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXFINISH_Msk

#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXFINISH_Msk   (0xff0000UL)

FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXFINISH (Bitfield-Mask: 0xff)

Definition at line 6426 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXFINISH_Pos

#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXFINISH_Pos   (16UL)

FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXFINISH (Bit 16)

Definition at line 6425 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXLATENCY_Msk

#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXLATENCY_Msk   (0xff00UL)

FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXLATENCY (Bitfield-Mask: 0xff)

Definition at line 6424 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXLATENCY_Pos

#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXLATENCY_Pos   (8UL)

FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXLATENCY (Bit 8)

Definition at line 6423 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXSTARTUP_Msk

#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXSTARTUP_Msk   (0xffUL)

FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXSTARTUP (Bitfield-Mask: 0xff)

Definition at line 6422 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXSTARTUP_Pos

#define FTDF_FTDF_PHY_PARAMETERS_2_REG_PHYTXSTARTUP_Pos   (0UL)

FTDF FTDF_PHY_PARAMETERS_2_REG: PHYTXSTARTUP (Bit 0)

Definition at line 6421 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYENABLE_Msk

#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYENABLE_Msk   (0xff0000UL)

FTDF FTDF_PHY_PARAMETERS_3_REG: PHYENABLE (Bitfield-Mask: 0xff)

Definition at line 6436 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYENABLE_Pos

#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYENABLE_Pos   (16UL)

FTDF FTDF_PHY_PARAMETERS_3_REG: PHYENABLE (Bit 16)

Definition at line 6435 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXLATENCY_Msk

#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXLATENCY_Msk   (0xff00UL)

FTDF FTDF_PHY_PARAMETERS_3_REG: PHYRXLATENCY (Bitfield-Mask: 0xff)

Definition at line 6434 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXLATENCY_Pos

#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXLATENCY_Pos   (8UL)

FTDF FTDF_PHY_PARAMETERS_3_REG: PHYRXLATENCY (Bit 8)

Definition at line 6433 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXSTARTUP_Msk

#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXSTARTUP_Msk   (0xffUL)

FTDF FTDF_PHY_PARAMETERS_3_REG: PHYRXSTARTUP (Bitfield-Mask: 0xff)

Definition at line 6432 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXSTARTUP_Pos

#define FTDF_FTDF_PHY_PARAMETERS_3_REG_PHYRXSTARTUP_Pos   (0UL)

FTDF FTDF_PHY_PARAMETERS_3_REG: PHYRXSTARTUP (Bit 0)

Definition at line 6431 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_3_REG_USE_LEGACY_PHY_EN_Msk

#define FTDF_FTDF_PHY_PARAMETERS_3_REG_USE_LEGACY_PHY_EN_Msk   (0x1000000UL)

FTDF FTDF_PHY_PARAMETERS_3_REG: USE_LEGACY_PHY_EN (Bitfield-Mask: 0x01)

Definition at line 6438 of file DA14680BA.h.

◆ FTDF_FTDF_PHY_PARAMETERS_3_REG_USE_LEGACY_PHY_EN_Pos

#define FTDF_FTDF_PHY_PARAMETERS_3_REG_USE_LEGACY_PHY_EN_Pos   (24UL)

FTDF FTDF_PHY_PARAMETERS_3_REG: USE_LEGACY_PHY_EN (Bit 24)

Definition at line 6437 of file DA14680BA.h.

◆ FTDF_FTDF_REL_NAME_0_REG_REL_NAME_Msk

#define FTDF_FTDF_REL_NAME_0_REG_REL_NAME_Msk   (0xffffffffUL)

FTDF FTDF_REL_NAME_0_REG: REL_NAME (Bitfield-Mask: 0xffffffff)

Definition at line 5982 of file DA14680BA.h.

◆ FTDF_FTDF_REL_NAME_0_REG_REL_NAME_Pos

#define FTDF_FTDF_REL_NAME_0_REG_REL_NAME_Pos   (0UL)

FTDF FTDF_REL_NAME_0_REG: REL_NAME (Bit 0)

Definition at line 5981 of file DA14680BA.h.

◆ FTDF_FTDF_REL_NAME_1_REG_REL_NAME_Msk

#define FTDF_FTDF_REL_NAME_1_REG_REL_NAME_Msk   (0xffffffffUL)

FTDF FTDF_REL_NAME_1_REG: REL_NAME (Bitfield-Mask: 0xffffffff)

Definition at line 5986 of file DA14680BA.h.

◆ FTDF_FTDF_REL_NAME_1_REG_REL_NAME_Pos

#define FTDF_FTDF_REL_NAME_1_REG_REL_NAME_Pos   (0UL)

FTDF FTDF_REL_NAME_1_REG: REL_NAME (Bit 0)

Definition at line 5985 of file DA14680BA.h.

◆ FTDF_FTDF_REL_NAME_2_REG_REL_NAME_Msk

#define FTDF_FTDF_REL_NAME_2_REG_REL_NAME_Msk   (0xffffffffUL)

FTDF FTDF_REL_NAME_2_REG: REL_NAME (Bitfield-Mask: 0xffffffff)

Definition at line 5990 of file DA14680BA.h.

◆ FTDF_FTDF_REL_NAME_2_REG_REL_NAME_Pos

#define FTDF_FTDF_REL_NAME_2_REG_REL_NAME_Pos   (0UL)

FTDF FTDF_REL_NAME_2_REG: REL_NAME (Bit 0)

Definition at line 5989 of file DA14680BA.h.

◆ FTDF_FTDF_REL_NAME_3_REG_REL_NAME_Msk

#define FTDF_FTDF_REL_NAME_3_REG_REL_NAME_Msk   (0xffffffffUL)

FTDF FTDF_REL_NAME_3_REG: REL_NAME (Bitfield-Mask: 0xffffffff)

Definition at line 5994 of file DA14680BA.h.

◆ FTDF_FTDF_REL_NAME_3_REG_REL_NAME_Pos

#define FTDF_FTDF_REL_NAME_3_REG_REL_NAME_Pos   (0UL)

FTDF FTDF_REL_NAME_3_REG: REL_NAME (Bit 0)

Definition at line 5993 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_DBGRXTRANSPARENTMODE_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_DBGRXTRANSPARENTMODE_Msk   (0x1UL)

FTDF FTDF_RX_CONTROL_0_REG: DBGRXTRANSPARENTMODE (Bitfield-Mask: 0x01)

Definition at line 6442 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_DBGRXTRANSPARENTMODE_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_DBGRXTRANSPARENTMODE_Pos   (0UL)

FTDF FTDF_RX_CONTROL_0_REG: DBGRXTRANSPARENTMODE (Bit 0)

Definition at line 6441 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_DISDATAREQUESTCA_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_DISDATAREQUESTCA_Msk   (0x400UL)

FTDF FTDF_RX_CONTROL_0_REG: DISDATAREQUESTCA (Bitfield-Mask: 0x01)

Definition at line 6456 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_DISDATAREQUESTCA_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_DISDATAREQUESTCA_Pos   (10UL)

FTDF FTDF_RX_CONTROL_0_REG: DISDATAREQUESTCA (Bit 10)

Definition at line 6455 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKRECEIVEDCA_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKRECEIVEDCA_Msk   (0x8000000UL)

FTDF FTDF_RX_CONTROL_0_REG: DISRXACKRECEIVEDCA (Bitfield-Mask: 0x01)

Definition at line 6476 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKRECEIVEDCA_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKRECEIVEDCA_Pos   (27UL)

FTDF FTDF_RX_CONTROL_0_REG: DISRXACKRECEIVEDCA (Bit 27)

Definition at line 6475 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKREQUESTCA_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKREQUESTCA_Msk   (0x100UL)

FTDF FTDF_RX_CONTROL_0_REG: DISRXACKREQUESTCA (Bitfield-Mask: 0x01)

Definition at line 6452 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKREQUESTCA_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXACKREQUESTCA_Pos   (8UL)

FTDF FTDF_RX_CONTROL_0_REG: DISRXACKREQUESTCA (Bit 8)

Definition at line 6451 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_DISRXFRMPENDINGCA_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXFRMPENDINGCA_Msk   (0x80UL)

FTDF FTDF_RX_CONTROL_0_REG: DISRXFRMPENDINGCA (Bitfield-Mask: 0x01)

Definition at line 6450 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_DISRXFRMPENDINGCA_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_DISRXFRMPENDINGCA_Pos   (7UL)

FTDF FTDF_RX_CONTROL_0_REG: DISRXFRMPENDINGCA (Bit 7)

Definition at line 6449 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSBEACONWRONGPANID_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSBEACONWRONGPANID_Msk   (0x4000UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSBEACONWRONGPANID (Bitfield-Mask: 0x01)

Definition at line 6464 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSBEACONWRONGPANID_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSBEACONWRONGPANID_Pos   (14UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSBEACONWRONGPANID (Bit 14)

Definition at line 6463 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSCRCERROR_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSCRCERROR_Msk   (0x200UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSCRCERROR (Bitfield-Mask: 0x01)

Definition at line 6454 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSCRCERROR_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSCRCERROR_Pos   (9UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSCRCERROR (Bit 9)

Definition at line 6453 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSFRMTYPE_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSFRMTYPE_Msk   (0xff0000UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSFRMTYPE (Bitfield-Mask: 0xff)

Definition at line 6468 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSFRMTYPE_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSFRMTYPE_Pos   (16UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSFRMTYPE (Bit 16)

Definition at line 6467 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSRESFRAMEVERSION_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSRESFRAMEVERSION_Msk   (0x800UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSRESFRAMEVERSION (Bitfield-Mask: 0x01)

Definition at line 6458 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSRESFRAMEVERSION_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSRESFRAMEVERSION_Pos   (11UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSRESFRAMEVERSION (Bit 11)

Definition at line 6457 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSTOPANCOORDINATOR_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSTOPANCOORDINATOR_Msk   (0x8000UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSTOPANCOORDINATOR (Bitfield-Mask: 0x01)

Definition at line 6466 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSTOPANCOORDINATOR_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSTOPANCOORDINATOR_Pos   (15UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSTOPANCOORDINATOR (Bit 15)

Definition at line 6465 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWAKEUP_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWAKEUP_Msk   (0x1000000UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWAKEUP (Bitfield-Mask: 0x01)

Definition at line 6470 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWAKEUP_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWAKEUP_Pos   (24UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWAKEUP (Bit 24)

Definition at line 6469 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDADDR_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDADDR_Msk   (0x2000UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWRONGDADDR (Bitfield-Mask: 0x01)

Definition at line 6462 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDADDR_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDADDR_Pos   (13UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWRONGDADDR (Bit 13)

Definition at line 6461 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDPANID_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDPANID_Msk   (0x1000UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWRONGDPANID (Bitfield-Mask: 0x01)

Definition at line 6460 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDPANID_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_MACALWAYSPASSWRONGDPANID_Pos   (12UL)

FTDF FTDF_RX_CONTROL_0_REG: MACALWAYSPASSWRONGDPANID (Bit 12)

Definition at line 6459 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACIMPLICITBROADCAST_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_MACIMPLICITBROADCAST_Msk   (0x4000000UL)

FTDF FTDF_RX_CONTROL_0_REG: MACIMPLICITBROADCAST (Bitfield-Mask: 0x01)

Definition at line 6474 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACIMPLICITBROADCAST_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_MACIMPLICITBROADCAST_Pos   (26UL)

FTDF FTDF_RX_CONTROL_0_REG: MACIMPLICITBROADCAST (Bit 26)

Definition at line 6473 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACPASSWAKEUP_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_MACPASSWAKEUP_Msk   (0x2000000UL)

FTDF FTDF_RX_CONTROL_0_REG: MACPASSWAKEUP (Bitfield-Mask: 0x01)

Definition at line 6472 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_MACPASSWAKEUP_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_MACPASSWAKEUP_Pos   (25UL)

FTDF FTDF_RX_CONTROL_0_REG: MACPASSWAKEUP (Bit 25)

Definition at line 6471 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_RX_READ_BUF_PTR_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_RX_READ_BUF_PTR_Msk   (0x78UL)

FTDF FTDF_RX_CONTROL_0_REG: RX_READ_BUF_PTR (Bitfield-Mask: 0x0f)

Definition at line 6448 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_RX_READ_BUF_PTR_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_RX_READ_BUF_PTR_Pos   (3UL)

FTDF FTDF_RX_CONTROL_0_REG: RX_READ_BUF_PTR (Bit 3)

Definition at line 6447 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_RXBEACONONLY_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_RXBEACONONLY_Msk   (0x2UL)

FTDF FTDF_RX_CONTROL_0_REG: RXBEACONONLY (Bitfield-Mask: 0x01)

Definition at line 6444 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_RXBEACONONLY_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_RXBEACONONLY_Pos   (1UL)

FTDF FTDF_RX_CONTROL_0_REG: RXBEACONONLY (Bit 1)

Definition at line 6443 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_RXCOORDREALIGNONLY_Msk

#define FTDF_FTDF_RX_CONTROL_0_REG_RXCOORDREALIGNONLY_Msk   (0x4UL)

FTDF FTDF_RX_CONTROL_0_REG: RXCOORDREALIGNONLY (Bitfield-Mask: 0x01)

Definition at line 6446 of file DA14680BA.h.

◆ FTDF_FTDF_RX_CONTROL_0_REG_RXCOORDREALIGNONLY_Pos

#define FTDF_FTDF_RX_CONTROL_0_REG_RXCOORDREALIGNONLY_Pos   (2UL)

FTDF FTDF_RX_CONTROL_0_REG: RXCOORDREALIGNONLY (Bit 2)

Definition at line 6445 of file DA14680BA.h.

◆ FTDF_FTDF_RX_EVENT_REG_RX_BUF_AVAIL_E_Msk

#define FTDF_FTDF_RX_EVENT_REG_RX_BUF_AVAIL_E_Msk   (0x4UL)

FTDF FTDF_RX_EVENT_REG: RX_BUF_AVAIL_E (Bitfield-Mask: 0x01)

Definition at line 6484 of file DA14680BA.h.

◆ FTDF_FTDF_RX_EVENT_REG_RX_BUF_AVAIL_E_Pos

#define FTDF_FTDF_RX_EVENT_REG_RX_BUF_AVAIL_E_Pos   (2UL)

FTDF FTDF_RX_EVENT_REG: RX_BUF_AVAIL_E (Bit 2)

Definition at line 6483 of file DA14680BA.h.

◆ FTDF_FTDF_RX_EVENT_REG_RX_OVERFLOW_E_Msk

#define FTDF_FTDF_RX_EVENT_REG_RX_OVERFLOW_E_Msk   (0x2UL)

FTDF FTDF_RX_EVENT_REG: RX_OVERFLOW_E (Bitfield-Mask: 0x01)

Definition at line 6482 of file DA14680BA.h.

◆ FTDF_FTDF_RX_EVENT_REG_RX_OVERFLOW_E_Pos

#define FTDF_FTDF_RX_EVENT_REG_RX_OVERFLOW_E_Pos   (1UL)

FTDF FTDF_RX_EVENT_REG: RX_OVERFLOW_E (Bit 1)

Definition at line 6481 of file DA14680BA.h.

◆ FTDF_FTDF_RX_EVENT_REG_RXBYTE_E_Msk

#define FTDF_FTDF_RX_EVENT_REG_RXBYTE_E_Msk   (0x8UL)

FTDF FTDF_RX_EVENT_REG: RXBYTE_E (Bitfield-Mask: 0x01)

Definition at line 6486 of file DA14680BA.h.

◆ FTDF_FTDF_RX_EVENT_REG_RXBYTE_E_Pos

#define FTDF_FTDF_RX_EVENT_REG_RXBYTE_E_Pos   (3UL)

FTDF FTDF_RX_EVENT_REG: RXBYTE_E (Bit 3)

Definition at line 6485 of file DA14680BA.h.

◆ FTDF_FTDF_RX_EVENT_REG_RXSOF_E_Msk

#define FTDF_FTDF_RX_EVENT_REG_RXSOF_E_Msk   (0x1UL)

FTDF FTDF_RX_EVENT_REG: RXSOF_E (Bitfield-Mask: 0x01)

Definition at line 6480 of file DA14680BA.h.

◆ FTDF_FTDF_RX_EVENT_REG_RXSOF_E_Pos

#define FTDF_FTDF_RX_EVENT_REG_RXSOF_E_Pos   (0UL)

FTDF FTDF_RX_EVENT_REG: RXSOF_E (Bit 0)

Definition at line 6479 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_0_0_REG_RX_FIFO_Msk

#define FTDF_FTDF_RX_FIFO_0_0_REG_RX_FIFO_Msk   (0xffffffffUL)

FTDF FTDF_RX_FIFO_0_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff)

Definition at line 5950 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_0_0_REG_RX_FIFO_Pos

#define FTDF_FTDF_RX_FIFO_0_0_REG_RX_FIFO_Pos   (0UL)

FTDF FTDF_RX_FIFO_0_0_REG: RX_FIFO (Bit 0)

Definition at line 5949 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_1_0_REG_RX_FIFO_Msk

#define FTDF_FTDF_RX_FIFO_1_0_REG_RX_FIFO_Msk   (0xffffffffUL)

FTDF FTDF_RX_FIFO_1_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff)

Definition at line 5954 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_1_0_REG_RX_FIFO_Pos

#define FTDF_FTDF_RX_FIFO_1_0_REG_RX_FIFO_Pos   (0UL)

FTDF FTDF_RX_FIFO_1_0_REG: RX_FIFO (Bit 0)

Definition at line 5953 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_2_0_REG_RX_FIFO_Msk

#define FTDF_FTDF_RX_FIFO_2_0_REG_RX_FIFO_Msk   (0xffffffffUL)

FTDF FTDF_RX_FIFO_2_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff)

Definition at line 5958 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_2_0_REG_RX_FIFO_Pos

#define FTDF_FTDF_RX_FIFO_2_0_REG_RX_FIFO_Pos   (0UL)

FTDF FTDF_RX_FIFO_2_0_REG: RX_FIFO (Bit 0)

Definition at line 5957 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_3_0_REG_RX_FIFO_Msk

#define FTDF_FTDF_RX_FIFO_3_0_REG_RX_FIFO_Msk   (0xffffffffUL)

FTDF FTDF_RX_FIFO_3_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff)

Definition at line 5962 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_3_0_REG_RX_FIFO_Pos

#define FTDF_FTDF_RX_FIFO_3_0_REG_RX_FIFO_Pos   (0UL)

FTDF FTDF_RX_FIFO_3_0_REG: RX_FIFO (Bit 0)

Definition at line 5961 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_4_0_REG_RX_FIFO_Msk

#define FTDF_FTDF_RX_FIFO_4_0_REG_RX_FIFO_Msk   (0xffffffffUL)

FTDF FTDF_RX_FIFO_4_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff)

Definition at line 5966 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_4_0_REG_RX_FIFO_Pos

#define FTDF_FTDF_RX_FIFO_4_0_REG_RX_FIFO_Pos   (0UL)

FTDF FTDF_RX_FIFO_4_0_REG: RX_FIFO (Bit 0)

Definition at line 5965 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_5_0_REG_RX_FIFO_Msk

#define FTDF_FTDF_RX_FIFO_5_0_REG_RX_FIFO_Msk   (0xffffffffUL)

FTDF FTDF_RX_FIFO_5_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff)

Definition at line 5970 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_5_0_REG_RX_FIFO_Pos

#define FTDF_FTDF_RX_FIFO_5_0_REG_RX_FIFO_Pos   (0UL)

FTDF FTDF_RX_FIFO_5_0_REG: RX_FIFO (Bit 0)

Definition at line 5969 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_6_0_REG_RX_FIFO_Msk

#define FTDF_FTDF_RX_FIFO_6_0_REG_RX_FIFO_Msk   (0xffffffffUL)

FTDF FTDF_RX_FIFO_6_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff)

Definition at line 5974 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_6_0_REG_RX_FIFO_Pos

#define FTDF_FTDF_RX_FIFO_6_0_REG_RX_FIFO_Pos   (0UL)

FTDF FTDF_RX_FIFO_6_0_REG: RX_FIFO (Bit 0)

Definition at line 5973 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_7_0_REG_RX_FIFO_Msk

#define FTDF_FTDF_RX_FIFO_7_0_REG_RX_FIFO_Msk   (0xffffffffUL)

FTDF FTDF_RX_FIFO_7_0_REG: RX_FIFO (Bitfield-Mask: 0xffffffff)

Definition at line 5978 of file DA14680BA.h.

◆ FTDF_FTDF_RX_FIFO_7_0_REG_RX_FIFO_Pos

#define FTDF_FTDF_RX_FIFO_7_0_REG_RX_FIFO_Pos   (0UL)

FTDF FTDF_RX_FIFO_7_0_REG: RX_FIFO (Bit 0)

Definition at line 5977 of file DA14680BA.h.

◆ FTDF_FTDF_RX_MASK_REG_RX_BUF_AVAIL_M_Msk

#define FTDF_FTDF_RX_MASK_REG_RX_BUF_AVAIL_M_Msk   (0x4UL)

FTDF FTDF_RX_MASK_REG: RX_BUF_AVAIL_M (Bitfield-Mask: 0x01)

Definition at line 6494 of file DA14680BA.h.

◆ FTDF_FTDF_RX_MASK_REG_RX_BUF_AVAIL_M_Pos

#define FTDF_FTDF_RX_MASK_REG_RX_BUF_AVAIL_M_Pos   (2UL)

FTDF FTDF_RX_MASK_REG: RX_BUF_AVAIL_M (Bit 2)

Definition at line 6493 of file DA14680BA.h.

◆ FTDF_FTDF_RX_MASK_REG_RX_OVERFLOW_M_Msk

#define FTDF_FTDF_RX_MASK_REG_RX_OVERFLOW_M_Msk   (0x2UL)

FTDF FTDF_RX_MASK_REG: RX_OVERFLOW_M (Bitfield-Mask: 0x01)

Definition at line 6492 of file DA14680BA.h.

◆ FTDF_FTDF_RX_MASK_REG_RX_OVERFLOW_M_Pos

#define FTDF_FTDF_RX_MASK_REG_RX_OVERFLOW_M_Pos   (1UL)

FTDF FTDF_RX_MASK_REG: RX_OVERFLOW_M (Bit 1)

Definition at line 6491 of file DA14680BA.h.

◆ FTDF_FTDF_RX_MASK_REG_RXBYTE_M_Msk

#define FTDF_FTDF_RX_MASK_REG_RXBYTE_M_Msk   (0x8UL)

FTDF FTDF_RX_MASK_REG: RXBYTE_M (Bitfield-Mask: 0x01)

Definition at line 6496 of file DA14680BA.h.

◆ FTDF_FTDF_RX_MASK_REG_RXBYTE_M_Pos

#define FTDF_FTDF_RX_MASK_REG_RXBYTE_M_Pos   (3UL)

FTDF FTDF_RX_MASK_REG: RXBYTE_M (Bit 3)

Definition at line 6495 of file DA14680BA.h.

◆ FTDF_FTDF_RX_MASK_REG_RXSOF_M_Msk

#define FTDF_FTDF_RX_MASK_REG_RXSOF_M_Msk   (0x1UL)

FTDF FTDF_RX_MASK_REG: RXSOF_M (Bitfield-Mask: 0x01)

Definition at line 6490 of file DA14680BA.h.

◆ FTDF_FTDF_RX_MASK_REG_RXSOF_M_Pos

#define FTDF_FTDF_RX_MASK_REG_RXSOF_M_Pos   (0UL)

FTDF FTDF_RX_MASK_REG: RXSOF_M (Bit 0)

Definition at line 6489 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_0_REG_RX_TIMESTAMP_Msk

#define FTDF_FTDF_RX_META_0_0_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)

FTDF FTDF_RX_META_0_0_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff)

Definition at line 5774 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_0_REG_RX_TIMESTAMP_Pos

#define FTDF_FTDF_RX_META_0_0_REG_RX_TIMESTAMP_Pos   (0UL)

FTDF FTDF_RX_META_0_0_REG: RX_TIMESTAMP (Bit 0)

Definition at line 5773 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_1_REG_RX_TIMESTAMP_Msk

#define FTDF_FTDF_RX_META_0_1_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)

FTDF FTDF_RX_META_0_1_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff)

Definition at line 5796 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_1_REG_RX_TIMESTAMP_Pos

#define FTDF_FTDF_RX_META_0_1_REG_RX_TIMESTAMP_Pos   (0UL)

FTDF FTDF_RX_META_0_1_REG: RX_TIMESTAMP (Bit 0)

Definition at line 5795 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_2_REG_RX_TIMESTAMP_Msk

#define FTDF_FTDF_RX_META_0_2_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)

FTDF FTDF_RX_META_0_2_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff)

Definition at line 5818 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_2_REG_RX_TIMESTAMP_Pos

#define FTDF_FTDF_RX_META_0_2_REG_RX_TIMESTAMP_Pos   (0UL)

FTDF FTDF_RX_META_0_2_REG: RX_TIMESTAMP (Bit 0)

Definition at line 5817 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_3_REG_RX_TIMESTAMP_Msk

#define FTDF_FTDF_RX_META_0_3_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)

FTDF FTDF_RX_META_0_3_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff)

Definition at line 5840 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_3_REG_RX_TIMESTAMP_Pos

#define FTDF_FTDF_RX_META_0_3_REG_RX_TIMESTAMP_Pos   (0UL)

FTDF FTDF_RX_META_0_3_REG: RX_TIMESTAMP (Bit 0)

Definition at line 5839 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_4_REG_RX_TIMESTAMP_Msk

#define FTDF_FTDF_RX_META_0_4_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)

FTDF FTDF_RX_META_0_4_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff)

Definition at line 5862 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_4_REG_RX_TIMESTAMP_Pos

#define FTDF_FTDF_RX_META_0_4_REG_RX_TIMESTAMP_Pos   (0UL)

FTDF FTDF_RX_META_0_4_REG: RX_TIMESTAMP (Bit 0)

Definition at line 5861 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_5_REG_RX_TIMESTAMP_Msk

#define FTDF_FTDF_RX_META_0_5_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)

FTDF FTDF_RX_META_0_5_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff)

Definition at line 5884 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_5_REG_RX_TIMESTAMP_Pos

#define FTDF_FTDF_RX_META_0_5_REG_RX_TIMESTAMP_Pos   (0UL)

FTDF FTDF_RX_META_0_5_REG: RX_TIMESTAMP (Bit 0)

Definition at line 5883 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_6_REG_RX_TIMESTAMP_Msk

#define FTDF_FTDF_RX_META_0_6_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)

FTDF FTDF_RX_META_0_6_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff)

Definition at line 5906 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_6_REG_RX_TIMESTAMP_Pos

#define FTDF_FTDF_RX_META_0_6_REG_RX_TIMESTAMP_Pos   (0UL)

FTDF FTDF_RX_META_0_6_REG: RX_TIMESTAMP (Bit 0)

Definition at line 5905 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_7_REG_RX_TIMESTAMP_Msk

#define FTDF_FTDF_RX_META_0_7_REG_RX_TIMESTAMP_Msk   (0xffffffffUL)

FTDF FTDF_RX_META_0_7_REG: RX_TIMESTAMP (Bitfield-Mask: 0xffffffff)

Definition at line 5928 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_0_7_REG_RX_TIMESTAMP_Pos

#define FTDF_FTDF_RX_META_0_7_REG_RX_TIMESTAMP_Pos   (0UL)

FTDF FTDF_RX_META_0_7_REG: RX_TIMESTAMP (Bit 0)

Definition at line 5927 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_CRC16_ERROR_Msk

#define FTDF_FTDF_RX_META_1_0_REG_CRC16_ERROR_Msk   (0x1UL)

FTDF FTDF_RX_META_1_0_REG: CRC16_ERROR (Bitfield-Mask: 0x01)

Definition at line 5778 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_CRC16_ERROR_Pos

#define FTDF_FTDF_RX_META_1_0_REG_CRC16_ERROR_Pos   (0UL)

FTDF FTDF_RX_META_1_0_REG: CRC16_ERROR (Bit 0)

Definition at line 5777 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_DADDR_ERROR_Msk

#define FTDF_FTDF_RX_META_1_0_REG_DADDR_ERROR_Msk   (0x20UL)

FTDF FTDF_RX_META_1_0_REG: DADDR_ERROR (Bitfield-Mask: 0x01)

Definition at line 5786 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_DADDR_ERROR_Pos

#define FTDF_FTDF_RX_META_1_0_REG_DADDR_ERROR_Pos   (5UL)

FTDF FTDF_RX_META_1_0_REG: DADDR_ERROR (Bit 5)

Definition at line 5785 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_DPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_0_REG_DPANID_ERROR_Msk   (0x10UL)

FTDF FTDF_RX_META_1_0_REG: DPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5784 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_DPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_0_REG_DPANID_ERROR_Pos   (4UL)

FTDF FTDF_RX_META_1_0_REG: DPANID_ERROR (Bit 4)

Definition at line 5783 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_ISPANID_COORD_ERROR_Msk

#define FTDF_FTDF_RX_META_1_0_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)

FTDF FTDF_RX_META_1_0_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01)

Definition at line 5790 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_ISPANID_COORD_ERROR_Pos

#define FTDF_FTDF_RX_META_1_0_REG_ISPANID_COORD_ERROR_Pos   (7UL)

FTDF FTDF_RX_META_1_0_REG: ISPANID_COORD_ERROR (Bit 7)

Definition at line 5789 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_QUALITY_INDICATOR_Msk

#define FTDF_FTDF_RX_META_1_0_REG_QUALITY_INDICATOR_Msk   (0xff00UL)

FTDF FTDF_RX_META_1_0_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff)

Definition at line 5792 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_QUALITY_INDICATOR_Pos

#define FTDF_FTDF_RX_META_1_0_REG_QUALITY_INDICATOR_Pos   (8UL)

FTDF FTDF_RX_META_1_0_REG: QUALITY_INDICATOR (Bit 8)

Definition at line 5791 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_RES_FRM_TYPE_ERROR_Msk

#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)

FTDF FTDF_RX_META_1_0_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01)

Definition at line 5780 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_RES_FRM_TYPE_ERROR_Pos

#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)

FTDF FTDF_RX_META_1_0_REG: RES_FRM_TYPE_ERROR (Bit 2)

Definition at line 5779 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_RES_FRM_VERSION_ERROR_Msk

#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)

FTDF FTDF_RX_META_1_0_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01)

Definition at line 5782 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_RES_FRM_VERSION_ERROR_Pos

#define FTDF_FTDF_RX_META_1_0_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)

FTDF FTDF_RX_META_1_0_REG: RES_FRM_VERSION_ERROR (Bit 3)

Definition at line 5781 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_SPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_0_REG_SPANID_ERROR_Msk   (0x40UL)

FTDF FTDF_RX_META_1_0_REG: SPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5788 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_0_REG_SPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_0_REG_SPANID_ERROR_Pos   (6UL)

FTDF FTDF_RX_META_1_0_REG: SPANID_ERROR (Bit 6)

Definition at line 5787 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_CRC16_ERROR_Msk

#define FTDF_FTDF_RX_META_1_1_REG_CRC16_ERROR_Msk   (0x1UL)

FTDF FTDF_RX_META_1_1_REG: CRC16_ERROR (Bitfield-Mask: 0x01)

Definition at line 5800 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_CRC16_ERROR_Pos

#define FTDF_FTDF_RX_META_1_1_REG_CRC16_ERROR_Pos   (0UL)

FTDF FTDF_RX_META_1_1_REG: CRC16_ERROR (Bit 0)

Definition at line 5799 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_DADDR_ERROR_Msk

#define FTDF_FTDF_RX_META_1_1_REG_DADDR_ERROR_Msk   (0x20UL)

FTDF FTDF_RX_META_1_1_REG: DADDR_ERROR (Bitfield-Mask: 0x01)

Definition at line 5808 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_DADDR_ERROR_Pos

#define FTDF_FTDF_RX_META_1_1_REG_DADDR_ERROR_Pos   (5UL)

FTDF FTDF_RX_META_1_1_REG: DADDR_ERROR (Bit 5)

Definition at line 5807 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_DPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_1_REG_DPANID_ERROR_Msk   (0x10UL)

FTDF FTDF_RX_META_1_1_REG: DPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5806 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_DPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_1_REG_DPANID_ERROR_Pos   (4UL)

FTDF FTDF_RX_META_1_1_REG: DPANID_ERROR (Bit 4)

Definition at line 5805 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_ISPANID_COORD_ERROR_Msk

#define FTDF_FTDF_RX_META_1_1_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)

FTDF FTDF_RX_META_1_1_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01)

Definition at line 5812 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_ISPANID_COORD_ERROR_Pos

#define FTDF_FTDF_RX_META_1_1_REG_ISPANID_COORD_ERROR_Pos   (7UL)

FTDF FTDF_RX_META_1_1_REG: ISPANID_COORD_ERROR (Bit 7)

Definition at line 5811 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_QUALITY_INDICATOR_Msk

#define FTDF_FTDF_RX_META_1_1_REG_QUALITY_INDICATOR_Msk   (0xff00UL)

FTDF FTDF_RX_META_1_1_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff)

Definition at line 5814 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_QUALITY_INDICATOR_Pos

#define FTDF_FTDF_RX_META_1_1_REG_QUALITY_INDICATOR_Pos   (8UL)

FTDF FTDF_RX_META_1_1_REG: QUALITY_INDICATOR (Bit 8)

Definition at line 5813 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_RES_FRM_TYPE_ERROR_Msk

#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)

FTDF FTDF_RX_META_1_1_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01)

Definition at line 5802 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_RES_FRM_TYPE_ERROR_Pos

#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)

FTDF FTDF_RX_META_1_1_REG: RES_FRM_TYPE_ERROR (Bit 2)

Definition at line 5801 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_RES_FRM_VERSION_ERROR_Msk

#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)

FTDF FTDF_RX_META_1_1_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01)

Definition at line 5804 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_RES_FRM_VERSION_ERROR_Pos

#define FTDF_FTDF_RX_META_1_1_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)

FTDF FTDF_RX_META_1_1_REG: RES_FRM_VERSION_ERROR (Bit 3)

Definition at line 5803 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_SPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_1_REG_SPANID_ERROR_Msk   (0x40UL)

FTDF FTDF_RX_META_1_1_REG: SPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5810 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_1_REG_SPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_1_REG_SPANID_ERROR_Pos   (6UL)

FTDF FTDF_RX_META_1_1_REG: SPANID_ERROR (Bit 6)

Definition at line 5809 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_CRC16_ERROR_Msk

#define FTDF_FTDF_RX_META_1_2_REG_CRC16_ERROR_Msk   (0x1UL)

FTDF FTDF_RX_META_1_2_REG: CRC16_ERROR (Bitfield-Mask: 0x01)

Definition at line 5822 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_CRC16_ERROR_Pos

#define FTDF_FTDF_RX_META_1_2_REG_CRC16_ERROR_Pos   (0UL)

FTDF FTDF_RX_META_1_2_REG: CRC16_ERROR (Bit 0)

Definition at line 5821 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_DADDR_ERROR_Msk

#define FTDF_FTDF_RX_META_1_2_REG_DADDR_ERROR_Msk   (0x20UL)

FTDF FTDF_RX_META_1_2_REG: DADDR_ERROR (Bitfield-Mask: 0x01)

Definition at line 5830 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_DADDR_ERROR_Pos

#define FTDF_FTDF_RX_META_1_2_REG_DADDR_ERROR_Pos   (5UL)

FTDF FTDF_RX_META_1_2_REG: DADDR_ERROR (Bit 5)

Definition at line 5829 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_DPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_2_REG_DPANID_ERROR_Msk   (0x10UL)

FTDF FTDF_RX_META_1_2_REG: DPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5828 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_DPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_2_REG_DPANID_ERROR_Pos   (4UL)

FTDF FTDF_RX_META_1_2_REG: DPANID_ERROR (Bit 4)

Definition at line 5827 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_ISPANID_COORD_ERROR_Msk

#define FTDF_FTDF_RX_META_1_2_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)

FTDF FTDF_RX_META_1_2_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01)

Definition at line 5834 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_ISPANID_COORD_ERROR_Pos

#define FTDF_FTDF_RX_META_1_2_REG_ISPANID_COORD_ERROR_Pos   (7UL)

FTDF FTDF_RX_META_1_2_REG: ISPANID_COORD_ERROR (Bit 7)

Definition at line 5833 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_QUALITY_INDICATOR_Msk

#define FTDF_FTDF_RX_META_1_2_REG_QUALITY_INDICATOR_Msk   (0xff00UL)

FTDF FTDF_RX_META_1_2_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff)

Definition at line 5836 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_QUALITY_INDICATOR_Pos

#define FTDF_FTDF_RX_META_1_2_REG_QUALITY_INDICATOR_Pos   (8UL)

FTDF FTDF_RX_META_1_2_REG: QUALITY_INDICATOR (Bit 8)

Definition at line 5835 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_RES_FRM_TYPE_ERROR_Msk

#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)

FTDF FTDF_RX_META_1_2_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01)

Definition at line 5824 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_RES_FRM_TYPE_ERROR_Pos

#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)

FTDF FTDF_RX_META_1_2_REG: RES_FRM_TYPE_ERROR (Bit 2)

Definition at line 5823 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_RES_FRM_VERSION_ERROR_Msk

#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)

FTDF FTDF_RX_META_1_2_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01)

Definition at line 5826 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_RES_FRM_VERSION_ERROR_Pos

#define FTDF_FTDF_RX_META_1_2_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)

FTDF FTDF_RX_META_1_2_REG: RES_FRM_VERSION_ERROR (Bit 3)

Definition at line 5825 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_SPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_2_REG_SPANID_ERROR_Msk   (0x40UL)

FTDF FTDF_RX_META_1_2_REG: SPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5832 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_2_REG_SPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_2_REG_SPANID_ERROR_Pos   (6UL)

FTDF FTDF_RX_META_1_2_REG: SPANID_ERROR (Bit 6)

Definition at line 5831 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_CRC16_ERROR_Msk

#define FTDF_FTDF_RX_META_1_3_REG_CRC16_ERROR_Msk   (0x1UL)

FTDF FTDF_RX_META_1_3_REG: CRC16_ERROR (Bitfield-Mask: 0x01)

Definition at line 5844 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_CRC16_ERROR_Pos

#define FTDF_FTDF_RX_META_1_3_REG_CRC16_ERROR_Pos   (0UL)

FTDF FTDF_RX_META_1_3_REG: CRC16_ERROR (Bit 0)

Definition at line 5843 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_DADDR_ERROR_Msk

#define FTDF_FTDF_RX_META_1_3_REG_DADDR_ERROR_Msk   (0x20UL)

FTDF FTDF_RX_META_1_3_REG: DADDR_ERROR (Bitfield-Mask: 0x01)

Definition at line 5852 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_DADDR_ERROR_Pos

#define FTDF_FTDF_RX_META_1_3_REG_DADDR_ERROR_Pos   (5UL)

FTDF FTDF_RX_META_1_3_REG: DADDR_ERROR (Bit 5)

Definition at line 5851 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_DPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_3_REG_DPANID_ERROR_Msk   (0x10UL)

FTDF FTDF_RX_META_1_3_REG: DPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5850 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_DPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_3_REG_DPANID_ERROR_Pos   (4UL)

FTDF FTDF_RX_META_1_3_REG: DPANID_ERROR (Bit 4)

Definition at line 5849 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_ISPANID_COORD_ERROR_Msk

#define FTDF_FTDF_RX_META_1_3_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)

FTDF FTDF_RX_META_1_3_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01)

Definition at line 5856 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_ISPANID_COORD_ERROR_Pos

#define FTDF_FTDF_RX_META_1_3_REG_ISPANID_COORD_ERROR_Pos   (7UL)

FTDF FTDF_RX_META_1_3_REG: ISPANID_COORD_ERROR (Bit 7)

Definition at line 5855 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_QUALITY_INDICATOR_Msk

#define FTDF_FTDF_RX_META_1_3_REG_QUALITY_INDICATOR_Msk   (0xff00UL)

FTDF FTDF_RX_META_1_3_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff)

Definition at line 5858 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_QUALITY_INDICATOR_Pos

#define FTDF_FTDF_RX_META_1_3_REG_QUALITY_INDICATOR_Pos   (8UL)

FTDF FTDF_RX_META_1_3_REG: QUALITY_INDICATOR (Bit 8)

Definition at line 5857 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_RES_FRM_TYPE_ERROR_Msk

#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)

FTDF FTDF_RX_META_1_3_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01)

Definition at line 5846 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_RES_FRM_TYPE_ERROR_Pos

#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)

FTDF FTDF_RX_META_1_3_REG: RES_FRM_TYPE_ERROR (Bit 2)

Definition at line 5845 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_RES_FRM_VERSION_ERROR_Msk

#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)

FTDF FTDF_RX_META_1_3_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01)

Definition at line 5848 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_RES_FRM_VERSION_ERROR_Pos

#define FTDF_FTDF_RX_META_1_3_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)

FTDF FTDF_RX_META_1_3_REG: RES_FRM_VERSION_ERROR (Bit 3)

Definition at line 5847 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_SPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_3_REG_SPANID_ERROR_Msk   (0x40UL)

FTDF FTDF_RX_META_1_3_REG: SPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5854 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_3_REG_SPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_3_REG_SPANID_ERROR_Pos   (6UL)

FTDF FTDF_RX_META_1_3_REG: SPANID_ERROR (Bit 6)

Definition at line 5853 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_CRC16_ERROR_Msk

#define FTDF_FTDF_RX_META_1_4_REG_CRC16_ERROR_Msk   (0x1UL)

FTDF FTDF_RX_META_1_4_REG: CRC16_ERROR (Bitfield-Mask: 0x01)

Definition at line 5866 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_CRC16_ERROR_Pos

#define FTDF_FTDF_RX_META_1_4_REG_CRC16_ERROR_Pos   (0UL)

FTDF FTDF_RX_META_1_4_REG: CRC16_ERROR (Bit 0)

Definition at line 5865 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_DADDR_ERROR_Msk

#define FTDF_FTDF_RX_META_1_4_REG_DADDR_ERROR_Msk   (0x20UL)

FTDF FTDF_RX_META_1_4_REG: DADDR_ERROR (Bitfield-Mask: 0x01)

Definition at line 5874 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_DADDR_ERROR_Pos

#define FTDF_FTDF_RX_META_1_4_REG_DADDR_ERROR_Pos   (5UL)

FTDF FTDF_RX_META_1_4_REG: DADDR_ERROR (Bit 5)

Definition at line 5873 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_DPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_4_REG_DPANID_ERROR_Msk   (0x10UL)

FTDF FTDF_RX_META_1_4_REG: DPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5872 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_DPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_4_REG_DPANID_ERROR_Pos   (4UL)

FTDF FTDF_RX_META_1_4_REG: DPANID_ERROR (Bit 4)

Definition at line 5871 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_ISPANID_COORD_ERROR_Msk

#define FTDF_FTDF_RX_META_1_4_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)

FTDF FTDF_RX_META_1_4_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01)

Definition at line 5878 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_ISPANID_COORD_ERROR_Pos

#define FTDF_FTDF_RX_META_1_4_REG_ISPANID_COORD_ERROR_Pos   (7UL)

FTDF FTDF_RX_META_1_4_REG: ISPANID_COORD_ERROR (Bit 7)

Definition at line 5877 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_QUALITY_INDICATOR_Msk

#define FTDF_FTDF_RX_META_1_4_REG_QUALITY_INDICATOR_Msk   (0xff00UL)

FTDF FTDF_RX_META_1_4_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff)

Definition at line 5880 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_QUALITY_INDICATOR_Pos

#define FTDF_FTDF_RX_META_1_4_REG_QUALITY_INDICATOR_Pos   (8UL)

FTDF FTDF_RX_META_1_4_REG: QUALITY_INDICATOR (Bit 8)

Definition at line 5879 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_RES_FRM_TYPE_ERROR_Msk

#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)

FTDF FTDF_RX_META_1_4_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01)

Definition at line 5868 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_RES_FRM_TYPE_ERROR_Pos

#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)

FTDF FTDF_RX_META_1_4_REG: RES_FRM_TYPE_ERROR (Bit 2)

Definition at line 5867 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_RES_FRM_VERSION_ERROR_Msk

#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)

FTDF FTDF_RX_META_1_4_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01)

Definition at line 5870 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_RES_FRM_VERSION_ERROR_Pos

#define FTDF_FTDF_RX_META_1_4_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)

FTDF FTDF_RX_META_1_4_REG: RES_FRM_VERSION_ERROR (Bit 3)

Definition at line 5869 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_SPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_4_REG_SPANID_ERROR_Msk   (0x40UL)

FTDF FTDF_RX_META_1_4_REG: SPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5876 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_4_REG_SPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_4_REG_SPANID_ERROR_Pos   (6UL)

FTDF FTDF_RX_META_1_4_REG: SPANID_ERROR (Bit 6)

Definition at line 5875 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_CRC16_ERROR_Msk

#define FTDF_FTDF_RX_META_1_5_REG_CRC16_ERROR_Msk   (0x1UL)

FTDF FTDF_RX_META_1_5_REG: CRC16_ERROR (Bitfield-Mask: 0x01)

Definition at line 5888 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_CRC16_ERROR_Pos

#define FTDF_FTDF_RX_META_1_5_REG_CRC16_ERROR_Pos   (0UL)

FTDF FTDF_RX_META_1_5_REG: CRC16_ERROR (Bit 0)

Definition at line 5887 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_DADDR_ERROR_Msk

#define FTDF_FTDF_RX_META_1_5_REG_DADDR_ERROR_Msk   (0x20UL)

FTDF FTDF_RX_META_1_5_REG: DADDR_ERROR (Bitfield-Mask: 0x01)

Definition at line 5896 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_DADDR_ERROR_Pos

#define FTDF_FTDF_RX_META_1_5_REG_DADDR_ERROR_Pos   (5UL)

FTDF FTDF_RX_META_1_5_REG: DADDR_ERROR (Bit 5)

Definition at line 5895 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_DPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_5_REG_DPANID_ERROR_Msk   (0x10UL)

FTDF FTDF_RX_META_1_5_REG: DPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5894 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_DPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_5_REG_DPANID_ERROR_Pos   (4UL)

FTDF FTDF_RX_META_1_5_REG: DPANID_ERROR (Bit 4)

Definition at line 5893 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_ISPANID_COORD_ERROR_Msk

#define FTDF_FTDF_RX_META_1_5_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)

FTDF FTDF_RX_META_1_5_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01)

Definition at line 5900 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_ISPANID_COORD_ERROR_Pos

#define FTDF_FTDF_RX_META_1_5_REG_ISPANID_COORD_ERROR_Pos   (7UL)

FTDF FTDF_RX_META_1_5_REG: ISPANID_COORD_ERROR (Bit 7)

Definition at line 5899 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_QUALITY_INDICATOR_Msk

#define FTDF_FTDF_RX_META_1_5_REG_QUALITY_INDICATOR_Msk   (0xff00UL)

FTDF FTDF_RX_META_1_5_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff)

Definition at line 5902 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_QUALITY_INDICATOR_Pos

#define FTDF_FTDF_RX_META_1_5_REG_QUALITY_INDICATOR_Pos   (8UL)

FTDF FTDF_RX_META_1_5_REG: QUALITY_INDICATOR (Bit 8)

Definition at line 5901 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_RES_FRM_TYPE_ERROR_Msk

#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)

FTDF FTDF_RX_META_1_5_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01)

Definition at line 5890 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_RES_FRM_TYPE_ERROR_Pos

#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)

FTDF FTDF_RX_META_1_5_REG: RES_FRM_TYPE_ERROR (Bit 2)

Definition at line 5889 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_RES_FRM_VERSION_ERROR_Msk

#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)

FTDF FTDF_RX_META_1_5_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01)

Definition at line 5892 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_RES_FRM_VERSION_ERROR_Pos

#define FTDF_FTDF_RX_META_1_5_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)

FTDF FTDF_RX_META_1_5_REG: RES_FRM_VERSION_ERROR (Bit 3)

Definition at line 5891 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_SPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_5_REG_SPANID_ERROR_Msk   (0x40UL)

FTDF FTDF_RX_META_1_5_REG: SPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5898 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_5_REG_SPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_5_REG_SPANID_ERROR_Pos   (6UL)

FTDF FTDF_RX_META_1_5_REG: SPANID_ERROR (Bit 6)

Definition at line 5897 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_CRC16_ERROR_Msk

#define FTDF_FTDF_RX_META_1_6_REG_CRC16_ERROR_Msk   (0x1UL)

FTDF FTDF_RX_META_1_6_REG: CRC16_ERROR (Bitfield-Mask: 0x01)

Definition at line 5910 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_CRC16_ERROR_Pos

#define FTDF_FTDF_RX_META_1_6_REG_CRC16_ERROR_Pos   (0UL)

FTDF FTDF_RX_META_1_6_REG: CRC16_ERROR (Bit 0)

Definition at line 5909 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_DADDR_ERROR_Msk

#define FTDF_FTDF_RX_META_1_6_REG_DADDR_ERROR_Msk   (0x20UL)

FTDF FTDF_RX_META_1_6_REG: DADDR_ERROR (Bitfield-Mask: 0x01)

Definition at line 5918 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_DADDR_ERROR_Pos

#define FTDF_FTDF_RX_META_1_6_REG_DADDR_ERROR_Pos   (5UL)

FTDF FTDF_RX_META_1_6_REG: DADDR_ERROR (Bit 5)

Definition at line 5917 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_DPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_6_REG_DPANID_ERROR_Msk   (0x10UL)

FTDF FTDF_RX_META_1_6_REG: DPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5916 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_DPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_6_REG_DPANID_ERROR_Pos   (4UL)

FTDF FTDF_RX_META_1_6_REG: DPANID_ERROR (Bit 4)

Definition at line 5915 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_ISPANID_COORD_ERROR_Msk

#define FTDF_FTDF_RX_META_1_6_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)

FTDF FTDF_RX_META_1_6_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01)

Definition at line 5922 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_ISPANID_COORD_ERROR_Pos

#define FTDF_FTDF_RX_META_1_6_REG_ISPANID_COORD_ERROR_Pos   (7UL)

FTDF FTDF_RX_META_1_6_REG: ISPANID_COORD_ERROR (Bit 7)

Definition at line 5921 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_QUALITY_INDICATOR_Msk

#define FTDF_FTDF_RX_META_1_6_REG_QUALITY_INDICATOR_Msk   (0xff00UL)

FTDF FTDF_RX_META_1_6_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff)

Definition at line 5924 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_QUALITY_INDICATOR_Pos

#define FTDF_FTDF_RX_META_1_6_REG_QUALITY_INDICATOR_Pos   (8UL)

FTDF FTDF_RX_META_1_6_REG: QUALITY_INDICATOR (Bit 8)

Definition at line 5923 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_RES_FRM_TYPE_ERROR_Msk

#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)

FTDF FTDF_RX_META_1_6_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01)

Definition at line 5912 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_RES_FRM_TYPE_ERROR_Pos

#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)

FTDF FTDF_RX_META_1_6_REG: RES_FRM_TYPE_ERROR (Bit 2)

Definition at line 5911 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_RES_FRM_VERSION_ERROR_Msk

#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)

FTDF FTDF_RX_META_1_6_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01)

Definition at line 5914 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_RES_FRM_VERSION_ERROR_Pos

#define FTDF_FTDF_RX_META_1_6_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)

FTDF FTDF_RX_META_1_6_REG: RES_FRM_VERSION_ERROR (Bit 3)

Definition at line 5913 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_SPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_6_REG_SPANID_ERROR_Msk   (0x40UL)

FTDF FTDF_RX_META_1_6_REG: SPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5920 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_6_REG_SPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_6_REG_SPANID_ERROR_Pos   (6UL)

FTDF FTDF_RX_META_1_6_REG: SPANID_ERROR (Bit 6)

Definition at line 5919 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_CRC16_ERROR_Msk

#define FTDF_FTDF_RX_META_1_7_REG_CRC16_ERROR_Msk   (0x1UL)

FTDF FTDF_RX_META_1_7_REG: CRC16_ERROR (Bitfield-Mask: 0x01)

Definition at line 5932 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_CRC16_ERROR_Pos

#define FTDF_FTDF_RX_META_1_7_REG_CRC16_ERROR_Pos   (0UL)

FTDF FTDF_RX_META_1_7_REG: CRC16_ERROR (Bit 0)

Definition at line 5931 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_DADDR_ERROR_Msk

#define FTDF_FTDF_RX_META_1_7_REG_DADDR_ERROR_Msk   (0x20UL)

FTDF FTDF_RX_META_1_7_REG: DADDR_ERROR (Bitfield-Mask: 0x01)

Definition at line 5940 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_DADDR_ERROR_Pos

#define FTDF_FTDF_RX_META_1_7_REG_DADDR_ERROR_Pos   (5UL)

FTDF FTDF_RX_META_1_7_REG: DADDR_ERROR (Bit 5)

Definition at line 5939 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_DPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_7_REG_DPANID_ERROR_Msk   (0x10UL)

FTDF FTDF_RX_META_1_7_REG: DPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5938 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_DPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_7_REG_DPANID_ERROR_Pos   (4UL)

FTDF FTDF_RX_META_1_7_REG: DPANID_ERROR (Bit 4)

Definition at line 5937 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_ISPANID_COORD_ERROR_Msk

#define FTDF_FTDF_RX_META_1_7_REG_ISPANID_COORD_ERROR_Msk   (0x80UL)

FTDF FTDF_RX_META_1_7_REG: ISPANID_COORD_ERROR (Bitfield-Mask: 0x01)

Definition at line 5944 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_ISPANID_COORD_ERROR_Pos

#define FTDF_FTDF_RX_META_1_7_REG_ISPANID_COORD_ERROR_Pos   (7UL)

FTDF FTDF_RX_META_1_7_REG: ISPANID_COORD_ERROR (Bit 7)

Definition at line 5943 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_QUALITY_INDICATOR_Msk

#define FTDF_FTDF_RX_META_1_7_REG_QUALITY_INDICATOR_Msk   (0xff00UL)

FTDF FTDF_RX_META_1_7_REG: QUALITY_INDICATOR (Bitfield-Mask: 0xff)

Definition at line 5946 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_QUALITY_INDICATOR_Pos

#define FTDF_FTDF_RX_META_1_7_REG_QUALITY_INDICATOR_Pos   (8UL)

FTDF FTDF_RX_META_1_7_REG: QUALITY_INDICATOR (Bit 8)

Definition at line 5945 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_RES_FRM_TYPE_ERROR_Msk

#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_TYPE_ERROR_Msk   (0x4UL)

FTDF FTDF_RX_META_1_7_REG: RES_FRM_TYPE_ERROR (Bitfield-Mask: 0x01)

Definition at line 5934 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_RES_FRM_TYPE_ERROR_Pos

#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_TYPE_ERROR_Pos   (2UL)

FTDF FTDF_RX_META_1_7_REG: RES_FRM_TYPE_ERROR (Bit 2)

Definition at line 5933 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_RES_FRM_VERSION_ERROR_Msk

#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_VERSION_ERROR_Msk   (0x8UL)

FTDF FTDF_RX_META_1_7_REG: RES_FRM_VERSION_ERROR (Bitfield-Mask: 0x01)

Definition at line 5936 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_RES_FRM_VERSION_ERROR_Pos

#define FTDF_FTDF_RX_META_1_7_REG_RES_FRM_VERSION_ERROR_Pos   (3UL)

FTDF FTDF_RX_META_1_7_REG: RES_FRM_VERSION_ERROR (Bit 3)

Definition at line 5935 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_SPANID_ERROR_Msk

#define FTDF_FTDF_RX_META_1_7_REG_SPANID_ERROR_Msk   (0x40UL)

FTDF FTDF_RX_META_1_7_REG: SPANID_ERROR (Bitfield-Mask: 0x01)

Definition at line 5942 of file DA14680BA.h.

◆ FTDF_FTDF_RX_META_1_7_REG_SPANID_ERROR_Pos

#define FTDF_FTDF_RX_META_1_7_REG_SPANID_ERROR_Pos   (6UL)

FTDF FTDF_RX_META_1_7_REG: SPANID_ERROR (Bit 6)

Definition at line 5941 of file DA14680BA.h.

◆ FTDF_FTDF_RX_STATUS_DELTA_REG_RX_BUFF_IS_FULL_D_Msk

#define FTDF_FTDF_RX_STATUS_DELTA_REG_RX_BUFF_IS_FULL_D_Msk   (0x1UL)

FTDF FTDF_RX_STATUS_DELTA_REG: RX_BUFF_IS_FULL_D (Bitfield-Mask: 0x01)

Definition at line 6510 of file DA14680BA.h.

◆ FTDF_FTDF_RX_STATUS_DELTA_REG_RX_BUFF_IS_FULL_D_Pos

#define FTDF_FTDF_RX_STATUS_DELTA_REG_RX_BUFF_IS_FULL_D_Pos   (0UL)

FTDF FTDF_RX_STATUS_DELTA_REG: RX_BUFF_IS_FULL_D (Bit 0)

Definition at line 6509 of file DA14680BA.h.

◆ FTDF_FTDF_RX_STATUS_MASK_REG_RX_BUFF_IS_FULL_M_Msk

#define FTDF_FTDF_RX_STATUS_MASK_REG_RX_BUFF_IS_FULL_M_Msk   (0x1UL)

FTDF FTDF_RX_STATUS_MASK_REG: RX_BUFF_IS_FULL_M (Bitfield-Mask: 0x01)

Definition at line 6514 of file DA14680BA.h.

◆ FTDF_FTDF_RX_STATUS_MASK_REG_RX_BUFF_IS_FULL_M_Pos

#define FTDF_FTDF_RX_STATUS_MASK_REG_RX_BUFF_IS_FULL_M_Pos   (0UL)

FTDF FTDF_RX_STATUS_MASK_REG: RX_BUFF_IS_FULL_M (Bit 0)

Definition at line 6513 of file DA14680BA.h.

◆ FTDF_FTDF_RX_STATUS_REG_RX_BUFF_IS_FULL_Msk

#define FTDF_FTDF_RX_STATUS_REG_RX_BUFF_IS_FULL_Msk   (0x1UL)

FTDF FTDF_RX_STATUS_REG: RX_BUFF_IS_FULL (Bitfield-Mask: 0x01)

Definition at line 6500 of file DA14680BA.h.

◆ FTDF_FTDF_RX_STATUS_REG_RX_BUFF_IS_FULL_Pos

#define FTDF_FTDF_RX_STATUS_REG_RX_BUFF_IS_FULL_Pos   (0UL)

FTDF FTDF_RX_STATUS_REG: RX_BUFF_IS_FULL (Bit 0)

Definition at line 6499 of file DA14680BA.h.

◆ FTDF_FTDF_RX_STATUS_REG_RX_WRITE_BUF_PTR_Msk

#define FTDF_FTDF_RX_STATUS_REG_RX_WRITE_BUF_PTR_Msk   (0x1eUL)

FTDF FTDF_RX_STATUS_REG: RX_WRITE_BUF_PTR (Bitfield-Mask: 0x0f)

Definition at line 6502 of file DA14680BA.h.

◆ FTDF_FTDF_RX_STATUS_REG_RX_WRITE_BUF_PTR_Pos

#define FTDF_FTDF_RX_STATUS_REG_RX_WRITE_BUF_PTR_Pos   (1UL)

FTDF FTDF_RX_STATUS_REG: RX_WRITE_BUF_PTR (Bit 1)

Definition at line 6501 of file DA14680BA.h.

◆ FTDF_FTDF_SECKEY_0_REG_SECKEY_0_Msk

#define FTDF_FTDF_SECKEY_0_REG_SECKEY_0_Msk   (0xffffffffUL)

FTDF FTDF_SECKEY_0_REG: SECKEY_0 (Bitfield-Mask: 0xffffffff)

Definition at line 6318 of file DA14680BA.h.

◆ FTDF_FTDF_SECKEY_0_REG_SECKEY_0_Pos

#define FTDF_FTDF_SECKEY_0_REG_SECKEY_0_Pos   (0UL)

FTDF FTDF_SECKEY_0_REG: SECKEY_0 (Bit 0)

Definition at line 6317 of file DA14680BA.h.

◆ FTDF_FTDF_SECKEY_1_REG_SECKEY_1_Msk

#define FTDF_FTDF_SECKEY_1_REG_SECKEY_1_Msk   (0xffffffffUL)

FTDF FTDF_SECKEY_1_REG: SECKEY_1 (Bitfield-Mask: 0xffffffff)

Definition at line 6322 of file DA14680BA.h.

◆ FTDF_FTDF_SECKEY_1_REG_SECKEY_1_Pos

#define FTDF_FTDF_SECKEY_1_REG_SECKEY_1_Pos   (0UL)

FTDF FTDF_SECKEY_1_REG: SECKEY_1 (Bit 0)

Definition at line 6321 of file DA14680BA.h.

◆ FTDF_FTDF_SECKEY_2_REG_SECKEY_2_Msk

#define FTDF_FTDF_SECKEY_2_REG_SECKEY_2_Msk   (0xffffffffUL)

FTDF FTDF_SECKEY_2_REG: SECKEY_2 (Bitfield-Mask: 0xffffffff)

Definition at line 6326 of file DA14680BA.h.

◆ FTDF_FTDF_SECKEY_2_REG_SECKEY_2_Pos

#define FTDF_FTDF_SECKEY_2_REG_SECKEY_2_Pos   (0UL)

FTDF FTDF_SECKEY_2_REG: SECKEY_2 (Bit 0)

Definition at line 6325 of file DA14680BA.h.

◆ FTDF_FTDF_SECKEY_3_REG_SECKEY_3_Msk

#define FTDF_FTDF_SECKEY_3_REG_SECKEY_3_Msk   (0xffffffffUL)

FTDF FTDF_SECKEY_3_REG: SECKEY_3 (Bitfield-Mask: 0xffffffff)

Definition at line 6330 of file DA14680BA.h.

◆ FTDF_FTDF_SECKEY_3_REG_SECKEY_3_Pos

#define FTDF_FTDF_SECKEY_3_REG_SECKEY_3_Pos   (0UL)

FTDF FTDF_SECKEY_3_REG: SECKEY_3 (Bit 0)

Definition at line 6329 of file DA14680BA.h.

◆ FTDF_FTDF_SECNONCE_0_REG_SECNONCE_0_Msk

#define FTDF_FTDF_SECNONCE_0_REG_SECNONCE_0_Msk   (0xffffffffUL)

FTDF FTDF_SECNONCE_0_REG: SECNONCE_0 (Bitfield-Mask: 0xffffffff)

Definition at line 6334 of file DA14680BA.h.

◆ FTDF_FTDF_SECNONCE_0_REG_SECNONCE_0_Pos

#define FTDF_FTDF_SECNONCE_0_REG_SECNONCE_0_Pos   (0UL)

FTDF FTDF_SECNONCE_0_REG: SECNONCE_0 (Bit 0)

Definition at line 6333 of file DA14680BA.h.

◆ FTDF_FTDF_SECNONCE_1_REG_SECNONCE_1_Msk

#define FTDF_FTDF_SECNONCE_1_REG_SECNONCE_1_Msk   (0xffffffffUL)

FTDF FTDF_SECNONCE_1_REG: SECNONCE_1 (Bitfield-Mask: 0xffffffff)

Definition at line 6338 of file DA14680BA.h.

◆ FTDF_FTDF_SECNONCE_1_REG_SECNONCE_1_Pos

#define FTDF_FTDF_SECNONCE_1_REG_SECNONCE_1_Pos   (0UL)

FTDF FTDF_SECNONCE_1_REG: SECNONCE_1 (Bit 0)

Definition at line 6337 of file DA14680BA.h.

◆ FTDF_FTDF_SECNONCE_2_REG_SECNONCE_2_Msk

#define FTDF_FTDF_SECNONCE_2_REG_SECNONCE_2_Msk   (0xffffffffUL)

FTDF FTDF_SECNONCE_2_REG: SECNONCE_2 (Bitfield-Mask: 0xffffffff)

Definition at line 6342 of file DA14680BA.h.

◆ FTDF_FTDF_SECNONCE_2_REG_SECNONCE_2_Pos

#define FTDF_FTDF_SECNONCE_2_REG_SECNONCE_2_Pos   (0UL)

FTDF FTDF_SECNONCE_2_REG: SECNONCE_2 (Bit 0)

Definition at line 6341 of file DA14680BA.h.

◆ FTDF_FTDF_SECNONCE_3_REG_SECNONCE_3_Msk

#define FTDF_FTDF_SECNONCE_3_REG_SECNONCE_3_Msk   (0xffUL)

FTDF FTDF_SECNONCE_3_REG: SECNONCE_3 (Bitfield-Mask: 0xff)

Definition at line 6346 of file DA14680BA.h.

◆ FTDF_FTDF_SECNONCE_3_REG_SECNONCE_3_Pos

#define FTDF_FTDF_SECNONCE_3_REG_SECNONCE_3_Pos   (0UL)

FTDF FTDF_SECNONCE_3_REG: SECNONCE_3 (Bit 0)

Definition at line 6345 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_0_REG_SECALENGTH_Msk

#define FTDF_FTDF_SECURITY_0_REG_SECALENGTH_Msk   (0x7f0000UL)

FTDF FTDF_SECURITY_0_REG: SECALENGTH (Bitfield-Mask: 0x7f)

Definition at line 6304 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_0_REG_SECALENGTH_Pos

#define FTDF_FTDF_SECURITY_0_REG_SECALENGTH_Pos   (16UL)

FTDF FTDF_SECURITY_0_REG: SECALENGTH (Bit 16)

Definition at line 6303 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_0_REG_SECENCDECN_Msk

#define FTDF_FTDF_SECURITY_0_REG_SECENCDECN_Msk   (0x80000000UL)

FTDF FTDF_SECURITY_0_REG: SECENCDECN (Bitfield-Mask: 0x01)

Definition at line 6308 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_0_REG_SECENCDECN_Pos

#define FTDF_FTDF_SECURITY_0_REG_SECENCDECN_Pos   (31UL)

FTDF FTDF_SECURITY_0_REG: SECENCDECN (Bit 31)

Definition at line 6307 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_0_REG_SECENTRY_Msk

#define FTDF_FTDF_SECURITY_0_REG_SECENTRY_Msk   (0xf00UL)

FTDF FTDF_SECURITY_0_REG: SECENTRY (Bitfield-Mask: 0x0f)

Definition at line 6302 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_0_REG_SECENTRY_Pos

#define FTDF_FTDF_SECURITY_0_REG_SECENTRY_Pos   (8UL)

FTDF FTDF_SECURITY_0_REG: SECENTRY (Bit 8)

Definition at line 6301 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_0_REG_SECMLENGTH_Msk

#define FTDF_FTDF_SECURITY_0_REG_SECMLENGTH_Msk   (0x7f000000UL)

FTDF FTDF_SECURITY_0_REG: SECMLENGTH (Bitfield-Mask: 0x7f)

Definition at line 6306 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_0_REG_SECMLENGTH_Pos

#define FTDF_FTDF_SECURITY_0_REG_SECMLENGTH_Pos   (24UL)

FTDF FTDF_SECURITY_0_REG: SECMLENGTH (Bit 24)

Definition at line 6305 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_0_REG_SECTXRXN_Msk

#define FTDF_FTDF_SECURITY_0_REG_SECTXRXN_Msk   (0x2UL)

FTDF FTDF_SECURITY_0_REG: SECTXRXN (Bitfield-Mask: 0x01)

Definition at line 6300 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_0_REG_SECTXRXN_Pos

#define FTDF_FTDF_SECURITY_0_REG_SECTXRXN_Pos   (1UL)

FTDF FTDF_SECURITY_0_REG: SECTXRXN (Bit 1)

Definition at line 6299 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_1_REG_SECAUTHFLAGS_Msk

#define FTDF_FTDF_SECURITY_1_REG_SECAUTHFLAGS_Msk   (0xffUL)

FTDF FTDF_SECURITY_1_REG: SECAUTHFLAGS (Bitfield-Mask: 0xff)

Definition at line 6312 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_1_REG_SECAUTHFLAGS_Pos

#define FTDF_FTDF_SECURITY_1_REG_SECAUTHFLAGS_Pos   (0UL)

FTDF FTDF_SECURITY_1_REG: SECAUTHFLAGS (Bit 0)

Definition at line 6311 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_1_REG_SECENCRFLAGS_Msk

#define FTDF_FTDF_SECURITY_1_REG_SECENCRFLAGS_Msk   (0xff00UL)

FTDF FTDF_SECURITY_1_REG: SECENCRFLAGS (Bitfield-Mask: 0xff)

Definition at line 6314 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_1_REG_SECENCRFLAGS_Pos

#define FTDF_FTDF_SECURITY_1_REG_SECENCRFLAGS_Pos   (8UL)

FTDF FTDF_SECURITY_1_REG: SECENCRFLAGS (Bit 8)

Definition at line 6313 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_EVENT_REG_SECREADY_E_Msk

#define FTDF_FTDF_SECURITY_EVENT_REG_SECREADY_E_Msk   (0x1UL)

FTDF FTDF_SECURITY_EVENT_REG: SECREADY_E (Bitfield-Mask: 0x01)

Definition at line 6362 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_EVENT_REG_SECREADY_E_Pos

#define FTDF_FTDF_SECURITY_EVENT_REG_SECREADY_E_Pos   (0UL)

FTDF FTDF_SECURITY_EVENT_REG: SECREADY_E (Bit 0)

Definition at line 6361 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_EVENTMASK_REG_SECREADY_M_Msk

#define FTDF_FTDF_SECURITY_EVENTMASK_REG_SECREADY_M_Msk   (0x1UL)

FTDF FTDF_SECURITY_EVENTMASK_REG: SECREADY_M (Bitfield-Mask: 0x01)

Definition at line 6366 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_EVENTMASK_REG_SECREADY_M_Pos

#define FTDF_FTDF_SECURITY_EVENTMASK_REG_SECREADY_M_Pos   (0UL)

FTDF FTDF_SECURITY_EVENTMASK_REG: SECREADY_M (Bit 0)

Definition at line 6365 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_OS_REG_SECABORT_Msk

#define FTDF_FTDF_SECURITY_OS_REG_SECABORT_Msk   (0x1UL)

FTDF FTDF_SECURITY_OS_REG: SECABORT (Bitfield-Mask: 0x01)

Definition at line 6350 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_OS_REG_SECABORT_Pos

#define FTDF_FTDF_SECURITY_OS_REG_SECABORT_Pos   (0UL)

FTDF FTDF_SECURITY_OS_REG: SECABORT (Bit 0)

Definition at line 6349 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_OS_REG_SECSTART_Msk

#define FTDF_FTDF_SECURITY_OS_REG_SECSTART_Msk   (0x2UL)

FTDF FTDF_SECURITY_OS_REG: SECSTART (Bitfield-Mask: 0x01)

Definition at line 6352 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_OS_REG_SECSTART_Pos

#define FTDF_FTDF_SECURITY_OS_REG_SECSTART_Pos   (1UL)

FTDF FTDF_SECURITY_OS_REG: SECSTART (Bit 1)

Definition at line 6351 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_STATUS_REG_SECAUTHFAIL_Msk

#define FTDF_FTDF_SECURITY_STATUS_REG_SECAUTHFAIL_Msk   (0x2UL)

FTDF FTDF_SECURITY_STATUS_REG: SECAUTHFAIL (Bitfield-Mask: 0x01)

Definition at line 6358 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_STATUS_REG_SECAUTHFAIL_Pos

#define FTDF_FTDF_SECURITY_STATUS_REG_SECAUTHFAIL_Pos   (1UL)

FTDF FTDF_SECURITY_STATUS_REG: SECAUTHFAIL (Bit 1)

Definition at line 6357 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_STATUS_REG_SECBUSY_Msk

#define FTDF_FTDF_SECURITY_STATUS_REG_SECBUSY_Msk   (0x1UL)

FTDF FTDF_SECURITY_STATUS_REG: SECBUSY (Bitfield-Mask: 0x01)

Definition at line 6356 of file DA14680BA.h.

◆ FTDF_FTDF_SECURITY_STATUS_REG_SECBUSY_Pos

#define FTDF_FTDF_SECURITY_STATUS_REG_SECBUSY_Pos   (0UL)

FTDF FTDF_SECURITY_STATUS_REG: SECBUSY (Bit 0)

Definition at line 6355 of file DA14680BA.h.

◆ FTDF_FTDF_SIZE_AND_VAL_0_REG_SHORT_LONGNOT_Msk

#define FTDF_FTDF_SIZE_AND_VAL_0_REG_SHORT_LONGNOT_Msk   (0x10UL)

FTDF FTDF_SIZE_AND_VAL_0_REG: SHORT_LONGNOT (Bitfield-Mask: 0x01)

Definition at line 6730 of file DA14680BA.h.

◆ FTDF_FTDF_SIZE_AND_VAL_0_REG_SHORT_LONGNOT_Pos

#define FTDF_FTDF_SIZE_AND_VAL_0_REG_SHORT_LONGNOT_Pos   (4UL)

FTDF FTDF_SIZE_AND_VAL_0_REG: SHORT_LONGNOT (Bit 4)

Definition at line 6729 of file DA14680BA.h.

◆ FTDF_FTDF_SIZE_AND_VAL_0_REG_VALID_SA_Msk

#define FTDF_FTDF_SIZE_AND_VAL_0_REG_VALID_SA_Msk   (0xfUL)

FTDF FTDF_SIZE_AND_VAL_0_REG: VALID_SA (Bitfield-Mask: 0x0f)

Definition at line 6728 of file DA14680BA.h.

◆ FTDF_FTDF_SIZE_AND_VAL_0_REG_VALID_SA_Pos

#define FTDF_FTDF_SIZE_AND_VAL_0_REG_VALID_SA_Pos   (0UL)

FTDF FTDF_SIZE_AND_VAL_0_REG: VALID_SA (Bit 0)

Definition at line 6727 of file DA14680BA.h.

◆ FTDF_FTDF_SYMBOLTIME2THR_REG_SYMBOLTIME2THR_Msk

#define FTDF_FTDF_SYMBOLTIME2THR_REG_SYMBOLTIME2THR_Msk   (0xffffffffUL)

FTDF FTDF_SYMBOLTIME2THR_REG: SYMBOLTIME2THR (Bitfield-Mask: 0xffffffff)

Definition at line 6604 of file DA14680BA.h.

◆ FTDF_FTDF_SYMBOLTIME2THR_REG_SYMBOLTIME2THR_Pos

#define FTDF_FTDF_SYMBOLTIME2THR_REG_SYMBOLTIME2THR_Pos   (0UL)

FTDF FTDF_SYMBOLTIME2THR_REG: SYMBOLTIME2THR (Bit 0)

Definition at line 6603 of file DA14680BA.h.

◆ FTDF_FTDF_SYMBOLTIMESNAPSHOTVAL_REG_SYMBOLTIMESNAPSHOTVAL_Msk

#define FTDF_FTDF_SYMBOLTIMESNAPSHOTVAL_REG_SYMBOLTIMESNAPSHOTVAL_Msk   (0xffffffffUL)

FTDF FTDF_SYMBOLTIMESNAPSHOTVAL_REG: SYMBOLTIMESNAPSHOTVAL (Bitfield-Mask: 0xffffffff)

Definition at line 6506 of file DA14680BA.h.

◆ FTDF_FTDF_SYMBOLTIMESNAPSHOTVAL_REG_SYMBOLTIMESNAPSHOTVAL_Pos

#define FTDF_FTDF_SYMBOLTIMESNAPSHOTVAL_REG_SYMBOLTIMESNAPSHOTVAL_Pos   (0UL)

FTDF FTDF_SYMBOLTIMESNAPSHOTVAL_REG: SYMBOLTIMESNAPSHOTVAL (Bit 0)

Definition at line 6505 of file DA14680BA.h.

◆ FTDF_FTDF_SYMBOLTIMETHR_REG_SYMBOLTIMETHR_Msk

#define FTDF_FTDF_SYMBOLTIMETHR_REG_SYMBOLTIMETHR_Msk   (0xffffffffUL)

FTDF FTDF_SYMBOLTIMETHR_REG: SYMBOLTIMETHR (Bitfield-Mask: 0xffffffff)

Definition at line 6600 of file DA14680BA.h.

◆ FTDF_FTDF_SYMBOLTIMETHR_REG_SYMBOLTIMETHR_Pos

#define FTDF_FTDF_SYMBOLTIMETHR_REG_SYMBOLTIMETHR_Pos   (0UL)

FTDF FTDF_SYMBOLTIMETHR_REG: SYMBOLTIMETHR (Bit 0)

Definition at line 6599 of file DA14680BA.h.

◆ FTDF_FTDF_SYNCTIMESTAMPPHASEVAL_REG_SYNCTIMESTAMPPHASEVAL_Msk

#define FTDF_FTDF_SYNCTIMESTAMPPHASEVAL_REG_SYNCTIMESTAMPPHASEVAL_Msk   (0xffUL)

FTDF FTDF_SYNCTIMESTAMPPHASEVAL_REG: SYNCTIMESTAMPPHASEVAL (Bitfield-Mask: 0xff)

Definition at line 6564 of file DA14680BA.h.

◆ FTDF_FTDF_SYNCTIMESTAMPPHASEVAL_REG_SYNCTIMESTAMPPHASEVAL_Pos

#define FTDF_FTDF_SYNCTIMESTAMPPHASEVAL_REG_SYNCTIMESTAMPPHASEVAL_Pos   (0UL)

FTDF FTDF_SYNCTIMESTAMPPHASEVAL_REG: SYNCTIMESTAMPPHASEVAL (Bit 0)

Definition at line 6563 of file DA14680BA.h.

◆ FTDF_FTDF_SYNCTIMESTAMPTHR_REG_SYNCTIMESTAMPTHR_Msk

#define FTDF_FTDF_SYNCTIMESTAMPTHR_REG_SYNCTIMESTAMPTHR_Msk   (0x1ffffffUL)

FTDF FTDF_SYNCTIMESTAMPTHR_REG: SYNCTIMESTAMPTHR (Bitfield-Mask: 0x1ffffff)

Definition at line 6536 of file DA14680BA.h.

◆ FTDF_FTDF_SYNCTIMESTAMPTHR_REG_SYNCTIMESTAMPTHR_Pos

#define FTDF_FTDF_SYNCTIMESTAMPTHR_REG_SYNCTIMESTAMPTHR_Pos   (0UL)

FTDF FTDF_SYNCTIMESTAMPTHR_REG: SYNCTIMESTAMPTHR (Bit 0)

Definition at line 6535 of file DA14680BA.h.

◆ FTDF_FTDF_SYNCTIMESTAMPVAL_REG_SYNCTIMESTAMPVAL_Msk

#define FTDF_FTDF_SYNCTIMESTAMPVAL_REG_SYNCTIMESTAMPVAL_Msk   (0xffffffffUL)

FTDF FTDF_SYNCTIMESTAMPVAL_REG: SYNCTIMESTAMPVAL (Bitfield-Mask: 0xffffffff)

Definition at line 6540 of file DA14680BA.h.

◆ FTDF_FTDF_SYNCTIMESTAMPVAL_REG_SYNCTIMESTAMPVAL_Pos

#define FTDF_FTDF_SYNCTIMESTAMPVAL_REG_SYNCTIMESTAMPVAL_Pos   (0UL)

FTDF FTDF_SYNCTIMESTAMPVAL_REG: SYNCTIMESTAMPVAL (Bit 0)

Definition at line 6539 of file DA14680BA.h.

◆ FTDF_FTDF_TIMER_CONTROL_1_REG_SYNCTIMESTAMPENA_Msk

#define FTDF_FTDF_TIMER_CONTROL_1_REG_SYNCTIMESTAMPENA_Msk   (0x2UL)

FTDF FTDF_TIMER_CONTROL_1_REG: SYNCTIMESTAMPENA (Bitfield-Mask: 0x01)

Definition at line 6544 of file DA14680BA.h.

◆ FTDF_FTDF_TIMER_CONTROL_1_REG_SYNCTIMESTAMPENA_Pos

#define FTDF_FTDF_TIMER_CONTROL_1_REG_SYNCTIMESTAMPENA_Pos   (1UL)

FTDF FTDF_TIMER_CONTROL_1_REG: SYNCTIMESTAMPENA (Bit 1)

Definition at line 6543 of file DA14680BA.h.

◆ FTDF_FTDF_TIMESTAMPCURRPHASEVAL_REG_TIMESTAMPCURRPHASEVAL_Msk

#define FTDF_FTDF_TIMESTAMPCURRPHASEVAL_REG_TIMESTAMPCURRPHASEVAL_Msk   (0xffUL)

FTDF FTDF_TIMESTAMPCURRPHASEVAL_REG: TIMESTAMPCURRPHASEVAL (Bitfield-Mask: 0xff)

Definition at line 6196 of file DA14680BA.h.

◆ FTDF_FTDF_TIMESTAMPCURRPHASEVAL_REG_TIMESTAMPCURRPHASEVAL_Pos

#define FTDF_FTDF_TIMESTAMPCURRPHASEVAL_REG_TIMESTAMPCURRPHASEVAL_Pos   (0UL)

FTDF FTDF_TIMESTAMPCURRPHASEVAL_REG: TIMESTAMPCURRPHASEVAL (Bit 0)

Definition at line 6195 of file DA14680BA.h.

◆ FTDF_FTDF_TIMESTAMPCURRVAL_REG_TIMESTAMPCURRVAL_Msk

#define FTDF_FTDF_TIMESTAMPCURRVAL_REG_TIMESTAMPCURRVAL_Msk   (0xffffffffUL)

FTDF FTDF_TIMESTAMPCURRVAL_REG: TIMESTAMPCURRVAL (Bitfield-Mask: 0xffffffff)

Definition at line 6128 of file DA14680BA.h.

◆ FTDF_FTDF_TIMESTAMPCURRVAL_REG_TIMESTAMPCURRVAL_Pos

#define FTDF_FTDF_TIMESTAMPCURRVAL_REG_TIMESTAMPCURRVAL_Pos   (0UL)

FTDF FTDF_TIMESTAMPCURRVAL_REG: TIMESTAMPCURRVAL (Bit 0)

Definition at line 6127 of file DA14680BA.h.

◆ FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSRXWAIT_Msk

#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSRXWAIT_Msk   (0xffff0000UL)

FTDF FTDF_TSCH_CONTROL_0_REG: MACTSRXWAIT (Bitfield-Mask: 0xffff)

Definition at line 6372 of file DA14680BA.h.

◆ FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSRXWAIT_Pos

#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSRXWAIT_Pos   (16UL)

FTDF FTDF_TSCH_CONTROL_0_REG: MACTSRXWAIT (Bit 16)

Definition at line 6371 of file DA14680BA.h.

◆ FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSTXACKDELAY_Msk

#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSTXACKDELAY_Msk   (0xffffUL)

FTDF FTDF_TSCH_CONTROL_0_REG: MACTSTXACKDELAY (Bitfield-Mask: 0xffff)

Definition at line 6370 of file DA14680BA.h.

◆ FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSTXACKDELAY_Pos

#define FTDF_FTDF_TSCH_CONTROL_0_REG_MACTSTXACKDELAY_Pos   (0UL)

FTDF FTDF_TSCH_CONTROL_0_REG: MACTSTXACKDELAY (Bit 0)

Definition at line 6369 of file DA14680BA.h.

◆ FTDF_FTDF_TSCH_CONTROL_1_REG_MACTSRXTX_Msk

#define FTDF_FTDF_TSCH_CONTROL_1_REG_MACTSRXTX_Msk   (0xffffUL)

FTDF FTDF_TSCH_CONTROL_1_REG: MACTSRXTX (Bitfield-Mask: 0xffff)

Definition at line 6376 of file DA14680BA.h.

◆ FTDF_FTDF_TSCH_CONTROL_1_REG_MACTSRXTX_Pos

#define FTDF_FTDF_TSCH_CONTROL_1_REG_MACTSRXTX_Pos   (0UL)

FTDF FTDF_TSCH_CONTROL_1_REG: MACTSRXTX (Bit 0)

Definition at line 6375 of file DA14680BA.h.

◆ FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSACKWAIT_Msk

#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSACKWAIT_Msk   (0xffff0000UL)

FTDF FTDF_TSCH_CONTROL_2_REG: MACTSACKWAIT (Bitfield-Mask: 0xffff)

Definition at line 6382 of file DA14680BA.h.

◆ FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSACKWAIT_Pos

#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSACKWAIT_Pos   (16UL)

FTDF FTDF_TSCH_CONTROL_2_REG: MACTSACKWAIT (Bit 16)

Definition at line 6381 of file DA14680BA.h.

◆ FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSRXACKDELAY_Msk

#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSRXACKDELAY_Msk   (0xffffUL)

FTDF FTDF_TSCH_CONTROL_2_REG: MACTSRXACKDELAY (Bitfield-Mask: 0xffff)

Definition at line 6380 of file DA14680BA.h.

◆ FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSRXACKDELAY_Pos

#define FTDF_FTDF_TSCH_CONTROL_2_REG_MACTSRXACKDELAY_Pos   (0UL)

FTDF FTDF_TSCH_CONTROL_2_REG: MACTSRXACKDELAY (Bit 0)

Definition at line 6379 of file DA14680BA.h.

◆ FTDF_FTDF_TX_CLEAR_OS_REG_TX_FLAG_CLEAR_Msk

#define FTDF_FTDF_TX_CLEAR_OS_REG_TX_FLAG_CLEAR_Msk   (0xfUL)

FTDF FTDF_TX_CLEAR_OS_REG: TX_FLAG_CLEAR (Bitfield-Mask: 0x0f)

Definition at line 6708 of file DA14680BA.h.

◆ FTDF_FTDF_TX_CLEAR_OS_REG_TX_FLAG_CLEAR_Pos

#define FTDF_FTDF_TX_CLEAR_OS_REG_TX_FLAG_CLEAR_Pos   (0UL)

FTDF FTDF_TX_CLEAR_OS_REG: TX_FLAG_CLEAR (Bit 0)

Definition at line 6707 of file DA14680BA.h.

◆ FTDF_FTDF_TX_CONTROL_0_REG_DBGTXTRANSPARENTMODE_Msk

#define FTDF_FTDF_TX_CONTROL_0_REG_DBGTXTRANSPARENTMODE_Msk   (0x1UL)

FTDF FTDF_TX_CONTROL_0_REG: DBGTXTRANSPARENTMODE (Bitfield-Mask: 0x01)

Definition at line 6518 of file DA14680BA.h.

◆ FTDF_FTDF_TX_CONTROL_0_REG_DBGTXTRANSPARENTMODE_Pos

#define FTDF_FTDF_TX_CONTROL_0_REG_DBGTXTRANSPARENTMODE_Pos   (0UL)

FTDF FTDF_TX_CONTROL_0_REG: DBGTXTRANSPARENTMODE (Bit 0)

Definition at line 6517 of file DA14680BA.h.

◆ FTDF_FTDF_TX_CONTROL_0_REG_MACMAXBE_Msk

#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXBE_Msk   (0xf0UL)

FTDF FTDF_TX_CONTROL_0_REG: MACMAXBE (Bitfield-Mask: 0x0f)

Definition at line 6520 of file DA14680BA.h.

◆ FTDF_FTDF_TX_CONTROL_0_REG_MACMAXBE_Pos

#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXBE_Pos   (4UL)

FTDF FTDF_TX_CONTROL_0_REG: MACMAXBE (Bit 4)

Definition at line 6519 of file DA14680BA.h.

◆ FTDF_FTDF_TX_CONTROL_0_REG_MACMAXCSMABACKOFFS_Msk

#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXCSMABACKOFFS_Msk   (0x7000UL)

FTDF FTDF_TX_CONTROL_0_REG: MACMAXCSMABACKOFFS (Bitfield-Mask: 0x07)

Definition at line 6524 of file DA14680BA.h.

◆ FTDF_FTDF_TX_CONTROL_0_REG_MACMAXCSMABACKOFFS_Pos

#define FTDF_FTDF_TX_CONTROL_0_REG_MACMAXCSMABACKOFFS_Pos   (12UL)

FTDF FTDF_TX_CONTROL_0_REG: MACMAXCSMABACKOFFS (Bit 12)

Definition at line 6523 of file DA14680BA.h.

◆ FTDF_FTDF_TX_CONTROL_0_REG_MACMINBE_Msk

#define FTDF_FTDF_TX_CONTROL_0_REG_MACMINBE_Msk   (0xf00UL)

FTDF FTDF_TX_CONTROL_0_REG: MACMINBE (Bitfield-Mask: 0x0f)

Definition at line 6522 of file DA14680BA.h.

◆ FTDF_FTDF_TX_CONTROL_0_REG_MACMINBE_Pos

#define FTDF_FTDF_TX_CONTROL_0_REG_MACMINBE_Pos   (8UL)

FTDF FTDF_TX_CONTROL_0_REG: MACMINBE (Bit 8)

Definition at line 6521 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FIFO_0_0_REG_TX_FIFO_Msk

#define FTDF_FTDF_TX_FIFO_0_0_REG_TX_FIFO_Msk   (0xffffffffUL)

FTDF FTDF_TX_FIFO_0_0_REG: TX_FIFO (Bitfield-Mask: 0xffffffff)

Definition at line 5606 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FIFO_0_0_REG_TX_FIFO_Pos

#define FTDF_FTDF_TX_FIFO_0_0_REG_TX_FIFO_Pos   (0UL)

FTDF FTDF_TX_FIFO_0_0_REG: TX_FIFO (Bit 0)

Definition at line 5605 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FIFO_1_0_REG_TX_FIFO_Msk

#define FTDF_FTDF_TX_FIFO_1_0_REG_TX_FIFO_Msk   (0xffffffffUL)

FTDF FTDF_TX_FIFO_1_0_REG: TX_FIFO (Bitfield-Mask: 0xffffffff)

Definition at line 5610 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FIFO_1_0_REG_TX_FIFO_Pos

#define FTDF_FTDF_TX_FIFO_1_0_REG_TX_FIFO_Pos   (0UL)

FTDF FTDF_TX_FIFO_1_0_REG: TX_FIFO (Bit 0)

Definition at line 5609 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FIFO_2_0_REG_TX_FIFO_Msk

#define FTDF_FTDF_TX_FIFO_2_0_REG_TX_FIFO_Msk   (0xffffffffUL)

FTDF FTDF_TX_FIFO_2_0_REG: TX_FIFO (Bitfield-Mask: 0xffffffff)

Definition at line 5614 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FIFO_2_0_REG_TX_FIFO_Pos

#define FTDF_FTDF_TX_FIFO_2_0_REG_TX_FIFO_Pos   (0UL)

FTDF FTDF_TX_FIFO_2_0_REG: TX_FIFO (Bit 0)

Definition at line 5613 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FIFO_3_0_REG_TX_FIFO_Msk

#define FTDF_FTDF_TX_FIFO_3_0_REG_TX_FIFO_Msk   (0xffffffffUL)

FTDF FTDF_TX_FIFO_3_0_REG: TX_FIFO (Bitfield-Mask: 0xffffffff)

Definition at line 5618 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FIFO_3_0_REG_TX_FIFO_Pos

#define FTDF_FTDF_TX_FIFO_3_0_REG_TX_FIFO_Pos   (0UL)

FTDF FTDF_TX_FIFO_3_0_REG: TX_FIFO (Bit 0)

Definition at line 5617 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_E_0_REG_TX_FLAG_CLEAR_E_Msk

#define FTDF_FTDF_TX_FLAG_CLEAR_E_0_REG_TX_FLAG_CLEAR_E_Msk   (0x1UL)

FTDF FTDF_TX_FLAG_CLEAR_E_0_REG: TX_FLAG_CLEAR_E (Bitfield-Mask: 0x01)

Definition at line 6628 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_E_0_REG_TX_FLAG_CLEAR_E_Pos

#define FTDF_FTDF_TX_FLAG_CLEAR_E_0_REG_TX_FLAG_CLEAR_E_Pos   (0UL)

FTDF FTDF_TX_FLAG_CLEAR_E_0_REG: TX_FLAG_CLEAR_E (Bit 0)

Definition at line 6627 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_E_1_REG_TX_FLAG_CLEAR_E_Msk

#define FTDF_FTDF_TX_FLAG_CLEAR_E_1_REG_TX_FLAG_CLEAR_E_Msk   (0x1UL)

FTDF FTDF_TX_FLAG_CLEAR_E_1_REG: TX_FLAG_CLEAR_E (Bitfield-Mask: 0x01)

Definition at line 6648 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_E_1_REG_TX_FLAG_CLEAR_E_Pos

#define FTDF_FTDF_TX_FLAG_CLEAR_E_1_REG_TX_FLAG_CLEAR_E_Pos   (0UL)

FTDF FTDF_TX_FLAG_CLEAR_E_1_REG: TX_FLAG_CLEAR_E (Bit 0)

Definition at line 6647 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_E_2_REG_TX_FLAG_CLEAR_E_Msk

#define FTDF_FTDF_TX_FLAG_CLEAR_E_2_REG_TX_FLAG_CLEAR_E_Msk   (0x1UL)

FTDF FTDF_TX_FLAG_CLEAR_E_2_REG: TX_FLAG_CLEAR_E (Bitfield-Mask: 0x01)

Definition at line 6668 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_E_2_REG_TX_FLAG_CLEAR_E_Pos

#define FTDF_FTDF_TX_FLAG_CLEAR_E_2_REG_TX_FLAG_CLEAR_E_Pos   (0UL)

FTDF FTDF_TX_FLAG_CLEAR_E_2_REG: TX_FLAG_CLEAR_E (Bit 0)

Definition at line 6667 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_E_3_REG_TX_FLAG_CLEAR_E_Msk

#define FTDF_FTDF_TX_FLAG_CLEAR_E_3_REG_TX_FLAG_CLEAR_E_Msk   (0x1UL)

FTDF FTDF_TX_FLAG_CLEAR_E_3_REG: TX_FLAG_CLEAR_E (Bitfield-Mask: 0x01)

Definition at line 6688 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_E_3_REG_TX_FLAG_CLEAR_E_Pos

#define FTDF_FTDF_TX_FLAG_CLEAR_E_3_REG_TX_FLAG_CLEAR_E_Pos   (0UL)

FTDF FTDF_TX_FLAG_CLEAR_E_3_REG: TX_FLAG_CLEAR_E (Bit 0)

Definition at line 6687 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_M_0_REG_TX_FLAG_CLEAR_M_Msk

#define FTDF_FTDF_TX_FLAG_CLEAR_M_0_REG_TX_FLAG_CLEAR_M_Msk   (0x1UL)

FTDF FTDF_TX_FLAG_CLEAR_M_0_REG: TX_FLAG_CLEAR_M (Bitfield-Mask: 0x01)

Definition at line 6632 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_M_0_REG_TX_FLAG_CLEAR_M_Pos

#define FTDF_FTDF_TX_FLAG_CLEAR_M_0_REG_TX_FLAG_CLEAR_M_Pos   (0UL)

FTDF FTDF_TX_FLAG_CLEAR_M_0_REG: TX_FLAG_CLEAR_M (Bit 0)

Definition at line 6631 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_M_1_REG_TX_FLAG_CLEAR_M_Msk

#define FTDF_FTDF_TX_FLAG_CLEAR_M_1_REG_TX_FLAG_CLEAR_M_Msk   (0x1UL)

FTDF FTDF_TX_FLAG_CLEAR_M_1_REG: TX_FLAG_CLEAR_M (Bitfield-Mask: 0x01)

Definition at line 6652 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_M_1_REG_TX_FLAG_CLEAR_M_Pos

#define FTDF_FTDF_TX_FLAG_CLEAR_M_1_REG_TX_FLAG_CLEAR_M_Pos   (0UL)

FTDF FTDF_TX_FLAG_CLEAR_M_1_REG: TX_FLAG_CLEAR_M (Bit 0)

Definition at line 6651 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_M_2_REG_TX_FLAG_CLEAR_M_Msk

#define FTDF_FTDF_TX_FLAG_CLEAR_M_2_REG_TX_FLAG_CLEAR_M_Msk   (0x1UL)

FTDF FTDF_TX_FLAG_CLEAR_M_2_REG: TX_FLAG_CLEAR_M (Bitfield-Mask: 0x01)

Definition at line 6672 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_M_2_REG_TX_FLAG_CLEAR_M_Pos

#define FTDF_FTDF_TX_FLAG_CLEAR_M_2_REG_TX_FLAG_CLEAR_M_Pos   (0UL)

FTDF FTDF_TX_FLAG_CLEAR_M_2_REG: TX_FLAG_CLEAR_M (Bit 0)

Definition at line 6671 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_M_3_REG_TX_FLAG_CLEAR_M_Msk

#define FTDF_FTDF_TX_FLAG_CLEAR_M_3_REG_TX_FLAG_CLEAR_M_Msk   (0x1UL)

FTDF FTDF_TX_FLAG_CLEAR_M_3_REG: TX_FLAG_CLEAR_M (Bitfield-Mask: 0x01)

Definition at line 6692 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_CLEAR_M_3_REG_TX_FLAG_CLEAR_M_Pos

#define FTDF_FTDF_TX_FLAG_CLEAR_M_3_REG_TX_FLAG_CLEAR_M_Pos   (0UL)

FTDF FTDF_TX_FLAG_CLEAR_M_3_REG: TX_FLAG_CLEAR_M (Bit 0)

Definition at line 6691 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_S_0_REG_TX_FLAG_STAT_Msk

#define FTDF_FTDF_TX_FLAG_S_0_REG_TX_FLAG_STAT_Msk   (0x1UL)

FTDF FTDF_TX_FLAG_S_0_REG: TX_FLAG_STAT (Bitfield-Mask: 0x01)

Definition at line 6624 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_S_0_REG_TX_FLAG_STAT_Pos

#define FTDF_FTDF_TX_FLAG_S_0_REG_TX_FLAG_STAT_Pos   (0UL)

FTDF FTDF_TX_FLAG_S_0_REG: TX_FLAG_STAT (Bit 0)

Definition at line 6623 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_S_1_REG_TX_FLAG_STAT_Msk

#define FTDF_FTDF_TX_FLAG_S_1_REG_TX_FLAG_STAT_Msk   (0x1UL)

FTDF FTDF_TX_FLAG_S_1_REG: TX_FLAG_STAT (Bitfield-Mask: 0x01)

Definition at line 6644 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_S_1_REG_TX_FLAG_STAT_Pos

#define FTDF_FTDF_TX_FLAG_S_1_REG_TX_FLAG_STAT_Pos   (0UL)

FTDF FTDF_TX_FLAG_S_1_REG: TX_FLAG_STAT (Bit 0)

Definition at line 6643 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_S_2_REG_TX_FLAG_STAT_Msk

#define FTDF_FTDF_TX_FLAG_S_2_REG_TX_FLAG_STAT_Msk   (0x1UL)

FTDF FTDF_TX_FLAG_S_2_REG: TX_FLAG_STAT (Bitfield-Mask: 0x01)

Definition at line 6664 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_S_2_REG_TX_FLAG_STAT_Pos

#define FTDF_FTDF_TX_FLAG_S_2_REG_TX_FLAG_STAT_Pos   (0UL)

FTDF FTDF_TX_FLAG_S_2_REG: TX_FLAG_STAT (Bit 0)

Definition at line 6663 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_S_3_REG_TX_FLAG_STAT_Msk

#define FTDF_FTDF_TX_FLAG_S_3_REG_TX_FLAG_STAT_Msk   (0x1UL)

FTDF FTDF_TX_FLAG_S_3_REG: TX_FLAG_STAT (Bitfield-Mask: 0x01)

Definition at line 6684 of file DA14680BA.h.

◆ FTDF_FTDF_TX_FLAG_S_3_REG_TX_FLAG_STAT_Pos

#define FTDF_FTDF_TX_FLAG_S_3_REG_TX_FLAG_STAT_Pos   (0UL)

FTDF FTDF_TX_FLAG_S_3_REG: TX_FLAG_STAT (Bit 0)

Definition at line 6683 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_ACKREQUEST_Msk

#define FTDF_FTDF_TX_META_DATA_0_0_REG_ACKREQUEST_Msk   (0x10000000UL)

FTDF FTDF_TX_META_DATA_0_0_REG: ACKREQUEST (Bitfield-Mask: 0x01)

Definition at line 5638 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_ACKREQUEST_Pos

#define FTDF_FTDF_TX_META_DATA_0_0_REG_ACKREQUEST_Pos   (28UL)

FTDF FTDF_TX_META_DATA_0_0_REG: ACKREQUEST (Bit 28)

Definition at line 5637 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_CRC16_ENA_Msk

#define FTDF_FTDF_TX_META_DATA_0_0_REG_CRC16_ENA_Msk   (0x40000000UL)

FTDF FTDF_TX_META_DATA_0_0_REG: CRC16_ENA (Bitfield-Mask: 0x01)

Definition at line 5640 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_CRC16_ENA_Pos

#define FTDF_FTDF_TX_META_DATA_0_0_REG_CRC16_ENA_Pos   (30UL)

FTDF FTDF_TX_META_DATA_0_0_REG: CRC16_ENA (Bit 30)

Definition at line 5639 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_CSMACA_ENA_Msk

#define FTDF_FTDF_TX_META_DATA_0_0_REG_CSMACA_ENA_Msk   (0x4000000UL)

FTDF FTDF_TX_META_DATA_0_0_REG: CSMACA_ENA (Bitfield-Mask: 0x01)

Definition at line 5636 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_CSMACA_ENA_Pos

#define FTDF_FTDF_TX_META_DATA_0_0_REG_CSMACA_ENA_Pos   (26UL)

FTDF FTDF_TX_META_DATA_0_0_REG: CSMACA_ENA (Bit 26)

Definition at line 5635 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_FRAME_LENGTH_Msk

#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAME_LENGTH_Msk   (0x7fUL)

FTDF FTDF_TX_META_DATA_0_0_REG: FRAME_LENGTH (Bitfield-Mask: 0x7f)

Definition at line 5622 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_FRAME_LENGTH_Pos

#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAME_LENGTH_Pos   (0UL)

FTDF FTDF_TX_META_DATA_0_0_REG: FRAME_LENGTH (Bit 0)

Definition at line 5621 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_FRAMETYPE_Msk

#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAMETYPE_Msk   (0x3800000UL)

FTDF FTDF_TX_META_DATA_0_0_REG: FRAMETYPE (Bitfield-Mask: 0x07)

Definition at line 5634 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_FRAMETYPE_Pos

#define FTDF_FTDF_TX_META_DATA_0_0_REG_FRAMETYPE_Pos   (23UL)

FTDF FTDF_TX_META_DATA_0_0_REG: FRAMETYPE (Bit 23)

Definition at line 5633 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CALCAP_Msk

#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CALCAP_Msk   (0x78000UL)

FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_CALCAP (Bitfield-Mask: 0x0f)

Definition at line 5628 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CALCAP_Pos

#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CALCAP_Pos   (15UL)

FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_CALCAP (Bit 15)

Definition at line 5627 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CN_Msk

#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CN_Msk   (0x7800UL)

FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_CN (Bitfield-Mask: 0x0f)

Definition at line 5626 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CN_Pos

#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_CN_Pos   (11UL)

FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_CN (Bit 11)

Definition at line 5625 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_DEM_PTI_Msk

#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_DEM_PTI_Msk   (0x780UL)

FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_DEM_PTI (Bitfield-Mask: 0x0f)

Definition at line 5624 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_DEM_PTI_Pos

#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_DEM_PTI_Pos   (7UL)

FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_DEM_PTI (Bit 7)

Definition at line 5623 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_HSI_Msk

#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_HSI_Msk   (0x400000UL)

FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_HSI (Bitfield-Mask: 0x01)

Definition at line 5632 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_HSI_Pos

#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_HSI_Pos   (22UL)

FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_HSI (Bit 22)

Definition at line 5631 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_RF_GPIO_PINS_Msk

#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_RF_GPIO_PINS_Msk   (0x380000UL)

FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07)

Definition at line 5630 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_RF_GPIO_PINS_Pos

#define FTDF_FTDF_TX_META_DATA_0_0_REG_PHYATTR_RF_GPIO_PINS_Pos   (19UL)

FTDF FTDF_TX_META_DATA_0_0_REG: PHYATTR_RF_GPIO_PINS (Bit 19)

Definition at line 5629 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_ACKREQUEST_Msk

#define FTDF_FTDF_TX_META_DATA_0_1_REG_ACKREQUEST_Msk   (0x10000000UL)

FTDF FTDF_TX_META_DATA_0_1_REG: ACKREQUEST (Bitfield-Mask: 0x01)

Definition at line 5664 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_ACKREQUEST_Pos

#define FTDF_FTDF_TX_META_DATA_0_1_REG_ACKREQUEST_Pos   (28UL)

FTDF FTDF_TX_META_DATA_0_1_REG: ACKREQUEST (Bit 28)

Definition at line 5663 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_CRC16_ENA_Msk

#define FTDF_FTDF_TX_META_DATA_0_1_REG_CRC16_ENA_Msk   (0x40000000UL)

FTDF FTDF_TX_META_DATA_0_1_REG: CRC16_ENA (Bitfield-Mask: 0x01)

Definition at line 5666 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_CRC16_ENA_Pos

#define FTDF_FTDF_TX_META_DATA_0_1_REG_CRC16_ENA_Pos   (30UL)

FTDF FTDF_TX_META_DATA_0_1_REG: CRC16_ENA (Bit 30)

Definition at line 5665 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_CSMACA_ENA_Msk

#define FTDF_FTDF_TX_META_DATA_0_1_REG_CSMACA_ENA_Msk   (0x4000000UL)

FTDF FTDF_TX_META_DATA_0_1_REG: CSMACA_ENA (Bitfield-Mask: 0x01)

Definition at line 5662 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_CSMACA_ENA_Pos

#define FTDF_FTDF_TX_META_DATA_0_1_REG_CSMACA_ENA_Pos   (26UL)

FTDF FTDF_TX_META_DATA_0_1_REG: CSMACA_ENA (Bit 26)

Definition at line 5661 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_FRAME_LENGTH_Msk

#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAME_LENGTH_Msk   (0x7fUL)

FTDF FTDF_TX_META_DATA_0_1_REG: FRAME_LENGTH (Bitfield-Mask: 0x7f)

Definition at line 5648 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_FRAME_LENGTH_Pos

#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAME_LENGTH_Pos   (0UL)

FTDF FTDF_TX_META_DATA_0_1_REG: FRAME_LENGTH (Bit 0)

Definition at line 5647 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_FRAMETYPE_Msk

#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAMETYPE_Msk   (0x3800000UL)

FTDF FTDF_TX_META_DATA_0_1_REG: FRAMETYPE (Bitfield-Mask: 0x07)

Definition at line 5660 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_FRAMETYPE_Pos

#define FTDF_FTDF_TX_META_DATA_0_1_REG_FRAMETYPE_Pos   (23UL)

FTDF FTDF_TX_META_DATA_0_1_REG: FRAMETYPE (Bit 23)

Definition at line 5659 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CALCAP_Msk

#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CALCAP_Msk   (0x78000UL)

FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_CALCAP (Bitfield-Mask: 0x0f)

Definition at line 5654 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CALCAP_Pos

#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CALCAP_Pos   (15UL)

FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_CALCAP (Bit 15)

Definition at line 5653 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CN_Msk

#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CN_Msk   (0x7800UL)

FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_CN (Bitfield-Mask: 0x0f)

Definition at line 5652 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CN_Pos

#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_CN_Pos   (11UL)

FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_CN (Bit 11)

Definition at line 5651 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_DEM_PTI_Msk

#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_DEM_PTI_Msk   (0x780UL)

FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_DEM_PTI (Bitfield-Mask: 0x0f)

Definition at line 5650 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_DEM_PTI_Pos

#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_DEM_PTI_Pos   (7UL)

FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_DEM_PTI (Bit 7)

Definition at line 5649 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_HSI_Msk

#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_HSI_Msk   (0x400000UL)

FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_HSI (Bitfield-Mask: 0x01)

Definition at line 5658 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_HSI_Pos

#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_HSI_Pos   (22UL)

FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_HSI (Bit 22)

Definition at line 5657 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_RF_GPIO_PINS_Msk

#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_RF_GPIO_PINS_Msk   (0x380000UL)

FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07)

Definition at line 5656 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_RF_GPIO_PINS_Pos

#define FTDF_FTDF_TX_META_DATA_0_1_REG_PHYATTR_RF_GPIO_PINS_Pos   (19UL)

FTDF FTDF_TX_META_DATA_0_1_REG: PHYATTR_RF_GPIO_PINS (Bit 19)

Definition at line 5655 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_ACKREQUEST_Msk

#define FTDF_FTDF_TX_META_DATA_0_2_REG_ACKREQUEST_Msk   (0x10000000UL)

FTDF FTDF_TX_META_DATA_0_2_REG: ACKREQUEST (Bitfield-Mask: 0x01)

Definition at line 5690 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_ACKREQUEST_Pos

#define FTDF_FTDF_TX_META_DATA_0_2_REG_ACKREQUEST_Pos   (28UL)

FTDF FTDF_TX_META_DATA_0_2_REG: ACKREQUEST (Bit 28)

Definition at line 5689 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_CRC16_ENA_Msk

#define FTDF_FTDF_TX_META_DATA_0_2_REG_CRC16_ENA_Msk   (0x40000000UL)

FTDF FTDF_TX_META_DATA_0_2_REG: CRC16_ENA (Bitfield-Mask: 0x01)

Definition at line 5692 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_CRC16_ENA_Pos

#define FTDF_FTDF_TX_META_DATA_0_2_REG_CRC16_ENA_Pos   (30UL)

FTDF FTDF_TX_META_DATA_0_2_REG: CRC16_ENA (Bit 30)

Definition at line 5691 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_CSMACA_ENA_Msk

#define FTDF_FTDF_TX_META_DATA_0_2_REG_CSMACA_ENA_Msk   (0x4000000UL)

FTDF FTDF_TX_META_DATA_0_2_REG: CSMACA_ENA (Bitfield-Mask: 0x01)

Definition at line 5688 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_CSMACA_ENA_Pos

#define FTDF_FTDF_TX_META_DATA_0_2_REG_CSMACA_ENA_Pos   (26UL)

FTDF FTDF_TX_META_DATA_0_2_REG: CSMACA_ENA (Bit 26)

Definition at line 5687 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_FRAME_LENGTH_Msk

#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAME_LENGTH_Msk   (0x7fUL)

FTDF FTDF_TX_META_DATA_0_2_REG: FRAME_LENGTH (Bitfield-Mask: 0x7f)

Definition at line 5674 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_FRAME_LENGTH_Pos

#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAME_LENGTH_Pos   (0UL)

FTDF FTDF_TX_META_DATA_0_2_REG: FRAME_LENGTH (Bit 0)

Definition at line 5673 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_FRAMETYPE_Msk

#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAMETYPE_Msk   (0x3800000UL)

FTDF FTDF_TX_META_DATA_0_2_REG: FRAMETYPE (Bitfield-Mask: 0x07)

Definition at line 5686 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_FRAMETYPE_Pos

#define FTDF_FTDF_TX_META_DATA_0_2_REG_FRAMETYPE_Pos   (23UL)

FTDF FTDF_TX_META_DATA_0_2_REG: FRAMETYPE (Bit 23)

Definition at line 5685 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CALCAP_Msk

#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CALCAP_Msk   (0x78000UL)

FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_CALCAP (Bitfield-Mask: 0x0f)

Definition at line 5680 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CALCAP_Pos

#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CALCAP_Pos   (15UL)

FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_CALCAP (Bit 15)

Definition at line 5679 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CN_Msk

#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CN_Msk   (0x7800UL)

FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_CN (Bitfield-Mask: 0x0f)

Definition at line 5678 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CN_Pos

#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_CN_Pos   (11UL)

FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_CN (Bit 11)

Definition at line 5677 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_DEM_PTI_Msk

#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_DEM_PTI_Msk   (0x780UL)

FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_DEM_PTI (Bitfield-Mask: 0x0f)

Definition at line 5676 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_DEM_PTI_Pos

#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_DEM_PTI_Pos   (7UL)

FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_DEM_PTI (Bit 7)

Definition at line 5675 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_HSI_Msk

#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_HSI_Msk   (0x400000UL)

FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_HSI (Bitfield-Mask: 0x01)

Definition at line 5684 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_HSI_Pos

#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_HSI_Pos   (22UL)

FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_HSI (Bit 22)

Definition at line 5683 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_RF_GPIO_PINS_Msk

#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_RF_GPIO_PINS_Msk   (0x380000UL)

FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07)

Definition at line 5682 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_RF_GPIO_PINS_Pos

#define FTDF_FTDF_TX_META_DATA_0_2_REG_PHYATTR_RF_GPIO_PINS_Pos   (19UL)

FTDF FTDF_TX_META_DATA_0_2_REG: PHYATTR_RF_GPIO_PINS (Bit 19)

Definition at line 5681 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_ACKREQUEST_Msk

#define FTDF_FTDF_TX_META_DATA_0_3_REG_ACKREQUEST_Msk   (0x10000000UL)

FTDF FTDF_TX_META_DATA_0_3_REG: ACKREQUEST (Bitfield-Mask: 0x01)

Definition at line 5716 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_ACKREQUEST_Pos

#define FTDF_FTDF_TX_META_DATA_0_3_REG_ACKREQUEST_Pos   (28UL)

FTDF FTDF_TX_META_DATA_0_3_REG: ACKREQUEST (Bit 28)

Definition at line 5715 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_CRC16_ENA_Msk

#define FTDF_FTDF_TX_META_DATA_0_3_REG_CRC16_ENA_Msk   (0x40000000UL)

FTDF FTDF_TX_META_DATA_0_3_REG: CRC16_ENA (Bitfield-Mask: 0x01)

Definition at line 5718 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_CRC16_ENA_Pos

#define FTDF_FTDF_TX_META_DATA_0_3_REG_CRC16_ENA_Pos   (30UL)

FTDF FTDF_TX_META_DATA_0_3_REG: CRC16_ENA (Bit 30)

Definition at line 5717 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_CSMACA_ENA_Msk

#define FTDF_FTDF_TX_META_DATA_0_3_REG_CSMACA_ENA_Msk   (0x4000000UL)

FTDF FTDF_TX_META_DATA_0_3_REG: CSMACA_ENA (Bitfield-Mask: 0x01)

Definition at line 5714 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_CSMACA_ENA_Pos

#define FTDF_FTDF_TX_META_DATA_0_3_REG_CSMACA_ENA_Pos   (26UL)

FTDF FTDF_TX_META_DATA_0_3_REG: CSMACA_ENA (Bit 26)

Definition at line 5713 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_FRAME_LENGTH_Msk

#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAME_LENGTH_Msk   (0x7fUL)

FTDF FTDF_TX_META_DATA_0_3_REG: FRAME_LENGTH (Bitfield-Mask: 0x7f)

Definition at line 5700 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_FRAME_LENGTH_Pos

#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAME_LENGTH_Pos   (0UL)

FTDF FTDF_TX_META_DATA_0_3_REG: FRAME_LENGTH (Bit 0)

Definition at line 5699 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_FRAMETYPE_Msk

#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAMETYPE_Msk   (0x3800000UL)

FTDF FTDF_TX_META_DATA_0_3_REG: FRAMETYPE (Bitfield-Mask: 0x07)

Definition at line 5712 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_FRAMETYPE_Pos

#define FTDF_FTDF_TX_META_DATA_0_3_REG_FRAMETYPE_Pos   (23UL)

FTDF FTDF_TX_META_DATA_0_3_REG: FRAMETYPE (Bit 23)

Definition at line 5711 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CALCAP_Msk

#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CALCAP_Msk   (0x78000UL)

FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_CALCAP (Bitfield-Mask: 0x0f)

Definition at line 5706 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CALCAP_Pos

#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CALCAP_Pos   (15UL)

FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_CALCAP (Bit 15)

Definition at line 5705 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CN_Msk

#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CN_Msk   (0x7800UL)

FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_CN (Bitfield-Mask: 0x0f)

Definition at line 5704 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CN_Pos

#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_CN_Pos   (11UL)

FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_CN (Bit 11)

Definition at line 5703 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_DEM_PTI_Msk

#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_DEM_PTI_Msk   (0x780UL)

FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_DEM_PTI (Bitfield-Mask: 0x0f)

Definition at line 5702 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_DEM_PTI_Pos

#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_DEM_PTI_Pos   (7UL)

FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_DEM_PTI (Bit 7)

Definition at line 5701 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_HSI_Msk

#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_HSI_Msk   (0x400000UL)

FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_HSI (Bitfield-Mask: 0x01)

Definition at line 5710 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_HSI_Pos

#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_HSI_Pos   (22UL)

FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_HSI (Bit 22)

Definition at line 5709 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_RF_GPIO_PINS_Msk

#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_RF_GPIO_PINS_Msk   (0x380000UL)

FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_RF_GPIO_PINS (Bitfield-Mask: 0x07)

Definition at line 5708 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_RF_GPIO_PINS_Pos

#define FTDF_FTDF_TX_META_DATA_0_3_REG_PHYATTR_RF_GPIO_PINS_Pos   (19UL)

FTDF FTDF_TX_META_DATA_0_3_REG: PHYATTR_RF_GPIO_PINS (Bit 19)

Definition at line 5707 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_1_0_REG_MACSN_Msk

#define FTDF_FTDF_TX_META_DATA_1_0_REG_MACSN_Msk   (0xffUL)

FTDF FTDF_TX_META_DATA_1_0_REG: MACSN (Bitfield-Mask: 0xff)

Definition at line 5644 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_1_0_REG_MACSN_Pos

#define FTDF_FTDF_TX_META_DATA_1_0_REG_MACSN_Pos   (0UL)

FTDF FTDF_TX_META_DATA_1_0_REG: MACSN (Bit 0)

Definition at line 5643 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_1_1_REG_MACSN_Msk

#define FTDF_FTDF_TX_META_DATA_1_1_REG_MACSN_Msk   (0xffUL)

FTDF FTDF_TX_META_DATA_1_1_REG: MACSN (Bitfield-Mask: 0xff)

Definition at line 5670 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_1_1_REG_MACSN_Pos

#define FTDF_FTDF_TX_META_DATA_1_1_REG_MACSN_Pos   (0UL)

FTDF FTDF_TX_META_DATA_1_1_REG: MACSN (Bit 0)

Definition at line 5669 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_1_2_REG_MACSN_Msk

#define FTDF_FTDF_TX_META_DATA_1_2_REG_MACSN_Msk   (0xffUL)

FTDF FTDF_TX_META_DATA_1_2_REG: MACSN (Bitfield-Mask: 0xff)

Definition at line 5696 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_1_2_REG_MACSN_Pos

#define FTDF_FTDF_TX_META_DATA_1_2_REG_MACSN_Pos   (0UL)

FTDF FTDF_TX_META_DATA_1_2_REG: MACSN (Bit 0)

Definition at line 5695 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_1_3_REG_MACSN_Msk

#define FTDF_FTDF_TX_META_DATA_1_3_REG_MACSN_Msk   (0xffUL)

FTDF FTDF_TX_META_DATA_1_3_REG: MACSN (Bitfield-Mask: 0xff)

Definition at line 5722 of file DA14680BA.h.

◆ FTDF_FTDF_TX_META_DATA_1_3_REG_MACSN_Pos

#define FTDF_FTDF_TX_META_DATA_1_3_REG_MACSN_Pos   (0UL)

FTDF FTDF_TX_META_DATA_1_3_REG: MACSN (Bit 0)

Definition at line 5721 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_0_REG_ISWAKEUP_Msk

#define FTDF_FTDF_TX_PRIORITY_0_REG_ISWAKEUP_Msk   (0x10UL)

FTDF FTDF_TX_PRIORITY_0_REG: ISWAKEUP (Bitfield-Mask: 0x01)

Definition at line 6638 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_0_REG_ISWAKEUP_Pos

#define FTDF_FTDF_TX_PRIORITY_0_REG_ISWAKEUP_Pos   (4UL)

FTDF FTDF_TX_PRIORITY_0_REG: ISWAKEUP (Bit 4)

Definition at line 6637 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_0_REG_PTI_TX_Msk

#define FTDF_FTDF_TX_PRIORITY_0_REG_PTI_TX_Msk   (0xf00UL)

FTDF FTDF_TX_PRIORITY_0_REG: PTI_TX (Bitfield-Mask: 0x0f)

Definition at line 6640 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_0_REG_PTI_TX_Pos

#define FTDF_FTDF_TX_PRIORITY_0_REG_PTI_TX_Pos   (8UL)

FTDF FTDF_TX_PRIORITY_0_REG: PTI_TX (Bit 8)

Definition at line 6639 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_0_REG_TX_PRIORITY_Msk

#define FTDF_FTDF_TX_PRIORITY_0_REG_TX_PRIORITY_Msk   (0xfUL)

FTDF FTDF_TX_PRIORITY_0_REG: TX_PRIORITY (Bitfield-Mask: 0x0f)

Definition at line 6636 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_0_REG_TX_PRIORITY_Pos

#define FTDF_FTDF_TX_PRIORITY_0_REG_TX_PRIORITY_Pos   (0UL)

FTDF FTDF_TX_PRIORITY_0_REG: TX_PRIORITY (Bit 0)

Definition at line 6635 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_1_REG_ISWAKEUP_Msk

#define FTDF_FTDF_TX_PRIORITY_1_REG_ISWAKEUP_Msk   (0x10UL)

FTDF FTDF_TX_PRIORITY_1_REG: ISWAKEUP (Bitfield-Mask: 0x01)

Definition at line 6658 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_1_REG_ISWAKEUP_Pos

#define FTDF_FTDF_TX_PRIORITY_1_REG_ISWAKEUP_Pos   (4UL)

FTDF FTDF_TX_PRIORITY_1_REG: ISWAKEUP (Bit 4)

Definition at line 6657 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_1_REG_PTI_TX_Msk

#define FTDF_FTDF_TX_PRIORITY_1_REG_PTI_TX_Msk   (0xf00UL)

FTDF FTDF_TX_PRIORITY_1_REG: PTI_TX (Bitfield-Mask: 0x0f)

Definition at line 6660 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_1_REG_PTI_TX_Pos

#define FTDF_FTDF_TX_PRIORITY_1_REG_PTI_TX_Pos   (8UL)

FTDF FTDF_TX_PRIORITY_1_REG: PTI_TX (Bit 8)

Definition at line 6659 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_1_REG_TX_PRIORITY_Msk

#define FTDF_FTDF_TX_PRIORITY_1_REG_TX_PRIORITY_Msk   (0xfUL)

FTDF FTDF_TX_PRIORITY_1_REG: TX_PRIORITY (Bitfield-Mask: 0x0f)

Definition at line 6656 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_1_REG_TX_PRIORITY_Pos

#define FTDF_FTDF_TX_PRIORITY_1_REG_TX_PRIORITY_Pos   (0UL)

FTDF FTDF_TX_PRIORITY_1_REG: TX_PRIORITY (Bit 0)

Definition at line 6655 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_2_REG_ISWAKEUP_Msk

#define FTDF_FTDF_TX_PRIORITY_2_REG_ISWAKEUP_Msk   (0x10UL)

FTDF FTDF_TX_PRIORITY_2_REG: ISWAKEUP (Bitfield-Mask: 0x01)

Definition at line 6678 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_2_REG_ISWAKEUP_Pos

#define FTDF_FTDF_TX_PRIORITY_2_REG_ISWAKEUP_Pos   (4UL)

FTDF FTDF_TX_PRIORITY_2_REG: ISWAKEUP (Bit 4)

Definition at line 6677 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_2_REG_PTI_TX_Msk

#define FTDF_FTDF_TX_PRIORITY_2_REG_PTI_TX_Msk   (0xf00UL)

FTDF FTDF_TX_PRIORITY_2_REG: PTI_TX (Bitfield-Mask: 0x0f)

Definition at line 6680 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_2_REG_PTI_TX_Pos

#define FTDF_FTDF_TX_PRIORITY_2_REG_PTI_TX_Pos   (8UL)

FTDF FTDF_TX_PRIORITY_2_REG: PTI_TX (Bit 8)

Definition at line 6679 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_2_REG_TX_PRIORITY_Msk

#define FTDF_FTDF_TX_PRIORITY_2_REG_TX_PRIORITY_Msk   (0xfUL)

FTDF FTDF_TX_PRIORITY_2_REG: TX_PRIORITY (Bitfield-Mask: 0x0f)

Definition at line 6676 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_2_REG_TX_PRIORITY_Pos

#define FTDF_FTDF_TX_PRIORITY_2_REG_TX_PRIORITY_Pos   (0UL)

FTDF FTDF_TX_PRIORITY_2_REG: TX_PRIORITY (Bit 0)

Definition at line 6675 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_3_REG_ISWAKEUP_Msk

#define FTDF_FTDF_TX_PRIORITY_3_REG_ISWAKEUP_Msk   (0x10UL)

FTDF FTDF_TX_PRIORITY_3_REG: ISWAKEUP (Bitfield-Mask: 0x01)

Definition at line 6698 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_3_REG_ISWAKEUP_Pos

#define FTDF_FTDF_TX_PRIORITY_3_REG_ISWAKEUP_Pos   (4UL)

FTDF FTDF_TX_PRIORITY_3_REG: ISWAKEUP (Bit 4)

Definition at line 6697 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_3_REG_PTI_TX_Msk

#define FTDF_FTDF_TX_PRIORITY_3_REG_PTI_TX_Msk   (0xf00UL)

FTDF FTDF_TX_PRIORITY_3_REG: PTI_TX (Bitfield-Mask: 0x0f)

Definition at line 6700 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_3_REG_PTI_TX_Pos

#define FTDF_FTDF_TX_PRIORITY_3_REG_PTI_TX_Pos   (8UL)

FTDF FTDF_TX_PRIORITY_3_REG: PTI_TX (Bit 8)

Definition at line 6699 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_3_REG_TX_PRIORITY_Msk

#define FTDF_FTDF_TX_PRIORITY_3_REG_TX_PRIORITY_Msk   (0xfUL)

FTDF FTDF_TX_PRIORITY_3_REG: TX_PRIORITY (Bitfield-Mask: 0x0f)

Definition at line 6696 of file DA14680BA.h.

◆ FTDF_FTDF_TX_PRIORITY_3_REG_TX_PRIORITY_Pos

#define FTDF_FTDF_TX_PRIORITY_3_REG_TX_PRIORITY_Pos   (0UL)

FTDF FTDF_TX_PRIORITY_3_REG: TX_PRIORITY (Bit 0)

Definition at line 6695 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_0_0_REG_TXTIMESTAMP_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_0_0_REG_TXTIMESTAMP_Msk   (0xffffffffUL)

FTDF FTDF_TX_RETURN_STATUS_0_0_REG: TXTIMESTAMP (Bitfield-Mask: 0xffffffff)

Definition at line 5726 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_0_0_REG_TXTIMESTAMP_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_0_0_REG_TXTIMESTAMP_Pos   (0UL)

FTDF FTDF_TX_RETURN_STATUS_0_0_REG: TXTIMESTAMP (Bit 0)

Definition at line 5725 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_0_1_REG_TXTIMESTAMP_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_0_1_REG_TXTIMESTAMP_Msk   (0xffffffffUL)

FTDF FTDF_TX_RETURN_STATUS_0_1_REG: TXTIMESTAMP (Bitfield-Mask: 0xffffffff)

Definition at line 5738 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_0_1_REG_TXTIMESTAMP_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_0_1_REG_TXTIMESTAMP_Pos   (0UL)

FTDF FTDF_TX_RETURN_STATUS_0_1_REG: TXTIMESTAMP (Bit 0)

Definition at line 5737 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_0_2_REG_TXTIMESTAMP_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_0_2_REG_TXTIMESTAMP_Msk   (0xffffffffUL)

FTDF FTDF_TX_RETURN_STATUS_0_2_REG: TXTIMESTAMP (Bitfield-Mask: 0xffffffff)

Definition at line 5750 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_0_2_REG_TXTIMESTAMP_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_0_2_REG_TXTIMESTAMP_Pos   (0UL)

FTDF FTDF_TX_RETURN_STATUS_0_2_REG: TXTIMESTAMP (Bit 0)

Definition at line 5749 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_0_3_REG_TXTIMESTAMP_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_0_3_REG_TXTIMESTAMP_Msk   (0xffffffffUL)

FTDF FTDF_TX_RETURN_STATUS_0_3_REG: TXTIMESTAMP (Bitfield-Mask: 0xffffffff)

Definition at line 5762 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_0_3_REG_TXTIMESTAMP_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_0_3_REG_TXTIMESTAMP_Pos   (0UL)

FTDF FTDF_TX_RETURN_STATUS_0_3_REG: TXTIMESTAMP (Bit 0)

Definition at line 5761 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_ACKFAIL_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_ACKFAIL_Msk   (0x1UL)

FTDF FTDF_TX_RETURN_STATUS_1_0_REG: ACKFAIL (Bitfield-Mask: 0x01)

Definition at line 5730 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_ACKFAIL_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_ACKFAIL_Pos   (0UL)

FTDF FTDF_TX_RETURN_STATUS_1_0_REG: ACKFAIL (Bit 0)

Definition at line 5729 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACAFAIL_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACAFAIL_Msk   (0x2UL)

FTDF FTDF_TX_RETURN_STATUS_1_0_REG: CSMACAFAIL (Bitfield-Mask: 0x01)

Definition at line 5732 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACAFAIL_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACAFAIL_Pos   (1UL)

FTDF FTDF_TX_RETURN_STATUS_1_0_REG: CSMACAFAIL (Bit 1)

Definition at line 5731 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACANRRETRIES_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACANRRETRIES_Msk   (0x1cUL)

FTDF FTDF_TX_RETURN_STATUS_1_0_REG: CSMACANRRETRIES (Bitfield-Mask: 0x07)

Definition at line 5734 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACANRRETRIES_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_1_0_REG_CSMACANRRETRIES_Pos   (2UL)

FTDF FTDF_TX_RETURN_STATUS_1_0_REG: CSMACANRRETRIES (Bit 2)

Definition at line 5733 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_ACKFAIL_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_ACKFAIL_Msk   (0x1UL)

FTDF FTDF_TX_RETURN_STATUS_1_1_REG: ACKFAIL (Bitfield-Mask: 0x01)

Definition at line 5742 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_ACKFAIL_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_ACKFAIL_Pos   (0UL)

FTDF FTDF_TX_RETURN_STATUS_1_1_REG: ACKFAIL (Bit 0)

Definition at line 5741 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACAFAIL_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACAFAIL_Msk   (0x2UL)

FTDF FTDF_TX_RETURN_STATUS_1_1_REG: CSMACAFAIL (Bitfield-Mask: 0x01)

Definition at line 5744 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACAFAIL_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACAFAIL_Pos   (1UL)

FTDF FTDF_TX_RETURN_STATUS_1_1_REG: CSMACAFAIL (Bit 1)

Definition at line 5743 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACANRRETRIES_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACANRRETRIES_Msk   (0x1cUL)

FTDF FTDF_TX_RETURN_STATUS_1_1_REG: CSMACANRRETRIES (Bitfield-Mask: 0x07)

Definition at line 5746 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACANRRETRIES_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_1_1_REG_CSMACANRRETRIES_Pos   (2UL)

FTDF FTDF_TX_RETURN_STATUS_1_1_REG: CSMACANRRETRIES (Bit 2)

Definition at line 5745 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_ACKFAIL_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_ACKFAIL_Msk   (0x1UL)

FTDF FTDF_TX_RETURN_STATUS_1_2_REG: ACKFAIL (Bitfield-Mask: 0x01)

Definition at line 5754 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_ACKFAIL_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_ACKFAIL_Pos   (0UL)

FTDF FTDF_TX_RETURN_STATUS_1_2_REG: ACKFAIL (Bit 0)

Definition at line 5753 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACAFAIL_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACAFAIL_Msk   (0x2UL)

FTDF FTDF_TX_RETURN_STATUS_1_2_REG: CSMACAFAIL (Bitfield-Mask: 0x01)

Definition at line 5756 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACAFAIL_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACAFAIL_Pos   (1UL)

FTDF FTDF_TX_RETURN_STATUS_1_2_REG: CSMACAFAIL (Bit 1)

Definition at line 5755 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACANRRETRIES_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACANRRETRIES_Msk   (0x1cUL)

FTDF FTDF_TX_RETURN_STATUS_1_2_REG: CSMACANRRETRIES (Bitfield-Mask: 0x07)

Definition at line 5758 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACANRRETRIES_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_1_2_REG_CSMACANRRETRIES_Pos   (2UL)

FTDF FTDF_TX_RETURN_STATUS_1_2_REG: CSMACANRRETRIES (Bit 2)

Definition at line 5757 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_ACKFAIL_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_ACKFAIL_Msk   (0x1UL)

FTDF FTDF_TX_RETURN_STATUS_1_3_REG: ACKFAIL (Bitfield-Mask: 0x01)

Definition at line 5766 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_ACKFAIL_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_ACKFAIL_Pos   (0UL)

FTDF FTDF_TX_RETURN_STATUS_1_3_REG: ACKFAIL (Bit 0)

Definition at line 5765 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACAFAIL_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACAFAIL_Msk   (0x2UL)

FTDF FTDF_TX_RETURN_STATUS_1_3_REG: CSMACAFAIL (Bitfield-Mask: 0x01)

Definition at line 5768 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACAFAIL_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACAFAIL_Pos   (1UL)

FTDF FTDF_TX_RETURN_STATUS_1_3_REG: CSMACAFAIL (Bit 1)

Definition at line 5767 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACANRRETRIES_Msk

#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACANRRETRIES_Msk   (0x1cUL)

FTDF FTDF_TX_RETURN_STATUS_1_3_REG: CSMACANRRETRIES (Bitfield-Mask: 0x07)

Definition at line 5770 of file DA14680BA.h.

◆ FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACANRRETRIES_Pos

#define FTDF_FTDF_TX_RETURN_STATUS_1_3_REG_CSMACANRRETRIES_Pos   (2UL)

FTDF FTDF_TX_RETURN_STATUS_1_3_REG: CSMACANRRETRIES (Bit 2)

Definition at line 5769 of file DA14680BA.h.

◆ FTDF_FTDF_TX_SET_OS_REG_TX_FLAG_SET_Msk

#define FTDF_FTDF_TX_SET_OS_REG_TX_FLAG_SET_Msk   (0xfUL)

FTDF FTDF_TX_SET_OS_REG: TX_FLAG_SET (Bitfield-Mask: 0x0f)

Definition at line 6704 of file DA14680BA.h.

◆ FTDF_FTDF_TX_SET_OS_REG_TX_FLAG_SET_Pos

#define FTDF_FTDF_TX_SET_OS_REG_TX_FLAG_SET_Pos   (0UL)

FTDF FTDF_TX_SET_OS_REG: TX_FLAG_SET (Bit 0)

Definition at line 6703 of file DA14680BA.h.

◆ FTDF_FTDF_TXBYTE_E_REG_TX_LAST_SYMBOL_E_Msk

#define FTDF_FTDF_TXBYTE_E_REG_TX_LAST_SYMBOL_E_Msk   (0x2UL)

FTDF FTDF_TXBYTE_E_REG: TX_LAST_SYMBOL_E (Bitfield-Mask: 0x01)

Definition at line 6614 of file DA14680BA.h.

◆ FTDF_FTDF_TXBYTE_E_REG_TX_LAST_SYMBOL_E_Pos

#define FTDF_FTDF_TXBYTE_E_REG_TX_LAST_SYMBOL_E_Pos   (1UL)

FTDF FTDF_TXBYTE_E_REG: TX_LAST_SYMBOL_E (Bit 1)

Definition at line 6613 of file DA14680BA.h.

◆ FTDF_FTDF_TXBYTE_E_REG_TXBYTE_E_Msk

#define FTDF_FTDF_TXBYTE_E_REG_TXBYTE_E_Msk   (0x1UL)

FTDF FTDF_TXBYTE_E_REG: TXBYTE_E (Bitfield-Mask: 0x01)

Definition at line 6612 of file DA14680BA.h.

◆ FTDF_FTDF_TXBYTE_E_REG_TXBYTE_E_Pos

#define FTDF_FTDF_TXBYTE_E_REG_TXBYTE_E_Pos   (0UL)

FTDF FTDF_TXBYTE_E_REG: TXBYTE_E (Bit 0)

Definition at line 6611 of file DA14680BA.h.

◆ FTDF_FTDF_TXBYTE_M_REG_TX_LAST_SYMBOL_M_Msk

#define FTDF_FTDF_TXBYTE_M_REG_TX_LAST_SYMBOL_M_Msk   (0x2UL)

FTDF FTDF_TXBYTE_M_REG: TX_LAST_SYMBOL_M (Bitfield-Mask: 0x01)

Definition at line 6620 of file DA14680BA.h.

◆ FTDF_FTDF_TXBYTE_M_REG_TX_LAST_SYMBOL_M_Pos

#define FTDF_FTDF_TXBYTE_M_REG_TX_LAST_SYMBOL_M_Pos   (1UL)

FTDF FTDF_TXBYTE_M_REG: TX_LAST_SYMBOL_M (Bit 1)

Definition at line 6619 of file DA14680BA.h.

◆ FTDF_FTDF_TXBYTE_M_REG_TXBYTE_M_Msk

#define FTDF_FTDF_TXBYTE_M_REG_TXBYTE_M_Msk   (0x1UL)

FTDF FTDF_TXBYTE_M_REG: TXBYTE_M (Bitfield-Mask: 0x01)

Definition at line 6618 of file DA14680BA.h.

◆ FTDF_FTDF_TXBYTE_M_REG_TXBYTE_M_Pos

#define FTDF_FTDF_TXBYTE_M_REG_TXBYTE_M_Pos   (0UL)

FTDF FTDF_TXBYTE_M_REG: TXBYTE_M (Bit 0)

Definition at line 6617 of file DA14680BA.h.

◆ FTDF_FTDF_TXPIPEPROPDELAY_REG_TXPIPEPROPDELAY_Msk

#define FTDF_FTDF_TXPIPEPROPDELAY_REG_TXPIPEPROPDELAY_Msk   (0xffUL)

FTDF FTDF_TXPIPEPROPDELAY_REG: TXPIPEPROPDELAY (Bitfield-Mask: 0xff)

Definition at line 6052 of file DA14680BA.h.

◆ FTDF_FTDF_TXPIPEPROPDELAY_REG_TXPIPEPROPDELAY_Pos

#define FTDF_FTDF_TXPIPEPROPDELAY_REG_TXPIPEPROPDELAY_Pos   (0UL)

FTDF FTDF_TXPIPEPROPDELAY_REG: TXPIPEPROPDELAY (Bit 0)

Definition at line 6051 of file DA14680BA.h.

◆ FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_CLEAR_Msk

#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_CLEAR_Msk   (0x2UL)

FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_CLEAR (Bitfield-Mask: 0x01)

Definition at line 6596 of file DA14680BA.h.

◆ FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_CLEAR_Pos

#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_CLEAR_Pos   (1UL)

FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_CLEAR (Bit 1)

Definition at line 6595 of file DA14680BA.h.

◆ FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_SET_Msk

#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_SET_Msk   (0x1UL)

FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_SET (Bitfield-Mask: 0x01)

Definition at line 6594 of file DA14680BA.h.

◆ FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_SET_Pos

#define FTDF_FTDF_WAKEUP_CONTROL_OS_REG_WAKEUPTIMERENABLE_SET_Pos   (0UL)

FTDF FTDF_WAKEUP_CONTROL_OS_REG: WAKEUPTIMERENABLE_SET (Bit 0)

Definition at line 6593 of file DA14680BA.h.

◆ FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUP_MODE_Msk

#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUP_MODE_Msk   (0xc0000000UL)

FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUP_MODE (Bitfield-Mask: 0x03)

Definition at line 6716 of file DA14680BA.h.

◆ FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUP_MODE_Pos

#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUP_MODE_Pos   (30UL)

FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUP_MODE (Bit 30)

Definition at line 6715 of file DA14680BA.h.

◆ FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Msk

#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Msk   (0x20000000UL)

FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPENABLE (Bitfield-Mask: 0x01)

Definition at line 6714 of file DA14680BA.h.

◆ FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Pos

#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPENABLE_Pos   (29UL)

FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPENABLE (Bit 29)

Definition at line 6713 of file DA14680BA.h.

◆ FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPINTTHR_Msk

#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPINTTHR_Msk   (0x1ffffffUL)

FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPINTTHR (Bitfield-Mask: 0x1ffffff)

Definition at line 6712 of file DA14680BA.h.

◆ FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPINTTHR_Pos

#define FTDF_FTDF_WAKEUP_CONTROL_REG_WAKEUPINTTHR_Pos   (0UL)

FTDF FTDF_WAKEUP_CONTROL_REG: WAKEUPINTTHR (Bit 0)

Definition at line 6711 of file DA14680BA.h.

◆ GP_TIMERS

#define GP_TIMERS   ((GP_TIMERS_Type *) GP_TIMERS_BASE)

Definition at line 12087 of file DA14680BA.h.

◆ GP_TIMERS_BASE

#define GP_TIMERS_BASE   0x50003400UL

Definition at line 12042 of file DA14680BA.h.

◆ GP_TIMERS_BREATH_CFG_REG_BRTH_DIV_Msk

#define GP_TIMERS_BREATH_CFG_REG_BRTH_DIV_Msk   (0xffUL)

GP_TIMERS BREATH_CFG_REG: BRTH_DIV (Bitfield-Mask: 0xff)

Definition at line 6800 of file DA14680BA.h.

◆ GP_TIMERS_BREATH_CFG_REG_BRTH_DIV_Pos

#define GP_TIMERS_BREATH_CFG_REG_BRTH_DIV_Pos   (0UL)

GP_TIMERS BREATH_CFG_REG: BRTH_DIV (Bit 0)

Definition at line 6799 of file DA14680BA.h.

◆ GP_TIMERS_BREATH_CFG_REG_BRTH_STEP_Msk

#define GP_TIMERS_BREATH_CFG_REG_BRTH_STEP_Msk   (0xff00UL)

GP_TIMERS BREATH_CFG_REG: BRTH_STEP (Bitfield-Mask: 0xff)

Definition at line 6802 of file DA14680BA.h.

◆ GP_TIMERS_BREATH_CFG_REG_BRTH_STEP_Pos

#define GP_TIMERS_BREATH_CFG_REG_BRTH_STEP_Pos   (8UL)

GP_TIMERS BREATH_CFG_REG: BRTH_STEP (Bit 8)

Definition at line 6801 of file DA14680BA.h.

◆ GP_TIMERS_BREATH_CTRL_REG_BRTH_EN_Msk

#define GP_TIMERS_BREATH_CTRL_REG_BRTH_EN_Msk   (0x1UL)

GP_TIMERS BREATH_CTRL_REG: BRTH_EN (Bitfield-Mask: 0x01)

Definition at line 6814 of file DA14680BA.h.

◆ GP_TIMERS_BREATH_CTRL_REG_BRTH_EN_Pos

#define GP_TIMERS_BREATH_CTRL_REG_BRTH_EN_Pos   (0UL)

GP_TIMERS BREATH_CTRL_REG: BRTH_EN (Bit 0)

Definition at line 6813 of file DA14680BA.h.

◆ GP_TIMERS_BREATH_CTRL_REG_BRTH_PWM_POL_Msk

#define GP_TIMERS_BREATH_CTRL_REG_BRTH_PWM_POL_Msk   (0x2UL)

GP_TIMERS BREATH_CTRL_REG: BRTH_PWM_POL (Bitfield-Mask: 0x01)

Definition at line 6816 of file DA14680BA.h.

◆ GP_TIMERS_BREATH_CTRL_REG_BRTH_PWM_POL_Pos

#define GP_TIMERS_BREATH_CTRL_REG_BRTH_PWM_POL_Pos   (1UL)

GP_TIMERS BREATH_CTRL_REG: BRTH_PWM_POL (Bit 1)

Definition at line 6815 of file DA14680BA.h.

◆ GP_TIMERS_BREATH_DUTY_MAX_REG_BRTH_DUTY_MAX_Msk

#define GP_TIMERS_BREATH_DUTY_MAX_REG_BRTH_DUTY_MAX_Msk   (0xffUL)

GP_TIMERS BREATH_DUTY_MAX_REG: BRTH_DUTY_MAX (Bitfield-Mask: 0xff)

Definition at line 6806 of file DA14680BA.h.

◆ GP_TIMERS_BREATH_DUTY_MAX_REG_BRTH_DUTY_MAX_Pos

#define GP_TIMERS_BREATH_DUTY_MAX_REG_BRTH_DUTY_MAX_Pos   (0UL)

GP_TIMERS BREATH_DUTY_MAX_REG: BRTH_DUTY_MAX (Bit 0)

Definition at line 6805 of file DA14680BA.h.

◆ GP_TIMERS_BREATH_DUTY_MIN_REG_BRTH_DUTY_MIN_Msk

#define GP_TIMERS_BREATH_DUTY_MIN_REG_BRTH_DUTY_MIN_Msk   (0xffUL)

GP_TIMERS BREATH_DUTY_MIN_REG: BRTH_DUTY_MIN (Bitfield-Mask: 0xff)

Definition at line 6810 of file DA14680BA.h.

◆ GP_TIMERS_BREATH_DUTY_MIN_REG_BRTH_DUTY_MIN_Pos

#define GP_TIMERS_BREATH_DUTY_MIN_REG_BRTH_DUTY_MIN_Pos   (0UL)

GP_TIMERS BREATH_DUTY_MIN_REG: BRTH_DUTY_MIN (Bit 0)

Definition at line 6809 of file DA14680BA.h.

◆ GP_TIMERS_PWM2_END_CYCLE_END_CYCLE_Msk

#define GP_TIMERS_PWM2_END_CYCLE_END_CYCLE_Msk   (0x3fffUL)

GP_TIMERS PWM2_END_CYCLE: END_CYCLE (Bitfield-Mask: 0x3fff)

Definition at line 6774 of file DA14680BA.h.

◆ GP_TIMERS_PWM2_END_CYCLE_END_CYCLE_Pos

#define GP_TIMERS_PWM2_END_CYCLE_END_CYCLE_Pos   (0UL)

GP_TIMERS PWM2_END_CYCLE: END_CYCLE (Bit 0)

Definition at line 6773 of file DA14680BA.h.

◆ GP_TIMERS_PWM2_START_CYCLE_START_CYCLE_Msk

#define GP_TIMERS_PWM2_START_CYCLE_START_CYCLE_Msk   (0x3fffUL)

GP_TIMERS PWM2_START_CYCLE: START_CYCLE (Bitfield-Mask: 0x3fff)

Definition at line 6762 of file DA14680BA.h.

◆ GP_TIMERS_PWM2_START_CYCLE_START_CYCLE_Pos

#define GP_TIMERS_PWM2_START_CYCLE_START_CYCLE_Pos   (0UL)

GP_TIMERS PWM2_START_CYCLE: START_CYCLE (Bit 0)

Definition at line 6761 of file DA14680BA.h.

◆ GP_TIMERS_PWM3_END_CYCLE_END_CYCLE_Msk

#define GP_TIMERS_PWM3_END_CYCLE_END_CYCLE_Msk   (0x3fffUL)

GP_TIMERS PWM3_END_CYCLE: END_CYCLE (Bitfield-Mask: 0x3fff)

Definition at line 6778 of file DA14680BA.h.

◆ GP_TIMERS_PWM3_END_CYCLE_END_CYCLE_Pos

#define GP_TIMERS_PWM3_END_CYCLE_END_CYCLE_Pos   (0UL)

GP_TIMERS PWM3_END_CYCLE: END_CYCLE (Bit 0)

Definition at line 6777 of file DA14680BA.h.

◆ GP_TIMERS_PWM3_START_CYCLE_START_CYCLE_Msk

#define GP_TIMERS_PWM3_START_CYCLE_START_CYCLE_Msk   (0x3fffUL)

GP_TIMERS PWM3_START_CYCLE: START_CYCLE (Bitfield-Mask: 0x3fff)

Definition at line 6766 of file DA14680BA.h.

◆ GP_TIMERS_PWM3_START_CYCLE_START_CYCLE_Pos

#define GP_TIMERS_PWM3_START_CYCLE_START_CYCLE_Pos   (0UL)

GP_TIMERS PWM3_START_CYCLE: START_CYCLE (Bit 0)

Definition at line 6765 of file DA14680BA.h.

◆ GP_TIMERS_PWM4_END_CYCLE_END_CYCLE_Msk

#define GP_TIMERS_PWM4_END_CYCLE_END_CYCLE_Msk   (0x3fffUL)

GP_TIMERS PWM4_END_CYCLE: END_CYCLE (Bitfield-Mask: 0x3fff)

Definition at line 6782 of file DA14680BA.h.

◆ GP_TIMERS_PWM4_END_CYCLE_END_CYCLE_Pos

#define GP_TIMERS_PWM4_END_CYCLE_END_CYCLE_Pos   (0UL)

GP_TIMERS PWM4_END_CYCLE: END_CYCLE (Bit 0)

Definition at line 6781 of file DA14680BA.h.

◆ GP_TIMERS_PWM4_START_CYCLE_START_CYCLE_Msk

#define GP_TIMERS_PWM4_START_CYCLE_START_CYCLE_Msk   (0x3fffUL)

GP_TIMERS PWM4_START_CYCLE: START_CYCLE (Bitfield-Mask: 0x3fff)

Definition at line 6770 of file DA14680BA.h.

◆ GP_TIMERS_PWM4_START_CYCLE_START_CYCLE_Pos

#define GP_TIMERS_PWM4_START_CYCLE_START_CYCLE_Pos   (0UL)

GP_TIMERS PWM4_START_CYCLE: START_CYCLE (Bit 0)

Definition at line 6769 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_CTRL_REG_PWM_MODE_Msk

#define GP_TIMERS_TIMER0_CTRL_REG_PWM_MODE_Msk   (0x8UL)

GP_TIMERS TIMER0_CTRL_REG: PWM_MODE (Bitfield-Mask: 0x01)

Definition at line 6746 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_CTRL_REG_PWM_MODE_Pos

#define GP_TIMERS_TIMER0_CTRL_REG_PWM_MODE_Pos   (3UL)

GP_TIMERS TIMER0_CTRL_REG: PWM_MODE (Bit 3)

Definition at line 6745 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_DIV_Msk

#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_DIV_Msk   (0x4UL)

GP_TIMERS TIMER0_CTRL_REG: TIM0_CLK_DIV (Bitfield-Mask: 0x01)

Definition at line 6744 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_DIV_Pos

#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_DIV_Pos   (2UL)

GP_TIMERS TIMER0_CTRL_REG: TIM0_CLK_DIV (Bit 2)

Definition at line 6743 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_SEL_Msk

#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_SEL_Msk   (0x2UL)

GP_TIMERS TIMER0_CTRL_REG: TIM0_CLK_SEL (Bitfield-Mask: 0x01)

Definition at line 6742 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_SEL_Pos

#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CLK_SEL_Pos   (1UL)

GP_TIMERS TIMER0_CTRL_REG: TIM0_CLK_SEL (Bit 1)

Definition at line 6741 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_CTRL_REG_TIM0_CTRL_Msk

#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CTRL_Msk   (0x1UL)

GP_TIMERS TIMER0_CTRL_REG: TIM0_CTRL (Bitfield-Mask: 0x01)

Definition at line 6740 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_CTRL_REG_TIM0_CTRL_Pos

#define GP_TIMERS_TIMER0_CTRL_REG_TIM0_CTRL_Pos   (0UL)

GP_TIMERS TIMER0_CTRL_REG: TIM0_CTRL (Bit 0)

Definition at line 6739 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_ON_REG_TIM0_ON_Msk

#define GP_TIMERS_TIMER0_ON_REG_TIM0_ON_Msk   (0xffffUL)

GP_TIMERS TIMER0_ON_REG: TIM0_ON (Bitfield-Mask: 0xffff)

Definition at line 6750 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_ON_REG_TIM0_ON_Pos

#define GP_TIMERS_TIMER0_ON_REG_TIM0_ON_Pos   (0UL)

GP_TIMERS TIMER0_ON_REG: TIM0_ON (Bit 0)

Definition at line 6749 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_RELOAD_M_REG_TIM0_M_Msk

#define GP_TIMERS_TIMER0_RELOAD_M_REG_TIM0_M_Msk   (0xffffUL)

GP_TIMERS TIMER0_RELOAD_M_REG: TIM0_M (Bitfield-Mask: 0xffff)

Definition at line 6754 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_RELOAD_M_REG_TIM0_M_Pos

#define GP_TIMERS_TIMER0_RELOAD_M_REG_TIM0_M_Pos   (0UL)

GP_TIMERS TIMER0_RELOAD_M_REG: TIM0_M (Bit 0)

Definition at line 6753 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_RELOAD_N_REG_TIM0_N_Msk

#define GP_TIMERS_TIMER0_RELOAD_N_REG_TIM0_N_Msk   (0xffffUL)

GP_TIMERS TIMER0_RELOAD_N_REG: TIM0_N (Bitfield-Mask: 0xffff)

Definition at line 6758 of file DA14680BA.h.

◆ GP_TIMERS_TIMER0_RELOAD_N_REG_TIM0_N_Pos

#define GP_TIMERS_TIMER0_RELOAD_N_REG_TIM0_N_Pos   (0UL)

GP_TIMERS TIMER0_RELOAD_N_REG: TIM0_N (Bit 0)

Definition at line 6757 of file DA14680BA.h.

◆ GP_TIMERS_TRIPLE_PWM_CTRL_REG_HW_PAUSE_EN_Msk

#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_HW_PAUSE_EN_Msk   (0x4UL)

GP_TIMERS TRIPLE_PWM_CTRL_REG: HW_PAUSE_EN (Bitfield-Mask: 0x01)

Definition at line 6794 of file DA14680BA.h.

◆ GP_TIMERS_TRIPLE_PWM_CTRL_REG_HW_PAUSE_EN_Pos

#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_HW_PAUSE_EN_Pos   (2UL)

GP_TIMERS TRIPLE_PWM_CTRL_REG: HW_PAUSE_EN (Bit 2)

Definition at line 6793 of file DA14680BA.h.

◆ GP_TIMERS_TRIPLE_PWM_CTRL_REG_SW_PAUSE_EN_Msk

#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_SW_PAUSE_EN_Msk   (0x2UL)

GP_TIMERS TRIPLE_PWM_CTRL_REG: SW_PAUSE_EN (Bitfield-Mask: 0x01)

Definition at line 6792 of file DA14680BA.h.

◆ GP_TIMERS_TRIPLE_PWM_CTRL_REG_SW_PAUSE_EN_Pos

#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_SW_PAUSE_EN_Pos   (1UL)

GP_TIMERS TRIPLE_PWM_CTRL_REG: SW_PAUSE_EN (Bit 1)

Definition at line 6791 of file DA14680BA.h.

◆ GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_CLK_SEL_Msk

#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_CLK_SEL_Msk   (0x8UL)

GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_CLK_SEL (Bitfield-Mask: 0x01)

Definition at line 6796 of file DA14680BA.h.

◆ GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_CLK_SEL_Pos

#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_CLK_SEL_Pos   (3UL)

GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_CLK_SEL (Bit 3)

Definition at line 6795 of file DA14680BA.h.

◆ GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_ENABLE_Msk

#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_ENABLE_Msk   (0x1UL)

GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_ENABLE (Bitfield-Mask: 0x01)

Definition at line 6790 of file DA14680BA.h.

◆ GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_ENABLE_Pos

#define GP_TIMERS_TRIPLE_PWM_CTRL_REG_TRIPLE_PWM_ENABLE_Pos   (0UL)

GP_TIMERS TRIPLE_PWM_CTRL_REG: TRIPLE_PWM_ENABLE (Bit 0)

Definition at line 6789 of file DA14680BA.h.

◆ GP_TIMERS_TRIPLE_PWM_FREQUENCY_FREQ_Msk

#define GP_TIMERS_TRIPLE_PWM_FREQUENCY_FREQ_Msk   (0x3fffUL)

GP_TIMERS TRIPLE_PWM_FREQUENCY: FREQ (Bitfield-Mask: 0x3fff)

Definition at line 6786 of file DA14680BA.h.

◆ GP_TIMERS_TRIPLE_PWM_FREQUENCY_FREQ_Pos

#define GP_TIMERS_TRIPLE_PWM_FREQUENCY_FREQ_Pos   (0UL)

GP_TIMERS TRIPLE_PWM_FREQUENCY: FREQ (Bit 0)

Definition at line 6785 of file DA14680BA.h.

◆ GPADC

#define GPADC   ((GPADC_Type *) GPADC_BASE)

Definition at line 12088 of file DA14680BA.h.

◆ GPADC_BASE

#define GPADC_BASE   0x50001900UL

Definition at line 12043 of file DA14680BA.h.

◆ GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Msk

#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Msk   (0xffffUL)

GPADC GP_ADC_CLEAR_INT_REG: GP_ADC_CLR_INT (Bitfield-Mask: 0xffff)

Definition at line 6882 of file DA14680BA.h.

◆ GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Pos

#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Pos   (0UL)

GPADC GP_ADC_CLEAR_INT_REG: GP_ADC_CLR_INT (Bit 0)

Definition at line 6881 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Msk

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Msk   (0x1UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_ATTN3X (Bitfield-Mask: 0x01)

Definition at line 6852 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Pos

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN3X_Pos   (0UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_ATTN3X (Bit 0)

Definition at line 6851 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Msk

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Msk   (0xe0UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_CONV_NRS (Bitfield-Mask: 0x07)

Definition at line 6860 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Pos

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Pos   (5UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_CONV_NRS (Bit 5)

Definition at line 6859 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Msk

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Msk   (0x8UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_DMA_EN (Bitfield-Mask: 0x01)

Definition at line 6858 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Pos

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_DMA_EN_Pos   (3UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_DMA_EN (Bit 3)

Definition at line 6857 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Msk

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Msk   (0x4UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_I20U (Bitfield-Mask: 0x01)

Definition at line 6856 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Pos

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Pos   (2UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_I20U (Bit 2)

Definition at line 6855 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Msk

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Msk   (0x2UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_IDYN (Bitfield-Mask: 0x01)

Definition at line 6854 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Pos

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_IDYN_Pos   (1UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_IDYN (Bit 1)

Definition at line 6853 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Msk

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Msk   (0xf00UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_SMPL_TIME (Bitfield-Mask: 0x0f)

Definition at line 6862 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Pos

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Pos   (8UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_SMPL_TIME (Bit 8)

Definition at line 6861 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Msk

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Msk   (0xf000UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_STORE_DEL (Bitfield-Mask: 0x0f)

Definition at line 6864 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Pos

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Pos   (12UL)

GPADC GP_ADC_CTRL2_REG: GP_ADC_STORE_DEL (Bit 12)

Definition at line 6863 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Msk

#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Msk   (0xffUL)

GPADC GP_ADC_CTRL3_REG: GP_ADC_EN_DEL (Bitfield-Mask: 0xff)

Definition at line 6868 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Pos

#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Pos   (0UL)

GPADC GP_ADC_CTRL3_REG: GP_ADC_EN_DEL (Bit 0)

Definition at line 6867 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Msk

#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Msk   (0xff00UL)

GPADC GP_ADC_CTRL3_REG: GP_ADC_INTERVAL (Bitfield-Mask: 0xff)

Definition at line 6870 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Pos

#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Pos   (8UL)

GPADC GP_ADC_CTRL3_REG: GP_ADC_INTERVAL (Bit 8)

Definition at line 6869 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Msk   (0x4000UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_CHOP (Bitfield-Mask: 0x01)

Definition at line 6846 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Pos   (14UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_CHOP (Bit 14)

Definition at line 6845 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Msk   (0x8UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_CLK_SEL (Bitfield-Mask: 0x01)

Definition at line 6832 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CLK_SEL_Pos   (3UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_CLK_SEL (Bit 3)

Definition at line 6831 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Msk   (0x4UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_CONT (Bitfield-Mask: 0x01)

Definition at line 6830 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Pos   (2UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_CONT (Bit 2)

Definition at line 6829 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Msk   (0x1UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_EN (Bitfield-Mask: 0x01)

Definition at line 6826 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Pos   (0UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_EN (Bit 0)

Definition at line 6825 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Msk   (0x10UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_INT (Bitfield-Mask: 0x01)

Definition at line 6834 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Pos   (4UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_INT (Bit 4)

Definition at line 6833 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Msk   (0x8000UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_LDO_ZERO (Bitfield-Mask: 0x01)

Definition at line 6848 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_ZERO_Pos   (15UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_LDO_ZERO (Bit 15)

Definition at line 6847 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Msk   (0x20UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_MINT (Bitfield-Mask: 0x01)

Definition at line 6836 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Pos   (5UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_MINT (Bit 5)

Definition at line 6835 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Msk   (0x80UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_MUTE (Bitfield-Mask: 0x01)

Definition at line 6840 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Pos   (7UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_MUTE (Bit 7)

Definition at line 6839 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Msk   (0x40UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_SE (Bitfield-Mask: 0x01)

Definition at line 6838 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Pos   (6UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_SE (Bit 6)

Definition at line 6837 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Msk   (0x1f00UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_SEL (Bitfield-Mask: 0x1f)

Definition at line 6842 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SEL_Pos   (8UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_SEL (Bit 8)

Definition at line 6841 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Msk   (0x2000UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_SIGN (Bitfield-Mask: 0x01)

Definition at line 6844 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Pos   (13UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_SIGN (Bit 13)

Definition at line 6843 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Msk   (0x2UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_START (Bitfield-Mask: 0x01)

Definition at line 6828 of file DA14680BA.h.

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Pos   (1UL)

GPADC GP_ADC_CTRL_REG: GP_ADC_START (Bit 1)

Definition at line 6827 of file DA14680BA.h.

◆ GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Msk

#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Msk   (0x3ffUL)

GPADC GP_ADC_OFFN_REG: GP_ADC_OFFN (Bitfield-Mask: 0x3ff)

Definition at line 6878 of file DA14680BA.h.

◆ GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Pos

#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Pos   (0UL)

GPADC GP_ADC_OFFN_REG: GP_ADC_OFFN (Bit 0)

Definition at line 6877 of file DA14680BA.h.

◆ GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Msk

#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Msk   (0x3ffUL)

GPADC GP_ADC_OFFP_REG: GP_ADC_OFFP (Bitfield-Mask: 0x3ff)

Definition at line 6874 of file DA14680BA.h.

◆ GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Pos

#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Pos   (0UL)

GPADC GP_ADC_OFFP_REG: GP_ADC_OFFP (Bit 0)

Definition at line 6873 of file DA14680BA.h.

◆ GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Msk

#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Msk   (0xffffUL)

GPADC GP_ADC_RESULT_REG: GP_ADC_VAL (Bitfield-Mask: 0xffff)

Definition at line 6886 of file DA14680BA.h.

◆ GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Pos

#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Pos   (0UL)

GPADC GP_ADC_RESULT_REG: GP_ADC_VAL (Bit 0)

Definition at line 6885 of file DA14680BA.h.

◆ GPIO

#define GPIO   ((GPIO_Type *) GPIO_BASE)

Definition at line 12089 of file DA14680BA.h.

◆ GPIO_BASE

#define GPIO_BASE   0x50003000UL

Definition at line 12044 of file DA14680BA.h.

◆ GPIO_BIST_CTRL_REG_RAM_BIST_CONFIG_Msk

#define GPIO_BIST_CTRL_REG_RAM_BIST_CONFIG_Msk   (0x3UL)

GPIO BIST_CTRL_REG: RAM_BIST_CONFIG (Bitfield-Mask: 0x03)

Definition at line 7276 of file DA14680BA.h.

◆ GPIO_BIST_CTRL_REG_RAM_BIST_CONFIG_Pos

#define GPIO_BIST_CTRL_REG_RAM_BIST_CONFIG_Pos   (0UL)

GPIO BIST_CTRL_REG: RAM_BIST_CONFIG (Bit 0)

Definition at line 7275 of file DA14680BA.h.

◆ GPIO_BIST_CTRL_REG_RAM_BIST_PATTERN_Msk

#define GPIO_BIST_CTRL_REG_RAM_BIST_PATTERN_Msk   (0xcUL)

GPIO BIST_CTRL_REG: RAM_BIST_PATTERN (Bitfield-Mask: 0x03)

Definition at line 7278 of file DA14680BA.h.

◆ GPIO_BIST_CTRL_REG_RAM_BIST_PATTERN_Pos

#define GPIO_BIST_CTRL_REG_RAM_BIST_PATTERN_Pos   (2UL)

GPIO BIST_CTRL_REG: RAM_BIST_PATTERN (Bit 2)

Definition at line 7277 of file DA14680BA.h.

◆ GPIO_BIST_CTRL_REG_RAMBIST_ENABLE_Msk

#define GPIO_BIST_CTRL_REG_RAMBIST_ENABLE_Msk   (0x20UL)

GPIO BIST_CTRL_REG: RAMBIST_ENABLE (Bitfield-Mask: 0x01)

Definition at line 7282 of file DA14680BA.h.

◆ GPIO_BIST_CTRL_REG_RAMBIST_ENABLE_Pos

#define GPIO_BIST_CTRL_REG_RAMBIST_ENABLE_Pos   (5UL)

GPIO BIST_CTRL_REG: RAMBIST_ENABLE (Bit 5)

Definition at line 7281 of file DA14680BA.h.

◆ GPIO_BIST_CTRL_REG_ROMBIST_ENABLE_Msk

#define GPIO_BIST_CTRL_REG_ROMBIST_ENABLE_Msk   (0x10UL)

GPIO BIST_CTRL_REG: ROMBIST_ENABLE (Bitfield-Mask: 0x01)

Definition at line 7280 of file DA14680BA.h.

◆ GPIO_BIST_CTRL_REG_ROMBIST_ENABLE_Pos

#define GPIO_BIST_CTRL_REG_ROMBIST_ENABLE_Pos   (4UL)

GPIO BIST_CTRL_REG: ROMBIST_ENABLE (Bit 4)

Definition at line 7279 of file DA14680BA.h.

◆ GPIO_BIST_CTRL_REG_SHOW_BIST_Msk

#define GPIO_BIST_CTRL_REG_SHOW_BIST_Msk   (0x80UL)

GPIO BIST_CTRL_REG: SHOW_BIST (Bitfield-Mask: 0x01)

Definition at line 7286 of file DA14680BA.h.

◆ GPIO_BIST_CTRL_REG_SHOW_BIST_Pos

#define GPIO_BIST_CTRL_REG_SHOW_BIST_Pos   (7UL)

GPIO BIST_CTRL_REG: SHOW_BIST (Bit 7)

Definition at line 7285 of file DA14680BA.h.

◆ GPIO_BIST_CTRL_REG_SYSRAMBIST_ENABLE_Msk

#define GPIO_BIST_CTRL_REG_SYSRAMBIST_ENABLE_Msk   (0x40UL)

GPIO BIST_CTRL_REG: SYSRAMBIST_ENABLE (Bitfield-Mask: 0x01)

Definition at line 7284 of file DA14680BA.h.

◆ GPIO_BIST_CTRL_REG_SYSRAMBIST_ENABLE_Pos

#define GPIO_BIST_CTRL_REG_SYSRAMBIST_ENABLE_Pos   (6UL)

GPIO BIST_CTRL_REG: SYSRAMBIST_ENABLE (Bit 6)

Definition at line 7283 of file DA14680BA.h.

◆ GPIO_GPIO_CLK_SEL_FUNC_CLOCK_SEL_Msk

#define GPIO_GPIO_CLK_SEL_FUNC_CLOCK_SEL_Msk   (0x7UL)

GPIO GPIO_CLK_SEL: FUNC_CLOCK_SEL (Bitfield-Mask: 0x07)

Definition at line 7272 of file DA14680BA.h.

◆ GPIO_GPIO_CLK_SEL_FUNC_CLOCK_SEL_Pos

#define GPIO_GPIO_CLK_SEL_FUNC_CLOCK_SEL_Pos   (0UL)

GPIO GPIO_CLK_SEL: FUNC_CLOCK_SEL (Bit 0)

Definition at line 7271 of file DA14680BA.h.

◆ GPIO_P00_MODE_REG_PID_Msk

#define GPIO_P00_MODE_REG_PID_Msk   (0x3fUL)

GPIO P00_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 6956 of file DA14680BA.h.

◆ GPIO_P00_MODE_REG_PID_Pos

#define GPIO_P00_MODE_REG_PID_Pos   (0UL)

GPIO P00_MODE_REG: PID (Bit 0)

Definition at line 6955 of file DA14680BA.h.

◆ GPIO_P00_MODE_REG_PPOD_Msk

#define GPIO_P00_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P00_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 6960 of file DA14680BA.h.

◆ GPIO_P00_MODE_REG_PPOD_Pos

#define GPIO_P00_MODE_REG_PPOD_Pos   (10UL)

GPIO P00_MODE_REG: PPOD (Bit 10)

Definition at line 6959 of file DA14680BA.h.

◆ GPIO_P00_MODE_REG_PUPD_Msk

#define GPIO_P00_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P00_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 6958 of file DA14680BA.h.

◆ GPIO_P00_MODE_REG_PUPD_Pos

#define GPIO_P00_MODE_REG_PUPD_Pos   (8UL)

GPIO P00_MODE_REG: PUPD (Bit 8)

Definition at line 6957 of file DA14680BA.h.

◆ GPIO_P01_MODE_REG_PID_Msk

#define GPIO_P01_MODE_REG_PID_Msk   (0x3fUL)

GPIO P01_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 6964 of file DA14680BA.h.

◆ GPIO_P01_MODE_REG_PID_Pos

#define GPIO_P01_MODE_REG_PID_Pos   (0UL)

GPIO P01_MODE_REG: PID (Bit 0)

Definition at line 6963 of file DA14680BA.h.

◆ GPIO_P01_MODE_REG_PPOD_Msk

#define GPIO_P01_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P01_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 6968 of file DA14680BA.h.

◆ GPIO_P01_MODE_REG_PPOD_Pos

#define GPIO_P01_MODE_REG_PPOD_Pos   (10UL)

GPIO P01_MODE_REG: PPOD (Bit 10)

Definition at line 6967 of file DA14680BA.h.

◆ GPIO_P01_MODE_REG_PUPD_Msk

#define GPIO_P01_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P01_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 6966 of file DA14680BA.h.

◆ GPIO_P01_MODE_REG_PUPD_Pos

#define GPIO_P01_MODE_REG_PUPD_Pos   (8UL)

GPIO P01_MODE_REG: PUPD (Bit 8)

Definition at line 6965 of file DA14680BA.h.

◆ GPIO_P02_MODE_REG_PID_Msk

#define GPIO_P02_MODE_REG_PID_Msk   (0x3fUL)

GPIO P02_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 6972 of file DA14680BA.h.

◆ GPIO_P02_MODE_REG_PID_Pos

#define GPIO_P02_MODE_REG_PID_Pos   (0UL)

GPIO P02_MODE_REG: PID (Bit 0)

Definition at line 6971 of file DA14680BA.h.

◆ GPIO_P02_MODE_REG_PPOD_Msk

#define GPIO_P02_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P02_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 6976 of file DA14680BA.h.

◆ GPIO_P02_MODE_REG_PPOD_Pos

#define GPIO_P02_MODE_REG_PPOD_Pos   (10UL)

GPIO P02_MODE_REG: PPOD (Bit 10)

Definition at line 6975 of file DA14680BA.h.

◆ GPIO_P02_MODE_REG_PUPD_Msk

#define GPIO_P02_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P02_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 6974 of file DA14680BA.h.

◆ GPIO_P02_MODE_REG_PUPD_Pos

#define GPIO_P02_MODE_REG_PUPD_Pos   (8UL)

GPIO P02_MODE_REG: PUPD (Bit 8)

Definition at line 6973 of file DA14680BA.h.

◆ GPIO_P03_MODE_REG_PID_Msk

#define GPIO_P03_MODE_REG_PID_Msk   (0x3fUL)

GPIO P03_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 6980 of file DA14680BA.h.

◆ GPIO_P03_MODE_REG_PID_Pos

#define GPIO_P03_MODE_REG_PID_Pos   (0UL)

GPIO P03_MODE_REG: PID (Bit 0)

Definition at line 6979 of file DA14680BA.h.

◆ GPIO_P03_MODE_REG_PPOD_Msk

#define GPIO_P03_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P03_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 6984 of file DA14680BA.h.

◆ GPIO_P03_MODE_REG_PPOD_Pos

#define GPIO_P03_MODE_REG_PPOD_Pos   (10UL)

GPIO P03_MODE_REG: PPOD (Bit 10)

Definition at line 6983 of file DA14680BA.h.

◆ GPIO_P03_MODE_REG_PUPD_Msk

#define GPIO_P03_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P03_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 6982 of file DA14680BA.h.

◆ GPIO_P03_MODE_REG_PUPD_Pos

#define GPIO_P03_MODE_REG_PUPD_Pos   (8UL)

GPIO P03_MODE_REG: PUPD (Bit 8)

Definition at line 6981 of file DA14680BA.h.

◆ GPIO_P04_MODE_REG_PID_Msk

#define GPIO_P04_MODE_REG_PID_Msk   (0x3fUL)

GPIO P04_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 6988 of file DA14680BA.h.

◆ GPIO_P04_MODE_REG_PID_Pos

#define GPIO_P04_MODE_REG_PID_Pos   (0UL)

GPIO P04_MODE_REG: PID (Bit 0)

Definition at line 6987 of file DA14680BA.h.

◆ GPIO_P04_MODE_REG_PPOD_Msk

#define GPIO_P04_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P04_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 6992 of file DA14680BA.h.

◆ GPIO_P04_MODE_REG_PPOD_Pos

#define GPIO_P04_MODE_REG_PPOD_Pos   (10UL)

GPIO P04_MODE_REG: PPOD (Bit 10)

Definition at line 6991 of file DA14680BA.h.

◆ GPIO_P04_MODE_REG_PUPD_Msk

#define GPIO_P04_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P04_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 6990 of file DA14680BA.h.

◆ GPIO_P04_MODE_REG_PUPD_Pos

#define GPIO_P04_MODE_REG_PUPD_Pos   (8UL)

GPIO P04_MODE_REG: PUPD (Bit 8)

Definition at line 6989 of file DA14680BA.h.

◆ GPIO_P05_MODE_REG_PID_Msk

#define GPIO_P05_MODE_REG_PID_Msk   (0x3fUL)

GPIO P05_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 6996 of file DA14680BA.h.

◆ GPIO_P05_MODE_REG_PID_Pos

#define GPIO_P05_MODE_REG_PID_Pos   (0UL)

GPIO P05_MODE_REG: PID (Bit 0)

Definition at line 6995 of file DA14680BA.h.

◆ GPIO_P05_MODE_REG_PPOD_Msk

#define GPIO_P05_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P05_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7000 of file DA14680BA.h.

◆ GPIO_P05_MODE_REG_PPOD_Pos

#define GPIO_P05_MODE_REG_PPOD_Pos   (10UL)

GPIO P05_MODE_REG: PPOD (Bit 10)

Definition at line 6999 of file DA14680BA.h.

◆ GPIO_P05_MODE_REG_PUPD_Msk

#define GPIO_P05_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P05_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 6998 of file DA14680BA.h.

◆ GPIO_P05_MODE_REG_PUPD_Pos

#define GPIO_P05_MODE_REG_PUPD_Pos   (8UL)

GPIO P05_MODE_REG: PUPD (Bit 8)

Definition at line 6997 of file DA14680BA.h.

◆ GPIO_P06_MODE_REG_PID_Msk

#define GPIO_P06_MODE_REG_PID_Msk   (0x3fUL)

GPIO P06_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7004 of file DA14680BA.h.

◆ GPIO_P06_MODE_REG_PID_Pos

#define GPIO_P06_MODE_REG_PID_Pos   (0UL)

GPIO P06_MODE_REG: PID (Bit 0)

Definition at line 7003 of file DA14680BA.h.

◆ GPIO_P06_MODE_REG_PPOD_Msk

#define GPIO_P06_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P06_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7008 of file DA14680BA.h.

◆ GPIO_P06_MODE_REG_PPOD_Pos

#define GPIO_P06_MODE_REG_PPOD_Pos   (10UL)

GPIO P06_MODE_REG: PPOD (Bit 10)

Definition at line 7007 of file DA14680BA.h.

◆ GPIO_P06_MODE_REG_PUPD_Msk

#define GPIO_P06_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P06_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7006 of file DA14680BA.h.

◆ GPIO_P06_MODE_REG_PUPD_Pos

#define GPIO_P06_MODE_REG_PUPD_Pos   (8UL)

GPIO P06_MODE_REG: PUPD (Bit 8)

Definition at line 7005 of file DA14680BA.h.

◆ GPIO_P07_MODE_REG_PID_Msk

#define GPIO_P07_MODE_REG_PID_Msk   (0x3fUL)

GPIO P07_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7012 of file DA14680BA.h.

◆ GPIO_P07_MODE_REG_PID_Pos

#define GPIO_P07_MODE_REG_PID_Pos   (0UL)

GPIO P07_MODE_REG: PID (Bit 0)

Definition at line 7011 of file DA14680BA.h.

◆ GPIO_P07_MODE_REG_PPOD_Msk

#define GPIO_P07_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P07_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7016 of file DA14680BA.h.

◆ GPIO_P07_MODE_REG_PPOD_Pos

#define GPIO_P07_MODE_REG_PPOD_Pos   (10UL)

GPIO P07_MODE_REG: PPOD (Bit 10)

Definition at line 7015 of file DA14680BA.h.

◆ GPIO_P07_MODE_REG_PUPD_Msk

#define GPIO_P07_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P07_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7014 of file DA14680BA.h.

◆ GPIO_P07_MODE_REG_PUPD_Pos

#define GPIO_P07_MODE_REG_PUPD_Pos   (8UL)

GPIO P07_MODE_REG: PUPD (Bit 8)

Definition at line 7013 of file DA14680BA.h.

◆ GPIO_P0_DATA_REG_P0_DATA_Msk

#define GPIO_P0_DATA_REG_P0_DATA_Msk   (0xffUL)

GPIO P0_DATA_REG: P0_DATA (Bitfield-Mask: 0xff)

Definition at line 6896 of file DA14680BA.h.

◆ GPIO_P0_DATA_REG_P0_DATA_Pos

#define GPIO_P0_DATA_REG_P0_DATA_Pos   (0UL)

GPIO P0_DATA_REG: P0_DATA (Bit 0)

Definition at line 6895 of file DA14680BA.h.

◆ GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Msk

#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Msk   (0xc0UL)

GPIO P0_PADPWR_CTRL_REG: P0_OUT_CTRL (Bitfield-Mask: 0x03)

Definition at line 7252 of file DA14680BA.h.

◆ GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Pos

#define GPIO_P0_PADPWR_CTRL_REG_P0_OUT_CTRL_Pos   (6UL)

GPIO P0_PADPWR_CTRL_REG: P0_OUT_CTRL (Bit 6)

Definition at line 7251 of file DA14680BA.h.

◆ GPIO_P0_RESET_DATA_REG_P0_RESET_Msk

#define GPIO_P0_RESET_DATA_REG_P0_RESET_Msk   (0xffUL)

GPIO P0_RESET_DATA_REG: P0_RESET (Bitfield-Mask: 0xff)

Definition at line 6936 of file DA14680BA.h.

◆ GPIO_P0_RESET_DATA_REG_P0_RESET_Pos

#define GPIO_P0_RESET_DATA_REG_P0_RESET_Pos   (0UL)

GPIO P0_RESET_DATA_REG: P0_RESET (Bit 0)

Definition at line 6935 of file DA14680BA.h.

◆ GPIO_P0_SET_DATA_REG_P0_SET_Msk

#define GPIO_P0_SET_DATA_REG_P0_SET_Msk   (0xffUL)

GPIO P0_SET_DATA_REG: P0_SET (Bitfield-Mask: 0xff)

Definition at line 6916 of file DA14680BA.h.

◆ GPIO_P0_SET_DATA_REG_P0_SET_Pos

#define GPIO_P0_SET_DATA_REG_P0_SET_Pos   (0UL)

GPIO P0_SET_DATA_REG: P0_SET (Bit 0)

Definition at line 6915 of file DA14680BA.h.

◆ GPIO_P10_MODE_REG_PID_Msk

#define GPIO_P10_MODE_REG_PID_Msk   (0x3fUL)

GPIO P10_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7020 of file DA14680BA.h.

◆ GPIO_P10_MODE_REG_PID_Pos

#define GPIO_P10_MODE_REG_PID_Pos   (0UL)

GPIO P10_MODE_REG: PID (Bit 0)

Definition at line 7019 of file DA14680BA.h.

◆ GPIO_P10_MODE_REG_PPOD_Msk

#define GPIO_P10_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P10_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7024 of file DA14680BA.h.

◆ GPIO_P10_MODE_REG_PPOD_Pos

#define GPIO_P10_MODE_REG_PPOD_Pos   (10UL)

GPIO P10_MODE_REG: PPOD (Bit 10)

Definition at line 7023 of file DA14680BA.h.

◆ GPIO_P10_MODE_REG_PUPD_Msk

#define GPIO_P10_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P10_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7022 of file DA14680BA.h.

◆ GPIO_P10_MODE_REG_PUPD_Pos

#define GPIO_P10_MODE_REG_PUPD_Pos   (8UL)

GPIO P10_MODE_REG: PUPD (Bit 8)

Definition at line 7021 of file DA14680BA.h.

◆ GPIO_P11_MODE_REG_PID_Msk

#define GPIO_P11_MODE_REG_PID_Msk   (0x3fUL)

GPIO P11_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7028 of file DA14680BA.h.

◆ GPIO_P11_MODE_REG_PID_Pos

#define GPIO_P11_MODE_REG_PID_Pos   (0UL)

GPIO P11_MODE_REG: PID (Bit 0)

Definition at line 7027 of file DA14680BA.h.

◆ GPIO_P11_MODE_REG_PPOD_Msk

#define GPIO_P11_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P11_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7032 of file DA14680BA.h.

◆ GPIO_P11_MODE_REG_PPOD_Pos

#define GPIO_P11_MODE_REG_PPOD_Pos   (10UL)

GPIO P11_MODE_REG: PPOD (Bit 10)

Definition at line 7031 of file DA14680BA.h.

◆ GPIO_P11_MODE_REG_PUPD_Msk

#define GPIO_P11_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P11_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7030 of file DA14680BA.h.

◆ GPIO_P11_MODE_REG_PUPD_Pos

#define GPIO_P11_MODE_REG_PUPD_Pos   (8UL)

GPIO P11_MODE_REG: PUPD (Bit 8)

Definition at line 7029 of file DA14680BA.h.

◆ GPIO_P12_MODE_REG_PID_Msk

#define GPIO_P12_MODE_REG_PID_Msk   (0x3fUL)

GPIO P12_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7036 of file DA14680BA.h.

◆ GPIO_P12_MODE_REG_PID_Pos

#define GPIO_P12_MODE_REG_PID_Pos   (0UL)

GPIO P12_MODE_REG: PID (Bit 0)

Definition at line 7035 of file DA14680BA.h.

◆ GPIO_P12_MODE_REG_PPOD_Msk

#define GPIO_P12_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P12_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7040 of file DA14680BA.h.

◆ GPIO_P12_MODE_REG_PPOD_Pos

#define GPIO_P12_MODE_REG_PPOD_Pos   (10UL)

GPIO P12_MODE_REG: PPOD (Bit 10)

Definition at line 7039 of file DA14680BA.h.

◆ GPIO_P12_MODE_REG_PUPD_Msk

#define GPIO_P12_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P12_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7038 of file DA14680BA.h.

◆ GPIO_P12_MODE_REG_PUPD_Pos

#define GPIO_P12_MODE_REG_PUPD_Pos   (8UL)

GPIO P12_MODE_REG: PUPD (Bit 8)

Definition at line 7037 of file DA14680BA.h.

◆ GPIO_P13_MODE_REG_PID_Msk

#define GPIO_P13_MODE_REG_PID_Msk   (0x3fUL)

GPIO P13_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7044 of file DA14680BA.h.

◆ GPIO_P13_MODE_REG_PID_Pos

#define GPIO_P13_MODE_REG_PID_Pos   (0UL)

GPIO P13_MODE_REG: PID (Bit 0)

Definition at line 7043 of file DA14680BA.h.

◆ GPIO_P13_MODE_REG_PPOD_Msk

#define GPIO_P13_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P13_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7048 of file DA14680BA.h.

◆ GPIO_P13_MODE_REG_PPOD_Pos

#define GPIO_P13_MODE_REG_PPOD_Pos   (10UL)

GPIO P13_MODE_REG: PPOD (Bit 10)

Definition at line 7047 of file DA14680BA.h.

◆ GPIO_P13_MODE_REG_PUPD_Msk

#define GPIO_P13_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P13_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7046 of file DA14680BA.h.

◆ GPIO_P13_MODE_REG_PUPD_Pos

#define GPIO_P13_MODE_REG_PUPD_Pos   (8UL)

GPIO P13_MODE_REG: PUPD (Bit 8)

Definition at line 7045 of file DA14680BA.h.

◆ GPIO_P14_MODE_REG_PID_Msk

#define GPIO_P14_MODE_REG_PID_Msk   (0x3fUL)

GPIO P14_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7052 of file DA14680BA.h.

◆ GPIO_P14_MODE_REG_PID_Pos

#define GPIO_P14_MODE_REG_PID_Pos   (0UL)

GPIO P14_MODE_REG: PID (Bit 0)

Definition at line 7051 of file DA14680BA.h.

◆ GPIO_P14_MODE_REG_PPOD_Msk

#define GPIO_P14_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P14_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7056 of file DA14680BA.h.

◆ GPIO_P14_MODE_REG_PPOD_Pos

#define GPIO_P14_MODE_REG_PPOD_Pos   (10UL)

GPIO P14_MODE_REG: PPOD (Bit 10)

Definition at line 7055 of file DA14680BA.h.

◆ GPIO_P14_MODE_REG_PUPD_Msk

#define GPIO_P14_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P14_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7054 of file DA14680BA.h.

◆ GPIO_P14_MODE_REG_PUPD_Pos

#define GPIO_P14_MODE_REG_PUPD_Pos   (8UL)

GPIO P14_MODE_REG: PUPD (Bit 8)

Definition at line 7053 of file DA14680BA.h.

◆ GPIO_P15_MODE_REG_PID_Msk

#define GPIO_P15_MODE_REG_PID_Msk   (0x3fUL)

GPIO P15_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7060 of file DA14680BA.h.

◆ GPIO_P15_MODE_REG_PID_Pos

#define GPIO_P15_MODE_REG_PID_Pos   (0UL)

GPIO P15_MODE_REG: PID (Bit 0)

Definition at line 7059 of file DA14680BA.h.

◆ GPIO_P15_MODE_REG_PPOD_Msk

#define GPIO_P15_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P15_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7064 of file DA14680BA.h.

◆ GPIO_P15_MODE_REG_PPOD_Pos

#define GPIO_P15_MODE_REG_PPOD_Pos   (10UL)

GPIO P15_MODE_REG: PPOD (Bit 10)

Definition at line 7063 of file DA14680BA.h.

◆ GPIO_P15_MODE_REG_PUPD_Msk

#define GPIO_P15_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P15_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7062 of file DA14680BA.h.

◆ GPIO_P15_MODE_REG_PUPD_Pos

#define GPIO_P15_MODE_REG_PUPD_Pos   (8UL)

GPIO P15_MODE_REG: PUPD (Bit 8)

Definition at line 7061 of file DA14680BA.h.

◆ GPIO_P16_MODE_REG_PID_Msk

#define GPIO_P16_MODE_REG_PID_Msk   (0x3fUL)

GPIO P16_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7068 of file DA14680BA.h.

◆ GPIO_P16_MODE_REG_PID_Pos

#define GPIO_P16_MODE_REG_PID_Pos   (0UL)

GPIO P16_MODE_REG: PID (Bit 0)

Definition at line 7067 of file DA14680BA.h.

◆ GPIO_P16_MODE_REG_PPOD_Msk

#define GPIO_P16_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P16_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7072 of file DA14680BA.h.

◆ GPIO_P16_MODE_REG_PPOD_Pos

#define GPIO_P16_MODE_REG_PPOD_Pos   (10UL)

GPIO P16_MODE_REG: PPOD (Bit 10)

Definition at line 7071 of file DA14680BA.h.

◆ GPIO_P16_MODE_REG_PUPD_Msk

#define GPIO_P16_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P16_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7070 of file DA14680BA.h.

◆ GPIO_P16_MODE_REG_PUPD_Pos

#define GPIO_P16_MODE_REG_PUPD_Pos   (8UL)

GPIO P16_MODE_REG: PUPD (Bit 8)

Definition at line 7069 of file DA14680BA.h.

◆ GPIO_P17_MODE_REG_PID_Msk

#define GPIO_P17_MODE_REG_PID_Msk   (0x3fUL)

GPIO P17_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7076 of file DA14680BA.h.

◆ GPIO_P17_MODE_REG_PID_Pos

#define GPIO_P17_MODE_REG_PID_Pos   (0UL)

GPIO P17_MODE_REG: PID (Bit 0)

Definition at line 7075 of file DA14680BA.h.

◆ GPIO_P17_MODE_REG_PPOD_Msk

#define GPIO_P17_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P17_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7080 of file DA14680BA.h.

◆ GPIO_P17_MODE_REG_PPOD_Pos

#define GPIO_P17_MODE_REG_PPOD_Pos   (10UL)

GPIO P17_MODE_REG: PPOD (Bit 10)

Definition at line 7079 of file DA14680BA.h.

◆ GPIO_P17_MODE_REG_PUPD_Msk

#define GPIO_P17_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P17_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7078 of file DA14680BA.h.

◆ GPIO_P17_MODE_REG_PUPD_Pos

#define GPIO_P17_MODE_REG_PUPD_Pos   (8UL)

GPIO P17_MODE_REG: PUPD (Bit 8)

Definition at line 7077 of file DA14680BA.h.

◆ GPIO_P1_DATA_REG_P1_DATA_Msk

#define GPIO_P1_DATA_REG_P1_DATA_Msk   (0xffUL)

GPIO P1_DATA_REG: P1_DATA (Bitfield-Mask: 0xff)

Definition at line 6900 of file DA14680BA.h.

◆ GPIO_P1_DATA_REG_P1_DATA_Pos

#define GPIO_P1_DATA_REG_P1_DATA_Pos   (0UL)

GPIO P1_DATA_REG: P1_DATA (Bit 0)

Definition at line 6899 of file DA14680BA.h.

◆ GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Msk

#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Msk   (0xffUL)

GPIO P1_PADPWR_CTRL_REG: P1_OUT_CTRL (Bitfield-Mask: 0xff)

Definition at line 7256 of file DA14680BA.h.

◆ GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Pos

#define GPIO_P1_PADPWR_CTRL_REG_P1_OUT_CTRL_Pos   (0UL)

GPIO P1_PADPWR_CTRL_REG: P1_OUT_CTRL (Bit 0)

Definition at line 7255 of file DA14680BA.h.

◆ GPIO_P1_RESET_DATA_REG_P1_RESET_Msk

#define GPIO_P1_RESET_DATA_REG_P1_RESET_Msk   (0xffUL)

GPIO P1_RESET_DATA_REG: P1_RESET (Bitfield-Mask: 0xff)

Definition at line 6940 of file DA14680BA.h.

◆ GPIO_P1_RESET_DATA_REG_P1_RESET_Pos

#define GPIO_P1_RESET_DATA_REG_P1_RESET_Pos   (0UL)

GPIO P1_RESET_DATA_REG: P1_RESET (Bit 0)

Definition at line 6939 of file DA14680BA.h.

◆ GPIO_P1_SET_DATA_REG_P1_SET_Msk

#define GPIO_P1_SET_DATA_REG_P1_SET_Msk   (0xffUL)

GPIO P1_SET_DATA_REG: P1_SET (Bitfield-Mask: 0xff)

Definition at line 6920 of file DA14680BA.h.

◆ GPIO_P1_SET_DATA_REG_P1_SET_Pos

#define GPIO_P1_SET_DATA_REG_P1_SET_Pos   (0UL)

GPIO P1_SET_DATA_REG: P1_SET (Bit 0)

Definition at line 6919 of file DA14680BA.h.

◆ GPIO_P20_MODE_REG_PID_Msk

#define GPIO_P20_MODE_REG_PID_Msk   (0x3fUL)

GPIO P20_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7084 of file DA14680BA.h.

◆ GPIO_P20_MODE_REG_PID_Pos

#define GPIO_P20_MODE_REG_PID_Pos   (0UL)

GPIO P20_MODE_REG: PID (Bit 0)

Definition at line 7083 of file DA14680BA.h.

◆ GPIO_P20_MODE_REG_PPOD_Msk

#define GPIO_P20_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P20_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7088 of file DA14680BA.h.

◆ GPIO_P20_MODE_REG_PPOD_Pos

#define GPIO_P20_MODE_REG_PPOD_Pos   (10UL)

GPIO P20_MODE_REG: PPOD (Bit 10)

Definition at line 7087 of file DA14680BA.h.

◆ GPIO_P20_MODE_REG_PUPD_Msk

#define GPIO_P20_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P20_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7086 of file DA14680BA.h.

◆ GPIO_P20_MODE_REG_PUPD_Pos

#define GPIO_P20_MODE_REG_PUPD_Pos   (8UL)

GPIO P20_MODE_REG: PUPD (Bit 8)

Definition at line 7085 of file DA14680BA.h.

◆ GPIO_P21_MODE_REG_PID_Msk

#define GPIO_P21_MODE_REG_PID_Msk   (0x3fUL)

GPIO P21_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7092 of file DA14680BA.h.

◆ GPIO_P21_MODE_REG_PID_Pos

#define GPIO_P21_MODE_REG_PID_Pos   (0UL)

GPIO P21_MODE_REG: PID (Bit 0)

Definition at line 7091 of file DA14680BA.h.

◆ GPIO_P21_MODE_REG_PPOD_Msk

#define GPIO_P21_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P21_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7096 of file DA14680BA.h.

◆ GPIO_P21_MODE_REG_PPOD_Pos

#define GPIO_P21_MODE_REG_PPOD_Pos   (10UL)

GPIO P21_MODE_REG: PPOD (Bit 10)

Definition at line 7095 of file DA14680BA.h.

◆ GPIO_P21_MODE_REG_PUPD_Msk

#define GPIO_P21_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P21_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7094 of file DA14680BA.h.

◆ GPIO_P21_MODE_REG_PUPD_Pos

#define GPIO_P21_MODE_REG_PUPD_Pos   (8UL)

GPIO P21_MODE_REG: PUPD (Bit 8)

Definition at line 7093 of file DA14680BA.h.

◆ GPIO_P22_MODE_REG_PID_Msk

#define GPIO_P22_MODE_REG_PID_Msk   (0x3fUL)

GPIO P22_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7100 of file DA14680BA.h.

◆ GPIO_P22_MODE_REG_PID_Pos

#define GPIO_P22_MODE_REG_PID_Pos   (0UL)

GPIO P22_MODE_REG: PID (Bit 0)

Definition at line 7099 of file DA14680BA.h.

◆ GPIO_P22_MODE_REG_PPOD_Msk

#define GPIO_P22_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P22_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7104 of file DA14680BA.h.

◆ GPIO_P22_MODE_REG_PPOD_Pos

#define GPIO_P22_MODE_REG_PPOD_Pos   (10UL)

GPIO P22_MODE_REG: PPOD (Bit 10)

Definition at line 7103 of file DA14680BA.h.

◆ GPIO_P22_MODE_REG_PUPD_Msk

#define GPIO_P22_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P22_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7102 of file DA14680BA.h.

◆ GPIO_P22_MODE_REG_PUPD_Pos

#define GPIO_P22_MODE_REG_PUPD_Pos   (8UL)

GPIO P22_MODE_REG: PUPD (Bit 8)

Definition at line 7101 of file DA14680BA.h.

◆ GPIO_P23_MODE_REG_PID_Msk

#define GPIO_P23_MODE_REG_PID_Msk   (0x3fUL)

GPIO P23_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7108 of file DA14680BA.h.

◆ GPIO_P23_MODE_REG_PID_Pos

#define GPIO_P23_MODE_REG_PID_Pos   (0UL)

GPIO P23_MODE_REG: PID (Bit 0)

Definition at line 7107 of file DA14680BA.h.

◆ GPIO_P23_MODE_REG_PPOD_Msk

#define GPIO_P23_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P23_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7112 of file DA14680BA.h.

◆ GPIO_P23_MODE_REG_PPOD_Pos

#define GPIO_P23_MODE_REG_PPOD_Pos   (10UL)

GPIO P23_MODE_REG: PPOD (Bit 10)

Definition at line 7111 of file DA14680BA.h.

◆ GPIO_P23_MODE_REG_PUPD_Msk

#define GPIO_P23_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P23_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7110 of file DA14680BA.h.

◆ GPIO_P23_MODE_REG_PUPD_Pos

#define GPIO_P23_MODE_REG_PUPD_Pos   (8UL)

GPIO P23_MODE_REG: PUPD (Bit 8)

Definition at line 7109 of file DA14680BA.h.

◆ GPIO_P24_MODE_REG_PID_Msk

#define GPIO_P24_MODE_REG_PID_Msk   (0x3fUL)

GPIO P24_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7116 of file DA14680BA.h.

◆ GPIO_P24_MODE_REG_PID_Pos

#define GPIO_P24_MODE_REG_PID_Pos   (0UL)

GPIO P24_MODE_REG: PID (Bit 0)

Definition at line 7115 of file DA14680BA.h.

◆ GPIO_P24_MODE_REG_PPOD_Msk

#define GPIO_P24_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P24_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7120 of file DA14680BA.h.

◆ GPIO_P24_MODE_REG_PPOD_Pos

#define GPIO_P24_MODE_REG_PPOD_Pos   (10UL)

GPIO P24_MODE_REG: PPOD (Bit 10)

Definition at line 7119 of file DA14680BA.h.

◆ GPIO_P24_MODE_REG_PUPD_Msk

#define GPIO_P24_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P24_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7118 of file DA14680BA.h.

◆ GPIO_P24_MODE_REG_PUPD_Pos

#define GPIO_P24_MODE_REG_PUPD_Pos   (8UL)

GPIO P24_MODE_REG: PUPD (Bit 8)

Definition at line 7117 of file DA14680BA.h.

◆ GPIO_P2_DATA_REG_P2_DATA_Msk

#define GPIO_P2_DATA_REG_P2_DATA_Msk   (0x1fUL)

GPIO P2_DATA_REG: P2_DATA (Bitfield-Mask: 0x1f)

Definition at line 6904 of file DA14680BA.h.

◆ GPIO_P2_DATA_REG_P2_DATA_Pos

#define GPIO_P2_DATA_REG_P2_DATA_Pos   (0UL)

GPIO P2_DATA_REG: P2_DATA (Bit 0)

Definition at line 6903 of file DA14680BA.h.

◆ GPIO_P2_PADPWR_CTRL_REG_P2_OUT_CTRL_Msk

#define GPIO_P2_PADPWR_CTRL_REG_P2_OUT_CTRL_Msk   (0x1fUL)

GPIO P2_PADPWR_CTRL_REG: P2_OUT_CTRL (Bitfield-Mask: 0x1f)

Definition at line 7260 of file DA14680BA.h.

◆ GPIO_P2_PADPWR_CTRL_REG_P2_OUT_CTRL_Pos

#define GPIO_P2_PADPWR_CTRL_REG_P2_OUT_CTRL_Pos   (0UL)

GPIO P2_PADPWR_CTRL_REG: P2_OUT_CTRL (Bit 0)

Definition at line 7259 of file DA14680BA.h.

◆ GPIO_P2_RESET_DATA_REG_P2_RESET_Msk

#define GPIO_P2_RESET_DATA_REG_P2_RESET_Msk   (0x1fUL)

GPIO P2_RESET_DATA_REG: P2_RESET (Bitfield-Mask: 0x1f)

Definition at line 6944 of file DA14680BA.h.

◆ GPIO_P2_RESET_DATA_REG_P2_RESET_Pos

#define GPIO_P2_RESET_DATA_REG_P2_RESET_Pos   (0UL)

GPIO P2_RESET_DATA_REG: P2_RESET (Bit 0)

Definition at line 6943 of file DA14680BA.h.

◆ GPIO_P2_SET_DATA_REG_P2_SET_Msk

#define GPIO_P2_SET_DATA_REG_P2_SET_Msk   (0x1fUL)

GPIO P2_SET_DATA_REG: P2_SET (Bitfield-Mask: 0x1f)

Definition at line 6924 of file DA14680BA.h.

◆ GPIO_P2_SET_DATA_REG_P2_SET_Pos

#define GPIO_P2_SET_DATA_REG_P2_SET_Pos   (0UL)

GPIO P2_SET_DATA_REG: P2_SET (Bit 0)

Definition at line 6923 of file DA14680BA.h.

◆ GPIO_P30_MODE_REG_PID_Msk

#define GPIO_P30_MODE_REG_PID_Msk   (0x3fUL)

GPIO P30_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7124 of file DA14680BA.h.

◆ GPIO_P30_MODE_REG_PID_Pos

#define GPIO_P30_MODE_REG_PID_Pos   (0UL)

GPIO P30_MODE_REG: PID (Bit 0)

Definition at line 7123 of file DA14680BA.h.

◆ GPIO_P30_MODE_REG_PPOD_Msk

#define GPIO_P30_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P30_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7128 of file DA14680BA.h.

◆ GPIO_P30_MODE_REG_PPOD_Pos

#define GPIO_P30_MODE_REG_PPOD_Pos   (10UL)

GPIO P30_MODE_REG: PPOD (Bit 10)

Definition at line 7127 of file DA14680BA.h.

◆ GPIO_P30_MODE_REG_PUPD_Msk

#define GPIO_P30_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P30_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7126 of file DA14680BA.h.

◆ GPIO_P30_MODE_REG_PUPD_Pos

#define GPIO_P30_MODE_REG_PUPD_Pos   (8UL)

GPIO P30_MODE_REG: PUPD (Bit 8)

Definition at line 7125 of file DA14680BA.h.

◆ GPIO_P31_MODE_REG_PID_Msk

#define GPIO_P31_MODE_REG_PID_Msk   (0x3fUL)

GPIO P31_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7132 of file DA14680BA.h.

◆ GPIO_P31_MODE_REG_PID_Pos

#define GPIO_P31_MODE_REG_PID_Pos   (0UL)

GPIO P31_MODE_REG: PID (Bit 0)

Definition at line 7131 of file DA14680BA.h.

◆ GPIO_P31_MODE_REG_PPOD_Msk

#define GPIO_P31_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P31_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7136 of file DA14680BA.h.

◆ GPIO_P31_MODE_REG_PPOD_Pos

#define GPIO_P31_MODE_REG_PPOD_Pos   (10UL)

GPIO P31_MODE_REG: PPOD (Bit 10)

Definition at line 7135 of file DA14680BA.h.

◆ GPIO_P31_MODE_REG_PUPD_Msk

#define GPIO_P31_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P31_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7134 of file DA14680BA.h.

◆ GPIO_P31_MODE_REG_PUPD_Pos

#define GPIO_P31_MODE_REG_PUPD_Pos   (8UL)

GPIO P31_MODE_REG: PUPD (Bit 8)

Definition at line 7133 of file DA14680BA.h.

◆ GPIO_P32_MODE_REG_PID_Msk

#define GPIO_P32_MODE_REG_PID_Msk   (0x3fUL)

GPIO P32_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7140 of file DA14680BA.h.

◆ GPIO_P32_MODE_REG_PID_Pos

#define GPIO_P32_MODE_REG_PID_Pos   (0UL)

GPIO P32_MODE_REG: PID (Bit 0)

Definition at line 7139 of file DA14680BA.h.

◆ GPIO_P32_MODE_REG_PPOD_Msk

#define GPIO_P32_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P32_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7144 of file DA14680BA.h.

◆ GPIO_P32_MODE_REG_PPOD_Pos

#define GPIO_P32_MODE_REG_PPOD_Pos   (10UL)

GPIO P32_MODE_REG: PPOD (Bit 10)

Definition at line 7143 of file DA14680BA.h.

◆ GPIO_P32_MODE_REG_PUPD_Msk

#define GPIO_P32_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P32_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7142 of file DA14680BA.h.

◆ GPIO_P32_MODE_REG_PUPD_Pos

#define GPIO_P32_MODE_REG_PUPD_Pos   (8UL)

GPIO P32_MODE_REG: PUPD (Bit 8)

Definition at line 7141 of file DA14680BA.h.

◆ GPIO_P33_MODE_REG_PID_Msk

#define GPIO_P33_MODE_REG_PID_Msk   (0x3fUL)

GPIO P33_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7148 of file DA14680BA.h.

◆ GPIO_P33_MODE_REG_PID_Pos

#define GPIO_P33_MODE_REG_PID_Pos   (0UL)

GPIO P33_MODE_REG: PID (Bit 0)

Definition at line 7147 of file DA14680BA.h.

◆ GPIO_P33_MODE_REG_PPOD_Msk

#define GPIO_P33_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P33_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7152 of file DA14680BA.h.

◆ GPIO_P33_MODE_REG_PPOD_Pos

#define GPIO_P33_MODE_REG_PPOD_Pos   (10UL)

GPIO P33_MODE_REG: PPOD (Bit 10)

Definition at line 7151 of file DA14680BA.h.

◆ GPIO_P33_MODE_REG_PUPD_Msk

#define GPIO_P33_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P33_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7150 of file DA14680BA.h.

◆ GPIO_P33_MODE_REG_PUPD_Pos

#define GPIO_P33_MODE_REG_PUPD_Pos   (8UL)

GPIO P33_MODE_REG: PUPD (Bit 8)

Definition at line 7149 of file DA14680BA.h.

◆ GPIO_P34_MODE_REG_PID_Msk

#define GPIO_P34_MODE_REG_PID_Msk   (0x3fUL)

GPIO P34_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7156 of file DA14680BA.h.

◆ GPIO_P34_MODE_REG_PID_Pos

#define GPIO_P34_MODE_REG_PID_Pos   (0UL)

GPIO P34_MODE_REG: PID (Bit 0)

Definition at line 7155 of file DA14680BA.h.

◆ GPIO_P34_MODE_REG_PPOD_Msk

#define GPIO_P34_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P34_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7160 of file DA14680BA.h.

◆ GPIO_P34_MODE_REG_PPOD_Pos

#define GPIO_P34_MODE_REG_PPOD_Pos   (10UL)

GPIO P34_MODE_REG: PPOD (Bit 10)

Definition at line 7159 of file DA14680BA.h.

◆ GPIO_P34_MODE_REG_PUPD_Msk

#define GPIO_P34_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P34_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7158 of file DA14680BA.h.

◆ GPIO_P34_MODE_REG_PUPD_Pos

#define GPIO_P34_MODE_REG_PUPD_Pos   (8UL)

GPIO P34_MODE_REG: PUPD (Bit 8)

Definition at line 7157 of file DA14680BA.h.

◆ GPIO_P35_MODE_REG_PID_Msk

#define GPIO_P35_MODE_REG_PID_Msk   (0x3fUL)

GPIO P35_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7164 of file DA14680BA.h.

◆ GPIO_P35_MODE_REG_PID_Pos

#define GPIO_P35_MODE_REG_PID_Pos   (0UL)

GPIO P35_MODE_REG: PID (Bit 0)

Definition at line 7163 of file DA14680BA.h.

◆ GPIO_P35_MODE_REG_PPOD_Msk

#define GPIO_P35_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P35_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7168 of file DA14680BA.h.

◆ GPIO_P35_MODE_REG_PPOD_Pos

#define GPIO_P35_MODE_REG_PPOD_Pos   (10UL)

GPIO P35_MODE_REG: PPOD (Bit 10)

Definition at line 7167 of file DA14680BA.h.

◆ GPIO_P35_MODE_REG_PUPD_Msk

#define GPIO_P35_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P35_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7166 of file DA14680BA.h.

◆ GPIO_P35_MODE_REG_PUPD_Pos

#define GPIO_P35_MODE_REG_PUPD_Pos   (8UL)

GPIO P35_MODE_REG: PUPD (Bit 8)

Definition at line 7165 of file DA14680BA.h.

◆ GPIO_P36_MODE_REG_PID_Msk

#define GPIO_P36_MODE_REG_PID_Msk   (0x3fUL)

GPIO P36_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7172 of file DA14680BA.h.

◆ GPIO_P36_MODE_REG_PID_Pos

#define GPIO_P36_MODE_REG_PID_Pos   (0UL)

GPIO P36_MODE_REG: PID (Bit 0)

Definition at line 7171 of file DA14680BA.h.

◆ GPIO_P36_MODE_REG_PPOD_Msk

#define GPIO_P36_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P36_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7176 of file DA14680BA.h.

◆ GPIO_P36_MODE_REG_PPOD_Pos

#define GPIO_P36_MODE_REG_PPOD_Pos   (10UL)

GPIO P36_MODE_REG: PPOD (Bit 10)

Definition at line 7175 of file DA14680BA.h.

◆ GPIO_P36_MODE_REG_PUPD_Msk

#define GPIO_P36_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P36_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7174 of file DA14680BA.h.

◆ GPIO_P36_MODE_REG_PUPD_Pos

#define GPIO_P36_MODE_REG_PUPD_Pos   (8UL)

GPIO P36_MODE_REG: PUPD (Bit 8)

Definition at line 7173 of file DA14680BA.h.

◆ GPIO_P37_MODE_REG_PID_Msk

#define GPIO_P37_MODE_REG_PID_Msk   (0x3fUL)

GPIO P37_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7180 of file DA14680BA.h.

◆ GPIO_P37_MODE_REG_PID_Pos

#define GPIO_P37_MODE_REG_PID_Pos   (0UL)

GPIO P37_MODE_REG: PID (Bit 0)

Definition at line 7179 of file DA14680BA.h.

◆ GPIO_P37_MODE_REG_PPOD_Msk

#define GPIO_P37_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P37_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7184 of file DA14680BA.h.

◆ GPIO_P37_MODE_REG_PPOD_Pos

#define GPIO_P37_MODE_REG_PPOD_Pos   (10UL)

GPIO P37_MODE_REG: PPOD (Bit 10)

Definition at line 7183 of file DA14680BA.h.

◆ GPIO_P37_MODE_REG_PUPD_Msk

#define GPIO_P37_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P37_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7182 of file DA14680BA.h.

◆ GPIO_P37_MODE_REG_PUPD_Pos

#define GPIO_P37_MODE_REG_PUPD_Pos   (8UL)

GPIO P37_MODE_REG: PUPD (Bit 8)

Definition at line 7181 of file DA14680BA.h.

◆ GPIO_P3_DATA_REG_P3_DATA_Msk

#define GPIO_P3_DATA_REG_P3_DATA_Msk   (0xffUL)

GPIO P3_DATA_REG: P3_DATA (Bitfield-Mask: 0xff)

Definition at line 6908 of file DA14680BA.h.

◆ GPIO_P3_DATA_REG_P3_DATA_Pos

#define GPIO_P3_DATA_REG_P3_DATA_Pos   (0UL)

GPIO P3_DATA_REG: P3_DATA (Bit 0)

Definition at line 6907 of file DA14680BA.h.

◆ GPIO_P3_PADPWR_CTRL_REG_P3_OUT_CTRL_Msk

#define GPIO_P3_PADPWR_CTRL_REG_P3_OUT_CTRL_Msk   (0xffUL)

GPIO P3_PADPWR_CTRL_REG: P3_OUT_CTRL (Bitfield-Mask: 0xff)

Definition at line 7264 of file DA14680BA.h.

◆ GPIO_P3_PADPWR_CTRL_REG_P3_OUT_CTRL_Pos

#define GPIO_P3_PADPWR_CTRL_REG_P3_OUT_CTRL_Pos   (0UL)

GPIO P3_PADPWR_CTRL_REG: P3_OUT_CTRL (Bit 0)

Definition at line 7263 of file DA14680BA.h.

◆ GPIO_P3_RESET_DATA_REG_P3_RESET_Msk

#define GPIO_P3_RESET_DATA_REG_P3_RESET_Msk   (0xffUL)

GPIO P3_RESET_DATA_REG: P3_RESET (Bitfield-Mask: 0xff)

Definition at line 6948 of file DA14680BA.h.

◆ GPIO_P3_RESET_DATA_REG_P3_RESET_Pos

#define GPIO_P3_RESET_DATA_REG_P3_RESET_Pos   (0UL)

GPIO P3_RESET_DATA_REG: P3_RESET (Bit 0)

Definition at line 6947 of file DA14680BA.h.

◆ GPIO_P3_SET_DATA_REG_P3_SET_Msk

#define GPIO_P3_SET_DATA_REG_P3_SET_Msk   (0xffUL)

GPIO P3_SET_DATA_REG: P3_SET (Bitfield-Mask: 0xff)

Definition at line 6928 of file DA14680BA.h.

◆ GPIO_P3_SET_DATA_REG_P3_SET_Pos

#define GPIO_P3_SET_DATA_REG_P3_SET_Pos   (0UL)

GPIO P3_SET_DATA_REG: P3_SET (Bit 0)

Definition at line 6927 of file DA14680BA.h.

◆ GPIO_P40_MODE_REG_PID_Msk

#define GPIO_P40_MODE_REG_PID_Msk   (0x3fUL)

GPIO P40_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7188 of file DA14680BA.h.

◆ GPIO_P40_MODE_REG_PID_Pos

#define GPIO_P40_MODE_REG_PID_Pos   (0UL)

GPIO P40_MODE_REG: PID (Bit 0)

Definition at line 7187 of file DA14680BA.h.

◆ GPIO_P40_MODE_REG_PPOD_Msk

#define GPIO_P40_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P40_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7192 of file DA14680BA.h.

◆ GPIO_P40_MODE_REG_PPOD_Pos

#define GPIO_P40_MODE_REG_PPOD_Pos   (10UL)

GPIO P40_MODE_REG: PPOD (Bit 10)

Definition at line 7191 of file DA14680BA.h.

◆ GPIO_P40_MODE_REG_PUPD_Msk

#define GPIO_P40_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P40_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7190 of file DA14680BA.h.

◆ GPIO_P40_MODE_REG_PUPD_Pos

#define GPIO_P40_MODE_REG_PUPD_Pos   (8UL)

GPIO P40_MODE_REG: PUPD (Bit 8)

Definition at line 7189 of file DA14680BA.h.

◆ GPIO_P41_MODE_REG_PID_Msk

#define GPIO_P41_MODE_REG_PID_Msk   (0x3fUL)

GPIO P41_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7196 of file DA14680BA.h.

◆ GPIO_P41_MODE_REG_PID_Pos

#define GPIO_P41_MODE_REG_PID_Pos   (0UL)

GPIO P41_MODE_REG: PID (Bit 0)

Definition at line 7195 of file DA14680BA.h.

◆ GPIO_P41_MODE_REG_PPOD_Msk

#define GPIO_P41_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P41_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7200 of file DA14680BA.h.

◆ GPIO_P41_MODE_REG_PPOD_Pos

#define GPIO_P41_MODE_REG_PPOD_Pos   (10UL)

GPIO P41_MODE_REG: PPOD (Bit 10)

Definition at line 7199 of file DA14680BA.h.

◆ GPIO_P41_MODE_REG_PUPD_Msk

#define GPIO_P41_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P41_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7198 of file DA14680BA.h.

◆ GPIO_P41_MODE_REG_PUPD_Pos

#define GPIO_P41_MODE_REG_PUPD_Pos   (8UL)

GPIO P41_MODE_REG: PUPD (Bit 8)

Definition at line 7197 of file DA14680BA.h.

◆ GPIO_P42_MODE_REG_PID_Msk

#define GPIO_P42_MODE_REG_PID_Msk   (0x3fUL)

GPIO P42_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7204 of file DA14680BA.h.

◆ GPIO_P42_MODE_REG_PID_Pos

#define GPIO_P42_MODE_REG_PID_Pos   (0UL)

GPIO P42_MODE_REG: PID (Bit 0)

Definition at line 7203 of file DA14680BA.h.

◆ GPIO_P42_MODE_REG_PPOD_Msk

#define GPIO_P42_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P42_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7208 of file DA14680BA.h.

◆ GPIO_P42_MODE_REG_PPOD_Pos

#define GPIO_P42_MODE_REG_PPOD_Pos   (10UL)

GPIO P42_MODE_REG: PPOD (Bit 10)

Definition at line 7207 of file DA14680BA.h.

◆ GPIO_P42_MODE_REG_PUPD_Msk

#define GPIO_P42_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P42_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7206 of file DA14680BA.h.

◆ GPIO_P42_MODE_REG_PUPD_Pos

#define GPIO_P42_MODE_REG_PUPD_Pos   (8UL)

GPIO P42_MODE_REG: PUPD (Bit 8)

Definition at line 7205 of file DA14680BA.h.

◆ GPIO_P43_MODE_REG_PID_Msk

#define GPIO_P43_MODE_REG_PID_Msk   (0x3fUL)

GPIO P43_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7212 of file DA14680BA.h.

◆ GPIO_P43_MODE_REG_PID_Pos

#define GPIO_P43_MODE_REG_PID_Pos   (0UL)

GPIO P43_MODE_REG: PID (Bit 0)

Definition at line 7211 of file DA14680BA.h.

◆ GPIO_P43_MODE_REG_PPOD_Msk

#define GPIO_P43_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P43_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7216 of file DA14680BA.h.

◆ GPIO_P43_MODE_REG_PPOD_Pos

#define GPIO_P43_MODE_REG_PPOD_Pos   (10UL)

GPIO P43_MODE_REG: PPOD (Bit 10)

Definition at line 7215 of file DA14680BA.h.

◆ GPIO_P43_MODE_REG_PUPD_Msk

#define GPIO_P43_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P43_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7214 of file DA14680BA.h.

◆ GPIO_P43_MODE_REG_PUPD_Pos

#define GPIO_P43_MODE_REG_PUPD_Pos   (8UL)

GPIO P43_MODE_REG: PUPD (Bit 8)

Definition at line 7213 of file DA14680BA.h.

◆ GPIO_P44_MODE_REG_PID_Msk

#define GPIO_P44_MODE_REG_PID_Msk   (0x3fUL)

GPIO P44_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7220 of file DA14680BA.h.

◆ GPIO_P44_MODE_REG_PID_Pos

#define GPIO_P44_MODE_REG_PID_Pos   (0UL)

GPIO P44_MODE_REG: PID (Bit 0)

Definition at line 7219 of file DA14680BA.h.

◆ GPIO_P44_MODE_REG_PPOD_Msk

#define GPIO_P44_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P44_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7224 of file DA14680BA.h.

◆ GPIO_P44_MODE_REG_PPOD_Pos

#define GPIO_P44_MODE_REG_PPOD_Pos   (10UL)

GPIO P44_MODE_REG: PPOD (Bit 10)

Definition at line 7223 of file DA14680BA.h.

◆ GPIO_P44_MODE_REG_PUPD_Msk

#define GPIO_P44_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P44_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7222 of file DA14680BA.h.

◆ GPIO_P44_MODE_REG_PUPD_Pos

#define GPIO_P44_MODE_REG_PUPD_Pos   (8UL)

GPIO P44_MODE_REG: PUPD (Bit 8)

Definition at line 7221 of file DA14680BA.h.

◆ GPIO_P45_MODE_REG_PID_Msk

#define GPIO_P45_MODE_REG_PID_Msk   (0x3fUL)

GPIO P45_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7228 of file DA14680BA.h.

◆ GPIO_P45_MODE_REG_PID_Pos

#define GPIO_P45_MODE_REG_PID_Pos   (0UL)

GPIO P45_MODE_REG: PID (Bit 0)

Definition at line 7227 of file DA14680BA.h.

◆ GPIO_P45_MODE_REG_PPOD_Msk

#define GPIO_P45_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P45_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7232 of file DA14680BA.h.

◆ GPIO_P45_MODE_REG_PPOD_Pos

#define GPIO_P45_MODE_REG_PPOD_Pos   (10UL)

GPIO P45_MODE_REG: PPOD (Bit 10)

Definition at line 7231 of file DA14680BA.h.

◆ GPIO_P45_MODE_REG_PUPD_Msk

#define GPIO_P45_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P45_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7230 of file DA14680BA.h.

◆ GPIO_P45_MODE_REG_PUPD_Pos

#define GPIO_P45_MODE_REG_PUPD_Pos   (8UL)

GPIO P45_MODE_REG: PUPD (Bit 8)

Definition at line 7229 of file DA14680BA.h.

◆ GPIO_P46_MODE_REG_PID_Msk

#define GPIO_P46_MODE_REG_PID_Msk   (0x3fUL)

GPIO P46_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7236 of file DA14680BA.h.

◆ GPIO_P46_MODE_REG_PID_Pos

#define GPIO_P46_MODE_REG_PID_Pos   (0UL)

GPIO P46_MODE_REG: PID (Bit 0)

Definition at line 7235 of file DA14680BA.h.

◆ GPIO_P46_MODE_REG_PPOD_Msk

#define GPIO_P46_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P46_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7240 of file DA14680BA.h.

◆ GPIO_P46_MODE_REG_PPOD_Pos

#define GPIO_P46_MODE_REG_PPOD_Pos   (10UL)

GPIO P46_MODE_REG: PPOD (Bit 10)

Definition at line 7239 of file DA14680BA.h.

◆ GPIO_P46_MODE_REG_PUPD_Msk

#define GPIO_P46_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P46_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7238 of file DA14680BA.h.

◆ GPIO_P46_MODE_REG_PUPD_Pos

#define GPIO_P46_MODE_REG_PUPD_Pos   (8UL)

GPIO P46_MODE_REG: PUPD (Bit 8)

Definition at line 7237 of file DA14680BA.h.

◆ GPIO_P47_MODE_REG_PID_Msk

#define GPIO_P47_MODE_REG_PID_Msk   (0x3fUL)

GPIO P47_MODE_REG: PID (Bitfield-Mask: 0x3f)

Definition at line 7244 of file DA14680BA.h.

◆ GPIO_P47_MODE_REG_PID_Pos

#define GPIO_P47_MODE_REG_PID_Pos   (0UL)

GPIO P47_MODE_REG: PID (Bit 0)

Definition at line 7243 of file DA14680BA.h.

◆ GPIO_P47_MODE_REG_PPOD_Msk

#define GPIO_P47_MODE_REG_PPOD_Msk   (0x400UL)

GPIO P47_MODE_REG: PPOD (Bitfield-Mask: 0x01)

Definition at line 7248 of file DA14680BA.h.

◆ GPIO_P47_MODE_REG_PPOD_Pos

#define GPIO_P47_MODE_REG_PPOD_Pos   (10UL)

GPIO P47_MODE_REG: PPOD (Bit 10)

Definition at line 7247 of file DA14680BA.h.

◆ GPIO_P47_MODE_REG_PUPD_Msk

#define GPIO_P47_MODE_REG_PUPD_Msk   (0x300UL)

GPIO P47_MODE_REG: PUPD (Bitfield-Mask: 0x03)

Definition at line 7246 of file DA14680BA.h.

◆ GPIO_P47_MODE_REG_PUPD_Pos

#define GPIO_P47_MODE_REG_PUPD_Pos   (8UL)

GPIO P47_MODE_REG: PUPD (Bit 8)

Definition at line 7245 of file DA14680BA.h.

◆ GPIO_P4_DATA_REG_P4_DATA_Msk

#define GPIO_P4_DATA_REG_P4_DATA_Msk   (0xffUL)

GPIO P4_DATA_REG: P4_DATA (Bitfield-Mask: 0xff)

Definition at line 6912 of file DA14680BA.h.

◆ GPIO_P4_DATA_REG_P4_DATA_Pos

#define GPIO_P4_DATA_REG_P4_DATA_Pos   (0UL)

GPIO P4_DATA_REG: P4_DATA (Bit 0)

Definition at line 6911 of file DA14680BA.h.

◆ GPIO_P4_PADPWR_CTRL_REG_P4_OUT_CTRL_Msk

#define GPIO_P4_PADPWR_CTRL_REG_P4_OUT_CTRL_Msk   (0xffUL)

GPIO P4_PADPWR_CTRL_REG: P4_OUT_CTRL (Bitfield-Mask: 0xff)

Definition at line 7268 of file DA14680BA.h.

◆ GPIO_P4_PADPWR_CTRL_REG_P4_OUT_CTRL_Pos

#define GPIO_P4_PADPWR_CTRL_REG_P4_OUT_CTRL_Pos   (0UL)

GPIO P4_PADPWR_CTRL_REG: P4_OUT_CTRL (Bit 0)

Definition at line 7267 of file DA14680BA.h.

◆ GPIO_P4_RESET_DATA_REG_P4_RESET_Msk

#define GPIO_P4_RESET_DATA_REG_P4_RESET_Msk   (0xffUL)

GPIO P4_RESET_DATA_REG: P4_RESET (Bitfield-Mask: 0xff)

Definition at line 6952 of file DA14680BA.h.

◆ GPIO_P4_RESET_DATA_REG_P4_RESET_Pos

#define GPIO_P4_RESET_DATA_REG_P4_RESET_Pos   (0UL)

GPIO P4_RESET_DATA_REG: P4_RESET (Bit 0)

Definition at line 6951 of file DA14680BA.h.

◆ GPIO_P4_SET_DATA_REG_P4_SET_Msk

#define GPIO_P4_SET_DATA_REG_P4_SET_Msk   (0xffUL)

GPIO P4_SET_DATA_REG: P4_SET (Bitfield-Mask: 0xff)

Definition at line 6932 of file DA14680BA.h.

◆ GPIO_P4_SET_DATA_REG_P4_SET_Pos

#define GPIO_P4_SET_DATA_REG_P4_SET_Pos   (0UL)

GPIO P4_SET_DATA_REG: P4_SET (Bit 0)

Definition at line 6931 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_BUSY_Msk

#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_BUSY_Msk   (0x100UL)

GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_BUSY (Bitfield-Mask: 0x01)

Definition at line 7306 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_BUSY_Pos

#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_BUSY_Pos   (8UL)

GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_BUSY (Bit 8)

Definition at line 7305 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_FAIL_Msk

#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_FAIL_Msk   (0x80UL)

GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_FAIL (Bitfield-Mask: 0x01)

Definition at line 7304 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_FAIL_Pos

#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_FAIL_Pos   (7UL)

GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_FAIL (Bit 7)

Definition at line 7303 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_LINE_FAIL_Msk

#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_LINE_FAIL_Msk   (0x40UL)

GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01)

Definition at line 7302 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_LINE_FAIL_Pos

#define GPIO_RAMBIST_STATUS1_REG_CDRAM_BIST_LINE_FAIL_Pos   (6UL)

GPIO RAMBIST_STATUS1_REG: CDRAM_BIST_LINE_FAIL (Bit 6)

Definition at line 7301 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_BUSY_Msk

#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_BUSY_Msk   (0x20UL)

GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_BUSY (Bitfield-Mask: 0x01)

Definition at line 7300 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_BUSY_Pos

#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_BUSY_Pos   (5UL)

GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_BUSY (Bit 5)

Definition at line 7299 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_FAIL_Msk

#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_FAIL_Msk   (0x10UL)

GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_FAIL (Bitfield-Mask: 0x01)

Definition at line 7298 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_FAIL_Pos

#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_FAIL_Pos   (4UL)

GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_FAIL (Bit 4)

Definition at line 7297 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_LINE_FAIL_Msk

#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_LINE_FAIL_Msk   (0x8UL)

GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01)

Definition at line 7296 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_LINE_FAIL_Pos

#define GPIO_RAMBIST_STATUS1_REG_CTRAM_BIST_LINE_FAIL_Pos   (3UL)

GPIO RAMBIST_STATUS1_REG: CTRAM_BIST_LINE_FAIL (Bit 3)

Definition at line 7295 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_BUSY_Msk

#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_BUSY_Msk   (0x4000UL)

GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_BUSY (Bitfield-Mask: 0x01)

Definition at line 7318 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_BUSY_Pos

#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_BUSY_Pos   (14UL)

GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_BUSY (Bit 14)

Definition at line 7317 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_FAIL_Msk

#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_FAIL_Msk   (0x2000UL)

GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_FAIL (Bitfield-Mask: 0x01)

Definition at line 7316 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_FAIL_Pos

#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_FAIL_Pos   (13UL)

GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_FAIL (Bit 13)

Definition at line 7315 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_LINE_FAIL_Msk

#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_LINE_FAIL_Msk   (0x1000UL)

GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01)

Definition at line 7314 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_LINE_FAIL_Pos

#define GPIO_RAMBIST_STATUS1_REG_QSPIRAM_BIST_LINE_FAIL_Pos   (12UL)

GPIO RAMBIST_STATUS1_REG: QSPIRAM_BIST_LINE_FAIL (Bit 12)

Definition at line 7313 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_ROM_BIST_BUSY_Msk

#define GPIO_RAMBIST_STATUS1_REG_ROM_BIST_BUSY_Msk   (0x8000UL)

GPIO RAMBIST_STATUS1_REG: ROM_BIST_BUSY (Bitfield-Mask: 0x01)

Definition at line 7320 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_ROM_BIST_BUSY_Pos

#define GPIO_RAMBIST_STATUS1_REG_ROM_BIST_BUSY_Pos   (15UL)

GPIO RAMBIST_STATUS1_REG: ROM_BIST_BUSY (Bit 15)

Definition at line 7319 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_BUSY_Msk

#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_BUSY_Msk   (0x4UL)

GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_BUSY (Bitfield-Mask: 0x01)

Definition at line 7294 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_BUSY_Pos

#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_BUSY_Pos   (2UL)

GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_BUSY (Bit 2)

Definition at line 7293 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_FAIL_Msk

#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_FAIL_Msk   (0x2UL)

GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_FAIL (Bitfield-Mask: 0x01)

Definition at line 7292 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_FAIL_Pos

#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_FAIL_Pos   (1UL)

GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_FAIL (Bit 1)

Definition at line 7291 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_LINE_FAIL_Msk

#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_LINE_FAIL_Msk   (0x1UL)

GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01)

Definition at line 7290 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_LINE_FAIL_Pos

#define GPIO_RAMBIST_STATUS1_REG_SYSRAM_BIST_LINE_FAIL_Pos   (0UL)

GPIO RAMBIST_STATUS1_REG: SYSRAM_BIST_LINE_FAIL (Bit 0)

Definition at line 7289 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_BUSY_Msk

#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_BUSY_Msk   (0x800UL)

GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_BUSY (Bitfield-Mask: 0x01)

Definition at line 7312 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_BUSY_Pos

#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_BUSY_Pos   (11UL)

GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_BUSY (Bit 11)

Definition at line 7311 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_FAIL_Msk

#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_FAIL_Msk   (0x400UL)

GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_FAIL (Bitfield-Mask: 0x01)

Definition at line 7310 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_FAIL_Pos

#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_FAIL_Pos   (10UL)

GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_FAIL (Bit 10)

Definition at line 7309 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_LINE_FAIL_Msk

#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_LINE_FAIL_Msk   (0x200UL)

GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01)

Definition at line 7308 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_LINE_FAIL_Pos

#define GPIO_RAMBIST_STATUS1_REG_USBRAM_BIST_LINE_FAIL_Pos   (9UL)

GPIO RAMBIST_STATUS1_REG: USBRAM_BIST_LINE_FAIL (Bit 9)

Definition at line 7307 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_BUSY_Msk

#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_BUSY_Msk   (0x4000UL)

GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_BUSY (Bitfield-Mask: 0x01)

Definition at line 7352 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_BUSY_Pos

#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_BUSY_Pos   (14UL)

GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_BUSY (Bit 14)

Definition at line 7351 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_FAIL_Msk

#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_FAIL_Msk   (0x2000UL)

GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_FAIL (Bitfield-Mask: 0x01)

Definition at line 7350 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_FAIL_Pos

#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_FAIL_Pos   (13UL)

GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_FAIL (Bit 13)

Definition at line 7349 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_LINE_FAIL_Msk

#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_LINE_FAIL_Msk   (0x1000UL)

GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01)

Definition at line 7348 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_LINE_FAIL_Pos

#define GPIO_RAMBIST_STATUS2_REG_CRYPTORAM_BIST_LINE_FAIL_Pos   (12UL)

GPIO RAMBIST_STATUS2_REG: CRYPTORAM_BIST_LINE_FAIL (Bit 12)

Definition at line 7347 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_BUSY_Msk

#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_BUSY_Msk   (0x100UL)

GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_BUSY (Bitfield-Mask: 0x01)

Definition at line 7340 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_BUSY_Pos

#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_BUSY_Pos   (8UL)

GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_BUSY (Bit 8)

Definition at line 7339 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_FAIL_Msk

#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_FAIL_Msk   (0x80UL)

GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_FAIL (Bitfield-Mask: 0x01)

Definition at line 7338 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_FAIL_Pos

#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_FAIL_Pos   (7UL)

GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_FAIL (Bit 7)

Definition at line 7337 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_LINE_FAIL_Msk

#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_LINE_FAIL_Msk   (0x40UL)

GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01)

Definition at line 7336 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_LINE_FAIL_Pos

#define GPIO_RAMBIST_STATUS2_REG_ECC_CODERAM_BIST_LINE_FAIL_Pos   (6UL)

GPIO RAMBIST_STATUS2_REG: ECC_CODERAM_BIST_LINE_FAIL (Bit 6)

Definition at line 7335 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_BUSY_Msk

#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_BUSY_Msk   (0x800UL)

GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_BUSY (Bitfield-Mask: 0x01)

Definition at line 7346 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_BUSY_Pos

#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_BUSY_Pos   (11UL)

GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_BUSY (Bit 11)

Definition at line 7345 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_FAIL_Msk

#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_FAIL_Msk   (0x400UL)

GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_FAIL (Bitfield-Mask: 0x01)

Definition at line 7344 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_FAIL_Pos

#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_FAIL_Pos   (10UL)

GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_FAIL (Bit 10)

Definition at line 7343 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_LINE_FAIL_Msk

#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_LINE_FAIL_Msk   (0x200UL)

GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01)

Definition at line 7342 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_LINE_FAIL_Pos

#define GPIO_RAMBIST_STATUS2_REG_ECC_TCMRAM_BIST_LINE_FAIL_Pos   (9UL)

GPIO RAMBIST_STATUS2_REG: ECC_TCMRAM_BIST_LINE_FAIL (Bit 9)

Definition at line 7341 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_BUSY_Msk

#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_BUSY_Msk   (0x20UL)

GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_BUSY (Bitfield-Mask: 0x01)

Definition at line 7334 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_BUSY_Pos

#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_BUSY_Pos   (5UL)

GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_BUSY (Bit 5)

Definition at line 7333 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_FAIL_Msk

#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_FAIL_Msk   (0x10UL)

GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_FAIL (Bitfield-Mask: 0x01)

Definition at line 7332 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_FAIL_Pos

#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_FAIL_Pos   (4UL)

GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_FAIL (Bit 4)

Definition at line 7331 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_LINE_FAIL_Msk

#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_LINE_FAIL_Msk   (0x8UL)

GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01)

Definition at line 7330 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_LINE_FAIL_Pos

#define GPIO_RAMBIST_STATUS2_REG_FTDF_RXRAM_BIST_LINE_FAIL_Pos   (3UL)

GPIO RAMBIST_STATUS2_REG: FTDF_RXRAM_BIST_LINE_FAIL (Bit 3)

Definition at line 7329 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_BUSY_Msk

#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_BUSY_Msk   (0x4UL)

GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_BUSY (Bitfield-Mask: 0x01)

Definition at line 7328 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_BUSY_Pos

#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_BUSY_Pos   (2UL)

GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_BUSY (Bit 2)

Definition at line 7327 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_FAIL_Msk

#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_FAIL_Msk   (0x2UL)

GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_FAIL (Bitfield-Mask: 0x01)

Definition at line 7326 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_FAIL_Pos

#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_FAIL_Pos   (1UL)

GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_FAIL (Bit 1)

Definition at line 7325 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_LINE_FAIL_Msk

#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_LINE_FAIL_Msk   (0x1UL)

GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01)

Definition at line 7324 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_LINE_FAIL_Pos

#define GPIO_RAMBIST_STATUS2_REG_FTDF_TXRAM_BIST_LINE_FAIL_Pos   (0UL)

GPIO RAMBIST_STATUS2_REG: FTDF_TXRAM_BIST_LINE_FAIL (Bit 0)

Definition at line 7323 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_BUSY_Msk

#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_BUSY_Msk   (0x4UL)

GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_BUSY (Bitfield-Mask: 0x01)

Definition at line 7360 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_BUSY_Pos

#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_BUSY_Pos   (2UL)

GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_BUSY (Bit 2)

Definition at line 7359 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_FAIL_Msk

#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_FAIL_Msk   (0x2UL)

GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_FAIL (Bitfield-Mask: 0x01)

Definition at line 7358 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_FAIL_Pos

#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_FAIL_Pos   (1UL)

GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_FAIL (Bit 1)

Definition at line 7357 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_LINE_FAIL_Msk

#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_LINE_FAIL_Msk   (0x1UL)

GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_LINE_FAIL (Bitfield-Mask: 0x01)

Definition at line 7356 of file DA14680BA.h.

◆ GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_LINE_FAIL_Pos

#define GPIO_RAMBIST_STATUS3_REG_FTDF_FPRAM_BIST_LINE_FAIL_Pos   (0UL)

GPIO RAMBIST_STATUS3_REG: FTDF_FPRAM_BIST_LINE_FAIL (Bit 0)

Definition at line 7355 of file DA14680BA.h.

◆ GPIO_ROMBIST_RESULTH_REG_ROMBIST_RESULTH_Msk

#define GPIO_ROMBIST_RESULTH_REG_ROMBIST_RESULTH_Msk   (0xffffUL)

GPIO ROMBIST_RESULTH_REG: ROMBIST_RESULTH (Bitfield-Mask: 0xffff)

Definition at line 7368 of file DA14680BA.h.

◆ GPIO_ROMBIST_RESULTH_REG_ROMBIST_RESULTH_Pos

#define GPIO_ROMBIST_RESULTH_REG_ROMBIST_RESULTH_Pos   (0UL)

GPIO ROMBIST_RESULTH_REG: ROMBIST_RESULTH (Bit 0)

Definition at line 7367 of file DA14680BA.h.

◆ GPIO_ROMBIST_RESULTL_REG_ROMBIST_RESULTL_Msk

#define GPIO_ROMBIST_RESULTL_REG_ROMBIST_RESULTL_Msk   (0xffffUL)

GPIO ROMBIST_RESULTL_REG: ROMBIST_RESULTL (Bitfield-Mask: 0xffff)

Definition at line 7364 of file DA14680BA.h.

◆ GPIO_ROMBIST_RESULTL_REG_ROMBIST_RESULTL_Pos

#define GPIO_ROMBIST_RESULTL_REG_ROMBIST_RESULTL_Pos   (0UL)

GPIO ROMBIST_RESULTL_REG: ROMBIST_RESULTL (Bit 0)

Definition at line 7363 of file DA14680BA.h.

◆ GPIO_TEST_CTRL2_REG_ANA_TESTMUX_CTRL_Msk

#define GPIO_TEST_CTRL2_REG_ANA_TESTMUX_CTRL_Msk   (0xfUL)

GPIO TEST_CTRL2_REG: ANA_TESTMUX_CTRL (Bitfield-Mask: 0x0f)

Definition at line 7396 of file DA14680BA.h.

◆ GPIO_TEST_CTRL2_REG_ANA_TESTMUX_CTRL_Pos

#define GPIO_TEST_CTRL2_REG_ANA_TESTMUX_CTRL_Pos   (0UL)

GPIO TEST_CTRL2_REG: ANA_TESTMUX_CTRL (Bit 0)

Definition at line 7395 of file DA14680BA.h.

◆ GPIO_TEST_CTRL2_REG_RF_IN_TESTMUX_CTRL_Msk

#define GPIO_TEST_CTRL2_REG_RF_IN_TESTMUX_CTRL_Msk   (0x300UL)

GPIO TEST_CTRL2_REG: RF_IN_TESTMUX_CTRL (Bitfield-Mask: 0x03)

Definition at line 7398 of file DA14680BA.h.

◆ GPIO_TEST_CTRL2_REG_RF_IN_TESTMUX_CTRL_Pos

#define GPIO_TEST_CTRL2_REG_RF_IN_TESTMUX_CTRL_Pos   (8UL)

GPIO TEST_CTRL2_REG: RF_IN_TESTMUX_CTRL (Bit 8)

Definition at line 7397 of file DA14680BA.h.

◆ GPIO_TEST_CTRL3_REG_RF_TEST_OUT_PARAM_Msk

#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_PARAM_Msk   (0xff00UL)

GPIO TEST_CTRL3_REG: RF_TEST_OUT_PARAM (Bitfield-Mask: 0xff)

Definition at line 7406 of file DA14680BA.h.

◆ GPIO_TEST_CTRL3_REG_RF_TEST_OUT_PARAM_Pos

#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_PARAM_Pos   (8UL)

GPIO TEST_CTRL3_REG: RF_TEST_OUT_PARAM (Bit 8)

Definition at line 7405 of file DA14680BA.h.

◆ GPIO_TEST_CTRL3_REG_RF_TEST_OUT_SEL_Msk

#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_SEL_Msk   (0x3fUL)

GPIO TEST_CTRL3_REG: RF_TEST_OUT_SEL (Bitfield-Mask: 0x3f)

Definition at line 7402 of file DA14680BA.h.

◆ GPIO_TEST_CTRL3_REG_RF_TEST_OUT_SEL_Pos

#define GPIO_TEST_CTRL3_REG_RF_TEST_OUT_SEL_Pos   (0UL)

GPIO TEST_CTRL3_REG: RF_TEST_OUT_SEL (Bit 0)

Definition at line 7401 of file DA14680BA.h.

◆ GPIO_TEST_CTRL3_REG_VBUS_COMPARATOR_TEST_Msk

#define GPIO_TEST_CTRL3_REG_VBUS_COMPARATOR_TEST_Msk   (0x40UL)

GPIO TEST_CTRL3_REG: VBUS_COMPARATOR_TEST (Bitfield-Mask: 0x01)

Definition at line 7404 of file DA14680BA.h.

◆ GPIO_TEST_CTRL3_REG_VBUS_COMPARATOR_TEST_Pos

#define GPIO_TEST_CTRL3_REG_VBUS_COMPARATOR_TEST_Pos   (6UL)

GPIO TEST_CTRL3_REG: VBUS_COMPARATOR_TEST (Bit 6)

Definition at line 7403 of file DA14680BA.h.

◆ GPIO_TEST_CTRL4_REG_RF_TEST_IN_PARAM_Msk

#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_PARAM_Msk   (0xff00UL)

GPIO TEST_CTRL4_REG: RF_TEST_IN_PARAM (Bitfield-Mask: 0xff)

Definition at line 7412 of file DA14680BA.h.

◆ GPIO_TEST_CTRL4_REG_RF_TEST_IN_PARAM_Pos

#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_PARAM_Pos   (8UL)

GPIO TEST_CTRL4_REG: RF_TEST_IN_PARAM (Bit 8)

Definition at line 7411 of file DA14680BA.h.

◆ GPIO_TEST_CTRL4_REG_RF_TEST_IN_SEL_Msk

#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_SEL_Msk   (0x7UL)

GPIO TEST_CTRL4_REG: RF_TEST_IN_SEL (Bitfield-Mask: 0x07)

Definition at line 7410 of file DA14680BA.h.

◆ GPIO_TEST_CTRL4_REG_RF_TEST_IN_SEL_Pos

#define GPIO_TEST_CTRL4_REG_RF_TEST_IN_SEL_Pos   (0UL)

GPIO TEST_CTRL4_REG: RF_TEST_IN_SEL (Bit 0)

Definition at line 7409 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_BANDGAP_I_TEST_Msk

#define GPIO_TEST_CTRL5_REG_TEST_BANDGAP_I_TEST_Msk   (0x80UL)

GPIO TEST_CTRL5_REG: TEST_BANDGAP_I_TEST (Bitfield-Mask: 0x01)

Definition at line 7430 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_BANDGAP_I_TEST_Pos

#define GPIO_TEST_CTRL5_REG_TEST_BANDGAP_I_TEST_Pos   (7UL)

GPIO TEST_CTRL5_REG: TEST_BANDGAP_I_TEST (Bit 7)

Definition at line 7429 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_IN_Msk

#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_IN_Msk   (0x400UL)

GPIO TEST_CTRL5_REG: TEST_BOD_VREF_IN (Bitfield-Mask: 0x01)

Definition at line 7436 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_IN_Pos

#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_IN_Pos   (10UL)

GPIO TEST_CTRL5_REG: TEST_BOD_VREF_IN (Bit 10)

Definition at line 7435 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_OUT_Msk

#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_OUT_Msk   (0x200UL)

GPIO TEST_CTRL5_REG: TEST_BOD_VREF_OUT (Bitfield-Mask: 0x01)

Definition at line 7434 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_OUT_Pos

#define GPIO_TEST_CTRL5_REG_TEST_BOD_VREF_OUT_Pos   (9UL)

GPIO TEST_CTRL5_REG: TEST_BOD_VREF_OUT (Bit 9)

Definition at line 7433 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_BUS_TO_AVS_Msk

#define GPIO_TEST_CTRL5_REG_TEST_BUS_TO_AVS_Msk   (0x1UL)

GPIO TEST_CTRL5_REG: TEST_BUS_TO_AVS (Bitfield-Mask: 0x01)

Definition at line 7416 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_BUS_TO_AVS_Pos

#define GPIO_TEST_CTRL5_REG_TEST_BUS_TO_AVS_Pos   (0UL)

GPIO TEST_CTRL5_REG: TEST_BUS_TO_AVS (Bit 0)

Definition at line 7415 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_I_DCDC_FILT_Msk

#define GPIO_TEST_CTRL5_REG_TEST_I_DCDC_FILT_Msk   (0x800UL)

GPIO TEST_CTRL5_REG: TEST_I_DCDC_FILT (Bitfield-Mask: 0x01)

Definition at line 7438 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_I_DCDC_FILT_Pos

#define GPIO_TEST_CTRL5_REG_TEST_I_DCDC_FILT_Pos   (11UL)

GPIO TEST_CTRL5_REG: TEST_I_DCDC_FILT (Bit 11)

Definition at line 7437 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_LDO_1V4_Msk

#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V4_Msk   (0x2UL)

GPIO TEST_CTRL5_REG: TEST_LDO_1V4 (Bitfield-Mask: 0x01)

Definition at line 7418 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_LDO_1V4_Pos

#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V4_Pos   (1UL)

GPIO TEST_CTRL5_REG: TEST_LDO_1V4 (Bit 1)

Definition at line 7417 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_FLASH_Msk

#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_FLASH_Msk   (0x4UL)

GPIO TEST_CTRL5_REG: TEST_LDO_1V8_FLASH (Bitfield-Mask: 0x01)

Definition at line 7420 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_FLASH_Pos

#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_FLASH_Pos   (2UL)

GPIO TEST_CTRL5_REG: TEST_LDO_1V8_FLASH (Bit 2)

Definition at line 7419 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_PA_Msk

#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_PA_Msk   (0x10UL)

GPIO TEST_CTRL5_REG: TEST_LDO_1V8_PA (Bitfield-Mask: 0x01)

Definition at line 7424 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_PA_Pos

#define GPIO_TEST_CTRL5_REG_TEST_LDO_1V8_PA_Pos   (4UL)

GPIO TEST_CTRL5_REG: TEST_LDO_1V8_PA (Bit 4)

Definition at line 7423 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_LDO_ADC_Msk

#define GPIO_TEST_CTRL5_REG_TEST_LDO_ADC_Msk   (0x20UL)

GPIO TEST_CTRL5_REG: TEST_LDO_ADC (Bitfield-Mask: 0x01)

Definition at line 7426 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_LDO_ADC_Pos

#define GPIO_TEST_CTRL5_REG_TEST_LDO_ADC_Pos   (5UL)

GPIO TEST_CTRL5_REG: TEST_LDO_ADC (Bit 5)

Definition at line 7425 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_LDO_CORE_Msk

#define GPIO_TEST_CTRL5_REG_TEST_LDO_CORE_Msk   (0x8UL)

GPIO TEST_CTRL5_REG: TEST_LDO_CORE (Bitfield-Mask: 0x01)

Definition at line 7422 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_LDO_CORE_Pos

#define GPIO_TEST_CTRL5_REG_TEST_LDO_CORE_Pos   (3UL)

GPIO TEST_CTRL5_REG: TEST_LDO_CORE (Bit 3)

Definition at line 7421 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_LDO_PLL_Msk

#define GPIO_TEST_CTRL5_REG_TEST_LDO_PLL_Msk   (0x40UL)

GPIO TEST_CTRL5_REG: TEST_LDO_PLL (Bitfield-Mask: 0x01)

Definition at line 7428 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_LDO_PLL_Pos

#define GPIO_TEST_CTRL5_REG_TEST_LDO_PLL_Pos   (6UL)

GPIO TEST_CTRL5_REG: TEST_LDO_PLL (Bit 6)

Definition at line 7427 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_POR_VBAT_NOK_AVD_Msk

#define GPIO_TEST_CTRL5_REG_TEST_POR_VBAT_NOK_AVD_Msk   (0x4000UL)

GPIO TEST_CTRL5_REG: TEST_POR_VBAT_NOK_AVD (Bitfield-Mask: 0x01)

Definition at line 7444 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_POR_VBAT_NOK_AVD_Pos

#define GPIO_TEST_CTRL5_REG_TEST_POR_VBAT_NOK_AVD_Pos   (14UL)

GPIO TEST_CTRL5_REG: TEST_POR_VBAT_NOK_AVD (Bit 14)

Definition at line 7443 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_SIMO_BUCK_Msk

#define GPIO_TEST_CTRL5_REG_TEST_SIMO_BUCK_Msk   (0x100UL)

GPIO TEST_CTRL5_REG: TEST_SIMO_BUCK (Bitfield-Mask: 0x01)

Definition at line 7432 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_SIMO_BUCK_Pos

#define GPIO_TEST_CTRL5_REG_TEST_SIMO_BUCK_Pos   (8UL)

GPIO TEST_CTRL5_REG: TEST_SIMO_BUCK (Bit 8)

Definition at line 7431 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_VCONT_A_Msk

#define GPIO_TEST_CTRL5_REG_TEST_VCONT_A_Msk   (0x1000UL)

GPIO TEST_CTRL5_REG: TEST_VCONT_A (Bitfield-Mask: 0x01)

Definition at line 7440 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_VCONT_A_Pos

#define GPIO_TEST_CTRL5_REG_TEST_VCONT_A_Pos   (12UL)

GPIO TEST_CTRL5_REG: TEST_VCONT_A (Bit 12)

Definition at line 7439 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_VREF_1V2_A_Msk

#define GPIO_TEST_CTRL5_REG_TEST_VREF_1V2_A_Msk   (0x2000UL)

GPIO TEST_CTRL5_REG: TEST_VREF_1V2_A (Bitfield-Mask: 0x01)

Definition at line 7442 of file DA14680BA.h.

◆ GPIO_TEST_CTRL5_REG_TEST_VREF_1V2_A_Pos

#define GPIO_TEST_CTRL5_REG_TEST_VREF_1V2_A_Pos   (13UL)

GPIO TEST_CTRL5_REG: TEST_VREF_1V2_A (Bit 13)

Definition at line 7441 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_ENABLE_RFPT_Msk

#define GPIO_TEST_CTRL_REG_ENABLE_RFPT_Msk   (0x2UL)

GPIO TEST_CTRL_REG: ENABLE_RFPT (Bitfield-Mask: 0x01)

Definition at line 7374 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_ENABLE_RFPT_Pos

#define GPIO_TEST_CTRL_REG_ENABLE_RFPT_Pos   (1UL)

GPIO TEST_CTRL_REG: ENABLE_RFPT (Bit 1)

Definition at line 7373 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_PLL_TST_MODE_Msk

#define GPIO_TEST_CTRL_REG_PLL_TST_MODE_Msk   (0x40UL)

GPIO TEST_CTRL_REG: PLL_TST_MODE (Bitfield-Mask: 0x01)

Definition at line 7384 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_PLL_TST_MODE_Pos

#define GPIO_TEST_CTRL_REG_PLL_TST_MODE_Pos   (6UL)

GPIO TEST_CTRL_REG: PLL_TST_MODE (Bit 6)

Definition at line 7383 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_SHOW_CLOCKS_Msk

#define GPIO_TEST_CTRL_REG_SHOW_CLOCKS_Msk   (0x1UL)

GPIO TEST_CTRL_REG: SHOW_CLOCKS (Bitfield-Mask: 0x01)

Definition at line 7372 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_SHOW_CLOCKS_Pos

#define GPIO_TEST_CTRL_REG_SHOW_CLOCKS_Pos   (0UL)

GPIO TEST_CTRL_REG: SHOW_CLOCKS (Bit 0)

Definition at line 7371 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_SHOW_DCDC_TESTBUS_Msk

#define GPIO_TEST_CTRL_REG_SHOW_DCDC_TESTBUS_Msk   (0x8UL)

GPIO TEST_CTRL_REG: SHOW_DCDC_TESTBUS (Bitfield-Mask: 0x01)

Definition at line 7378 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_SHOW_DCDC_TESTBUS_Pos

#define GPIO_TEST_CTRL_REG_SHOW_DCDC_TESTBUS_Pos   (3UL)

GPIO TEST_CTRL_REG: SHOW_DCDC_TESTBUS (Bit 3)

Definition at line 7377 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_SHOW_IF_RO_Msk

#define GPIO_TEST_CTRL_REG_SHOW_IF_RO_Msk   (0x20UL)

GPIO TEST_CTRL_REG: SHOW_IF_RO (Bitfield-Mask: 0x01)

Definition at line 7382 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_SHOW_IF_RO_Pos

#define GPIO_TEST_CTRL_REG_SHOW_IF_RO_Pos   (5UL)

GPIO TEST_CTRL_REG: SHOW_IF_RO (Bit 5)

Definition at line 7381 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_SHOW_PLL_TEST_OUT_Msk

#define GPIO_TEST_CTRL_REG_SHOW_PLL_TEST_OUT_Msk   (0x4UL)

GPIO TEST_CTRL_REG: SHOW_PLL_TEST_OUT (Bitfield-Mask: 0x01)

Definition at line 7376 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_SHOW_PLL_TEST_OUT_Pos

#define GPIO_TEST_CTRL_REG_SHOW_PLL_TEST_OUT_Pos   (2UL)

GPIO TEST_CTRL_REG: SHOW_PLL_TEST_OUT (Bit 2)

Definition at line 7375 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_SHOW_PWR_TST_OUT_Msk

#define GPIO_TEST_CTRL_REG_SHOW_PWR_TST_OUT_Msk   (0x700UL)

GPIO TEST_CTRL_REG: SHOW_PWR_TST_OUT (Bitfield-Mask: 0x07)

Definition at line 7388 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_SHOW_PWR_TST_OUT_Pos

#define GPIO_TEST_CTRL_REG_SHOW_PWR_TST_OUT_Pos   (8UL)

GPIO TEST_CTRL_REG: SHOW_PWR_TST_OUT (Bit 8)

Definition at line 7387 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_SHOW_TXDAC_MOD_Msk

#define GPIO_TEST_CTRL_REG_SHOW_TXDAC_MOD_Msk   (0x80UL)

GPIO TEST_CTRL_REG: SHOW_TXDAC_MOD (Bitfield-Mask: 0x01)

Definition at line 7386 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_SHOW_TXDAC_MOD_Pos

#define GPIO_TEST_CTRL_REG_SHOW_TXDAC_MOD_Pos   (7UL)

GPIO TEST_CTRL_REG: SHOW_TXDAC_MOD (Bit 7)

Definition at line 7385 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_XTAL16M_CAP_TEST_EN_Msk

#define GPIO_TEST_CTRL_REG_XTAL16M_CAP_TEST_EN_Msk   (0x10UL)

GPIO TEST_CTRL_REG: XTAL16M_CAP_TEST_EN (Bitfield-Mask: 0x01)

Definition at line 7380 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_XTAL16M_CAP_TEST_EN_Pos

#define GPIO_TEST_CTRL_REG_XTAL16M_CAP_TEST_EN_Pos   (4UL)

GPIO TEST_CTRL_REG: XTAL16M_CAP_TEST_EN (Bit 4)

Definition at line 7379 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_XTAL16M_TRIM_TEST_EN_Msk

#define GPIO_TEST_CTRL_REG_XTAL16M_TRIM_TEST_EN_Msk   (0x4000UL)

GPIO TEST_CTRL_REG: XTAL16M_TRIM_TEST_EN (Bitfield-Mask: 0x01)

Definition at line 7392 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_XTAL16M_TRIM_TEST_EN_Pos

#define GPIO_TEST_CTRL_REG_XTAL16M_TRIM_TEST_EN_Pos   (14UL)

GPIO TEST_CTRL_REG: XTAL16M_TRIM_TEST_EN (Bit 14)

Definition at line 7391 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_XTAL16M_TST_SYS_Msk

#define GPIO_TEST_CTRL_REG_XTAL16M_TST_SYS_Msk   (0x3000UL)

GPIO TEST_CTRL_REG: XTAL16M_TST_SYS (Bitfield-Mask: 0x03)

Definition at line 7390 of file DA14680BA.h.

◆ GPIO_TEST_CTRL_REG_XTAL16M_TST_SYS_Pos

#define GPIO_TEST_CTRL_REG_XTAL16M_TST_SYS_Pos   (12UL)

GPIO TEST_CTRL_REG: XTAL16M_TST_SYS (Bit 12)

Definition at line 7389 of file DA14680BA.h.

◆ GPREG

#define GPREG   ((GPREG_Type *) GPREG_BASE)

Definition at line 12090 of file DA14680BA.h.

◆ GPREG_BASE

#define GPREG_BASE   0x50003300UL

Definition at line 12045 of file DA14680BA.h.

◆ GPREG_BLE_FINECNT_SAMP_REG_BLE_FINECNT_SAMP_Msk

#define GPREG_BLE_FINECNT_SAMP_REG_BLE_FINECNT_SAMP_Msk   (0x3ffUL)

GPREG BLE_FINECNT_SAMP_REG: BLE_FINECNT_SAMP (Bitfield-Mask: 0x3ff)

Definition at line 7526 of file DA14680BA.h.

◆ GPREG_BLE_FINECNT_SAMP_REG_BLE_FINECNT_SAMP_Pos

#define GPREG_BLE_FINECNT_SAMP_REG_BLE_FINECNT_SAMP_Pos   (0UL)

GPREG BLE_FINECNT_SAMP_REG: BLE_FINECNT_SAMP (Bit 0)

Definition at line 7525 of file DA14680BA.h.

◆ GPREG_DEBUG_REG_DEBUGS_FREEZE_EN_Msk

#define GPREG_DEBUG_REG_DEBUGS_FREEZE_EN_Msk   (0x1UL)

GPREG DEBUG_REG: DEBUGS_FREEZE_EN (Bitfield-Mask: 0x01)

Definition at line 7490 of file DA14680BA.h.

◆ GPREG_DEBUG_REG_DEBUGS_FREEZE_EN_Pos

#define GPREG_DEBUG_REG_DEBUGS_FREEZE_EN_Pos   (0UL)

GPREG DEBUG_REG: DEBUGS_FREEZE_EN (Bit 0)

Definition at line 7489 of file DA14680BA.h.

◆ GPREG_ECC_BASE_ADDR_REG_ECC_BASE_ADDR_Msk

#define GPREG_ECC_BASE_ADDR_REG_ECC_BASE_ADDR_Msk   (0x7fUL)

GPREG ECC_BASE_ADDR_REG: ECC_BASE_ADDR (Bitfield-Mask: 0x7f)

Definition at line 7506 of file DA14680BA.h.

◆ GPREG_ECC_BASE_ADDR_REG_ECC_BASE_ADDR_Pos

#define GPREG_ECC_BASE_ADDR_REG_ECC_BASE_ADDR_Pos   (0UL)

GPREG ECC_BASE_ADDR_REG: ECC_BASE_ADDR (Bit 0)

Definition at line 7505 of file DA14680BA.h.

◆ GPREG_GP_CONTROL_REG_BLE_H2H_BRIDGE_BYPASS_Msk

#define GPREG_GP_CONTROL_REG_BLE_H2H_BRIDGE_BYPASS_Msk   (0x2UL)

GPREG GP_CONTROL_REG: BLE_H2H_BRIDGE_BYPASS (Bitfield-Mask: 0x01)

Definition at line 7500 of file DA14680BA.h.

◆ GPREG_GP_CONTROL_REG_BLE_H2H_BRIDGE_BYPASS_Pos

#define GPREG_GP_CONTROL_REG_BLE_H2H_BRIDGE_BYPASS_Pos   (1UL)

GPREG GP_CONTROL_REG: BLE_H2H_BRIDGE_BYPASS (Bit 1)

Definition at line 7499 of file DA14680BA.h.

◆ GPREG_GP_CONTROL_REG_BLE_WAKEUP_LP_IRQ_Msk

#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_LP_IRQ_Msk   (0x4UL)

GPREG GP_CONTROL_REG: BLE_WAKEUP_LP_IRQ (Bitfield-Mask: 0x01)

Definition at line 7502 of file DA14680BA.h.

◆ GPREG_GP_CONTROL_REG_BLE_WAKEUP_LP_IRQ_Pos

#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_LP_IRQ_Pos   (2UL)

GPREG GP_CONTROL_REG: BLE_WAKEUP_LP_IRQ (Bit 2)

Definition at line 7501 of file DA14680BA.h.

◆ GPREG_GP_CONTROL_REG_BLE_WAKEUP_REQ_Msk

#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_REQ_Msk   (0x1UL)

GPREG GP_CONTROL_REG: BLE_WAKEUP_REQ (Bitfield-Mask: 0x01)

Definition at line 7498 of file DA14680BA.h.

◆ GPREG_GP_CONTROL_REG_BLE_WAKEUP_REQ_Pos

#define GPREG_GP_CONTROL_REG_BLE_WAKEUP_REQ_Pos   (0UL)

GPREG GP_CONTROL_REG: BLE_WAKEUP_REQ (Bit 0)

Definition at line 7497 of file DA14680BA.h.

◆ GPREG_GP_STATUS_REG_CAL_PHASE_Msk

#define GPREG_GP_STATUS_REG_CAL_PHASE_Msk   (0x1UL)

GPREG GP_STATUS_REG: CAL_PHASE (Bitfield-Mask: 0x01)

Definition at line 7494 of file DA14680BA.h.

◆ GPREG_GP_STATUS_REG_CAL_PHASE_Pos

#define GPREG_GP_STATUS_REG_CAL_PHASE_Pos   (0UL)

GPREG GP_STATUS_REG: CAL_PHASE (Bit 0)

Definition at line 7493 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED1_EN_Msk

#define GPREG_LED_CONTROL_REG_LED1_EN_Msk   (0x8UL)

GPREG LED_CONTROL_REG: LED1_EN (Bitfield-Mask: 0x01)

Definition at line 7516 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED1_EN_Pos

#define GPREG_LED_CONTROL_REG_LED1_EN_Pos   (3UL)

GPREG LED_CONTROL_REG: LED1_EN (Bit 3)

Definition at line 7515 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED1_SRC_SEL_Msk

#define GPREG_LED_CONTROL_REG_LED1_SRC_SEL_Msk   (0x1UL)

GPREG LED_CONTROL_REG: LED1_SRC_SEL (Bitfield-Mask: 0x01)

Definition at line 7510 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED1_SRC_SEL_Pos

#define GPREG_LED_CONTROL_REG_LED1_SRC_SEL_Pos   (0UL)

GPREG LED_CONTROL_REG: LED1_SRC_SEL (Bit 0)

Definition at line 7509 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED2_EN_Msk

#define GPREG_LED_CONTROL_REG_LED2_EN_Msk   (0x10UL)

GPREG LED_CONTROL_REG: LED2_EN (Bitfield-Mask: 0x01)

Definition at line 7518 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED2_EN_Pos

#define GPREG_LED_CONTROL_REG_LED2_EN_Pos   (4UL)

GPREG LED_CONTROL_REG: LED2_EN (Bit 4)

Definition at line 7517 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED2_SRC_SEL_Msk

#define GPREG_LED_CONTROL_REG_LED2_SRC_SEL_Msk   (0x2UL)

GPREG LED_CONTROL_REG: LED2_SRC_SEL (Bitfield-Mask: 0x01)

Definition at line 7512 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED2_SRC_SEL_Pos

#define GPREG_LED_CONTROL_REG_LED2_SRC_SEL_Pos   (1UL)

GPREG LED_CONTROL_REG: LED2_SRC_SEL (Bit 1)

Definition at line 7511 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED3_EN_Msk

#define GPREG_LED_CONTROL_REG_LED3_EN_Msk   (0x20UL)

GPREG LED_CONTROL_REG: LED3_EN (Bitfield-Mask: 0x01)

Definition at line 7520 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED3_EN_Pos

#define GPREG_LED_CONTROL_REG_LED3_EN_Pos   (5UL)

GPREG LED_CONTROL_REG: LED3_EN (Bit 5)

Definition at line 7519 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED3_SRC_SEL_Msk

#define GPREG_LED_CONTROL_REG_LED3_SRC_SEL_Msk   (0x4UL)

GPREG LED_CONTROL_REG: LED3_SRC_SEL (Bitfield-Mask: 0x01)

Definition at line 7514 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED3_SRC_SEL_Pos

#define GPREG_LED_CONTROL_REG_LED3_SRC_SEL_Pos   (2UL)

GPREG LED_CONTROL_REG: LED3_SRC_SEL (Bit 2)

Definition at line 7513 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED_TRIM_Msk

#define GPREG_LED_CONTROL_REG_LED_TRIM_Msk   (0x3c0UL)

GPREG LED_CONTROL_REG: LED_TRIM (Bitfield-Mask: 0x0f)

Definition at line 7522 of file DA14680BA.h.

◆ GPREG_LED_CONTROL_REG_LED_TRIM_Pos

#define GPREG_LED_CONTROL_REG_LED_TRIM_Pos   (6UL)

GPREG LED_CONTROL_REG: LED_TRIM (Bit 6)

Definition at line 7521 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Msk

#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Msk   (0x2UL)

GPREG PLL_SYS_CTRL1_REG: LDO_PLL_ENABLE (Bitfield-Mask: 0x01)

Definition at line 7532 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Pos

#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_ENABLE_Pos   (1UL)

GPREG PLL_SYS_CTRL1_REG: LDO_PLL_ENABLE (Bit 1)

Definition at line 7531 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Msk

#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Msk   (0x4UL)

GPREG PLL_SYS_CTRL1_REG: LDO_PLL_VREF_HOLD (Bitfield-Mask: 0x01)

Definition at line 7534 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Pos

#define GPREG_PLL_SYS_CTRL1_REG_LDO_PLL_VREF_HOLD_Pos   (2UL)

GPREG PLL_SYS_CTRL1_REG: LDO_PLL_VREF_HOLD (Bit 2)

Definition at line 7533 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL1_REG_PLL_EN_Msk

#define GPREG_PLL_SYS_CTRL1_REG_PLL_EN_Msk   (0x1UL)

GPREG PLL_SYS_CTRL1_REG: PLL_EN (Bitfield-Mask: 0x01)

Definition at line 7530 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL1_REG_PLL_EN_Pos

#define GPREG_PLL_SYS_CTRL1_REG_PLL_EN_Pos   (0UL)

GPREG PLL_SYS_CTRL1_REG: PLL_EN (Bit 0)

Definition at line 7529 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL1_REG_PLL_R_DIV_Msk

#define GPREG_PLL_SYS_CTRL1_REG_PLL_R_DIV_Msk   (0x7f00UL)

GPREG PLL_SYS_CTRL1_REG: PLL_R_DIV (Bitfield-Mask: 0x7f)

Definition at line 7536 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL1_REG_PLL_R_DIV_Pos

#define GPREG_PLL_SYS_CTRL1_REG_PLL_R_DIV_Pos   (8UL)

GPREG PLL_SYS_CTRL1_REG: PLL_R_DIV (Bit 8)

Definition at line 7535 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL2_REG_PLL_DEL_SEL_Msk

#define GPREG_PLL_SYS_CTRL2_REG_PLL_DEL_SEL_Msk   (0x3000UL)

GPREG PLL_SYS_CTRL2_REG: PLL_DEL_SEL (Bitfield-Mask: 0x03)

Definition at line 7542 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL2_REG_PLL_DEL_SEL_Pos

#define GPREG_PLL_SYS_CTRL2_REG_PLL_DEL_SEL_Pos   (12UL)

GPREG PLL_SYS_CTRL2_REG: PLL_DEL_SEL (Bit 12)

Definition at line 7541 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL2_REG_PLL_N_DIV_Msk

#define GPREG_PLL_SYS_CTRL2_REG_PLL_N_DIV_Msk   (0x7fUL)

GPREG PLL_SYS_CTRL2_REG: PLL_N_DIV (Bitfield-Mask: 0x7f)

Definition at line 7540 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL2_REG_PLL_N_DIV_Pos

#define GPREG_PLL_SYS_CTRL2_REG_PLL_N_DIV_Pos   (0UL)

GPREG PLL_SYS_CTRL2_REG: PLL_N_DIV (Bit 0)

Definition at line 7539 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL2_REG_PLL_SEL_MIN_CUR_INT_Msk

#define GPREG_PLL_SYS_CTRL2_REG_PLL_SEL_MIN_CUR_INT_Msk   (0x4000UL)

GPREG PLL_SYS_CTRL2_REG: PLL_SEL_MIN_CUR_INT (Bitfield-Mask: 0x01)

Definition at line 7544 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL2_REG_PLL_SEL_MIN_CUR_INT_Pos

#define GPREG_PLL_SYS_CTRL2_REG_PLL_SEL_MIN_CUR_INT_Pos   (14UL)

GPREG PLL_SYS_CTRL2_REG: PLL_SEL_MIN_CUR_INT (Bit 14)

Definition at line 7543 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL3_REG_PLL_ICP_SEL_Msk

#define GPREG_PLL_SYS_CTRL3_REG_PLL_ICP_SEL_Msk   (0x1fUL)

GPREG PLL_SYS_CTRL3_REG: PLL_ICP_SEL (Bitfield-Mask: 0x1f)

Definition at line 7548 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL3_REG_PLL_ICP_SEL_Pos

#define GPREG_PLL_SYS_CTRL3_REG_PLL_ICP_SEL_Pos   (0UL)

GPREG PLL_SYS_CTRL3_REG: PLL_ICP_SEL (Bit 0)

Definition at line 7547 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL3_REG_PLL_RECALIB_Msk

#define GPREG_PLL_SYS_CTRL3_REG_PLL_RECALIB_Msk   (0x8000UL)

GPREG PLL_SYS_CTRL3_REG: PLL_RECALIB (Bitfield-Mask: 0x01)

Definition at line 7552 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL3_REG_PLL_RECALIB_Pos

#define GPREG_PLL_SYS_CTRL3_REG_PLL_RECALIB_Pos   (15UL)

GPREG PLL_SYS_CTRL3_REG: PLL_RECALIB (Bit 15)

Definition at line 7551 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL3_REG_PLL_START_DEL_Msk

#define GPREG_PLL_SYS_CTRL3_REG_PLL_START_DEL_Msk   (0x7c00UL)

GPREG PLL_SYS_CTRL3_REG: PLL_START_DEL (Bitfield-Mask: 0x1f)

Definition at line 7550 of file DA14680BA.h.

◆ GPREG_PLL_SYS_CTRL3_REG_PLL_START_DEL_Pos

#define GPREG_PLL_SYS_CTRL3_REG_PLL_START_DEL_Pos   (10UL)

GPREG PLL_SYS_CTRL3_REG: PLL_START_DEL (Bit 10)

Definition at line 7549 of file DA14680BA.h.

◆ GPREG_PLL_SYS_STATUS_REG_LDO_PLL_OK_Msk

#define GPREG_PLL_SYS_STATUS_REG_LDO_PLL_OK_Msk   (0x2UL)

GPREG PLL_SYS_STATUS_REG: LDO_PLL_OK (Bitfield-Mask: 0x01)

Definition at line 7558 of file DA14680BA.h.

◆ GPREG_PLL_SYS_STATUS_REG_LDO_PLL_OK_Pos

#define GPREG_PLL_SYS_STATUS_REG_LDO_PLL_OK_Pos   (1UL)

GPREG PLL_SYS_STATUS_REG: LDO_PLL_OK (Bit 1)

Definition at line 7557 of file DA14680BA.h.

◆ GPREG_PLL_SYS_STATUS_REG_PLL_CALIBR_END_Msk

#define GPREG_PLL_SYS_STATUS_REG_PLL_CALIBR_END_Msk   (0x800UL)

GPREG PLL_SYS_STATUS_REG: PLL_CALIBR_END (Bitfield-Mask: 0x01)

Definition at line 7562 of file DA14680BA.h.

◆ GPREG_PLL_SYS_STATUS_REG_PLL_CALIBR_END_Pos

#define GPREG_PLL_SYS_STATUS_REG_PLL_CALIBR_END_Pos   (11UL)

GPREG PLL_SYS_STATUS_REG: PLL_CALIBR_END (Bit 11)

Definition at line 7561 of file DA14680BA.h.

◆ GPREG_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Msk

#define GPREG_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Msk   (0x1UL)

GPREG PLL_SYS_STATUS_REG: PLL_LOCK_FINE (Bitfield-Mask: 0x01)

Definition at line 7556 of file DA14680BA.h.

◆ GPREG_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Pos

#define GPREG_PLL_SYS_STATUS_REG_PLL_LOCK_FINE_Pos   (0UL)

GPREG PLL_SYS_STATUS_REG: PLL_LOCK_FINE (Bit 0)

Definition at line 7555 of file DA14680BA.h.

◆ GPREG_PLL_SYS_STATUS_REG_PLL_PLL_BEST_MIN_CUR_Msk

#define GPREG_PLL_SYS_STATUS_REG_PLL_PLL_BEST_MIN_CUR_Msk   (0x7e0UL)

GPREG PLL_SYS_STATUS_REG: PLL_PLL_BEST_MIN_CUR (Bitfield-Mask: 0x3f)

Definition at line 7560 of file DA14680BA.h.

◆ GPREG_PLL_SYS_STATUS_REG_PLL_PLL_BEST_MIN_CUR_Pos

#define GPREG_PLL_SYS_STATUS_REG_PLL_PLL_BEST_MIN_CUR_Pos   (5UL)

GPREG PLL_SYS_STATUS_REG: PLL_PLL_BEST_MIN_CUR (Bit 5)

Definition at line 7559 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_CHANGE_Msk

#define GPREG_PLL_SYS_TEST_REG_PLL_CHANGE_Msk   (0x200UL)

GPREG PLL_SYS_TEST_REG: PLL_CHANGE (Bitfield-Mask: 0x01)

Definition at line 7574 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_CHANGE_Pos

#define GPREG_PLL_SYS_TEST_REG_PLL_CHANGE_Pos   (9UL)

GPREG PLL_SYS_TEST_REG: PLL_CHANGE (Bit 9)

Definition at line 7573 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_DIS_LOOPFILT_Msk

#define GPREG_PLL_SYS_TEST_REG_PLL_DIS_LOOPFILT_Msk   (0x1UL)

GPREG PLL_SYS_TEST_REG: PLL_DIS_LOOPFILT (Bitfield-Mask: 0x01)

Definition at line 7566 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_DIS_LOOPFILT_Pos

#define GPREG_PLL_SYS_TEST_REG_PLL_DIS_LOOPFILT_Pos   (0UL)

GPREG PLL_SYS_TEST_REG: PLL_DIS_LOOPFILT (Bit 0)

Definition at line 7565 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_LOCK_DET_RES_CNT_Msk

#define GPREG_PLL_SYS_TEST_REG_PLL_LOCK_DET_RES_CNT_Msk   (0xe000UL)

GPREG PLL_SYS_TEST_REG: PLL_LOCK_DET_RES_CNT (Bitfield-Mask: 0x07)

Definition at line 7580 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_LOCK_DET_RES_CNT_Pos

#define GPREG_PLL_SYS_TEST_REG_PLL_LOCK_DET_RES_CNT_Pos   (13UL)

GPREG PLL_SYS_TEST_REG: PLL_LOCK_DET_RES_CNT (Bit 13)

Definition at line 7579 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_MIN_CURRENT_Msk

#define GPREG_PLL_SYS_TEST_REG_PLL_MIN_CURRENT_Msk   (0x7eUL)

GPREG PLL_SYS_TEST_REG: PLL_MIN_CURRENT (Bitfield-Mask: 0x3f)

Definition at line 7568 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_MIN_CURRENT_Pos

#define GPREG_PLL_SYS_TEST_REG_PLL_MIN_CURRENT_Pos   (1UL)

GPREG PLL_SYS_TEST_REG: PLL_MIN_CURRENT (Bit 1)

Definition at line 7567 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_OPEN_LOOP_Msk

#define GPREG_PLL_SYS_TEST_REG_PLL_OPEN_LOOP_Msk   (0x100UL)

GPREG PLL_SYS_TEST_REG: PLL_OPEN_LOOP (Bitfield-Mask: 0x01)

Definition at line 7572 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_OPEN_LOOP_Pos

#define GPREG_PLL_SYS_TEST_REG_PLL_OPEN_LOOP_Pos   (8UL)

GPREG PLL_SYS_TEST_REG: PLL_OPEN_LOOP (Bit 8)

Definition at line 7571 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_SEL_N_DIV_TEST_Msk

#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_N_DIV_TEST_Msk   (0x400UL)

GPREG PLL_SYS_TEST_REG: PLL_SEL_N_DIV_TEST (Bitfield-Mask: 0x01)

Definition at line 7576 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_SEL_N_DIV_TEST_Pos

#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_N_DIV_TEST_Pos   (10UL)

GPREG PLL_SYS_TEST_REG: PLL_SEL_N_DIV_TEST (Bit 10)

Definition at line 7575 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_SEL_R_DIV_TEST_Msk

#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_R_DIV_TEST_Msk   (0x800UL)

GPREG PLL_SYS_TEST_REG: PLL_SEL_R_DIV_TEST (Bitfield-Mask: 0x01)

Definition at line 7578 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_SEL_R_DIV_TEST_Pos

#define GPREG_PLL_SYS_TEST_REG_PLL_SEL_R_DIV_TEST_Pos   (11UL)

GPREG PLL_SYS_TEST_REG: PLL_SEL_R_DIV_TEST (Bit 11)

Definition at line 7577 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_TEST_VCTR_Msk

#define GPREG_PLL_SYS_TEST_REG_PLL_TEST_VCTR_Msk   (0x80UL)

GPREG PLL_SYS_TEST_REG: PLL_TEST_VCTR (Bitfield-Mask: 0x01)

Definition at line 7570 of file DA14680BA.h.

◆ GPREG_PLL_SYS_TEST_REG_PLL_TEST_VCTR_Pos

#define GPREG_PLL_SYS_TEST_REG_PLL_TEST_VCTR_Pos   (7UL)

GPREG PLL_SYS_TEST_REG: PLL_TEST_VCTR (Bit 7)

Definition at line 7569 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_BLETIM_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_BLETIM_Msk   (0x4UL)

GPREG RESET_FREEZE_REG: FRZ_BLETIM (Bitfield-Mask: 0x01)

Definition at line 7476 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_BLETIM_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_BLETIM_Pos   (2UL)

GPREG RESET_FREEZE_REG: FRZ_BLETIM (Bit 2)

Definition at line 7475 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_DMA_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Msk   (0x20UL)

GPREG RESET_FREEZE_REG: FRZ_DMA (Bitfield-Mask: 0x01)

Definition at line 7482 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_DMA_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Pos   (5UL)

GPREG RESET_FREEZE_REG: FRZ_DMA (Bit 5)

Definition at line 7481 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM0_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM0_Msk   (0x2UL)

GPREG RESET_FREEZE_REG: FRZ_SWTIM0 (Bitfield-Mask: 0x01)

Definition at line 7474 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM0_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM0_Pos   (1UL)

GPREG RESET_FREEZE_REG: FRZ_SWTIM0 (Bit 1)

Definition at line 7473 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM1_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM1_Msk   (0x40UL)

GPREG RESET_FREEZE_REG: FRZ_SWTIM1 (Bitfield-Mask: 0x01)

Definition at line 7484 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM1_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM1_Pos   (6UL)

GPREG RESET_FREEZE_REG: FRZ_SWTIM1 (Bit 6)

Definition at line 7483 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Msk   (0x80UL)

GPREG RESET_FREEZE_REG: FRZ_SWTIM2 (Bitfield-Mask: 0x01)

Definition at line 7486 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Pos   (7UL)

GPREG RESET_FREEZE_REG: FRZ_SWTIM2 (Bit 7)

Definition at line 7485 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_USB_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_USB_Msk   (0x10UL)

GPREG RESET_FREEZE_REG: FRZ_USB (Bitfield-Mask: 0x01)

Definition at line 7480 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_USB_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_USB_Pos   (4UL)

GPREG RESET_FREEZE_REG: FRZ_USB (Bit 4)

Definition at line 7479 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_WDOG_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_WDOG_Msk   (0x8UL)

GPREG RESET_FREEZE_REG: FRZ_WDOG (Bitfield-Mask: 0x01)

Definition at line 7478 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_WDOG_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_WDOG_Pos   (3UL)

GPREG RESET_FREEZE_REG: FRZ_WDOG (Bit 3)

Definition at line 7477 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk   (0x1UL)

GPREG RESET_FREEZE_REG: FRZ_WKUPTIM (Bitfield-Mask: 0x01)

Definition at line 7472 of file DA14680BA.h.

◆ GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Pos   (0UL)

GPREG RESET_FREEZE_REG: FRZ_WKUPTIM (Bit 0)

Definition at line 7471 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_BLETIM_Msk

#define GPREG_SET_FREEZE_REG_FRZ_BLETIM_Msk   (0x4UL)

GPREG SET_FREEZE_REG: FRZ_BLETIM (Bitfield-Mask: 0x01)

Definition at line 7458 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_BLETIM_Pos

#define GPREG_SET_FREEZE_REG_FRZ_BLETIM_Pos   (2UL)

GPREG SET_FREEZE_REG: FRZ_BLETIM (Bit 2)

Definition at line 7457 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_DMA_Msk

#define GPREG_SET_FREEZE_REG_FRZ_DMA_Msk   (0x20UL)

GPREG SET_FREEZE_REG: FRZ_DMA (Bitfield-Mask: 0x01)

Definition at line 7464 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_DMA_Pos

#define GPREG_SET_FREEZE_REG_FRZ_DMA_Pos   (5UL)

GPREG SET_FREEZE_REG: FRZ_DMA (Bit 5)

Definition at line 7463 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM0_Msk

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM0_Msk   (0x2UL)

GPREG SET_FREEZE_REG: FRZ_SWTIM0 (Bitfield-Mask: 0x01)

Definition at line 7456 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM0_Pos

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM0_Pos   (1UL)

GPREG SET_FREEZE_REG: FRZ_SWTIM0 (Bit 1)

Definition at line 7455 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Msk

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Msk   (0x40UL)

GPREG SET_FREEZE_REG: FRZ_SWTIM1 (Bitfield-Mask: 0x01)

Definition at line 7466 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Pos

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM1_Pos   (6UL)

GPREG SET_FREEZE_REG: FRZ_SWTIM1 (Bit 6)

Definition at line 7465 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk   (0x80UL)

GPREG SET_FREEZE_REG: FRZ_SWTIM2 (Bitfield-Mask: 0x01)

Definition at line 7468 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Pos

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Pos   (7UL)

GPREG SET_FREEZE_REG: FRZ_SWTIM2 (Bit 7)

Definition at line 7467 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_USB_Msk

#define GPREG_SET_FREEZE_REG_FRZ_USB_Msk   (0x10UL)

GPREG SET_FREEZE_REG: FRZ_USB (Bitfield-Mask: 0x01)

Definition at line 7462 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_USB_Pos

#define GPREG_SET_FREEZE_REG_FRZ_USB_Pos   (4UL)

GPREG SET_FREEZE_REG: FRZ_USB (Bit 4)

Definition at line 7461 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk

#define GPREG_SET_FREEZE_REG_FRZ_WDOG_Msk   (0x8UL)

GPREG SET_FREEZE_REG: FRZ_WDOG (Bitfield-Mask: 0x01)

Definition at line 7460 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_WDOG_Pos

#define GPREG_SET_FREEZE_REG_FRZ_WDOG_Pos   (3UL)

GPREG SET_FREEZE_REG: FRZ_WDOG (Bit 3)

Definition at line 7459 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Msk

#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Msk   (0x1UL)

GPREG SET_FREEZE_REG: FRZ_WKUPTIM (Bitfield-Mask: 0x01)

Definition at line 7454 of file DA14680BA.h.

◆ GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Pos

#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Pos   (0UL)

GPREG SET_FREEZE_REG: FRZ_WKUPTIM (Bit 0)

Definition at line 7453 of file DA14680BA.h.

◆ I2C

#define I2C   ((I2C_Type *) I2C_BASE)

Definition at line 12091 of file DA14680BA.h.

◆ I2C2

#define I2C2   ((I2C2_Type *) I2C2_BASE)

Definition at line 12092 of file DA14680BA.h.

◆ I2C2_BASE

#define I2C2_BASE   0x50001500UL

Definition at line 12047 of file DA14680BA.h.

◆ I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk

#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk   (0x1UL)

I2C2 I2C2_ACK_GENERAL_CALL_REG: ACK_GEN_CALL (Bitfield-Mask: 0x01)

Definition at line 8168 of file DA14680BA.h.

◆ I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos

#define I2C2_I2C2_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos   (0UL)

I2C2 I2C2_ACK_GENERAL_CALL_REG: ACK_GEN_CALL (Bit 0)

Definition at line 8167 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk

#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk   (0x1UL)

I2C2 I2C2_CLR_ACTIVITY_REG: CLR_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 8068 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos

#define I2C2_I2C2_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos   (0UL)

I2C2 I2C2_CLR_ACTIVITY_REG: CLR_ACTIVITY (Bit 0)

Definition at line 8067 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk

#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk   (0x1UL)

I2C2 I2C2_CLR_GEN_CALL_REG: CLR_GEN_CALL (Bitfield-Mask: 0x01)

Definition at line 8080 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos

#define I2C2_I2C2_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos   (0UL)

I2C2 I2C2_CLR_GEN_CALL_REG: CLR_GEN_CALL (Bit 0)

Definition at line 8079 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Msk

#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Msk   (0x1UL)

I2C2 I2C2_CLR_INTR_REG: CLR_INTR (Bitfield-Mask: 0x01)

Definition at line 8040 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Pos

#define I2C2_I2C2_CLR_INTR_REG_CLR_INTR_Pos   (0UL)

I2C2 I2C2_CLR_INTR_REG: CLR_INTR (Bit 0)

Definition at line 8039 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Msk

#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Msk   (0x1UL)

I2C2 I2C2_CLR_RD_REQ_REG: CLR_RD_REQ (Bitfield-Mask: 0x01)

Definition at line 8056 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Pos

#define I2C2_I2C2_CLR_RD_REQ_REG_CLR_RD_REQ_Pos   (0UL)

I2C2 I2C2_CLR_RD_REQ_REG: CLR_RD_REQ (Bit 0)

Definition at line 8055 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Msk

#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Msk   (0x1UL)

I2C2 I2C2_CLR_RX_DONE_REG: CLR_RX_DONE (Bitfield-Mask: 0x01)

Definition at line 8064 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Pos

#define I2C2_I2C2_CLR_RX_DONE_REG_CLR_RX_DONE_Pos   (0UL)

I2C2 I2C2_CLR_RX_DONE_REG: CLR_RX_DONE (Bit 0)

Definition at line 8063 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Msk

#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Msk   (0x1UL)

I2C2 I2C2_CLR_RX_OVER_REG: CLR_RX_OVER (Bitfield-Mask: 0x01)

Definition at line 8048 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Pos

#define I2C2_I2C2_CLR_RX_OVER_REG_CLR_RX_OVER_Pos   (0UL)

I2C2 I2C2_CLR_RX_OVER_REG: CLR_RX_OVER (Bit 0)

Definition at line 8047 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk

#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk   (0x1UL)

I2C2 I2C2_CLR_RX_UNDER_REG: CLR_RX_UNDER (Bitfield-Mask: 0x01)

Definition at line 8044 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos

#define I2C2_I2C2_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos   (0UL)

I2C2 I2C2_CLR_RX_UNDER_REG: CLR_RX_UNDER (Bit 0)

Definition at line 8043 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Msk

#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Msk   (0x1UL)

I2C2 I2C2_CLR_START_DET_REG: CLR_START_DET (Bitfield-Mask: 0x01)

Definition at line 8076 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Pos

#define I2C2_I2C2_CLR_START_DET_REG_CLR_START_DET_Pos   (0UL)

I2C2 I2C2_CLR_START_DET_REG: CLR_START_DET (Bit 0)

Definition at line 8075 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_STOP_DET_REG_CLR_ACTIVITY_Msk

#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_ACTIVITY_Msk   (0x1UL)

I2C2 I2C2_CLR_STOP_DET_REG: CLR_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 8072 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_STOP_DET_REG_CLR_ACTIVITY_Pos

#define I2C2_I2C2_CLR_STOP_DET_REG_CLR_ACTIVITY_Pos   (0UL)

I2C2 I2C2_CLR_STOP_DET_REG: CLR_ACTIVITY (Bit 0)

Definition at line 8071 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk

#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk   (0x1UL)

I2C2 I2C2_CLR_TX_ABRT_REG: CLR_TX_ABRT (Bitfield-Mask: 0x01)

Definition at line 8060 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos

#define I2C2_I2C2_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos   (0UL)

I2C2 I2C2_CLR_TX_ABRT_REG: CLR_TX_ABRT (Bit 0)

Definition at line 8059 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Msk

#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Msk   (0x1UL)

I2C2 I2C2_CLR_TX_OVER_REG: CLR_TX_OVER (Bitfield-Mask: 0x01)

Definition at line 8052 of file DA14680BA.h.

◆ I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Pos

#define I2C2_I2C2_CLR_TX_OVER_REG_CLR_TX_OVER_Pos   (0UL)

I2C2 I2C2_CLR_TX_OVER_REG: CLR_TX_OVER (Bit 0)

Definition at line 8051 of file DA14680BA.h.

◆ I2C2_I2C2_COMP2_VERSION_IC_COMP2_VERSION_Msk

#define I2C2_I2C2_COMP2_VERSION_IC_COMP2_VERSION_Msk   (0xffffUL)

I2C2 I2C2_COMP2_VERSION: IC_COMP2_VERSION (Bitfield-Mask: 0xffff)

Definition at line 8196 of file DA14680BA.h.

◆ I2C2_I2C2_COMP2_VERSION_IC_COMP2_VERSION_Pos

#define I2C2_I2C2_COMP2_VERSION_IC_COMP2_VERSION_Pos   (0UL)

I2C2 I2C2_COMP2_VERSION: IC_COMP2_VERSION (Bit 0)

Definition at line 8195 of file DA14680BA.h.

◆ I2C2_I2C2_COMP_PARAM1_REG_IC_COMP_PARAM1_Msk

#define I2C2_I2C2_COMP_PARAM1_REG_IC_COMP_PARAM1_Msk   (0xffffUL)

I2C2 I2C2_COMP_PARAM1_REG: IC_COMP_PARAM1 (Bitfield-Mask: 0xffff)

Definition at line 8184 of file DA14680BA.h.

◆ I2C2_I2C2_COMP_PARAM1_REG_IC_COMP_PARAM1_Pos

#define I2C2_I2C2_COMP_PARAM1_REG_IC_COMP_PARAM1_Pos   (0UL)

I2C2 I2C2_COMP_PARAM1_REG: IC_COMP_PARAM1 (Bit 0)

Definition at line 8183 of file DA14680BA.h.

◆ I2C2_I2C2_COMP_PARAM2_REG_IC_COMP_PARAM2_Msk

#define I2C2_I2C2_COMP_PARAM2_REG_IC_COMP_PARAM2_Msk   (0xffffUL)

I2C2 I2C2_COMP_PARAM2_REG: IC_COMP_PARAM2 (Bitfield-Mask: 0xffff)

Definition at line 8188 of file DA14680BA.h.

◆ I2C2_I2C2_COMP_PARAM2_REG_IC_COMP_PARAM2_Pos

#define I2C2_I2C2_COMP_PARAM2_REG_IC_COMP_PARAM2_Pos   (0UL)

I2C2 I2C2_COMP_PARAM2_REG: IC_COMP_PARAM2 (Bit 0)

Definition at line 8187 of file DA14680BA.h.

◆ I2C2_I2C2_COMP_TYPE2_REG_IC_COMP2_TYPE_Msk

#define I2C2_I2C2_COMP_TYPE2_REG_IC_COMP2_TYPE_Msk   (0xffffUL)

I2C2 I2C2_COMP_TYPE2_REG: IC_COMP2_TYPE (Bitfield-Mask: 0xffff)

Definition at line 8204 of file DA14680BA.h.

◆ I2C2_I2C2_COMP_TYPE2_REG_IC_COMP2_TYPE_Pos

#define I2C2_I2C2_COMP_TYPE2_REG_IC_COMP2_TYPE_Pos   (0UL)

I2C2 I2C2_COMP_TYPE2_REG: IC_COMP2_TYPE (Bit 0)

Definition at line 8203 of file DA14680BA.h.

◆ I2C2_I2C2_COMP_TYPE_REG_IC_COMP_TYPE_Msk

#define I2C2_I2C2_COMP_TYPE_REG_IC_COMP_TYPE_Msk   (0xffffUL)

I2C2 I2C2_COMP_TYPE_REG: IC_COMP_TYPE (Bitfield-Mask: 0xffff)

Definition at line 8200 of file DA14680BA.h.

◆ I2C2_I2C2_COMP_TYPE_REG_IC_COMP_TYPE_Pos

#define I2C2_I2C2_COMP_TYPE_REG_IC_COMP_TYPE_Pos   (0UL)

I2C2 I2C2_COMP_TYPE_REG: IC_COMP_TYPE (Bit 0)

Definition at line 8199 of file DA14680BA.h.

◆ I2C2_I2C2_COMP_VERSION_REG_IC_COMP_VERSION_Msk

#define I2C2_I2C2_COMP_VERSION_REG_IC_COMP_VERSION_Msk   (0xffffUL)

I2C2 I2C2_COMP_VERSION_REG: IC_COMP_VERSION (Bitfield-Mask: 0xffff)

Definition at line 8192 of file DA14680BA.h.

◆ I2C2_I2C2_COMP_VERSION_REG_IC_COMP_VERSION_Pos

#define I2C2_I2C2_COMP_VERSION_REG_IC_COMP_VERSION_Pos   (0UL)

I2C2 I2C2_COMP_VERSION_REG: IC_COMP_VERSION (Bit 0)

Definition at line 8191 of file DA14680BA.h.

◆ I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Msk

#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Msk   (0x10UL)

I2C2 I2C2_CON_REG: I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01)

Definition at line 7908 of file DA14680BA.h.

◆ I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Pos

#define I2C2_I2C2_CON_REG_I2C_10BITADDR_MASTER_Pos   (4UL)

I2C2 I2C2_CON_REG: I2C_10BITADDR_MASTER (Bit 4)

Definition at line 7907 of file DA14680BA.h.

◆ I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Msk

#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Msk   (0x8UL)

I2C2 I2C2_CON_REG: I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01)

Definition at line 7906 of file DA14680BA.h.

◆ I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Pos

#define I2C2_I2C2_CON_REG_I2C_10BITADDR_SLAVE_Pos   (3UL)

I2C2 I2C2_CON_REG: I2C_10BITADDR_SLAVE (Bit 3)

Definition at line 7905 of file DA14680BA.h.

◆ I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Msk

#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Msk   (0x1UL)

I2C2 I2C2_CON_REG: I2C_MASTER_MODE (Bitfield-Mask: 0x01)

Definition at line 7902 of file DA14680BA.h.

◆ I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Pos

#define I2C2_I2C2_CON_REG_I2C_MASTER_MODE_Pos   (0UL)

I2C2 I2C2_CON_REG: I2C_MASTER_MODE (Bit 0)

Definition at line 7901 of file DA14680BA.h.

◆ I2C2_I2C2_CON_REG_I2C_RESTART_EN_Msk

#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Msk   (0x20UL)

I2C2 I2C2_CON_REG: I2C_RESTART_EN (Bitfield-Mask: 0x01)

Definition at line 7910 of file DA14680BA.h.

◆ I2C2_I2C2_CON_REG_I2C_RESTART_EN_Pos

#define I2C2_I2C2_CON_REG_I2C_RESTART_EN_Pos   (5UL)

I2C2 I2C2_CON_REG: I2C_RESTART_EN (Bit 5)

Definition at line 7909 of file DA14680BA.h.

◆ I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Msk

#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Msk   (0x40UL)

I2C2 I2C2_CON_REG: I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01)

Definition at line 7912 of file DA14680BA.h.

◆ I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Pos

#define I2C2_I2C2_CON_REG_I2C_SLAVE_DISABLE_Pos   (6UL)

I2C2 I2C2_CON_REG: I2C_SLAVE_DISABLE (Bit 6)

Definition at line 7911 of file DA14680BA.h.

◆ I2C2_I2C2_CON_REG_I2C_SPEED_Msk

#define I2C2_I2C2_CON_REG_I2C_SPEED_Msk   (0x6UL)

I2C2 I2C2_CON_REG: I2C_SPEED (Bitfield-Mask: 0x03)

Definition at line 7904 of file DA14680BA.h.

◆ I2C2_I2C2_CON_REG_I2C_SPEED_Pos

#define I2C2_I2C2_CON_REG_I2C_SPEED_Pos   (1UL)

I2C2 I2C2_CON_REG: I2C_SPEED (Bit 1)

Definition at line 7903 of file DA14680BA.h.

◆ I2C2_I2C2_DATA_CMD_REG_CMD_Msk

#define I2C2_I2C2_DATA_CMD_REG_CMD_Msk   (0x100UL)

I2C2 I2C2_DATA_CMD_REG: CMD (Bitfield-Mask: 0x01)

Definition at line 7930 of file DA14680BA.h.

◆ I2C2_I2C2_DATA_CMD_REG_CMD_Pos

#define I2C2_I2C2_DATA_CMD_REG_CMD_Pos   (8UL)

I2C2 I2C2_DATA_CMD_REG: CMD (Bit 8)

Definition at line 7929 of file DA14680BA.h.

◆ I2C2_I2C2_DATA_CMD_REG_DAT_Msk

#define I2C2_I2C2_DATA_CMD_REG_DAT_Msk   (0xffUL)

I2C2 I2C2_DATA_CMD_REG: DAT (Bitfield-Mask: 0xff)

Definition at line 7928 of file DA14680BA.h.

◆ I2C2_I2C2_DATA_CMD_REG_DAT_Pos

#define I2C2_I2C2_DATA_CMD_REG_DAT_Pos   (0UL)

I2C2 I2C2_DATA_CMD_REG: DAT (Bit 0)

Definition at line 7927 of file DA14680BA.h.

◆ I2C2_I2C2_DATA_CMD_REG_RESTART_Msk

#define I2C2_I2C2_DATA_CMD_REG_RESTART_Msk   (0x400UL)

I2C2 I2C2_DATA_CMD_REG: RESTART (Bitfield-Mask: 0x01)

Definition at line 7934 of file DA14680BA.h.

◆ I2C2_I2C2_DATA_CMD_REG_RESTART_Pos

#define I2C2_I2C2_DATA_CMD_REG_RESTART_Pos   (10UL)

I2C2 I2C2_DATA_CMD_REG: RESTART (Bit 10)

Definition at line 7933 of file DA14680BA.h.

◆ I2C2_I2C2_DATA_CMD_REG_STOP_Msk

#define I2C2_I2C2_DATA_CMD_REG_STOP_Msk   (0x200UL)

I2C2 I2C2_DATA_CMD_REG: STOP (Bitfield-Mask: 0x01)

Definition at line 7932 of file DA14680BA.h.

◆ I2C2_I2C2_DATA_CMD_REG_STOP_Pos

#define I2C2_I2C2_DATA_CMD_REG_STOP_Pos   (9UL)

I2C2 I2C2_DATA_CMD_REG: STOP (Bit 9)

Definition at line 7931 of file DA14680BA.h.

◆ I2C2_I2C2_DMA_CR_REG_RDMAE_Msk

#define I2C2_I2C2_DMA_CR_REG_RDMAE_Msk   (0x1UL)

I2C2 I2C2_DMA_CR_REG: RDMAE (Bitfield-Mask: 0x01)

Definition at line 8150 of file DA14680BA.h.

◆ I2C2_I2C2_DMA_CR_REG_RDMAE_Pos

#define I2C2_I2C2_DMA_CR_REG_RDMAE_Pos   (0UL)

I2C2 I2C2_DMA_CR_REG: RDMAE (Bit 0)

Definition at line 8149 of file DA14680BA.h.

◆ I2C2_I2C2_DMA_CR_REG_TDMAE_Msk

#define I2C2_I2C2_DMA_CR_REG_TDMAE_Msk   (0x2UL)

I2C2 I2C2_DMA_CR_REG: TDMAE (Bitfield-Mask: 0x01)

Definition at line 8152 of file DA14680BA.h.

◆ I2C2_I2C2_DMA_CR_REG_TDMAE_Pos

#define I2C2_I2C2_DMA_CR_REG_TDMAE_Pos   (1UL)

I2C2 I2C2_DMA_CR_REG: TDMAE (Bit 1)

Definition at line 8151 of file DA14680BA.h.

◆ I2C2_I2C2_DMA_RDLR_REG_DMARDL_Msk

#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Msk   (0x1fUL)

I2C2 I2C2_DMA_RDLR_REG: DMARDL (Bitfield-Mask: 0x1f)

Definition at line 8160 of file DA14680BA.h.

◆ I2C2_I2C2_DMA_RDLR_REG_DMARDL_Pos

#define I2C2_I2C2_DMA_RDLR_REG_DMARDL_Pos   (0UL)

I2C2 I2C2_DMA_RDLR_REG: DMARDL (Bit 0)

Definition at line 8159 of file DA14680BA.h.

◆ I2C2_I2C2_DMA_TDLR_REG_DMATDL_Msk

#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Msk   (0x1fUL)

I2C2 I2C2_DMA_TDLR_REG: DMATDL (Bitfield-Mask: 0x1f)

Definition at line 8156 of file DA14680BA.h.

◆ I2C2_I2C2_DMA_TDLR_REG_DMATDL_Pos

#define I2C2_I2C2_DMA_TDLR_REG_DMATDL_Pos   (0UL)

I2C2 I2C2_DMA_TDLR_REG: DMATDL (Bit 0)

Definition at line 8155 of file DA14680BA.h.

◆ I2C2_I2C2_ENABLE_REG_CTRL_ENABLE_Msk

#define I2C2_I2C2_ENABLE_REG_CTRL_ENABLE_Msk   (0x1UL)

I2C2 I2C2_ENABLE_REG: CTRL_ENABLE (Bitfield-Mask: 0x01)

Definition at line 8084 of file DA14680BA.h.

◆ I2C2_I2C2_ENABLE_REG_CTRL_ENABLE_Pos

#define I2C2_I2C2_ENABLE_REG_CTRL_ENABLE_Pos   (0UL)

I2C2 I2C2_ENABLE_REG: CTRL_ENABLE (Bit 0)

Definition at line 8083 of file DA14680BA.h.

◆ I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Msk

#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Msk   (0x1UL)

I2C2 I2C2_ENABLE_STATUS_REG: IC_EN (Bitfield-Mask: 0x01)

Definition at line 8172 of file DA14680BA.h.

◆ I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Pos

#define I2C2_I2C2_ENABLE_STATUS_REG_IC_EN_Pos   (0UL)

I2C2 I2C2_ENABLE_STATUS_REG: IC_EN (Bit 0)

Definition at line 8171 of file DA14680BA.h.

◆ I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk

#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk   (0x2UL)

I2C2 I2C2_ENABLE_STATUS_REG: SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01)

Definition at line 8174 of file DA14680BA.h.

◆ I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos

#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos   (1UL)

I2C2 I2C2_ENABLE_STATUS_REG: SLV_DISABLED_WHILE_BUSY (Bit 1)

Definition at line 8173 of file DA14680BA.h.

◆ I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk

#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk   (0x4UL)

I2C2 I2C2_ENABLE_STATUS_REG: SLV_RX_DATA_LOST (Bitfield-Mask: 0x01)

Definition at line 8176 of file DA14680BA.h.

◆ I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos

#define I2C2_I2C2_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos   (2UL)

I2C2 I2C2_ENABLE_STATUS_REG: SLV_RX_DATA_LOST (Bit 2)

Definition at line 8175 of file DA14680BA.h.

◆ I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk

#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk   (0xffffUL)

I2C2 I2C2_FS_SCL_HCNT_REG: IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff)

Definition at line 7946 of file DA14680BA.h.

◆ I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos

#define I2C2_I2C2_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos   (0UL)

I2C2 I2C2_FS_SCL_HCNT_REG: IC_FS_SCL_HCNT (Bit 0)

Definition at line 7945 of file DA14680BA.h.

◆ I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk

#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk   (0xffffUL)

I2C2 I2C2_FS_SCL_LCNT_REG: IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff)

Definition at line 7950 of file DA14680BA.h.

◆ I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos

#define I2C2_I2C2_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos   (0UL)

I2C2 I2C2_FS_SCL_LCNT_REG: IC_FS_SCL_LCNT (Bit 0)

Definition at line 7949 of file DA14680BA.h.

◆ I2C2_I2C2_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Msk

#define I2C2_I2C2_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Msk   (0xffUL)

I2C2 I2C2_IC_FS_SPKLEN_REG: IC_FS_SPKLEN (Bitfield-Mask: 0xff)

Definition at line 8180 of file DA14680BA.h.

◆ I2C2_I2C2_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Pos

#define I2C2_I2C2_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Pos   (0UL)

I2C2 I2C2_IC_FS_SPKLEN_REG: IC_FS_SPKLEN (Bit 0)

Definition at line 8179 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Msk

#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Msk   (0x100UL)

I2C2 I2C2_INTR_MASK_REG: M_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 7996 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Pos

#define I2C2_I2C2_INTR_MASK_REG_M_ACTIVITY_Pos   (8UL)

I2C2 I2C2_INTR_MASK_REG: M_ACTIVITY (Bit 8)

Definition at line 7995 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Msk

#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Msk   (0x800UL)

I2C2 I2C2_INTR_MASK_REG: M_GEN_CALL (Bitfield-Mask: 0x01)

Definition at line 8002 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Pos

#define I2C2_I2C2_INTR_MASK_REG_M_GEN_CALL_Pos   (11UL)

I2C2 I2C2_INTR_MASK_REG: M_GEN_CALL (Bit 11)

Definition at line 8001 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Msk

#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Msk   (0x20UL)

I2C2 I2C2_INTR_MASK_REG: M_RD_REQ (Bitfield-Mask: 0x01)

Definition at line 7990 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Pos

#define I2C2_I2C2_INTR_MASK_REG_M_RD_REQ_Pos   (5UL)

I2C2 I2C2_INTR_MASK_REG: M_RD_REQ (Bit 5)

Definition at line 7989 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Msk

#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Msk   (0x80UL)

I2C2 I2C2_INTR_MASK_REG: M_RX_DONE (Bitfield-Mask: 0x01)

Definition at line 7994 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Pos

#define I2C2_I2C2_INTR_MASK_REG_M_RX_DONE_Pos   (7UL)

I2C2 I2C2_INTR_MASK_REG: M_RX_DONE (Bit 7)

Definition at line 7993 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Msk

#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Msk   (0x4UL)

I2C2 I2C2_INTR_MASK_REG: M_RX_FULL (Bitfield-Mask: 0x01)

Definition at line 7984 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Pos

#define I2C2_I2C2_INTR_MASK_REG_M_RX_FULL_Pos   (2UL)

I2C2 I2C2_INTR_MASK_REG: M_RX_FULL (Bit 2)

Definition at line 7983 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Msk

#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Msk   (0x2UL)

I2C2 I2C2_INTR_MASK_REG: M_RX_OVER (Bitfield-Mask: 0x01)

Definition at line 7982 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Pos

#define I2C2_I2C2_INTR_MASK_REG_M_RX_OVER_Pos   (1UL)

I2C2 I2C2_INTR_MASK_REG: M_RX_OVER (Bit 1)

Definition at line 7981 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Msk

#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Msk   (0x1UL)

I2C2 I2C2_INTR_MASK_REG: M_RX_UNDER (Bitfield-Mask: 0x01)

Definition at line 7980 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Pos

#define I2C2_I2C2_INTR_MASK_REG_M_RX_UNDER_Pos   (0UL)

I2C2 I2C2_INTR_MASK_REG: M_RX_UNDER (Bit 0)

Definition at line 7979 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_START_DET_Msk

#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Msk   (0x400UL)

I2C2 I2C2_INTR_MASK_REG: M_START_DET (Bitfield-Mask: 0x01)

Definition at line 8000 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_START_DET_Pos

#define I2C2_I2C2_INTR_MASK_REG_M_START_DET_Pos   (10UL)

I2C2 I2C2_INTR_MASK_REG: M_START_DET (Bit 10)

Definition at line 7999 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Msk

#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Msk   (0x200UL)

I2C2 I2C2_INTR_MASK_REG: M_STOP_DET (Bitfield-Mask: 0x01)

Definition at line 7998 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Pos

#define I2C2_I2C2_INTR_MASK_REG_M_STOP_DET_Pos   (9UL)

I2C2 I2C2_INTR_MASK_REG: M_STOP_DET (Bit 9)

Definition at line 7997 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Msk

#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Msk   (0x40UL)

I2C2 I2C2_INTR_MASK_REG: M_TX_ABRT (Bitfield-Mask: 0x01)

Definition at line 7992 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Pos

#define I2C2_I2C2_INTR_MASK_REG_M_TX_ABRT_Pos   (6UL)

I2C2 I2C2_INTR_MASK_REG: M_TX_ABRT (Bit 6)

Definition at line 7991 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Msk

#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Msk   (0x10UL)

I2C2 I2C2_INTR_MASK_REG: M_TX_EMPTY (Bitfield-Mask: 0x01)

Definition at line 7988 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Pos

#define I2C2_I2C2_INTR_MASK_REG_M_TX_EMPTY_Pos   (4UL)

I2C2 I2C2_INTR_MASK_REG: M_TX_EMPTY (Bit 4)

Definition at line 7987 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Msk

#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Msk   (0x8UL)

I2C2 I2C2_INTR_MASK_REG: M_TX_OVER (Bitfield-Mask: 0x01)

Definition at line 7986 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Pos

#define I2C2_I2C2_INTR_MASK_REG_M_TX_OVER_Pos   (3UL)

I2C2 I2C2_INTR_MASK_REG: M_TX_OVER (Bit 3)

Definition at line 7985 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Msk

#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Msk   (0x100UL)

I2C2 I2C2_INTR_STAT_REG: R_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 7970 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Pos

#define I2C2_I2C2_INTR_STAT_REG_R_ACTIVITY_Pos   (8UL)

I2C2 I2C2_INTR_STAT_REG: R_ACTIVITY (Bit 8)

Definition at line 7969 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Msk

#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Msk   (0x800UL)

I2C2 I2C2_INTR_STAT_REG: R_GEN_CALL (Bitfield-Mask: 0x01)

Definition at line 7976 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Pos

#define I2C2_I2C2_INTR_STAT_REG_R_GEN_CALL_Pos   (11UL)

I2C2 I2C2_INTR_STAT_REG: R_GEN_CALL (Bit 11)

Definition at line 7975 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Msk

#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Msk   (0x20UL)

I2C2 I2C2_INTR_STAT_REG: R_RD_REQ (Bitfield-Mask: 0x01)

Definition at line 7964 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Pos

#define I2C2_I2C2_INTR_STAT_REG_R_RD_REQ_Pos   (5UL)

I2C2 I2C2_INTR_STAT_REG: R_RD_REQ (Bit 5)

Definition at line 7963 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Msk

#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Msk   (0x80UL)

I2C2 I2C2_INTR_STAT_REG: R_RX_DONE (Bitfield-Mask: 0x01)

Definition at line 7968 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Pos

#define I2C2_I2C2_INTR_STAT_REG_R_RX_DONE_Pos   (7UL)

I2C2 I2C2_INTR_STAT_REG: R_RX_DONE (Bit 7)

Definition at line 7967 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Msk

#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Msk   (0x4UL)

I2C2 I2C2_INTR_STAT_REG: R_RX_FULL (Bitfield-Mask: 0x01)

Definition at line 7958 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Pos

#define I2C2_I2C2_INTR_STAT_REG_R_RX_FULL_Pos   (2UL)

I2C2 I2C2_INTR_STAT_REG: R_RX_FULL (Bit 2)

Definition at line 7957 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Msk

#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Msk   (0x2UL)

I2C2 I2C2_INTR_STAT_REG: R_RX_OVER (Bitfield-Mask: 0x01)

Definition at line 7956 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Pos

#define I2C2_I2C2_INTR_STAT_REG_R_RX_OVER_Pos   (1UL)

I2C2 I2C2_INTR_STAT_REG: R_RX_OVER (Bit 1)

Definition at line 7955 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Msk

#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Msk   (0x1UL)

I2C2 I2C2_INTR_STAT_REG: R_RX_UNDER (Bitfield-Mask: 0x01)

Definition at line 7954 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Pos

#define I2C2_I2C2_INTR_STAT_REG_R_RX_UNDER_Pos   (0UL)

I2C2 I2C2_INTR_STAT_REG: R_RX_UNDER (Bit 0)

Definition at line 7953 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_START_DET_Msk

#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Msk   (0x400UL)

I2C2 I2C2_INTR_STAT_REG: R_START_DET (Bitfield-Mask: 0x01)

Definition at line 7974 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_START_DET_Pos

#define I2C2_I2C2_INTR_STAT_REG_R_START_DET_Pos   (10UL)

I2C2 I2C2_INTR_STAT_REG: R_START_DET (Bit 10)

Definition at line 7973 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Msk

#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Msk   (0x200UL)

I2C2 I2C2_INTR_STAT_REG: R_STOP_DET (Bitfield-Mask: 0x01)

Definition at line 7972 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Pos

#define I2C2_I2C2_INTR_STAT_REG_R_STOP_DET_Pos   (9UL)

I2C2 I2C2_INTR_STAT_REG: R_STOP_DET (Bit 9)

Definition at line 7971 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Msk

#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Msk   (0x40UL)

I2C2 I2C2_INTR_STAT_REG: R_TX_ABRT (Bitfield-Mask: 0x01)

Definition at line 7966 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Pos

#define I2C2_I2C2_INTR_STAT_REG_R_TX_ABRT_Pos   (6UL)

I2C2 I2C2_INTR_STAT_REG: R_TX_ABRT (Bit 6)

Definition at line 7965 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Msk

#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Msk   (0x10UL)

I2C2 I2C2_INTR_STAT_REG: R_TX_EMPTY (Bitfield-Mask: 0x01)

Definition at line 7962 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Pos

#define I2C2_I2C2_INTR_STAT_REG_R_TX_EMPTY_Pos   (4UL)

I2C2 I2C2_INTR_STAT_REG: R_TX_EMPTY (Bit 4)

Definition at line 7961 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Msk

#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Msk   (0x8UL)

I2C2 I2C2_INTR_STAT_REG: R_TX_OVER (Bitfield-Mask: 0x01)

Definition at line 7960 of file DA14680BA.h.

◆ I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Pos

#define I2C2_I2C2_INTR_STAT_REG_R_TX_OVER_Pos   (3UL)

I2C2 I2C2_INTR_STAT_REG: R_TX_OVER (Bit 3)

Definition at line 7959 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Msk

#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Msk   (0x100UL)

I2C2 I2C2_RAW_INTR_STAT_REG: ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 8022 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Pos

#define I2C2_I2C2_RAW_INTR_STAT_REG_ACTIVITY_Pos   (8UL)

I2C2 I2C2_RAW_INTR_STAT_REG: ACTIVITY (Bit 8)

Definition at line 8021 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Msk

#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Msk   (0x800UL)

I2C2 I2C2_RAW_INTR_STAT_REG: GEN_CALL (Bitfield-Mask: 0x01)

Definition at line 8028 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Pos

#define I2C2_I2C2_RAW_INTR_STAT_REG_GEN_CALL_Pos   (11UL)

I2C2 I2C2_RAW_INTR_STAT_REG: GEN_CALL (Bit 11)

Definition at line 8027 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Msk

#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Msk   (0x20UL)

I2C2 I2C2_RAW_INTR_STAT_REG: RD_REQ (Bitfield-Mask: 0x01)

Definition at line 8016 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Pos

#define I2C2_I2C2_RAW_INTR_STAT_REG_RD_REQ_Pos   (5UL)

I2C2 I2C2_RAW_INTR_STAT_REG: RD_REQ (Bit 5)

Definition at line 8015 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Msk

#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Msk   (0x80UL)

I2C2 I2C2_RAW_INTR_STAT_REG: RX_DONE (Bitfield-Mask: 0x01)

Definition at line 8020 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Pos

#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_DONE_Pos   (7UL)

I2C2 I2C2_RAW_INTR_STAT_REG: RX_DONE (Bit 7)

Definition at line 8019 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Msk

#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Msk   (0x4UL)

I2C2 I2C2_RAW_INTR_STAT_REG: RX_FULL (Bitfield-Mask: 0x01)

Definition at line 8010 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Pos

#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_FULL_Pos   (2UL)

I2C2 I2C2_RAW_INTR_STAT_REG: RX_FULL (Bit 2)

Definition at line 8009 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Msk

#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Msk   (0x2UL)

I2C2 I2C2_RAW_INTR_STAT_REG: RX_OVER (Bitfield-Mask: 0x01)

Definition at line 8008 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Pos

#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_OVER_Pos   (1UL)

I2C2 I2C2_RAW_INTR_STAT_REG: RX_OVER (Bit 1)

Definition at line 8007 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Msk

#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Msk   (0x1UL)

I2C2 I2C2_RAW_INTR_STAT_REG: RX_UNDER (Bitfield-Mask: 0x01)

Definition at line 8006 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Pos

#define I2C2_I2C2_RAW_INTR_STAT_REG_RX_UNDER_Pos   (0UL)

I2C2 I2C2_RAW_INTR_STAT_REG: RX_UNDER (Bit 0)

Definition at line 8005 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Msk

#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Msk   (0x400UL)

I2C2 I2C2_RAW_INTR_STAT_REG: START_DET (Bitfield-Mask: 0x01)

Definition at line 8026 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Pos

#define I2C2_I2C2_RAW_INTR_STAT_REG_START_DET_Pos   (10UL)

I2C2 I2C2_RAW_INTR_STAT_REG: START_DET (Bit 10)

Definition at line 8025 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Msk

#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Msk   (0x200UL)

I2C2 I2C2_RAW_INTR_STAT_REG: STOP_DET (Bitfield-Mask: 0x01)

Definition at line 8024 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Pos

#define I2C2_I2C2_RAW_INTR_STAT_REG_STOP_DET_Pos   (9UL)

I2C2 I2C2_RAW_INTR_STAT_REG: STOP_DET (Bit 9)

Definition at line 8023 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Msk

#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Msk   (0x40UL)

I2C2 I2C2_RAW_INTR_STAT_REG: TX_ABRT (Bitfield-Mask: 0x01)

Definition at line 8018 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Pos

#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_ABRT_Pos   (6UL)

I2C2 I2C2_RAW_INTR_STAT_REG: TX_ABRT (Bit 6)

Definition at line 8017 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Msk

#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Msk   (0x10UL)

I2C2 I2C2_RAW_INTR_STAT_REG: TX_EMPTY (Bitfield-Mask: 0x01)

Definition at line 8014 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Pos

#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_EMPTY_Pos   (4UL)

I2C2 I2C2_RAW_INTR_STAT_REG: TX_EMPTY (Bit 4)

Definition at line 8013 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Msk

#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Msk   (0x8UL)

I2C2 I2C2_RAW_INTR_STAT_REG: TX_OVER (Bitfield-Mask: 0x01)

Definition at line 8012 of file DA14680BA.h.

◆ I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Pos

#define I2C2_I2C2_RAW_INTR_STAT_REG_TX_OVER_Pos   (3UL)

I2C2 I2C2_RAW_INTR_STAT_REG: TX_OVER (Bit 3)

Definition at line 8011 of file DA14680BA.h.

◆ I2C2_I2C2_RX_TL_REG_RX_TL_Msk

#define I2C2_I2C2_RX_TL_REG_RX_TL_Msk   (0x1fUL)

I2C2 I2C2_RX_TL_REG: RX_TL (Bitfield-Mask: 0x1f)

Definition at line 8032 of file DA14680BA.h.

◆ I2C2_I2C2_RX_TL_REG_RX_TL_Pos

#define I2C2_I2C2_RX_TL_REG_RX_TL_Pos   (0UL)

I2C2 I2C2_RX_TL_REG: RX_TL (Bit 0)

Definition at line 8031 of file DA14680BA.h.

◆ I2C2_I2C2_RXFLR_REG_RXFLR_Msk

#define I2C2_I2C2_RXFLR_REG_RXFLR_Msk   (0x3fUL)

I2C2 I2C2_RXFLR_REG: RXFLR (Bitfield-Mask: 0x3f)

Definition at line 8108 of file DA14680BA.h.

◆ I2C2_I2C2_RXFLR_REG_RXFLR_Pos

#define I2C2_I2C2_RXFLR_REG_RXFLR_Pos   (0UL)

I2C2 I2C2_RXFLR_REG: RXFLR (Bit 0)

Definition at line 8107 of file DA14680BA.h.

◆ I2C2_I2C2_SAR_REG_IC_SAR_Msk

#define I2C2_I2C2_SAR_REG_IC_SAR_Msk   (0x3ffUL)

I2C2 I2C2_SAR_REG: IC_SAR (Bitfield-Mask: 0x3ff)

Definition at line 7924 of file DA14680BA.h.

◆ I2C2_I2C2_SAR_REG_IC_SAR_Pos

#define I2C2_I2C2_SAR_REG_IC_SAR_Pos   (0UL)

I2C2 I2C2_SAR_REG: IC_SAR (Bit 0)

Definition at line 7923 of file DA14680BA.h.

◆ I2C2_I2C2_SDA_HOLD_REG_IC_SDA_HOLD_Msk

#define I2C2_I2C2_SDA_HOLD_REG_IC_SDA_HOLD_Msk   (0xffffUL)

I2C2 I2C2_SDA_HOLD_REG: IC_SDA_HOLD (Bitfield-Mask: 0xffff)

Definition at line 8112 of file DA14680BA.h.

◆ I2C2_I2C2_SDA_HOLD_REG_IC_SDA_HOLD_Pos

#define I2C2_I2C2_SDA_HOLD_REG_IC_SDA_HOLD_Pos   (0UL)

I2C2 I2C2_SDA_HOLD_REG: IC_SDA_HOLD (Bit 0)

Definition at line 8111 of file DA14680BA.h.

◆ I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Msk

#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Msk   (0xffUL)

I2C2 I2C2_SDA_SETUP_REG: SDA_SETUP (Bitfield-Mask: 0xff)

Definition at line 8164 of file DA14680BA.h.

◆ I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Pos

#define I2C2_I2C2_SDA_SETUP_REG_SDA_SETUP_Pos   (0UL)

I2C2 I2C2_SDA_SETUP_REG: SDA_SETUP (Bit 0)

Definition at line 8163 of file DA14680BA.h.

◆ I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk

#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk   (0xffffUL)

I2C2 I2C2_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff)

Definition at line 7938 of file DA14680BA.h.

◆ I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos

#define I2C2_I2C2_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos   (0UL)

I2C2 I2C2_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bit 0)

Definition at line 7937 of file DA14680BA.h.

◆ I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk

#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk   (0xffffUL)

I2C2 I2C2_SS_SCL_LCNT_REG: IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff)

Definition at line 7942 of file DA14680BA.h.

◆ I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos

#define I2C2_I2C2_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos   (0UL)

I2C2 I2C2_SS_SCL_LCNT_REG: IC_SS_SCL_LCNT (Bit 0)

Definition at line 7941 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Msk

#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Msk   (0x1UL)

I2C2 I2C2_STATUS_REG: I2C_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 8088 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Pos

#define I2C2_I2C2_STATUS_REG_I2C_ACTIVITY_Pos   (0UL)

I2C2 I2C2_STATUS_REG: I2C_ACTIVITY (Bit 0)

Definition at line 8087 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Msk

#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Msk   (0x20UL)

I2C2 I2C2_STATUS_REG: MST_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 8098 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Pos

#define I2C2_I2C2_STATUS_REG_MST_ACTIVITY_Pos   (5UL)

I2C2 I2C2_STATUS_REG: MST_ACTIVITY (Bit 5)

Definition at line 8097 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_RFF_Msk

#define I2C2_I2C2_STATUS_REG_RFF_Msk   (0x10UL)

I2C2 I2C2_STATUS_REG: RFF (Bitfield-Mask: 0x01)

Definition at line 8096 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_RFF_Pos

#define I2C2_I2C2_STATUS_REG_RFF_Pos   (4UL)

I2C2 I2C2_STATUS_REG: RFF (Bit 4)

Definition at line 8095 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_RFNE_Msk

#define I2C2_I2C2_STATUS_REG_RFNE_Msk   (0x8UL)

I2C2 I2C2_STATUS_REG: RFNE (Bitfield-Mask: 0x01)

Definition at line 8094 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_RFNE_Pos

#define I2C2_I2C2_STATUS_REG_RFNE_Pos   (3UL)

I2C2 I2C2_STATUS_REG: RFNE (Bit 3)

Definition at line 8093 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Msk

#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Msk   (0x40UL)

I2C2 I2C2_STATUS_REG: SLV_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 8100 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Pos

#define I2C2_I2C2_STATUS_REG_SLV_ACTIVITY_Pos   (6UL)

I2C2 I2C2_STATUS_REG: SLV_ACTIVITY (Bit 6)

Definition at line 8099 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_TFE_Msk

#define I2C2_I2C2_STATUS_REG_TFE_Msk   (0x4UL)

I2C2 I2C2_STATUS_REG: TFE (Bitfield-Mask: 0x01)

Definition at line 8092 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_TFE_Pos

#define I2C2_I2C2_STATUS_REG_TFE_Pos   (2UL)

I2C2 I2C2_STATUS_REG: TFE (Bit 2)

Definition at line 8091 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_TFNF_Msk

#define I2C2_I2C2_STATUS_REG_TFNF_Msk   (0x2UL)

I2C2 I2C2_STATUS_REG: TFNF (Bitfield-Mask: 0x01)

Definition at line 8090 of file DA14680BA.h.

◆ I2C2_I2C2_STATUS_REG_TFNF_Pos

#define I2C2_I2C2_STATUS_REG_TFNF_Pos   (1UL)

I2C2 I2C2_STATUS_REG: TFNF (Bit 1)

Definition at line 8089 of file DA14680BA.h.

◆ I2C2_I2C2_TAR_REG_GC_OR_START_Msk

#define I2C2_I2C2_TAR_REG_GC_OR_START_Msk   (0x400UL)

I2C2 I2C2_TAR_REG: GC_OR_START (Bitfield-Mask: 0x01)

Definition at line 7918 of file DA14680BA.h.

◆ I2C2_I2C2_TAR_REG_GC_OR_START_Pos

#define I2C2_I2C2_TAR_REG_GC_OR_START_Pos   (10UL)

I2C2 I2C2_TAR_REG: GC_OR_START (Bit 10)

Definition at line 7917 of file DA14680BA.h.

◆ I2C2_I2C2_TAR_REG_IC_TAR_Msk

#define I2C2_I2C2_TAR_REG_IC_TAR_Msk   (0x3ffUL)

I2C2 I2C2_TAR_REG: IC_TAR (Bitfield-Mask: 0x3ff)

Definition at line 7916 of file DA14680BA.h.

◆ I2C2_I2C2_TAR_REG_IC_TAR_Pos

#define I2C2_I2C2_TAR_REG_IC_TAR_Pos   (0UL)

I2C2 I2C2_TAR_REG: IC_TAR (Bit 0)

Definition at line 7915 of file DA14680BA.h.

◆ I2C2_I2C2_TAR_REG_SPECIAL_Msk

#define I2C2_I2C2_TAR_REG_SPECIAL_Msk   (0x800UL)

I2C2 I2C2_TAR_REG: SPECIAL (Bitfield-Mask: 0x01)

Definition at line 7920 of file DA14680BA.h.

◆ I2C2_I2C2_TAR_REG_SPECIAL_Pos

#define I2C2_I2C2_TAR_REG_SPECIAL_Pos   (11UL)

I2C2 I2C2_TAR_REG: SPECIAL (Bit 11)

Definition at line 7919 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk   (0x2UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01)

Definition at line 8118 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos   (1UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10ADDR1_NOACK (Bit 1)

Definition at line 8117 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk   (0x4UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01)

Definition at line 8120 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos   (2UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10ADDR2_NOACK (Bit 2)

Definition at line 8119 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk   (0x400UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01)

Definition at line 8136 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos   (10UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_10B_RD_NORSTRT (Bit 10)

Definition at line 8135 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk   (0x1UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01)

Definition at line 8116 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos   (0UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_7B_ADDR_NOACK (Bit 0)

Definition at line 8115 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk   (0x10UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_GCALL_NOACK (Bitfield-Mask: 0x01)

Definition at line 8124 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos   (4UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_GCALL_NOACK (Bit 4)

Definition at line 8123 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk   (0x20UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_GCALL_READ (Bitfield-Mask: 0x01)

Definition at line 8126 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos   (5UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_GCALL_READ (Bit 5)

Definition at line 8125 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk   (0x40UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_HS_ACKDET (Bitfield-Mask: 0x01)

Definition at line 8128 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos   (6UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_HS_ACKDET (Bit 6)

Definition at line 8127 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk   (0x100UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_HS_NORSTRT (Bitfield-Mask: 0x01)

Definition at line 8132 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos   (8UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_HS_NORSTRT (Bit 8)

Definition at line 8131 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk   (0x800UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_MASTER_DIS (Bitfield-Mask: 0x01)

Definition at line 8138 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos   (11UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_MASTER_DIS (Bit 11)

Definition at line 8137 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk   (0x80UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01)

Definition at line 8130 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos   (7UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SBYTE_ACKDET (Bit 7)

Definition at line 8129 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk   (0x200UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01)

Definition at line 8134 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos   (9UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SBYTE_NORSTRT (Bit 9)

Definition at line 8133 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk   (0x4000UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01)

Definition at line 8144 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos   (14UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLV_ARBLOST (Bit 14)

Definition at line 8143 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk   (0x2000UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01)

Definition at line 8142 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos   (13UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLVFLUSH_TXFIFO (Bit 13)

Definition at line 8141 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk   (0x8000UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLVRD_INTX (Bitfield-Mask: 0x01)

Definition at line 8146 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos   (15UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_SLVRD_INTX (Bit 15)

Definition at line 8145 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk   (0x8UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01)

Definition at line 8122 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos   (3UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ABRT_TXDATA_NOACK (Bit 3)

Definition at line 8121 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Msk

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Msk   (0x1000UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ARB_LOST (Bitfield-Mask: 0x01)

Definition at line 8140 of file DA14680BA.h.

◆ I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Pos

#define I2C2_I2C2_TX_ABRT_SOURCE_REG_ARB_LOST_Pos   (12UL)

I2C2 I2C2_TX_ABRT_SOURCE_REG: ARB_LOST (Bit 12)

Definition at line 8139 of file DA14680BA.h.

◆ I2C2_I2C2_TX_TL_REG_TX_TL_Msk

#define I2C2_I2C2_TX_TL_REG_TX_TL_Msk   (0x1fUL)

I2C2 I2C2_TX_TL_REG: TX_TL (Bitfield-Mask: 0x1f)

Definition at line 8036 of file DA14680BA.h.

◆ I2C2_I2C2_TX_TL_REG_TX_TL_Pos

#define I2C2_I2C2_TX_TL_REG_TX_TL_Pos   (0UL)

I2C2 I2C2_TX_TL_REG: TX_TL (Bit 0)

Definition at line 8035 of file DA14680BA.h.

◆ I2C2_I2C2_TXFLR_REG_TXFLR_Msk

#define I2C2_I2C2_TXFLR_REG_TXFLR_Msk   (0x3fUL)

I2C2 I2C2_TXFLR_REG: TXFLR (Bitfield-Mask: 0x3f)

Definition at line 8104 of file DA14680BA.h.

◆ I2C2_I2C2_TXFLR_REG_TXFLR_Pos

#define I2C2_I2C2_TXFLR_REG_TXFLR_Pos   (0UL)

I2C2 I2C2_TXFLR_REG: TXFLR (Bit 0)

Definition at line 8103 of file DA14680BA.h.

◆ I2C_BASE

#define I2C_BASE   0x50001400UL

Definition at line 12046 of file DA14680BA.h.

◆ I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk

#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk   (0x1UL)

I2C I2C_ACK_GENERAL_CALL_REG: ACK_GEN_CALL (Bitfield-Mask: 0x01)

Definition at line 7856 of file DA14680BA.h.

◆ I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos

#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos   (0UL)

I2C I2C_ACK_GENERAL_CALL_REG: ACK_GEN_CALL (Bit 0)

Definition at line 7855 of file DA14680BA.h.

◆ I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk

#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk   (0x1UL)

I2C I2C_CLR_ACTIVITY_REG: CLR_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 7756 of file DA14680BA.h.

◆ I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos

#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos   (0UL)

I2C I2C_CLR_ACTIVITY_REG: CLR_ACTIVITY (Bit 0)

Definition at line 7755 of file DA14680BA.h.

◆ I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk

#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk   (0x1UL)

I2C I2C_CLR_GEN_CALL_REG: CLR_GEN_CALL (Bitfield-Mask: 0x01)

Definition at line 7768 of file DA14680BA.h.

◆ I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos

#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos   (0UL)

I2C I2C_CLR_GEN_CALL_REG: CLR_GEN_CALL (Bit 0)

Definition at line 7767 of file DA14680BA.h.

◆ I2C_I2C_CLR_INTR_REG_CLR_INTR_Msk

#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Msk   (0x1UL)

I2C I2C_CLR_INTR_REG: CLR_INTR (Bitfield-Mask: 0x01)

Definition at line 7728 of file DA14680BA.h.

◆ I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos

#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos   (0UL)

I2C I2C_CLR_INTR_REG: CLR_INTR (Bit 0)

Definition at line 7727 of file DA14680BA.h.

◆ I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Msk

#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Msk   (0x1UL)

I2C I2C_CLR_RD_REQ_REG: CLR_RD_REQ (Bitfield-Mask: 0x01)

Definition at line 7744 of file DA14680BA.h.

◆ I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Pos

#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Pos   (0UL)

I2C I2C_CLR_RD_REQ_REG: CLR_RD_REQ (Bit 0)

Definition at line 7743 of file DA14680BA.h.

◆ I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Msk

#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Msk   (0x1UL)

I2C I2C_CLR_RX_DONE_REG: CLR_RX_DONE (Bitfield-Mask: 0x01)

Definition at line 7752 of file DA14680BA.h.

◆ I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Pos

#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Pos   (0UL)

I2C I2C_CLR_RX_DONE_REG: CLR_RX_DONE (Bit 0)

Definition at line 7751 of file DA14680BA.h.

◆ I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Msk

#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Msk   (0x1UL)

I2C I2C_CLR_RX_OVER_REG: CLR_RX_OVER (Bitfield-Mask: 0x01)

Definition at line 7736 of file DA14680BA.h.

◆ I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Pos

#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Pos   (0UL)

I2C I2C_CLR_RX_OVER_REG: CLR_RX_OVER (Bit 0)

Definition at line 7735 of file DA14680BA.h.

◆ I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk

#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk   (0x1UL)

I2C I2C_CLR_RX_UNDER_REG: CLR_RX_UNDER (Bitfield-Mask: 0x01)

Definition at line 7732 of file DA14680BA.h.

◆ I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos

#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos   (0UL)

I2C I2C_CLR_RX_UNDER_REG: CLR_RX_UNDER (Bit 0)

Definition at line 7731 of file DA14680BA.h.

◆ I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Msk

#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Msk   (0x1UL)

I2C I2C_CLR_START_DET_REG: CLR_START_DET (Bitfield-Mask: 0x01)

Definition at line 7764 of file DA14680BA.h.

◆ I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Pos

#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Pos   (0UL)

I2C I2C_CLR_START_DET_REG: CLR_START_DET (Bit 0)

Definition at line 7763 of file DA14680BA.h.

◆ I2C_I2C_CLR_STOP_DET_REG_CLR_ACTIVITY_Msk

#define I2C_I2C_CLR_STOP_DET_REG_CLR_ACTIVITY_Msk   (0x1UL)

I2C I2C_CLR_STOP_DET_REG: CLR_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 7760 of file DA14680BA.h.

◆ I2C_I2C_CLR_STOP_DET_REG_CLR_ACTIVITY_Pos

#define I2C_I2C_CLR_STOP_DET_REG_CLR_ACTIVITY_Pos   (0UL)

I2C I2C_CLR_STOP_DET_REG: CLR_ACTIVITY (Bit 0)

Definition at line 7759 of file DA14680BA.h.

◆ I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk

#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk   (0x1UL)

I2C I2C_CLR_TX_ABRT_REG: CLR_TX_ABRT (Bitfield-Mask: 0x01)

Definition at line 7748 of file DA14680BA.h.

◆ I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos

#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos   (0UL)

I2C I2C_CLR_TX_ABRT_REG: CLR_TX_ABRT (Bit 0)

Definition at line 7747 of file DA14680BA.h.

◆ I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Msk

#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Msk   (0x1UL)

I2C I2C_CLR_TX_OVER_REG: CLR_TX_OVER (Bitfield-Mask: 0x01)

Definition at line 7740 of file DA14680BA.h.

◆ I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Pos

#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Pos   (0UL)

I2C I2C_CLR_TX_OVER_REG: CLR_TX_OVER (Bit 0)

Definition at line 7739 of file DA14680BA.h.

◆ I2C_I2C_COMP2_VERSION_IC_COMP2_VERSION_Msk

#define I2C_I2C_COMP2_VERSION_IC_COMP2_VERSION_Msk   (0xffffUL)

I2C I2C_COMP2_VERSION: IC_COMP2_VERSION (Bitfield-Mask: 0xffff)

Definition at line 7884 of file DA14680BA.h.

◆ I2C_I2C_COMP2_VERSION_IC_COMP2_VERSION_Pos

#define I2C_I2C_COMP2_VERSION_IC_COMP2_VERSION_Pos   (0UL)

I2C I2C_COMP2_VERSION: IC_COMP2_VERSION (Bit 0)

Definition at line 7883 of file DA14680BA.h.

◆ I2C_I2C_COMP_PARAM1_REG_IC_COMP_PARAM1_Msk

#define I2C_I2C_COMP_PARAM1_REG_IC_COMP_PARAM1_Msk   (0xffffUL)

I2C I2C_COMP_PARAM1_REG: IC_COMP_PARAM1 (Bitfield-Mask: 0xffff)

Definition at line 7872 of file DA14680BA.h.

◆ I2C_I2C_COMP_PARAM1_REG_IC_COMP_PARAM1_Pos

#define I2C_I2C_COMP_PARAM1_REG_IC_COMP_PARAM1_Pos   (0UL)

I2C I2C_COMP_PARAM1_REG: IC_COMP_PARAM1 (Bit 0)

Definition at line 7871 of file DA14680BA.h.

◆ I2C_I2C_COMP_PARAM2_REG_IC_COMP_PARAM2_Msk

#define I2C_I2C_COMP_PARAM2_REG_IC_COMP_PARAM2_Msk   (0xffffUL)

I2C I2C_COMP_PARAM2_REG: IC_COMP_PARAM2 (Bitfield-Mask: 0xffff)

Definition at line 7876 of file DA14680BA.h.

◆ I2C_I2C_COMP_PARAM2_REG_IC_COMP_PARAM2_Pos

#define I2C_I2C_COMP_PARAM2_REG_IC_COMP_PARAM2_Pos   (0UL)

I2C I2C_COMP_PARAM2_REG: IC_COMP_PARAM2 (Bit 0)

Definition at line 7875 of file DA14680BA.h.

◆ I2C_I2C_COMP_TYPE2_REG_IC_COMP2_TYPE_Msk

#define I2C_I2C_COMP_TYPE2_REG_IC_COMP2_TYPE_Msk   (0xffffUL)

I2C I2C_COMP_TYPE2_REG: IC_COMP2_TYPE (Bitfield-Mask: 0xffff)

Definition at line 7892 of file DA14680BA.h.

◆ I2C_I2C_COMP_TYPE2_REG_IC_COMP2_TYPE_Pos

#define I2C_I2C_COMP_TYPE2_REG_IC_COMP2_TYPE_Pos   (0UL)

I2C I2C_COMP_TYPE2_REG: IC_COMP2_TYPE (Bit 0)

Definition at line 7891 of file DA14680BA.h.

◆ I2C_I2C_COMP_TYPE_REG_IC_COMP_TYPE_Msk

#define I2C_I2C_COMP_TYPE_REG_IC_COMP_TYPE_Msk   (0xffffUL)

I2C I2C_COMP_TYPE_REG: IC_COMP_TYPE (Bitfield-Mask: 0xffff)

Definition at line 7888 of file DA14680BA.h.

◆ I2C_I2C_COMP_TYPE_REG_IC_COMP_TYPE_Pos

#define I2C_I2C_COMP_TYPE_REG_IC_COMP_TYPE_Pos   (0UL)

I2C I2C_COMP_TYPE_REG: IC_COMP_TYPE (Bit 0)

Definition at line 7887 of file DA14680BA.h.

◆ I2C_I2C_COMP_VERSION_REG_IC_COMP_VERSION_Msk

#define I2C_I2C_COMP_VERSION_REG_IC_COMP_VERSION_Msk   (0xffffUL)

I2C I2C_COMP_VERSION_REG: IC_COMP_VERSION (Bitfield-Mask: 0xffff)

Definition at line 7880 of file DA14680BA.h.

◆ I2C_I2C_COMP_VERSION_REG_IC_COMP_VERSION_Pos

#define I2C_I2C_COMP_VERSION_REG_IC_COMP_VERSION_Pos   (0UL)

I2C I2C_COMP_VERSION_REG: IC_COMP_VERSION (Bit 0)

Definition at line 7879 of file DA14680BA.h.

◆ I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk

#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk   (0x10UL)

I2C I2C_CON_REG: I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01)

Definition at line 7596 of file DA14680BA.h.

◆ I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Pos

#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Pos   (4UL)

I2C I2C_CON_REG: I2C_10BITADDR_MASTER (Bit 4)

Definition at line 7595 of file DA14680BA.h.

◆ I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Msk

#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Msk   (0x8UL)

I2C I2C_CON_REG: I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01)

Definition at line 7594 of file DA14680BA.h.

◆ I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Pos

#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Pos   (3UL)

I2C I2C_CON_REG: I2C_10BITADDR_SLAVE (Bit 3)

Definition at line 7593 of file DA14680BA.h.

◆ I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk

#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk   (0x1UL)

I2C I2C_CON_REG: I2C_MASTER_MODE (Bitfield-Mask: 0x01)

Definition at line 7590 of file DA14680BA.h.

◆ I2C_I2C_CON_REG_I2C_MASTER_MODE_Pos

#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Pos   (0UL)

I2C I2C_CON_REG: I2C_MASTER_MODE (Bit 0)

Definition at line 7589 of file DA14680BA.h.

◆ I2C_I2C_CON_REG_I2C_RESTART_EN_Msk

#define I2C_I2C_CON_REG_I2C_RESTART_EN_Msk   (0x20UL)

I2C I2C_CON_REG: I2C_RESTART_EN (Bitfield-Mask: 0x01)

Definition at line 7598 of file DA14680BA.h.

◆ I2C_I2C_CON_REG_I2C_RESTART_EN_Pos

#define I2C_I2C_CON_REG_I2C_RESTART_EN_Pos   (5UL)

I2C I2C_CON_REG: I2C_RESTART_EN (Bit 5)

Definition at line 7597 of file DA14680BA.h.

◆ I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk

#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk   (0x40UL)

I2C I2C_CON_REG: I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01)

Definition at line 7600 of file DA14680BA.h.

◆ I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Pos

#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Pos   (6UL)

I2C I2C_CON_REG: I2C_SLAVE_DISABLE (Bit 6)

Definition at line 7599 of file DA14680BA.h.

◆ I2C_I2C_CON_REG_I2C_SPEED_Msk

#define I2C_I2C_CON_REG_I2C_SPEED_Msk   (0x6UL)

I2C I2C_CON_REG: I2C_SPEED (Bitfield-Mask: 0x03)

Definition at line 7592 of file DA14680BA.h.

◆ I2C_I2C_CON_REG_I2C_SPEED_Pos

#define I2C_I2C_CON_REG_I2C_SPEED_Pos   (1UL)

I2C I2C_CON_REG: I2C_SPEED (Bit 1)

Definition at line 7591 of file DA14680BA.h.

◆ I2C_I2C_DATA_CMD_REG_CMD_Msk

#define I2C_I2C_DATA_CMD_REG_CMD_Msk   (0x100UL)

I2C I2C_DATA_CMD_REG: CMD (Bitfield-Mask: 0x01)

Definition at line 7618 of file DA14680BA.h.

◆ I2C_I2C_DATA_CMD_REG_CMD_Pos

#define I2C_I2C_DATA_CMD_REG_CMD_Pos   (8UL)

I2C I2C_DATA_CMD_REG: CMD (Bit 8)

Definition at line 7617 of file DA14680BA.h.

◆ I2C_I2C_DATA_CMD_REG_DAT_Msk

#define I2C_I2C_DATA_CMD_REG_DAT_Msk   (0xffUL)

I2C I2C_DATA_CMD_REG: DAT (Bitfield-Mask: 0xff)

Definition at line 7616 of file DA14680BA.h.

◆ I2C_I2C_DATA_CMD_REG_DAT_Pos

#define I2C_I2C_DATA_CMD_REG_DAT_Pos   (0UL)

I2C I2C_DATA_CMD_REG: DAT (Bit 0)

Definition at line 7615 of file DA14680BA.h.

◆ I2C_I2C_DATA_CMD_REG_RESTART_Msk

#define I2C_I2C_DATA_CMD_REG_RESTART_Msk   (0x400UL)

I2C I2C_DATA_CMD_REG: RESTART (Bitfield-Mask: 0x01)

Definition at line 7622 of file DA14680BA.h.

◆ I2C_I2C_DATA_CMD_REG_RESTART_Pos

#define I2C_I2C_DATA_CMD_REG_RESTART_Pos   (10UL)

I2C I2C_DATA_CMD_REG: RESTART (Bit 10)

Definition at line 7621 of file DA14680BA.h.

◆ I2C_I2C_DATA_CMD_REG_STOP_Msk

#define I2C_I2C_DATA_CMD_REG_STOP_Msk   (0x200UL)

I2C I2C_DATA_CMD_REG: STOP (Bitfield-Mask: 0x01)

Definition at line 7620 of file DA14680BA.h.

◆ I2C_I2C_DATA_CMD_REG_STOP_Pos

#define I2C_I2C_DATA_CMD_REG_STOP_Pos   (9UL)

I2C I2C_DATA_CMD_REG: STOP (Bit 9)

Definition at line 7619 of file DA14680BA.h.

◆ I2C_I2C_DMA_CR_REG_RDMAE_Msk

#define I2C_I2C_DMA_CR_REG_RDMAE_Msk   (0x1UL)

I2C I2C_DMA_CR_REG: RDMAE (Bitfield-Mask: 0x01)

Definition at line 7838 of file DA14680BA.h.

◆ I2C_I2C_DMA_CR_REG_RDMAE_Pos

#define I2C_I2C_DMA_CR_REG_RDMAE_Pos   (0UL)

I2C I2C_DMA_CR_REG: RDMAE (Bit 0)

Definition at line 7837 of file DA14680BA.h.

◆ I2C_I2C_DMA_CR_REG_TDMAE_Msk

#define I2C_I2C_DMA_CR_REG_TDMAE_Msk   (0x2UL)

I2C I2C_DMA_CR_REG: TDMAE (Bitfield-Mask: 0x01)

Definition at line 7840 of file DA14680BA.h.

◆ I2C_I2C_DMA_CR_REG_TDMAE_Pos

#define I2C_I2C_DMA_CR_REG_TDMAE_Pos   (1UL)

I2C I2C_DMA_CR_REG: TDMAE (Bit 1)

Definition at line 7839 of file DA14680BA.h.

◆ I2C_I2C_DMA_RDLR_REG_DMARDL_Msk

#define I2C_I2C_DMA_RDLR_REG_DMARDL_Msk   (0x1fUL)

I2C I2C_DMA_RDLR_REG: DMARDL (Bitfield-Mask: 0x1f)

Definition at line 7848 of file DA14680BA.h.

◆ I2C_I2C_DMA_RDLR_REG_DMARDL_Pos

#define I2C_I2C_DMA_RDLR_REG_DMARDL_Pos   (0UL)

I2C I2C_DMA_RDLR_REG: DMARDL (Bit 0)

Definition at line 7847 of file DA14680BA.h.

◆ I2C_I2C_DMA_TDLR_REG_DMATDL_Msk

#define I2C_I2C_DMA_TDLR_REG_DMATDL_Msk   (0x1fUL)

I2C I2C_DMA_TDLR_REG: DMATDL (Bitfield-Mask: 0x1f)

Definition at line 7844 of file DA14680BA.h.

◆ I2C_I2C_DMA_TDLR_REG_DMATDL_Pos

#define I2C_I2C_DMA_TDLR_REG_DMATDL_Pos   (0UL)

I2C I2C_DMA_TDLR_REG: DMATDL (Bit 0)

Definition at line 7843 of file DA14680BA.h.

◆ I2C_I2C_ENABLE_REG_CTRL_ENABLE_Msk

#define I2C_I2C_ENABLE_REG_CTRL_ENABLE_Msk   (0x1UL)

I2C I2C_ENABLE_REG: CTRL_ENABLE (Bitfield-Mask: 0x01)

Definition at line 7772 of file DA14680BA.h.

◆ I2C_I2C_ENABLE_REG_CTRL_ENABLE_Pos

#define I2C_I2C_ENABLE_REG_CTRL_ENABLE_Pos   (0UL)

I2C I2C_ENABLE_REG: CTRL_ENABLE (Bit 0)

Definition at line 7771 of file DA14680BA.h.

◆ I2C_I2C_ENABLE_STATUS_REG_IC_EN_Msk

#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Msk   (0x1UL)

I2C I2C_ENABLE_STATUS_REG: IC_EN (Bitfield-Mask: 0x01)

Definition at line 7860 of file DA14680BA.h.

◆ I2C_I2C_ENABLE_STATUS_REG_IC_EN_Pos

#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Pos   (0UL)

I2C I2C_ENABLE_STATUS_REG: IC_EN (Bit 0)

Definition at line 7859 of file DA14680BA.h.

◆ I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk

#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk   (0x2UL)

I2C I2C_ENABLE_STATUS_REG: SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01)

Definition at line 7862 of file DA14680BA.h.

◆ I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos

#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos   (1UL)

I2C I2C_ENABLE_STATUS_REG: SLV_DISABLED_WHILE_BUSY (Bit 1)

Definition at line 7861 of file DA14680BA.h.

◆ I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk

#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk   (0x4UL)

I2C I2C_ENABLE_STATUS_REG: SLV_RX_DATA_LOST (Bitfield-Mask: 0x01)

Definition at line 7864 of file DA14680BA.h.

◆ I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos

#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos   (2UL)

I2C I2C_ENABLE_STATUS_REG: SLV_RX_DATA_LOST (Bit 2)

Definition at line 7863 of file DA14680BA.h.

◆ I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk

#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk   (0xffffUL)

I2C I2C_FS_SCL_HCNT_REG: IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff)

Definition at line 7634 of file DA14680BA.h.

◆ I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos

#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos   (0UL)

I2C I2C_FS_SCL_HCNT_REG: IC_FS_SCL_HCNT (Bit 0)

Definition at line 7633 of file DA14680BA.h.

◆ I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk

#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk   (0xffffUL)

I2C I2C_FS_SCL_LCNT_REG: IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff)

Definition at line 7638 of file DA14680BA.h.

◆ I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos

#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos   (0UL)

I2C I2C_FS_SCL_LCNT_REG: IC_FS_SCL_LCNT (Bit 0)

Definition at line 7637 of file DA14680BA.h.

◆ I2C_I2C_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Msk

#define I2C_I2C_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Msk   (0xffUL)

I2C I2C_IC_FS_SPKLEN_REG: IC_FS_SPKLEN (Bitfield-Mask: 0xff)

Definition at line 7868 of file DA14680BA.h.

◆ I2C_I2C_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Pos

#define I2C_I2C_IC_FS_SPKLEN_REG_IC_FS_SPKLEN_Pos   (0UL)

I2C I2C_IC_FS_SPKLEN_REG: IC_FS_SPKLEN (Bit 0)

Definition at line 7867 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Msk

#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Msk   (0x100UL)

I2C I2C_INTR_MASK_REG: M_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 7684 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Pos

#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Pos   (8UL)

I2C I2C_INTR_MASK_REG: M_ACTIVITY (Bit 8)

Definition at line 7683 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Msk

#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Msk   (0x800UL)

I2C I2C_INTR_MASK_REG: M_GEN_CALL (Bitfield-Mask: 0x01)

Definition at line 7690 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Pos

#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Pos   (11UL)

I2C I2C_INTR_MASK_REG: M_GEN_CALL (Bit 11)

Definition at line 7689 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_RD_REQ_Msk

#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Msk   (0x20UL)

I2C I2C_INTR_MASK_REG: M_RD_REQ (Bitfield-Mask: 0x01)

Definition at line 7678 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_RD_REQ_Pos

#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Pos   (5UL)

I2C I2C_INTR_MASK_REG: M_RD_REQ (Bit 5)

Definition at line 7677 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_RX_DONE_Msk

#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Msk   (0x80UL)

I2C I2C_INTR_MASK_REG: M_RX_DONE (Bitfield-Mask: 0x01)

Definition at line 7682 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_RX_DONE_Pos

#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Pos   (7UL)

I2C I2C_INTR_MASK_REG: M_RX_DONE (Bit 7)

Definition at line 7681 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk

#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk   (0x4UL)

I2C I2C_INTR_MASK_REG: M_RX_FULL (Bitfield-Mask: 0x01)

Definition at line 7672 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_RX_FULL_Pos

#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Pos   (2UL)

I2C I2C_INTR_MASK_REG: M_RX_FULL (Bit 2)

Definition at line 7671 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_RX_OVER_Msk

#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Msk   (0x2UL)

I2C I2C_INTR_MASK_REG: M_RX_OVER (Bitfield-Mask: 0x01)

Definition at line 7670 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_RX_OVER_Pos

#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Pos   (1UL)

I2C I2C_INTR_MASK_REG: M_RX_OVER (Bit 1)

Definition at line 7669 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Msk

#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Msk   (0x1UL)

I2C I2C_INTR_MASK_REG: M_RX_UNDER (Bitfield-Mask: 0x01)

Definition at line 7668 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Pos

#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Pos   (0UL)

I2C I2C_INTR_MASK_REG: M_RX_UNDER (Bit 0)

Definition at line 7667 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_START_DET_Msk

#define I2C_I2C_INTR_MASK_REG_M_START_DET_Msk   (0x400UL)

I2C I2C_INTR_MASK_REG: M_START_DET (Bitfield-Mask: 0x01)

Definition at line 7688 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_START_DET_Pos

#define I2C_I2C_INTR_MASK_REG_M_START_DET_Pos   (10UL)

I2C I2C_INTR_MASK_REG: M_START_DET (Bit 10)

Definition at line 7687 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_STOP_DET_Msk

#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Msk   (0x200UL)

I2C I2C_INTR_MASK_REG: M_STOP_DET (Bitfield-Mask: 0x01)

Definition at line 7686 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_STOP_DET_Pos

#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Pos   (9UL)

I2C I2C_INTR_MASK_REG: M_STOP_DET (Bit 9)

Definition at line 7685 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Msk

#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Msk   (0x40UL)

I2C I2C_INTR_MASK_REG: M_TX_ABRT (Bitfield-Mask: 0x01)

Definition at line 7680 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Pos

#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Pos   (6UL)

I2C I2C_INTR_MASK_REG: M_TX_ABRT (Bit 6)

Definition at line 7679 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk

#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk   (0x10UL)

I2C I2C_INTR_MASK_REG: M_TX_EMPTY (Bitfield-Mask: 0x01)

Definition at line 7676 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Pos

#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Pos   (4UL)

I2C I2C_INTR_MASK_REG: M_TX_EMPTY (Bit 4)

Definition at line 7675 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_TX_OVER_Msk

#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Msk   (0x8UL)

I2C I2C_INTR_MASK_REG: M_TX_OVER (Bitfield-Mask: 0x01)

Definition at line 7674 of file DA14680BA.h.

◆ I2C_I2C_INTR_MASK_REG_M_TX_OVER_Pos

#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Pos   (3UL)

I2C I2C_INTR_MASK_REG: M_TX_OVER (Bit 3)

Definition at line 7673 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk

#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk   (0x100UL)

I2C I2C_INTR_STAT_REG: R_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 7658 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Pos

#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Pos   (8UL)

I2C I2C_INTR_STAT_REG: R_ACTIVITY (Bit 8)

Definition at line 7657 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk

#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk   (0x800UL)

I2C I2C_INTR_STAT_REG: R_GEN_CALL (Bitfield-Mask: 0x01)

Definition at line 7664 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Pos

#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Pos   (11UL)

I2C I2C_INTR_STAT_REG: R_GEN_CALL (Bit 11)

Definition at line 7663 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk

#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk   (0x20UL)

I2C I2C_INTR_STAT_REG: R_RD_REQ (Bitfield-Mask: 0x01)

Definition at line 7652 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_RD_REQ_Pos

#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Pos   (5UL)

I2C I2C_INTR_STAT_REG: R_RD_REQ (Bit 5)

Definition at line 7651 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk

#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk   (0x80UL)

I2C I2C_INTR_STAT_REG: R_RX_DONE (Bitfield-Mask: 0x01)

Definition at line 7656 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_RX_DONE_Pos

#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Pos   (7UL)

I2C I2C_INTR_STAT_REG: R_RX_DONE (Bit 7)

Definition at line 7655 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk

#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk   (0x4UL)

I2C I2C_INTR_STAT_REG: R_RX_FULL (Bitfield-Mask: 0x01)

Definition at line 7646 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_RX_FULL_Pos

#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Pos   (2UL)

I2C I2C_INTR_STAT_REG: R_RX_FULL (Bit 2)

Definition at line 7645 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk

#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk   (0x2UL)

I2C I2C_INTR_STAT_REG: R_RX_OVER (Bitfield-Mask: 0x01)

Definition at line 7644 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_RX_OVER_Pos

#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Pos   (1UL)

I2C I2C_INTR_STAT_REG: R_RX_OVER (Bit 1)

Definition at line 7643 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk

#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk   (0x1UL)

I2C I2C_INTR_STAT_REG: R_RX_UNDER (Bitfield-Mask: 0x01)

Definition at line 7642 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Pos

#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Pos   (0UL)

I2C I2C_INTR_STAT_REG: R_RX_UNDER (Bit 0)

Definition at line 7641 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_START_DET_Msk

#define I2C_I2C_INTR_STAT_REG_R_START_DET_Msk   (0x400UL)

I2C I2C_INTR_STAT_REG: R_START_DET (Bitfield-Mask: 0x01)

Definition at line 7662 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_START_DET_Pos

#define I2C_I2C_INTR_STAT_REG_R_START_DET_Pos   (10UL)

I2C I2C_INTR_STAT_REG: R_START_DET (Bit 10)

Definition at line 7661 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk

#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk   (0x200UL)

I2C I2C_INTR_STAT_REG: R_STOP_DET (Bitfield-Mask: 0x01)

Definition at line 7660 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_STOP_DET_Pos

#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Pos   (9UL)

I2C I2C_INTR_STAT_REG: R_STOP_DET (Bit 9)

Definition at line 7659 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk

#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk   (0x40UL)

I2C I2C_INTR_STAT_REG: R_TX_ABRT (Bitfield-Mask: 0x01)

Definition at line 7654 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Pos

#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Pos   (6UL)

I2C I2C_INTR_STAT_REG: R_TX_ABRT (Bit 6)

Definition at line 7653 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk

#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk   (0x10UL)

I2C I2C_INTR_STAT_REG: R_TX_EMPTY (Bitfield-Mask: 0x01)

Definition at line 7650 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Pos

#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Pos   (4UL)

I2C I2C_INTR_STAT_REG: R_TX_EMPTY (Bit 4)

Definition at line 7649 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk

#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk   (0x8UL)

I2C I2C_INTR_STAT_REG: R_TX_OVER (Bitfield-Mask: 0x01)

Definition at line 7648 of file DA14680BA.h.

◆ I2C_I2C_INTR_STAT_REG_R_TX_OVER_Pos

#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Pos   (3UL)

I2C I2C_INTR_STAT_REG: R_TX_OVER (Bit 3)

Definition at line 7647 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Msk   (0x100UL)

I2C I2C_RAW_INTR_STAT_REG: ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 7710 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Pos   (8UL)

I2C I2C_RAW_INTR_STAT_REG: ACTIVITY (Bit 8)

Definition at line 7709 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Msk   (0x800UL)

I2C I2C_RAW_INTR_STAT_REG: GEN_CALL (Bitfield-Mask: 0x01)

Definition at line 7716 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Pos   (11UL)

I2C I2C_RAW_INTR_STAT_REG: GEN_CALL (Bit 11)

Definition at line 7715 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Msk   (0x20UL)

I2C I2C_RAW_INTR_STAT_REG: RD_REQ (Bitfield-Mask: 0x01)

Definition at line 7704 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Pos   (5UL)

I2C I2C_RAW_INTR_STAT_REG: RD_REQ (Bit 5)

Definition at line 7703 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Msk   (0x80UL)

I2C I2C_RAW_INTR_STAT_REG: RX_DONE (Bitfield-Mask: 0x01)

Definition at line 7708 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Pos   (7UL)

I2C I2C_RAW_INTR_STAT_REG: RX_DONE (Bit 7)

Definition at line 7707 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Msk   (0x4UL)

I2C I2C_RAW_INTR_STAT_REG: RX_FULL (Bitfield-Mask: 0x01)

Definition at line 7698 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Pos   (2UL)

I2C I2C_RAW_INTR_STAT_REG: RX_FULL (Bit 2)

Definition at line 7697 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Msk   (0x2UL)

I2C I2C_RAW_INTR_STAT_REG: RX_OVER (Bitfield-Mask: 0x01)

Definition at line 7696 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Pos   (1UL)

I2C I2C_RAW_INTR_STAT_REG: RX_OVER (Bit 1)

Definition at line 7695 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Msk   (0x1UL)

I2C I2C_RAW_INTR_STAT_REG: RX_UNDER (Bitfield-Mask: 0x01)

Definition at line 7694 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Pos   (0UL)

I2C I2C_RAW_INTR_STAT_REG: RX_UNDER (Bit 0)

Definition at line 7693 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_START_DET_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Msk   (0x400UL)

I2C I2C_RAW_INTR_STAT_REG: START_DET (Bitfield-Mask: 0x01)

Definition at line 7714 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_START_DET_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Pos   (10UL)

I2C I2C_RAW_INTR_STAT_REG: START_DET (Bit 10)

Definition at line 7713 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Msk   (0x200UL)

I2C I2C_RAW_INTR_STAT_REG: STOP_DET (Bitfield-Mask: 0x01)

Definition at line 7712 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Pos   (9UL)

I2C I2C_RAW_INTR_STAT_REG: STOP_DET (Bit 9)

Definition at line 7711 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Msk   (0x40UL)

I2C I2C_RAW_INTR_STAT_REG: TX_ABRT (Bitfield-Mask: 0x01)

Definition at line 7706 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Pos   (6UL)

I2C I2C_RAW_INTR_STAT_REG: TX_ABRT (Bit 6)

Definition at line 7705 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Msk   (0x10UL)

I2C I2C_RAW_INTR_STAT_REG: TX_EMPTY (Bitfield-Mask: 0x01)

Definition at line 7702 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Pos   (4UL)

I2C I2C_RAW_INTR_STAT_REG: TX_EMPTY (Bit 4)

Definition at line 7701 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Msk   (0x8UL)

I2C I2C_RAW_INTR_STAT_REG: TX_OVER (Bitfield-Mask: 0x01)

Definition at line 7700 of file DA14680BA.h.

◆ I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Pos   (3UL)

I2C I2C_RAW_INTR_STAT_REG: TX_OVER (Bit 3)

Definition at line 7699 of file DA14680BA.h.

◆ I2C_I2C_RX_TL_REG_RX_TL_Msk

#define I2C_I2C_RX_TL_REG_RX_TL_Msk   (0x1fUL)

I2C I2C_RX_TL_REG: RX_TL (Bitfield-Mask: 0x1f)

Definition at line 7720 of file DA14680BA.h.

◆ I2C_I2C_RX_TL_REG_RX_TL_Pos

#define I2C_I2C_RX_TL_REG_RX_TL_Pos   (0UL)

I2C I2C_RX_TL_REG: RX_TL (Bit 0)

Definition at line 7719 of file DA14680BA.h.

◆ I2C_I2C_RXFLR_REG_RXFLR_Msk

#define I2C_I2C_RXFLR_REG_RXFLR_Msk   (0x3fUL)

I2C I2C_RXFLR_REG: RXFLR (Bitfield-Mask: 0x3f)

Definition at line 7796 of file DA14680BA.h.

◆ I2C_I2C_RXFLR_REG_RXFLR_Pos

#define I2C_I2C_RXFLR_REG_RXFLR_Pos   (0UL)

I2C I2C_RXFLR_REG: RXFLR (Bit 0)

Definition at line 7795 of file DA14680BA.h.

◆ I2C_I2C_SAR_REG_IC_SAR_Msk

#define I2C_I2C_SAR_REG_IC_SAR_Msk   (0x3ffUL)

I2C I2C_SAR_REG: IC_SAR (Bitfield-Mask: 0x3ff)

Definition at line 7612 of file DA14680BA.h.

◆ I2C_I2C_SAR_REG_IC_SAR_Pos

#define I2C_I2C_SAR_REG_IC_SAR_Pos   (0UL)

I2C I2C_SAR_REG: IC_SAR (Bit 0)

Definition at line 7611 of file DA14680BA.h.

◆ I2C_I2C_SDA_HOLD_REG_IC_SDA_HOLD_Msk

#define I2C_I2C_SDA_HOLD_REG_IC_SDA_HOLD_Msk   (0xffffUL)

I2C I2C_SDA_HOLD_REG: IC_SDA_HOLD (Bitfield-Mask: 0xffff)

Definition at line 7800 of file DA14680BA.h.

◆ I2C_I2C_SDA_HOLD_REG_IC_SDA_HOLD_Pos

#define I2C_I2C_SDA_HOLD_REG_IC_SDA_HOLD_Pos   (0UL)

I2C I2C_SDA_HOLD_REG: IC_SDA_HOLD (Bit 0)

Definition at line 7799 of file DA14680BA.h.

◆ I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Msk

#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Msk   (0xffUL)

I2C I2C_SDA_SETUP_REG: SDA_SETUP (Bitfield-Mask: 0xff)

Definition at line 7852 of file DA14680BA.h.

◆ I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Pos

#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Pos   (0UL)

I2C I2C_SDA_SETUP_REG: SDA_SETUP (Bit 0)

Definition at line 7851 of file DA14680BA.h.

◆ I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk

#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk   (0xffffUL)

I2C I2C_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff)

Definition at line 7626 of file DA14680BA.h.

◆ I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos

#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos   (0UL)

I2C I2C_SS_SCL_HCNT_REG: IC_SS_SCL_HCNT (Bit 0)

Definition at line 7625 of file DA14680BA.h.

◆ I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk

#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk   (0xffffUL)

I2C I2C_SS_SCL_LCNT_REG: IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff)

Definition at line 7630 of file DA14680BA.h.

◆ I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos

#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos   (0UL)

I2C I2C_SS_SCL_LCNT_REG: IC_SS_SCL_LCNT (Bit 0)

Definition at line 7629 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk

#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk   (0x1UL)

I2C I2C_STATUS_REG: I2C_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 7776 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_I2C_ACTIVITY_Pos

#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Pos   (0UL)

I2C I2C_STATUS_REG: I2C_ACTIVITY (Bit 0)

Definition at line 7775 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_MST_ACTIVITY_Msk

#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Msk   (0x20UL)

I2C I2C_STATUS_REG: MST_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 7786 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_MST_ACTIVITY_Pos

#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Pos   (5UL)

I2C I2C_STATUS_REG: MST_ACTIVITY (Bit 5)

Definition at line 7785 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_RFF_Msk

#define I2C_I2C_STATUS_REG_RFF_Msk   (0x10UL)

I2C I2C_STATUS_REG: RFF (Bitfield-Mask: 0x01)

Definition at line 7784 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_RFF_Pos

#define I2C_I2C_STATUS_REG_RFF_Pos   (4UL)

I2C I2C_STATUS_REG: RFF (Bit 4)

Definition at line 7783 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_RFNE_Msk

#define I2C_I2C_STATUS_REG_RFNE_Msk   (0x8UL)

I2C I2C_STATUS_REG: RFNE (Bitfield-Mask: 0x01)

Definition at line 7782 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_RFNE_Pos

#define I2C_I2C_STATUS_REG_RFNE_Pos   (3UL)

I2C I2C_STATUS_REG: RFNE (Bit 3)

Definition at line 7781 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_SLV_ACTIVITY_Msk

#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Msk   (0x40UL)

I2C I2C_STATUS_REG: SLV_ACTIVITY (Bitfield-Mask: 0x01)

Definition at line 7788 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_SLV_ACTIVITY_Pos

#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Pos   (6UL)

I2C I2C_STATUS_REG: SLV_ACTIVITY (Bit 6)

Definition at line 7787 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_TFE_Msk

#define I2C_I2C_STATUS_REG_TFE_Msk   (0x4UL)

I2C I2C_STATUS_REG: TFE (Bitfield-Mask: 0x01)

Definition at line 7780 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_TFE_Pos

#define I2C_I2C_STATUS_REG_TFE_Pos   (2UL)

I2C I2C_STATUS_REG: TFE (Bit 2)

Definition at line 7779 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_TFNF_Msk

#define I2C_I2C_STATUS_REG_TFNF_Msk   (0x2UL)

I2C I2C_STATUS_REG: TFNF (Bitfield-Mask: 0x01)

Definition at line 7778 of file DA14680BA.h.

◆ I2C_I2C_STATUS_REG_TFNF_Pos

#define I2C_I2C_STATUS_REG_TFNF_Pos   (1UL)

I2C I2C_STATUS_REG: TFNF (Bit 1)

Definition at line 7777 of file DA14680BA.h.

◆ I2C_I2C_TAR_REG_GC_OR_START_Msk

#define I2C_I2C_TAR_REG_GC_OR_START_Msk   (0x400UL)

I2C I2C_TAR_REG: GC_OR_START (Bitfield-Mask: 0x01)

Definition at line 7606 of file DA14680BA.h.

◆ I2C_I2C_TAR_REG_GC_OR_START_Pos

#define I2C_I2C_TAR_REG_GC_OR_START_Pos   (10UL)

I2C I2C_TAR_REG: GC_OR_START (Bit 10)

Definition at line 7605 of file DA14680BA.h.

◆ I2C_I2C_TAR_REG_IC_TAR_Msk

#define I2C_I2C_TAR_REG_IC_TAR_Msk   (0x3ffUL)

I2C I2C_TAR_REG: IC_TAR (Bitfield-Mask: 0x3ff)

Definition at line 7604 of file DA14680BA.h.

◆ I2C_I2C_TAR_REG_IC_TAR_Pos

#define I2C_I2C_TAR_REG_IC_TAR_Pos   (0UL)

I2C I2C_TAR_REG: IC_TAR (Bit 0)

Definition at line 7603 of file DA14680BA.h.

◆ I2C_I2C_TAR_REG_SPECIAL_Msk

#define I2C_I2C_TAR_REG_SPECIAL_Msk   (0x800UL)

I2C I2C_TAR_REG: SPECIAL (Bitfield-Mask: 0x01)

Definition at line 7608 of file DA14680BA.h.

◆ I2C_I2C_TAR_REG_SPECIAL_Pos

#define I2C_I2C_TAR_REG_SPECIAL_Pos   (11UL)

I2C I2C_TAR_REG: SPECIAL (Bit 11)

Definition at line 7607 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk   (0x2UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01)

Definition at line 7806 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos   (1UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10ADDR1_NOACK (Bit 1)

Definition at line 7805 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk   (0x4UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01)

Definition at line 7808 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos   (2UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10ADDR2_NOACK (Bit 2)

Definition at line 7807 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk   (0x400UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01)

Definition at line 7824 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos   (10UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_10B_RD_NORSTRT (Bit 10)

Definition at line 7823 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk   (0x1UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01)

Definition at line 7804 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos   (0UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_7B_ADDR_NOACK (Bit 0)

Definition at line 7803 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk   (0x10UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_GCALL_NOACK (Bitfield-Mask: 0x01)

Definition at line 7812 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos   (4UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_GCALL_NOACK (Bit 4)

Definition at line 7811 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk   (0x20UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_GCALL_READ (Bitfield-Mask: 0x01)

Definition at line 7814 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos   (5UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_GCALL_READ (Bit 5)

Definition at line 7813 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk   (0x40UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_HS_ACKDET (Bitfield-Mask: 0x01)

Definition at line 7816 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos   (6UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_HS_ACKDET (Bit 6)

Definition at line 7815 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk   (0x100UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_HS_NORSTRT (Bitfield-Mask: 0x01)

Definition at line 7820 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos   (8UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_HS_NORSTRT (Bit 8)

Definition at line 7819 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk   (0x800UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_MASTER_DIS (Bitfield-Mask: 0x01)

Definition at line 7826 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos   (11UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_MASTER_DIS (Bit 11)

Definition at line 7825 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk   (0x80UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01)

Definition at line 7818 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos   (7UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SBYTE_ACKDET (Bit 7)

Definition at line 7817 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk   (0x200UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01)

Definition at line 7822 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos   (9UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SBYTE_NORSTRT (Bit 9)

Definition at line 7821 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk   (0x4000UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01)

Definition at line 7832 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos   (14UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLV_ARBLOST (Bit 14)

Definition at line 7831 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk   (0x2000UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01)

Definition at line 7830 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos   (13UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLVFLUSH_TXFIFO (Bit 13)

Definition at line 7829 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk   (0x8000UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLVRD_INTX (Bitfield-Mask: 0x01)

Definition at line 7834 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos   (15UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_SLVRD_INTX (Bit 15)

Definition at line 7833 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk   (0x8UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01)

Definition at line 7810 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos   (3UL)

I2C I2C_TX_ABRT_SOURCE_REG: ABRT_TXDATA_NOACK (Bit 3)

Definition at line 7809 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk   (0x1000UL)

I2C I2C_TX_ABRT_SOURCE_REG: ARB_LOST (Bitfield-Mask: 0x01)

Definition at line 7828 of file DA14680BA.h.

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Pos   (12UL)

I2C I2C_TX_ABRT_SOURCE_REG: ARB_LOST (Bit 12)

Definition at line 7827 of file DA14680BA.h.

◆ I2C_I2C_TX_TL_REG_TX_TL_Msk

#define I2C_I2C_TX_TL_REG_TX_TL_Msk   (0x1fUL)

I2C I2C_TX_TL_REG: TX_TL (Bitfield-Mask: 0x1f)

Definition at line 7724 of file DA14680BA.h.

◆ I2C_I2C_TX_TL_REG_TX_TL_Pos

#define I2C_I2C_TX_TL_REG_TX_TL_Pos   (0UL)

I2C I2C_TX_TL_REG: TX_TL (Bit 0)

Definition at line 7723 of file DA14680BA.h.

◆ I2C_I2C_TXFLR_REG_TXFLR_Msk

#define I2C_I2C_TXFLR_REG_TXFLR_Msk   (0x3fUL)

I2C I2C_TXFLR_REG: TXFLR (Bitfield-Mask: 0x3f)

Definition at line 7792 of file DA14680BA.h.

◆ I2C_I2C_TXFLR_REG_TXFLR_Pos

#define I2C_I2C_TXFLR_REG_TXFLR_Pos   (0UL)

I2C I2C_TXFLR_REG: TXFLR (Bit 0)

Definition at line 7791 of file DA14680BA.h.

◆ IR

#define IR   ((IR_Type *) IR_BASE)

Definition at line 12093 of file DA14680BA.h.

◆ IR_BASE

#define IR_BASE   0x50001700UL

Definition at line 12048 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_CODE_FIFO_RESET_Msk

#define IR_IR_CTRL_REG_IR_CODE_FIFO_RESET_Msk   (0x1UL)

IR IR_CTRL_REG: IR_CODE_FIFO_RESET (Bitfield-Mask: 0x01)

Definition at line 8234 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_CODE_FIFO_RESET_Pos

#define IR_IR_CTRL_REG_IR_CODE_FIFO_RESET_Pos   (0UL)

IR IR_CTRL_REG: IR_CODE_FIFO_RESET (Bit 0)

Definition at line 8233 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_ENABLE_Msk

#define IR_IR_CTRL_REG_IR_ENABLE_Msk   (0x4UL)

IR IR_CTRL_REG: IR_ENABLE (Bitfield-Mask: 0x01)

Definition at line 8238 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_ENABLE_Pos

#define IR_IR_CTRL_REG_IR_ENABLE_Pos   (2UL)

IR IR_CTRL_REG: IR_ENABLE (Bit 2)

Definition at line 8237 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_INVERT_OUTPUT_Msk

#define IR_IR_CTRL_REG_IR_INVERT_OUTPUT_Msk   (0x20UL)

IR IR_CTRL_REG: IR_INVERT_OUTPUT (Bitfield-Mask: 0x01)

Definition at line 8244 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_INVERT_OUTPUT_Pos

#define IR_IR_CTRL_REG_IR_INVERT_OUTPUT_Pos   (5UL)

IR IR_CTRL_REG: IR_INVERT_OUTPUT (Bit 5)

Definition at line 8243 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_IRQ_EN_Msk

#define IR_IR_CTRL_REG_IR_IRQ_EN_Msk   (0x100UL)

IR IR_CTRL_REG: IR_IRQ_EN (Bitfield-Mask: 0x01)

Definition at line 8250 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_IRQ_EN_Pos

#define IR_IR_CTRL_REG_IR_IRQ_EN_Pos   (8UL)

IR IR_CTRL_REG: IR_IRQ_EN (Bit 8)

Definition at line 8249 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_LOGIC_ONE_FORMAT_Msk

#define IR_IR_CTRL_REG_IR_LOGIC_ONE_FORMAT_Msk   (0x80UL)

IR IR_CTRL_REG: IR_LOGIC_ONE_FORMAT (Bitfield-Mask: 0x01)

Definition at line 8248 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_LOGIC_ONE_FORMAT_Pos

#define IR_IR_CTRL_REG_IR_LOGIC_ONE_FORMAT_Pos   (7UL)

IR IR_CTRL_REG: IR_LOGIC_ONE_FORMAT (Bit 7)

Definition at line 8247 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_LOGIC_ZERO_FORMAT_Msk

#define IR_IR_CTRL_REG_IR_LOGIC_ZERO_FORMAT_Msk   (0x40UL)

IR IR_CTRL_REG: IR_LOGIC_ZERO_FORMAT (Bitfield-Mask: 0x01)

Definition at line 8246 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_LOGIC_ZERO_FORMAT_Pos

#define IR_IR_CTRL_REG_IR_LOGIC_ZERO_FORMAT_Pos   (6UL)

IR IR_CTRL_REG: IR_LOGIC_ZERO_FORMAT (Bit 6)

Definition at line 8245 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_REP_FIFO_RESET_Msk

#define IR_IR_CTRL_REG_IR_REP_FIFO_RESET_Msk   (0x2UL)

IR IR_CTRL_REG: IR_REP_FIFO_RESET (Bitfield-Mask: 0x01)

Definition at line 8236 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_REP_FIFO_RESET_Pos

#define IR_IR_CTRL_REG_IR_REP_FIFO_RESET_Pos   (1UL)

IR IR_CTRL_REG: IR_REP_FIFO_RESET (Bit 1)

Definition at line 8235 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_REPEAT_TYPE_Msk

#define IR_IR_CTRL_REG_IR_REPEAT_TYPE_Msk   (0x10UL)

IR IR_CTRL_REG: IR_REPEAT_TYPE (Bitfield-Mask: 0x01)

Definition at line 8242 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_REPEAT_TYPE_Pos

#define IR_IR_CTRL_REG_IR_REPEAT_TYPE_Pos   (4UL)

IR IR_CTRL_REG: IR_REPEAT_TYPE (Bit 4)

Definition at line 8241 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_TX_START_Msk

#define IR_IR_CTRL_REG_IR_TX_START_Msk   (0x8UL)

IR IR_CTRL_REG: IR_TX_START (Bitfield-Mask: 0x01)

Definition at line 8240 of file DA14680BA.h.

◆ IR_IR_CTRL_REG_IR_TX_START_Pos

#define IR_IR_CTRL_REG_IR_TX_START_Pos   (3UL)

IR IR_CTRL_REG: IR_TX_START (Bit 3)

Definition at line 8239 of file DA14680BA.h.

◆ IR_IR_FREQ_CARRIER_OFF_REG_IR_FREQ_CARRIER_OFF_Msk

#define IR_IR_FREQ_CARRIER_OFF_REG_IR_FREQ_CARRIER_OFF_Msk   (0x3ffUL)

IR IR_FREQ_CARRIER_OFF_REG: IR_FREQ_CARRIER_OFF (Bitfield-Mask: 0x3ff)

Definition at line 8218 of file DA14680BA.h.

◆ IR_IR_FREQ_CARRIER_OFF_REG_IR_FREQ_CARRIER_OFF_Pos

#define IR_IR_FREQ_CARRIER_OFF_REG_IR_FREQ_CARRIER_OFF_Pos   (0UL)

IR IR_FREQ_CARRIER_OFF_REG: IR_FREQ_CARRIER_OFF (Bit 0)

Definition at line 8217 of file DA14680BA.h.

◆ IR_IR_FREQ_CARRIER_ON_REG_IR_FREQ_CARRIER_ON_Msk

#define IR_IR_FREQ_CARRIER_ON_REG_IR_FREQ_CARRIER_ON_Msk   (0x3ffUL)

IR IR_FREQ_CARRIER_ON_REG: IR_FREQ_CARRIER_ON (Bitfield-Mask: 0x3ff)

Definition at line 8214 of file DA14680BA.h.

◆ IR_IR_FREQ_CARRIER_ON_REG_IR_FREQ_CARRIER_ON_Pos

#define IR_IR_FREQ_CARRIER_ON_REG_IR_FREQ_CARRIER_ON_Pos   (0UL)

IR IR_FREQ_CARRIER_ON_REG: IR_FREQ_CARRIER_ON (Bit 0)

Definition at line 8213 of file DA14680BA.h.

◆ IR_IR_IRQ_STATUS_REG_IR_IRQ_ACK_Msk

#define IR_IR_IRQ_STATUS_REG_IR_IRQ_ACK_Msk   (0x1UL)

IR IR_IRQ_STATUS_REG: IR_IRQ_ACK (Bitfield-Mask: 0x01)

Definition at line 8274 of file DA14680BA.h.

◆ IR_IR_IRQ_STATUS_REG_IR_IRQ_ACK_Pos

#define IR_IR_IRQ_STATUS_REG_IR_IRQ_ACK_Pos   (0UL)

IR IR_IRQ_STATUS_REG: IR_IRQ_ACK (Bit 0)

Definition at line 8273 of file DA14680BA.h.

◆ IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_MARK_Msk

#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_MARK_Msk   (0xff00UL)

IR IR_LOGIC_ONE_TIME_REG: IR_LOGIC_ONE_MARK (Bitfield-Mask: 0xff)

Definition at line 8224 of file DA14680BA.h.

◆ IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_MARK_Pos

#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_MARK_Pos   (8UL)

IR IR_LOGIC_ONE_TIME_REG: IR_LOGIC_ONE_MARK (Bit 8)

Definition at line 8223 of file DA14680BA.h.

◆ IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_SPACE_Msk

#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_SPACE_Msk   (0xffUL)

IR IR_LOGIC_ONE_TIME_REG: IR_LOGIC_ONE_SPACE (Bitfield-Mask: 0xff)

Definition at line 8222 of file DA14680BA.h.

◆ IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_SPACE_Pos

#define IR_IR_LOGIC_ONE_TIME_REG_IR_LOGIC_ONE_SPACE_Pos   (0UL)

IR IR_LOGIC_ONE_TIME_REG: IR_LOGIC_ONE_SPACE (Bit 0)

Definition at line 8221 of file DA14680BA.h.

◆ IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_MARK_Msk

#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_MARK_Msk   (0xff00UL)

IR IR_LOGIC_ZERO_TIME_REG: IR_LOGIC_ZERO_MARK (Bitfield-Mask: 0xff)

Definition at line 8230 of file DA14680BA.h.

◆ IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_MARK_Pos

#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_MARK_Pos   (8UL)

IR IR_LOGIC_ZERO_TIME_REG: IR_LOGIC_ZERO_MARK (Bit 8)

Definition at line 8229 of file DA14680BA.h.

◆ IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_SPACE_Msk

#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_SPACE_Msk   (0xffUL)

IR IR_LOGIC_ZERO_TIME_REG: IR_LOGIC_ZERO_SPACE (Bitfield-Mask: 0xff)

Definition at line 8228 of file DA14680BA.h.

◆ IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_SPACE_Pos

#define IR_IR_LOGIC_ZERO_TIME_REG_IR_LOGIC_ZERO_SPACE_Pos   (0UL)

IR IR_LOGIC_ZERO_TIME_REG: IR_LOGIC_ZERO_SPACE (Bit 0)

Definition at line 8227 of file DA14680BA.h.

◆ IR_IR_MAIN_FIFO_REG_IR_CODE_FIFO_DATA_Msk

#define IR_IR_MAIN_FIFO_REG_IR_CODE_FIFO_DATA_Msk   (0xffffUL)

IR IR_MAIN_FIFO_REG: IR_CODE_FIFO_DATA (Bitfield-Mask: 0xffff)

Definition at line 8266 of file DA14680BA.h.

◆ IR_IR_MAIN_FIFO_REG_IR_CODE_FIFO_DATA_Pos

#define IR_IR_MAIN_FIFO_REG_IR_CODE_FIFO_DATA_Pos   (0UL)

IR IR_MAIN_FIFO_REG: IR_CODE_FIFO_DATA (Bit 0)

Definition at line 8265 of file DA14680BA.h.

◆ IR_IR_REPEAT_FIFO_REG_IR_REPEAT_FIFO_DATA_Msk

#define IR_IR_REPEAT_FIFO_REG_IR_REPEAT_FIFO_DATA_Msk   (0xffffUL)

IR IR_REPEAT_FIFO_REG: IR_REPEAT_FIFO_DATA (Bitfield-Mask: 0xffff)

Definition at line 8270 of file DA14680BA.h.

◆ IR_IR_REPEAT_FIFO_REG_IR_REPEAT_FIFO_DATA_Pos

#define IR_IR_REPEAT_FIFO_REG_IR_REPEAT_FIFO_DATA_Pos   (0UL)

IR IR_REPEAT_FIFO_REG: IR_REPEAT_FIFO_DATA (Bit 0)

Definition at line 8269 of file DA14680BA.h.

◆ IR_IR_REPEAT_TIME_REG_IR_REPEAT_TIME_Msk

#define IR_IR_REPEAT_TIME_REG_IR_REPEAT_TIME_Msk   (0xffffUL)

IR IR_REPEAT_TIME_REG: IR_REPEAT_TIME (Bitfield-Mask: 0xffff)

Definition at line 8262 of file DA14680BA.h.

◆ IR_IR_REPEAT_TIME_REG_IR_REPEAT_TIME_Pos

#define IR_IR_REPEAT_TIME_REG_IR_REPEAT_TIME_Pos   (0UL)

IR IR_REPEAT_TIME_REG: IR_REPEAT_TIME (Bit 0)

Definition at line 8261 of file DA14680BA.h.

◆ IR_IR_STATUS_REG_IR_BUSY_Msk

#define IR_IR_STATUS_REG_IR_BUSY_Msk   (0x400UL)

IR IR_STATUS_REG: IR_BUSY (Bitfield-Mask: 0x01)

Definition at line 8258 of file DA14680BA.h.

◆ IR_IR_STATUS_REG_IR_BUSY_Pos

#define IR_IR_STATUS_REG_IR_BUSY_Pos   (10UL)

IR IR_STATUS_REG: IR_BUSY (Bit 10)

Definition at line 8257 of file DA14680BA.h.

◆ IR_IR_STATUS_REG_IR_CODE_FIFO_WRDS_Msk

#define IR_IR_STATUS_REG_IR_CODE_FIFO_WRDS_Msk   (0x3fUL)

IR IR_STATUS_REG: IR_CODE_FIFO_WRDS (Bitfield-Mask: 0x3f)

Definition at line 8254 of file DA14680BA.h.

◆ IR_IR_STATUS_REG_IR_CODE_FIFO_WRDS_Pos

#define IR_IR_STATUS_REG_IR_CODE_FIFO_WRDS_Pos   (0UL)

IR IR_STATUS_REG: IR_CODE_FIFO_WRDS (Bit 0)

Definition at line 8253 of file DA14680BA.h.

◆ IR_IR_STATUS_REG_IR_REP_FIFO_WRDS_Msk

#define IR_IR_STATUS_REG_IR_REP_FIFO_WRDS_Msk   (0x3c0UL)

IR IR_STATUS_REG: IR_REP_FIFO_WRDS (Bitfield-Mask: 0x0f)

Definition at line 8256 of file DA14680BA.h.

◆ IR_IR_STATUS_REG_IR_REP_FIFO_WRDS_Pos

#define IR_IR_STATUS_REG_IR_REP_FIFO_WRDS_Pos   (6UL)

IR IR_STATUS_REG: IR_REP_FIFO_WRDS (Bit 6)

Definition at line 8255 of file DA14680BA.h.

◆ KBSCAN

#define KBSCAN   ((KBSCAN_Type *) KBSCAN_BASE)

Definition at line 12094 of file DA14680BA.h.

◆ KBSCAN_BASE

#define KBSCAN_BASE   0x50001600UL

Definition at line 12049 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL2_REG_KBSCN_ROW_ACTIVE_TIME_Msk

#define KBSCAN_KBSCN_CTRL2_REG_KBSCN_ROW_ACTIVE_TIME_Msk   (0xffffUL)

KBSCAN KBSCN_CTRL2_REG: KBSCN_ROW_ACTIVE_TIME (Bitfield-Mask: 0xffff)

Definition at line 8302 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL2_REG_KBSCN_ROW_ACTIVE_TIME_Pos

#define KBSCAN_KBSCN_CTRL2_REG_KBSCN_ROW_ACTIVE_TIME_Pos   (0UL)

KBSCAN KBSCN_CTRL2_REG: KBSCN_ROW_ACTIVE_TIME (Bit 0)

Definition at line 8301 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_CLKDIV_Msk

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_CLKDIV_Msk   (0x3000UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_CLKDIV (Bitfield-Mask: 0x03)

Definition at line 8296 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_CLKDIV_Pos

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_CLKDIV_Pos   (12UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_CLKDIV (Bit 12)

Definition at line 8295 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_EN_Msk

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_EN_Msk   (0x1UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_EN (Bitfield-Mask: 0x01)

Definition at line 8284 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_EN_Pos

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_EN_Pos   (0UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_EN (Bit 0)

Definition at line 8283 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_EN_Msk

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_EN_Msk   (0x800UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_INACTIVE_EN (Bitfield-Mask: 0x01)

Definition at line 8294 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_EN_Pos

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_EN_Pos   (11UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_INACTIVE_EN (Bit 11)

Definition at line 8293 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_TIME_Msk

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_TIME_Msk   (0x7f0UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_INACTIVE_TIME (Bitfield-Mask: 0x7f)

Definition at line 8292 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_TIME_Pos

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_INACTIVE_TIME_Pos   (4UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_INACTIVE_TIME (Bit 4)

Definition at line 8291 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_FIFO_MASK_Msk

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_FIFO_MASK_Msk   (0x8UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_FIFO_MASK (Bitfield-Mask: 0x01)

Definition at line 8290 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_FIFO_MASK_Pos

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_FIFO_MASK_Pos   (3UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_FIFO_MASK (Bit 3)

Definition at line 8289 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_INACTIVE_MASK_Msk

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_INACTIVE_MASK_Msk   (0x4UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_INACTIVE_MASK (Bitfield-Mask: 0x01)

Definition at line 8288 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_INACTIVE_MASK_Pos

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_INACTIVE_MASK_Pos   (2UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_INACTIVE_MASK (Bit 2)

Definition at line 8287 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_MESSAGE_MASK_Msk

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_MESSAGE_MASK_Msk   (0x2UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_MESSAGE_MASK (Bitfield-Mask: 0x01)

Definition at line 8286 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_MESSAGE_MASK_Pos

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_IRQ_MESSAGE_MASK_Pos   (1UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_IRQ_MESSAGE_MASK (Bit 1)

Definition at line 8285 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_RESET_FIFO_Msk

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_RESET_FIFO_Msk   (0x4000UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_RESET_FIFO (Bitfield-Mask: 0x01)

Definition at line 8298 of file DA14680BA.h.

◆ KBSCAN_KBSCN_CTRL_REG_KBSCN_RESET_FIFO_Pos

#define KBSCAN_KBSCN_CTRL_REG_KBSCN_RESET_FIFO_Pos   (14UL)

KBSCAN KBSCN_CTRL_REG: KBSCN_RESET_FIFO (Bit 14)

Definition at line 8297 of file DA14680BA.h.

◆ KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_PRESS_TIME_Msk

#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_PRESS_TIME_Msk   (0xfc0UL)

KBSCAN KBSCN_DEBOUNCE_REG: KBSCN_DEBOUNCE_PRESS_TIME (Bitfield-Mask: 0x3f)

Definition at line 8314 of file DA14680BA.h.

◆ KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_PRESS_TIME_Pos

#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_PRESS_TIME_Pos   (6UL)

KBSCAN KBSCN_DEBOUNCE_REG: KBSCN_DEBOUNCE_PRESS_TIME (Bit 6)

Definition at line 8313 of file DA14680BA.h.

◆ KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_RELEASE_TIME_Msk

#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_RELEASE_TIME_Msk   (0x3fUL)

KBSCAN KBSCN_DEBOUNCE_REG: KBSCN_DEBOUNCE_RELEASE_TIME (Bitfield-Mask: 0x3f)

Definition at line 8312 of file DA14680BA.h.

◆ KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_RELEASE_TIME_Pos

#define KBSCAN_KBSCN_DEBOUNCE_REG_KBSCN_DEBOUNCE_RELEASE_TIME_Pos   (0UL)

KBSCAN KBSCN_DEBOUNCE_REG: KBSCN_DEBOUNCE_RELEASE_TIME (Bit 0)

Definition at line 8311 of file DA14680BA.h.

◆ KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_COLUMN_Msk

#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_COLUMN_Msk   (0x1f0UL)

KBSCAN KBSCN_MATRIX_SIZE_REG: KBSCN_MATRIX_COLUMN (Bitfield-Mask: 0x1f)

Definition at line 8308 of file DA14680BA.h.

◆ KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_COLUMN_Pos

#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_COLUMN_Pos   (4UL)

KBSCAN KBSCN_MATRIX_SIZE_REG: KBSCN_MATRIX_COLUMN (Bit 4)

Definition at line 8307 of file DA14680BA.h.

◆ KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_ROW_Msk

#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_ROW_Msk   (0xfUL)

KBSCAN KBSCN_MATRIX_SIZE_REG: KBSCN_MATRIX_ROW (Bitfield-Mask: 0x0f)

Definition at line 8306 of file DA14680BA.h.

◆ KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_ROW_Pos

#define KBSCAN_KBSCN_MATRIX_SIZE_REG_KBSCN_MATRIX_ROW_Pos   (0UL)

KBSCAN KBSCN_MATRIX_SIZE_REG: KBSCN_MATRIX_ROW (Bit 0)

Definition at line 8305 of file DA14680BA.h.

◆ KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEY_STATE_Msk

#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEY_STATE_Msk   (0x200UL)

KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEY_STATE (Bitfield-Mask: 0x01)

Definition at line 8334 of file DA14680BA.h.

◆ KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEY_STATE_Pos

#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEY_STATE_Pos   (9UL)

KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEY_STATE (Bit 9)

Definition at line 8333 of file DA14680BA.h.

◆ KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_COLUMN_Msk

#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_COLUMN_Msk   (0x1f0UL)

KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEYID_COLUMN (Bitfield-Mask: 0x1f)

Definition at line 8332 of file DA14680BA.h.

◆ KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_COLUMN_Pos

#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_COLUMN_Pos   (4UL)

KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEYID_COLUMN (Bit 4)

Definition at line 8331 of file DA14680BA.h.

◆ KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_ROW_Msk

#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_ROW_Msk   (0xfUL)

KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEYID_ROW (Bitfield-Mask: 0x0f)

Definition at line 8330 of file DA14680BA.h.

◆ KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_ROW_Pos

#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_KEYID_ROW_Pos   (0UL)

KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_KEYID_ROW (Bit 0)

Definition at line 8329 of file DA14680BA.h.

◆ KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_LAST_ENTRY_Msk

#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_LAST_ENTRY_Msk   (0x400UL)

KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_LAST_ENTRY (Bitfield-Mask: 0x01)

Definition at line 8336 of file DA14680BA.h.

◆ KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_LAST_ENTRY_Pos

#define KBSCAN_KBSCN_MESSAGE_KEY_REG_KBSCN_LAST_ENTRY_Pos   (10UL)

KBSCAN KBSCN_MESSAGE_KEY_REG: KBSCN_LAST_ENTRY (Bit 10)

Definition at line 8335 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P00_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P00_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8344 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P00_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P00_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8343 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P00_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P00_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8340 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P00_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P00_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8339 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P00_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P00_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8342 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P00_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P00_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P00_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8341 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P01_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P01_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8352 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P01_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P01_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8351 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P01_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P01_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8348 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P01_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P01_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8347 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P01_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P01_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8350 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P01_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P01_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P01_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8349 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P02_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P02_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8360 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P02_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P02_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8359 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P02_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P02_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8356 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P02_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P02_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8355 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P02_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P02_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8358 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P02_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P02_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P02_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8357 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P03_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P03_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8368 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P03_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P03_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8367 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P03_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P03_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8364 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P03_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P03_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8363 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P03_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P03_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8366 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P03_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P03_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P03_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8365 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P04_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P04_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8376 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P04_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P04_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8375 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P04_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P04_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8372 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P04_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P04_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8371 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P04_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P04_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8374 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P04_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P04_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P04_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8373 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P05_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P05_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8384 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P05_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P05_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8383 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P05_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P05_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8380 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P05_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P05_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8379 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P05_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P05_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8382 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P05_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P05_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P05_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8381 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P06_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P06_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8392 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P06_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P06_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8391 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P06_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P06_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8388 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P06_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P06_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8387 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P06_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P06_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8390 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P06_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P06_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P06_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8389 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P07_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P07_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8400 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P07_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P07_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8399 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P07_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P07_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8396 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P07_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P07_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8395 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P07_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P07_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8398 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P07_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P07_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P07_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8397 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P10_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P10_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8408 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P10_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P10_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8407 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P10_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P10_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8404 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P10_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P10_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8403 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P10_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P10_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8406 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P10_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P10_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P10_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8405 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P11_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P11_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8416 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P11_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P11_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8415 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P11_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P11_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8412 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P11_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P11_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8411 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P11_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P11_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8414 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P11_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P11_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P11_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8413 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P12_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P12_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8424 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P12_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P12_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8423 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P12_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P12_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8420 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P12_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P12_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8419 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P12_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P12_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8422 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P12_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P12_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P12_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8421 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P13_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P13_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8432 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P13_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P13_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8431 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P13_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P13_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8428 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P13_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P13_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8427 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P13_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P13_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8430 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P13_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P13_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P13_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8429 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P14_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P14_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8440 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P14_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P14_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8439 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P14_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P14_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8436 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P14_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P14_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8435 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P14_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P14_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8438 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P14_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P14_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P14_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8437 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P15_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P15_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8448 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P15_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P15_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8447 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P15_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P15_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8444 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P15_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P15_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8443 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P15_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P15_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8446 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P15_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P15_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P15_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8445 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P16_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P16_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8456 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P16_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P16_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8455 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P16_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P16_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8452 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P16_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P16_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8451 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P16_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P16_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8454 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P16_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P16_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P16_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8453 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P17_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P17_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8464 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P17_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P17_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8463 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P17_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P17_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8460 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P17_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P17_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8459 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P17_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P17_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8462 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P17_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P17_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P17_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8461 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P20_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P20_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8472 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P20_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P20_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8471 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P20_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P20_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8468 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P20_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P20_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8467 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P20_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P20_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8470 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P20_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P20_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P20_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8469 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P21_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P21_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8480 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P21_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P21_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8479 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P21_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P21_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8476 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P21_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P21_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8475 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P21_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P21_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8478 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P21_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P21_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P21_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8477 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P22_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P22_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8488 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P22_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P22_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8487 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P22_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P22_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8484 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P22_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P22_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8483 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P22_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P22_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8486 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P22_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P22_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P22_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8485 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P23_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P23_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8496 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P23_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P23_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8495 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P23_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P23_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8492 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P23_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P23_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8491 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P23_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P23_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8494 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P23_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P23_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P23_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8493 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P24_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P24_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8504 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P24_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P24_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8503 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P24_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P24_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8500 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P24_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P24_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8499 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P24_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P24_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8502 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P24_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P24_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P24_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8501 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P30_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P30_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8512 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P30_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P30_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8511 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P30_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P30_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8508 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P30_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P30_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8507 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P30_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P30_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8510 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P30_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P30_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P30_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8509 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P31_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P31_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8520 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P31_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P31_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8519 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P31_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P31_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8516 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P31_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P31_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8515 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P31_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P31_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8518 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P31_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P31_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P31_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8517 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P32_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P32_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8528 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P32_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P32_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8527 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P32_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P32_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8524 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P32_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P32_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8523 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P32_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P32_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8526 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P32_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P32_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P32_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8525 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P33_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P33_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8536 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P33_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P33_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8535 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P33_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P33_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8532 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P33_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P33_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8531 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P33_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P33_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8534 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P33_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P33_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P33_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8533 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P34_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P34_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8544 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P34_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P34_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8543 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P34_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P34_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8540 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P34_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P34_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8539 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P34_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P34_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8542 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P34_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P34_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P34_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8541 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P35_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P35_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8552 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P35_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P35_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8551 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P35_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P35_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8548 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P35_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P35_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8547 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P35_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P35_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8550 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P35_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P35_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P35_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8549 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P36_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P36_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8560 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P36_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P36_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8559 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P36_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P36_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8556 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P36_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P36_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8555 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P36_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P36_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8558 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P36_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P36_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P36_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8557 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P37_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P37_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8568 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P37_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P37_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8567 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P37_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P37_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8564 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P37_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P37_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8563 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P37_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P37_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8566 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P37_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P37_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P37_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8565 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P40_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P40_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8576 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P40_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P40_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8575 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P40_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P40_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8572 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P40_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P40_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8571 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P40_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P40_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8574 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P40_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P40_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P40_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8573 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P41_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P41_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8584 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P41_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P41_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8583 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P41_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P41_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8580 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P41_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P41_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8579 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P41_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P41_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8582 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P41_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P41_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P41_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8581 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P42_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P42_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8592 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P42_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P42_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8591 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P42_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P42_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8588 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P42_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P42_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8587 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P42_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P42_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8590 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P42_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P42_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P42_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8589 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P43_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P43_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8600 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P43_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P43_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8599 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P43_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P43_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8596 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P43_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P43_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8595 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P43_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P43_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8598 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P43_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P43_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P43_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8597 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P44_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P44_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8608 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P44_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P44_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8607 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P44_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P44_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8604 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P44_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P44_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8603 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P44_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P44_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8606 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P44_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P44_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P44_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8605 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P45_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P45_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8616 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P45_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P45_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8615 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P45_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P45_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8612 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P45_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P45_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8611 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P45_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P45_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8614 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P45_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P45_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P45_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8613 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P46_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P46_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8624 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P46_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P46_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8623 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P46_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P46_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8620 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P46_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P46_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8619 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P46_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P46_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8622 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P46_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P46_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P46_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8621 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P47_MODE_REG_KBSCN_GPIO_EN_Msk

#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_GPIO_EN_Msk   (0x40UL)

KBSCAN KBSCN_P47_MODE_REG: KBSCN_GPIO_EN (Bitfield-Mask: 0x01)

Definition at line 8632 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P47_MODE_REG_KBSCN_GPIO_EN_Pos

#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_GPIO_EN_Pos   (6UL)

KBSCAN KBSCN_P47_MODE_REG: KBSCN_GPIO_EN (Bit 6)

Definition at line 8631 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P47_MODE_REG_KBSCN_MODE_Msk

#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_MODE_Msk   (0x1fUL)

KBSCAN KBSCN_P47_MODE_REG: KBSCN_MODE (Bitfield-Mask: 0x1f)

Definition at line 8628 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P47_MODE_REG_KBSCN_MODE_Pos

#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_MODE_Pos   (0UL)

KBSCAN KBSCN_P47_MODE_REG: KBSCN_MODE (Bit 0)

Definition at line 8627 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P47_MODE_REG_KBSCN_ROW_Msk

#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_ROW_Msk   (0x20UL)

KBSCAN KBSCN_P47_MODE_REG: KBSCN_ROW (Bitfield-Mask: 0x01)

Definition at line 8630 of file DA14680BA.h.

◆ KBSCAN_KBSCN_P47_MODE_REG_KBSCN_ROW_Pos

#define KBSCAN_KBSCN_P47_MODE_REG_KBSCN_ROW_Pos   (5UL)

KBSCAN KBSCN_P47_MODE_REG: KBSCN_ROW (Bit 5)

Definition at line 8629 of file DA14680BA.h.

◆ KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_OVERFL_Msk

#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_OVERFL_Msk   (0x80UL)

KBSCAN KBSCN_STATUS_REG: KBSCN_FIFO_OVERFL (Bitfield-Mask: 0x01)

Definition at line 8324 of file DA14680BA.h.

◆ KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_OVERFL_Pos

#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_OVERFL_Pos   (7UL)

KBSCAN KBSCN_STATUS_REG: KBSCN_FIFO_OVERFL (Bit 7)

Definition at line 8323 of file DA14680BA.h.

◆ KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_UNDERFL_Msk

#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_UNDERFL_Msk   (0x100UL)

KBSCAN KBSCN_STATUS_REG: KBSCN_FIFO_UNDERFL (Bitfield-Mask: 0x01)

Definition at line 8326 of file DA14680BA.h.

◆ KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_UNDERFL_Pos

#define KBSCAN_KBSCN_STATUS_REG_KBSCN_FIFO_UNDERFL_Pos   (8UL)

KBSCAN KBSCN_STATUS_REG: KBSCN_FIFO_UNDERFL (Bit 8)

Definition at line 8325 of file DA14680BA.h.

◆ KBSCAN_KBSCN_STATUS_REG_KBSCN_INACTIVE_IRQ_STATUS_Msk

#define KBSCAN_KBSCN_STATUS_REG_KBSCN_INACTIVE_IRQ_STATUS_Msk   (0x2UL)

KBSCAN KBSCN_STATUS_REG: KBSCN_INACTIVE_IRQ_STATUS (Bitfield-Mask: 0x01)

Definition at line 8320 of file DA14680BA.h.

◆ KBSCAN_KBSCN_STATUS_REG_KBSCN_INACTIVE_IRQ_STATUS_Pos

#define KBSCAN_KBSCN_STATUS_REG_KBSCN_INACTIVE_IRQ_STATUS_Pos   (1UL)

KBSCAN KBSCN_STATUS_REG: KBSCN_INACTIVE_IRQ_STATUS (Bit 1)

Definition at line 8319 of file DA14680BA.h.

◆ KBSCAN_KBSCN_STATUS_REG_KBSCN_MES_IRQ_STATUS_Msk

#define KBSCAN_KBSCN_STATUS_REG_KBSCN_MES_IRQ_STATUS_Msk   (0x1UL)

KBSCAN KBSCN_STATUS_REG: KBSCN_MES_IRQ_STATUS (Bitfield-Mask: 0x01)

Definition at line 8318 of file DA14680BA.h.

◆ KBSCAN_KBSCN_STATUS_REG_KBSCN_MES_IRQ_STATUS_Pos

#define KBSCAN_KBSCN_STATUS_REG_KBSCN_MES_IRQ_STATUS_Pos   (0UL)

KBSCAN KBSCN_STATUS_REG: KBSCN_MES_IRQ_STATUS (Bit 0)

Definition at line 8317 of file DA14680BA.h.

◆ KBSCAN_KBSCN_STATUS_REG_KBSCN_NUM_MESSAGE_Msk

#define KBSCAN_KBSCN_STATUS_REG_KBSCN_NUM_MESSAGE_Msk   (0x7cUL)

KBSCAN KBSCN_STATUS_REG: KBSCN_NUM_MESSAGE (Bitfield-Mask: 0x1f)

Definition at line 8322 of file DA14680BA.h.

◆ KBSCAN_KBSCN_STATUS_REG_KBSCN_NUM_MESSAGE_Pos

#define KBSCAN_KBSCN_STATUS_REG_KBSCN_NUM_MESSAGE_Pos   (2UL)

KBSCAN KBSCN_STATUS_REG: KBSCN_NUM_MESSAGE (Bit 2)

Definition at line 8321 of file DA14680BA.h.

◆ NVIC_ICER_ADC_IRQn_Msk

#define NVIC_ICER_ADC_IRQn_Msk   (0x4000UL)

NVIC ICER: ADC_IRQn (Bitfield-Mask: 0x01)

Definition at line 2286 of file DA14680BA.h.

◆ NVIC_ICER_ADC_IRQn_Pos

#define NVIC_ICER_ADC_IRQn_Pos   (14UL)

NVIC ICER: ADC_IRQn (Bit 14)

Definition at line 2285 of file DA14680BA.h.

◆ NVIC_ICER_BLE_GEN_IRQn_Msk

#define NVIC_ICER_BLE_GEN_IRQn_Msk   (0x2UL)

NVIC ICER: BLE_GEN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2260 of file DA14680BA.h.

◆ NVIC_ICER_BLE_GEN_IRQn_Pos

#define NVIC_ICER_BLE_GEN_IRQn_Pos   (1UL)

NVIC ICER: BLE_GEN_IRQn (Bit 1)

Definition at line 2259 of file DA14680BA.h.

◆ NVIC_ICER_BLE_WAKEUP_LP_IRQn_Msk

#define NVIC_ICER_BLE_WAKEUP_LP_IRQn_Msk   (0x1UL)

NVIC ICER: BLE_WAKEUP_LP_IRQn (Bitfield-Mask: 0x01)

Definition at line 2258 of file DA14680BA.h.

◆ NVIC_ICER_BLE_WAKEUP_LP_IRQn_Pos

#define NVIC_ICER_BLE_WAKEUP_LP_IRQn_Pos   (0UL)

NVIC ICER: BLE_WAKEUP_LP_IRQn (Bit 0)

Definition at line 2257 of file DA14680BA.h.

◆ NVIC_ICER_COEX_IRQn_Msk

#define NVIC_ICER_COEX_IRQn_Msk   (0x20UL)

NVIC ICER: COEX_IRQn (Bitfield-Mask: 0x01)

Definition at line 2268 of file DA14680BA.h.

◆ NVIC_ICER_COEX_IRQn_Pos

#define NVIC_ICER_COEX_IRQn_Pos   (5UL)

NVIC ICER: COEX_IRQn (Bit 5)

Definition at line 2267 of file DA14680BA.h.

◆ NVIC_ICER_CRYPTO_IRQn_Msk

#define NVIC_ICER_CRYPTO_IRQn_Msk   (0x40UL)

NVIC ICER: CRYPTO_IRQn (Bitfield-Mask: 0x01)

Definition at line 2270 of file DA14680BA.h.

◆ NVIC_ICER_CRYPTO_IRQn_Pos

#define NVIC_ICER_CRYPTO_IRQn_Pos   (6UL)

NVIC ICER: CRYPTO_IRQn (Bit 6)

Definition at line 2269 of file DA14680BA.h.

◆ NVIC_ICER_DCDC_IRQn_Msk

#define NVIC_ICER_DCDC_IRQn_Msk   (0x20000000UL)

NVIC ICER: DCDC_IRQn (Bitfield-Mask: 0x01)

Definition at line 2316 of file DA14680BA.h.

◆ NVIC_ICER_DCDC_IRQn_Pos

#define NVIC_ICER_DCDC_IRQn_Pos   (29UL)

NVIC ICER: DCDC_IRQn (Bit 29)

Definition at line 2315 of file DA14680BA.h.

◆ NVIC_ICER_DMA_IRQn_Msk

#define NVIC_ICER_DMA_IRQn_Msk   (0x4000000UL)

NVIC ICER: DMA_IRQn (Bitfield-Mask: 0x01)

Definition at line 2310 of file DA14680BA.h.

◆ NVIC_ICER_DMA_IRQn_Pos

#define NVIC_ICER_DMA_IRQn_Pos   (26UL)

NVIC ICER: DMA_IRQn (Bit 26)

Definition at line 2309 of file DA14680BA.h.

◆ NVIC_ICER_FTDF_GEN_IRQn_Msk

#define NVIC_ICER_FTDF_GEN_IRQn_Msk   (0x8UL)

NVIC ICER: FTDF_GEN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2264 of file DA14680BA.h.

◆ NVIC_ICER_FTDF_GEN_IRQn_Pos

#define NVIC_ICER_FTDF_GEN_IRQn_Pos   (3UL)

NVIC ICER: FTDF_GEN_IRQn (Bit 3)

Definition at line 2263 of file DA14680BA.h.

◆ NVIC_ICER_FTDF_WAKEUP_IRQn_Msk

#define NVIC_ICER_FTDF_WAKEUP_IRQn_Msk   (0x4UL)

NVIC ICER: FTDF_WAKEUP_IRQn (Bitfield-Mask: 0x01)

Definition at line 2262 of file DA14680BA.h.

◆ NVIC_ICER_FTDF_WAKEUP_IRQn_Pos

#define NVIC_ICER_FTDF_WAKEUP_IRQn_Pos   (2UL)

NVIC ICER: FTDF_WAKEUP_IRQn (Bit 2)

Definition at line 2261 of file DA14680BA.h.

◆ NVIC_ICER_I2C2_IRQn_Msk

#define NVIC_ICER_I2C2_IRQn_Msk   (0x800UL)

NVIC ICER: I2C2_IRQn (Bitfield-Mask: 0x01)

Definition at line 2280 of file DA14680BA.h.

◆ NVIC_ICER_I2C2_IRQn_Pos

#define NVIC_ICER_I2C2_IRQn_Pos   (11UL)

NVIC ICER: I2C2_IRQn (Bit 11)

Definition at line 2279 of file DA14680BA.h.

◆ NVIC_ICER_I2C_IRQn_Msk

#define NVIC_ICER_I2C_IRQn_Msk   (0x400UL)

NVIC ICER: I2C_IRQn (Bitfield-Mask: 0x01)

Definition at line 2278 of file DA14680BA.h.

◆ NVIC_ICER_I2C_IRQn_Pos

#define NVIC_ICER_I2C_IRQn_Pos   (10UL)

NVIC ICER: I2C_IRQn (Bit 10)

Definition at line 2277 of file DA14680BA.h.

◆ NVIC_ICER_IRGEN_IRQn_Msk

#define NVIC_ICER_IRGEN_IRQn_Msk   (0x10000UL)

NVIC ICER: IRGEN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2290 of file DA14680BA.h.

◆ NVIC_ICER_IRGEN_IRQn_Pos

#define NVIC_ICER_IRGEN_IRQn_Pos   (16UL)

NVIC ICER: IRGEN_IRQn (Bit 16)

Definition at line 2289 of file DA14680BA.h.

◆ NVIC_ICER_KEYBRD_IRQn_Msk

#define NVIC_ICER_KEYBRD_IRQn_Msk   (0x8000UL)

NVIC ICER: KEYBRD_IRQn (Bitfield-Mask: 0x01)

Definition at line 2288 of file DA14680BA.h.

◆ NVIC_ICER_KEYBRD_IRQn_Pos

#define NVIC_ICER_KEYBRD_IRQn_Pos   (15UL)

NVIC ICER: KEYBRD_IRQn (Bit 15)

Definition at line 2287 of file DA14680BA.h.

◆ NVIC_ICER_MRM_IRQn_Msk

#define NVIC_ICER_MRM_IRQn_Msk   (0x80UL)

NVIC ICER: MRM_IRQn (Bitfield-Mask: 0x01)

Definition at line 2272 of file DA14680BA.h.

◆ NVIC_ICER_MRM_IRQn_Pos

#define NVIC_ICER_MRM_IRQn_Pos   (7UL)

NVIC ICER: MRM_IRQn (Bit 7)

Definition at line 2271 of file DA14680BA.h.

◆ NVIC_ICER_PCM_IRQn_Msk

#define NVIC_ICER_PCM_IRQn_Msk   (0x400000UL)

NVIC ICER: PCM_IRQn (Bitfield-Mask: 0x01)

Definition at line 2302 of file DA14680BA.h.

◆ NVIC_ICER_PCM_IRQn_Pos

#define NVIC_ICER_PCM_IRQn_Pos   (22UL)

NVIC ICER: PCM_IRQn (Bit 22)

Definition at line 2301 of file DA14680BA.h.

◆ NVIC_ICER_QUADEC_IRQn_Msk

#define NVIC_ICER_QUADEC_IRQn_Msk   (0x100000UL)

NVIC ICER: QUADEC_IRQn (Bitfield-Mask: 0x01)

Definition at line 2298 of file DA14680BA.h.

◆ NVIC_ICER_QUADEC_IRQn_Pos

#define NVIC_ICER_QUADEC_IRQn_Pos   (20UL)

NVIC ICER: QUADEC_IRQn (Bit 20)

Definition at line 2297 of file DA14680BA.h.

◆ NVIC_ICER_RF_DIAG_IRQn_Msk

#define NVIC_ICER_RF_DIAG_IRQn_Msk   (0x8000000UL)

NVIC ICER: RF_DIAG_IRQn (Bitfield-Mask: 0x01)

Definition at line 2312 of file DA14680BA.h.

◆ NVIC_ICER_RF_DIAG_IRQn_Pos

#define NVIC_ICER_RF_DIAG_IRQn_Pos   (27UL)

NVIC ICER: RF_DIAG_IRQn (Bit 27)

Definition at line 2311 of file DA14680BA.h.

◆ NVIC_ICER_RFCAL_IRQn_Msk

#define NVIC_ICER_RFCAL_IRQn_Msk   (0x10UL)

NVIC ICER: RFCAL_IRQn (Bitfield-Mask: 0x01)

Definition at line 2266 of file DA14680BA.h.

◆ NVIC_ICER_RFCAL_IRQn_Pos

#define NVIC_ICER_RFCAL_IRQn_Pos   (4UL)

NVIC ICER: RFCAL_IRQn (Bit 4)

Definition at line 2265 of file DA14680BA.h.

◆ NVIC_ICER_Rsvd__irq__n_Msk

#define NVIC_ICER_Rsvd__irq__n_Msk   (0x80000000UL)

NVIC ICER: Rsvd__irq__n (Bitfield-Mask: 0x01)

Definition at line 2320 of file DA14680BA.h.

◆ NVIC_ICER_Rsvd__irq__n_Pos

#define NVIC_ICER_Rsvd__irq__n_Pos   (31UL)

NVIC ICER: Rsvd__irq__n (Bit 31)

Definition at line 2319 of file DA14680BA.h.

◆ NVIC_ICER_SPI2_IRQn_Msk

#define NVIC_ICER_SPI2_IRQn_Msk   (0x2000UL)

NVIC ICER: SPI2_IRQn (Bitfield-Mask: 0x01)

Definition at line 2284 of file DA14680BA.h.

◆ NVIC_ICER_SPI2_IRQn_Pos

#define NVIC_ICER_SPI2_IRQn_Pos   (13UL)

NVIC ICER: SPI2_IRQn (Bit 13)

Definition at line 2283 of file DA14680BA.h.

◆ NVIC_ICER_SPI_IRQn_Msk

#define NVIC_ICER_SPI_IRQn_Msk   (0x1000UL)

NVIC ICER: SPI_IRQn (Bitfield-Mask: 0x01)

Definition at line 2282 of file DA14680BA.h.

◆ NVIC_ICER_SPI_IRQn_Pos

#define NVIC_ICER_SPI_IRQn_Pos   (12UL)

NVIC ICER: SPI_IRQn (Bit 12)

Definition at line 2281 of file DA14680BA.h.

◆ NVIC_ICER_SRC_IN_IRQn_Msk

#define NVIC_ICER_SRC_IN_IRQn_Msk   (0x800000UL)

NVIC ICER: SRC_IN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2304 of file DA14680BA.h.

◆ NVIC_ICER_SRC_IN_IRQn_Pos

#define NVIC_ICER_SRC_IN_IRQn_Pos   (23UL)

NVIC ICER: SRC_IN_IRQn (Bit 23)

Definition at line 2303 of file DA14680BA.h.

◆ NVIC_ICER_SRC_OUT_IRQn_Msk

#define NVIC_ICER_SRC_OUT_IRQn_Msk   (0x1000000UL)

NVIC ICER: SRC_OUT_IRQn (Bitfield-Mask: 0x01)

Definition at line 2306 of file DA14680BA.h.

◆ NVIC_ICER_SRC_OUT_IRQn_Pos

#define NVIC_ICER_SRC_OUT_IRQn_Pos   (24UL)

NVIC ICER: SRC_OUT_IRQn (Bit 24)

Definition at line 2305 of file DA14680BA.h.

◆ NVIC_ICER_SWTIM0_IRQn_Msk

#define NVIC_ICER_SWTIM0_IRQn_Msk   (0x40000UL)

NVIC ICER: SWTIM0_IRQn (Bitfield-Mask: 0x01)

Definition at line 2294 of file DA14680BA.h.

◆ NVIC_ICER_SWTIM0_IRQn_Pos

#define NVIC_ICER_SWTIM0_IRQn_Pos   (18UL)

NVIC ICER: SWTIM0_IRQn (Bit 18)

Definition at line 2293 of file DA14680BA.h.

◆ NVIC_ICER_SWTIM1_IRQn_Msk

#define NVIC_ICER_SWTIM1_IRQn_Msk   (0x80000UL)

NVIC ICER: SWTIM1_IRQn (Bitfield-Mask: 0x01)

Definition at line 2296 of file DA14680BA.h.

◆ NVIC_ICER_SWTIM1_IRQn_Pos

#define NVIC_ICER_SWTIM1_IRQn_Pos   (19UL)

NVIC ICER: SWTIM1_IRQn (Bit 19)

Definition at line 2295 of file DA14680BA.h.

◆ NVIC_ICER_TRNG_IRQn_Msk

#define NVIC_ICER_TRNG_IRQn_Msk   (0x10000000UL)

NVIC ICER: TRNG_IRQn (Bitfield-Mask: 0x01)

Definition at line 2314 of file DA14680BA.h.

◆ NVIC_ICER_TRNG_IRQn_Pos

#define NVIC_ICER_TRNG_IRQn_Pos   (28UL)

NVIC ICER: TRNG_IRQn (Bit 28)

Definition at line 2313 of file DA14680BA.h.

◆ NVIC_ICER_UART2_IRQn_Msk

#define NVIC_ICER_UART2_IRQn_Msk   (0x200UL)

NVIC ICER: UART2_IRQn (Bitfield-Mask: 0x01)

Definition at line 2276 of file DA14680BA.h.

◆ NVIC_ICER_UART2_IRQn_Pos

#define NVIC_ICER_UART2_IRQn_Pos   (9UL)

NVIC ICER: UART2_IRQn (Bit 9)

Definition at line 2275 of file DA14680BA.h.

◆ NVIC_ICER_UART_IRQn_Msk

#define NVIC_ICER_UART_IRQn_Msk   (0x100UL)

NVIC ICER: UART_IRQn (Bitfield-Mask: 0x01)

Definition at line 2274 of file DA14680BA.h.

◆ NVIC_ICER_UART_IRQn_Pos

#define NVIC_ICER_UART_IRQn_Pos   (8UL)

NVIC ICER: UART_IRQn (Bit 8)

Definition at line 2273 of file DA14680BA.h.

◆ NVIC_ICER_USB_IRQn_Msk

#define NVIC_ICER_USB_IRQn_Msk   (0x200000UL)

NVIC ICER: USB_IRQn (Bitfield-Mask: 0x01)

Definition at line 2300 of file DA14680BA.h.

◆ NVIC_ICER_USB_IRQn_Pos

#define NVIC_ICER_USB_IRQn_Pos   (21UL)

NVIC ICER: USB_IRQn (Bit 21)

Definition at line 2299 of file DA14680BA.h.

◆ NVIC_ICER_VBUS_IRQn_Msk

#define NVIC_ICER_VBUS_IRQn_Msk   (0x2000000UL)

NVIC ICER: VBUS_IRQn (Bitfield-Mask: 0x01)

Definition at line 2308 of file DA14680BA.h.

◆ NVIC_ICER_VBUS_IRQn_Pos

#define NVIC_ICER_VBUS_IRQn_Pos   (25UL)

NVIC ICER: VBUS_IRQn (Bit 25)

Definition at line 2307 of file DA14680BA.h.

◆ NVIC_ICER_WKUP_GPIO_IRQn_Msk

#define NVIC_ICER_WKUP_GPIO_IRQn_Msk   (0x20000UL)

NVIC ICER: WKUP_GPIO_IRQn (Bitfield-Mask: 0x01)

Definition at line 2292 of file DA14680BA.h.

◆ NVIC_ICER_WKUP_GPIO_IRQn_Pos

#define NVIC_ICER_WKUP_GPIO_IRQn_Pos   (17UL)

NVIC ICER: WKUP_GPIO_IRQn (Bit 17)

Definition at line 2291 of file DA14680BA.h.

◆ NVIC_ICER_XTAL16RDY_IRQn_Msk

#define NVIC_ICER_XTAL16RDY_IRQn_Msk   (0x40000000UL)

NVIC ICER: XTAL16RDY_IRQn (Bitfield-Mask: 0x01)

Definition at line 2318 of file DA14680BA.h.

◆ NVIC_ICER_XTAL16RDY_IRQn_Pos

#define NVIC_ICER_XTAL16RDY_IRQn_Pos   (30UL)

NVIC ICER: XTAL16RDY_IRQn (Bit 30)

Definition at line 2317 of file DA14680BA.h.

◆ NVIC_ICPR_ADC_IRQn_Msk

#define NVIC_ICPR_ADC_IRQn_Msk   (0x4000UL)

NVIC ICPR: ADC_IRQn (Bitfield-Mask: 0x01)

Definition at line 2418 of file DA14680BA.h.

◆ NVIC_ICPR_ADC_IRQn_Pos

#define NVIC_ICPR_ADC_IRQn_Pos   (14UL)

NVIC ICPR: ADC_IRQn (Bit 14)

Definition at line 2417 of file DA14680BA.h.

◆ NVIC_ICPR_BLE_GEN_IRQn_Msk

#define NVIC_ICPR_BLE_GEN_IRQn_Msk   (0x2UL)

NVIC ICPR: BLE_GEN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2392 of file DA14680BA.h.

◆ NVIC_ICPR_BLE_GEN_IRQn_Pos

#define NVIC_ICPR_BLE_GEN_IRQn_Pos   (1UL)

NVIC ICPR: BLE_GEN_IRQn (Bit 1)

Definition at line 2391 of file DA14680BA.h.

◆ NVIC_ICPR_BLE_WAKEUP_LP_IRQn_Msk

#define NVIC_ICPR_BLE_WAKEUP_LP_IRQn_Msk   (0x1UL)

NVIC ICPR: BLE_WAKEUP_LP_IRQn (Bitfield-Mask: 0x01)

Definition at line 2390 of file DA14680BA.h.

◆ NVIC_ICPR_BLE_WAKEUP_LP_IRQn_Pos

#define NVIC_ICPR_BLE_WAKEUP_LP_IRQn_Pos   (0UL)

NVIC ICPR: BLE_WAKEUP_LP_IRQn (Bit 0)

Definition at line 2389 of file DA14680BA.h.

◆ NVIC_ICPR_COEX_IRQn_Msk

#define NVIC_ICPR_COEX_IRQn_Msk   (0x20UL)

NVIC ICPR: COEX_IRQn (Bitfield-Mask: 0x01)

Definition at line 2400 of file DA14680BA.h.

◆ NVIC_ICPR_COEX_IRQn_Pos

#define NVIC_ICPR_COEX_IRQn_Pos   (5UL)

NVIC ICPR: COEX_IRQn (Bit 5)

Definition at line 2399 of file DA14680BA.h.

◆ NVIC_ICPR_CRYPTO_IRQn_Msk

#define NVIC_ICPR_CRYPTO_IRQn_Msk   (0x40UL)

NVIC ICPR: CRYPTO_IRQn (Bitfield-Mask: 0x01)

Definition at line 2402 of file DA14680BA.h.

◆ NVIC_ICPR_CRYPTO_IRQn_Pos

#define NVIC_ICPR_CRYPTO_IRQn_Pos   (6UL)

NVIC ICPR: CRYPTO_IRQn (Bit 6)

Definition at line 2401 of file DA14680BA.h.

◆ NVIC_ICPR_DCDC_IRQn_Msk

#define NVIC_ICPR_DCDC_IRQn_Msk   (0x20000000UL)

NVIC ICPR: DCDC_IRQn (Bitfield-Mask: 0x01)

Definition at line 2448 of file DA14680BA.h.

◆ NVIC_ICPR_DCDC_IRQn_Pos

#define NVIC_ICPR_DCDC_IRQn_Pos   (29UL)

NVIC ICPR: DCDC_IRQn (Bit 29)

Definition at line 2447 of file DA14680BA.h.

◆ NVIC_ICPR_DMA_IRQn_Msk

#define NVIC_ICPR_DMA_IRQn_Msk   (0x4000000UL)

NVIC ICPR: DMA_IRQn (Bitfield-Mask: 0x01)

Definition at line 2442 of file DA14680BA.h.

◆ NVIC_ICPR_DMA_IRQn_Pos

#define NVIC_ICPR_DMA_IRQn_Pos   (26UL)

NVIC ICPR: DMA_IRQn (Bit 26)

Definition at line 2441 of file DA14680BA.h.

◆ NVIC_ICPR_FTDF_GEN_IRQn_Msk

#define NVIC_ICPR_FTDF_GEN_IRQn_Msk   (0x8UL)

NVIC ICPR: FTDF_GEN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2396 of file DA14680BA.h.

◆ NVIC_ICPR_FTDF_GEN_IRQn_Pos

#define NVIC_ICPR_FTDF_GEN_IRQn_Pos   (3UL)

NVIC ICPR: FTDF_GEN_IRQn (Bit 3)

Definition at line 2395 of file DA14680BA.h.

◆ NVIC_ICPR_FTDF_WAKEUP_IRQn_Msk

#define NVIC_ICPR_FTDF_WAKEUP_IRQn_Msk   (0x4UL)

NVIC ICPR: FTDF_WAKEUP_IRQn (Bitfield-Mask: 0x01)

Definition at line 2394 of file DA14680BA.h.

◆ NVIC_ICPR_FTDF_WAKEUP_IRQn_Pos

#define NVIC_ICPR_FTDF_WAKEUP_IRQn_Pos   (2UL)

NVIC ICPR: FTDF_WAKEUP_IRQn (Bit 2)

Definition at line 2393 of file DA14680BA.h.

◆ NVIC_ICPR_I2C2_IRQn_Msk

#define NVIC_ICPR_I2C2_IRQn_Msk   (0x800UL)

NVIC ICPR: I2C2_IRQn (Bitfield-Mask: 0x01)

Definition at line 2412 of file DA14680BA.h.

◆ NVIC_ICPR_I2C2_IRQn_Pos

#define NVIC_ICPR_I2C2_IRQn_Pos   (11UL)

NVIC ICPR: I2C2_IRQn (Bit 11)

Definition at line 2411 of file DA14680BA.h.

◆ NVIC_ICPR_I2C_IRQn_Msk

#define NVIC_ICPR_I2C_IRQn_Msk   (0x400UL)

NVIC ICPR: I2C_IRQn (Bitfield-Mask: 0x01)

Definition at line 2410 of file DA14680BA.h.

◆ NVIC_ICPR_I2C_IRQn_Pos

#define NVIC_ICPR_I2C_IRQn_Pos   (10UL)

NVIC ICPR: I2C_IRQn (Bit 10)

Definition at line 2409 of file DA14680BA.h.

◆ NVIC_ICPR_IRGEN_IRQn_Msk

#define NVIC_ICPR_IRGEN_IRQn_Msk   (0x10000UL)

NVIC ICPR: IRGEN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2422 of file DA14680BA.h.

◆ NVIC_ICPR_IRGEN_IRQn_Pos

#define NVIC_ICPR_IRGEN_IRQn_Pos   (16UL)

NVIC ICPR: IRGEN_IRQn (Bit 16)

Definition at line 2421 of file DA14680BA.h.

◆ NVIC_ICPR_KEYBRD_IRQn_Msk

#define NVIC_ICPR_KEYBRD_IRQn_Msk   (0x8000UL)

NVIC ICPR: KEYBRD_IRQn (Bitfield-Mask: 0x01)

Definition at line 2420 of file DA14680BA.h.

◆ NVIC_ICPR_KEYBRD_IRQn_Pos

#define NVIC_ICPR_KEYBRD_IRQn_Pos   (15UL)

NVIC ICPR: KEYBRD_IRQn (Bit 15)

Definition at line 2419 of file DA14680BA.h.

◆ NVIC_ICPR_MRM_IRQn_Msk

#define NVIC_ICPR_MRM_IRQn_Msk   (0x80UL)

NVIC ICPR: MRM_IRQn (Bitfield-Mask: 0x01)

Definition at line 2404 of file DA14680BA.h.

◆ NVIC_ICPR_MRM_IRQn_Pos

#define NVIC_ICPR_MRM_IRQn_Pos   (7UL)

NVIC ICPR: MRM_IRQn (Bit 7)

Definition at line 2403 of file DA14680BA.h.

◆ NVIC_ICPR_PCM_IRQn_Msk

#define NVIC_ICPR_PCM_IRQn_Msk   (0x400000UL)

NVIC ICPR: PCM_IRQn (Bitfield-Mask: 0x01)

Definition at line 2434 of file DA14680BA.h.

◆ NVIC_ICPR_PCM_IRQn_Pos

#define NVIC_ICPR_PCM_IRQn_Pos   (22UL)

NVIC ICPR: PCM_IRQn (Bit 22)

Definition at line 2433 of file DA14680BA.h.

◆ NVIC_ICPR_QUADEC_IRQn_Msk

#define NVIC_ICPR_QUADEC_IRQn_Msk   (0x100000UL)

NVIC ICPR: QUADEC_IRQn (Bitfield-Mask: 0x01)

Definition at line 2430 of file DA14680BA.h.

◆ NVIC_ICPR_QUADEC_IRQn_Pos

#define NVIC_ICPR_QUADEC_IRQn_Pos   (20UL)

NVIC ICPR: QUADEC_IRQn (Bit 20)

Definition at line 2429 of file DA14680BA.h.

◆ NVIC_ICPR_RF_DIAG_IRQn_Msk

#define NVIC_ICPR_RF_DIAG_IRQn_Msk   (0x8000000UL)

NVIC ICPR: RF_DIAG_IRQn (Bitfield-Mask: 0x01)

Definition at line 2444 of file DA14680BA.h.

◆ NVIC_ICPR_RF_DIAG_IRQn_Pos

#define NVIC_ICPR_RF_DIAG_IRQn_Pos   (27UL)

NVIC ICPR: RF_DIAG_IRQn (Bit 27)

Definition at line 2443 of file DA14680BA.h.

◆ NVIC_ICPR_RFCAL_IRQn_Msk

#define NVIC_ICPR_RFCAL_IRQn_Msk   (0x10UL)

NVIC ICPR: RFCAL_IRQn (Bitfield-Mask: 0x01)

Definition at line 2398 of file DA14680BA.h.

◆ NVIC_ICPR_RFCAL_IRQn_Pos

#define NVIC_ICPR_RFCAL_IRQn_Pos   (4UL)

NVIC ICPR: RFCAL_IRQn (Bit 4)

Definition at line 2397 of file DA14680BA.h.

◆ NVIC_ICPR_Rsvd__irq__n_Msk

#define NVIC_ICPR_Rsvd__irq__n_Msk   (0x80000000UL)

NVIC ICPR: Rsvd__irq__n (Bitfield-Mask: 0x01)

Definition at line 2452 of file DA14680BA.h.

◆ NVIC_ICPR_Rsvd__irq__n_Pos

#define NVIC_ICPR_Rsvd__irq__n_Pos   (31UL)

NVIC ICPR: Rsvd__irq__n (Bit 31)

Definition at line 2451 of file DA14680BA.h.

◆ NVIC_ICPR_SPI2_IRQn_Msk

#define NVIC_ICPR_SPI2_IRQn_Msk   (0x2000UL)

NVIC ICPR: SPI2_IRQn (Bitfield-Mask: 0x01)

Definition at line 2416 of file DA14680BA.h.

◆ NVIC_ICPR_SPI2_IRQn_Pos

#define NVIC_ICPR_SPI2_IRQn_Pos   (13UL)

NVIC ICPR: SPI2_IRQn (Bit 13)

Definition at line 2415 of file DA14680BA.h.

◆ NVIC_ICPR_SPI_IRQn_Msk

#define NVIC_ICPR_SPI_IRQn_Msk   (0x1000UL)

NVIC ICPR: SPI_IRQn (Bitfield-Mask: 0x01)

Definition at line 2414 of file DA14680BA.h.

◆ NVIC_ICPR_SPI_IRQn_Pos

#define NVIC_ICPR_SPI_IRQn_Pos   (12UL)

NVIC ICPR: SPI_IRQn (Bit 12)

Definition at line 2413 of file DA14680BA.h.

◆ NVIC_ICPR_SRC_IN_IRQn_Msk

#define NVIC_ICPR_SRC_IN_IRQn_Msk   (0x800000UL)

NVIC ICPR: SRC_IN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2436 of file DA14680BA.h.

◆ NVIC_ICPR_SRC_IN_IRQn_Pos

#define NVIC_ICPR_SRC_IN_IRQn_Pos   (23UL)

NVIC ICPR: SRC_IN_IRQn (Bit 23)

Definition at line 2435 of file DA14680BA.h.

◆ NVIC_ICPR_SRC_OUT_IRQn_Msk

#define NVIC_ICPR_SRC_OUT_IRQn_Msk   (0x1000000UL)

NVIC ICPR: SRC_OUT_IRQn (Bitfield-Mask: 0x01)

Definition at line 2438 of file DA14680BA.h.

◆ NVIC_ICPR_SRC_OUT_IRQn_Pos

#define NVIC_ICPR_SRC_OUT_IRQn_Pos   (24UL)

NVIC ICPR: SRC_OUT_IRQn (Bit 24)

Definition at line 2437 of file DA14680BA.h.

◆ NVIC_ICPR_SWTIM0_IRQn_Msk

#define NVIC_ICPR_SWTIM0_IRQn_Msk   (0x40000UL)

NVIC ICPR: SWTIM0_IRQn (Bitfield-Mask: 0x01)

Definition at line 2426 of file DA14680BA.h.

◆ NVIC_ICPR_SWTIM0_IRQn_Pos

#define NVIC_ICPR_SWTIM0_IRQn_Pos   (18UL)

NVIC ICPR: SWTIM0_IRQn (Bit 18)

Definition at line 2425 of file DA14680BA.h.

◆ NVIC_ICPR_SWTIM1_IRQn_Msk

#define NVIC_ICPR_SWTIM1_IRQn_Msk   (0x80000UL)

NVIC ICPR: SWTIM1_IRQn (Bitfield-Mask: 0x01)

Definition at line 2428 of file DA14680BA.h.

◆ NVIC_ICPR_SWTIM1_IRQn_Pos

#define NVIC_ICPR_SWTIM1_IRQn_Pos   (19UL)

NVIC ICPR: SWTIM1_IRQn (Bit 19)

Definition at line 2427 of file DA14680BA.h.

◆ NVIC_ICPR_TRNG_IRQn_Msk

#define NVIC_ICPR_TRNG_IRQn_Msk   (0x10000000UL)

NVIC ICPR: TRNG_IRQn (Bitfield-Mask: 0x01)

Definition at line 2446 of file DA14680BA.h.

◆ NVIC_ICPR_TRNG_IRQn_Pos

#define NVIC_ICPR_TRNG_IRQn_Pos   (28UL)

NVIC ICPR: TRNG_IRQn (Bit 28)

Definition at line 2445 of file DA14680BA.h.

◆ NVIC_ICPR_UART2_IRQn_Msk

#define NVIC_ICPR_UART2_IRQn_Msk   (0x200UL)

NVIC ICPR: UART2_IRQn (Bitfield-Mask: 0x01)

Definition at line 2408 of file DA14680BA.h.

◆ NVIC_ICPR_UART2_IRQn_Pos

#define NVIC_ICPR_UART2_IRQn_Pos   (9UL)

NVIC ICPR: UART2_IRQn (Bit 9)

Definition at line 2407 of file DA14680BA.h.

◆ NVIC_ICPR_UART_IRQn_Msk

#define NVIC_ICPR_UART_IRQn_Msk   (0x100UL)

NVIC ICPR: UART_IRQn (Bitfield-Mask: 0x01)

Definition at line 2406 of file DA14680BA.h.

◆ NVIC_ICPR_UART_IRQn_Pos

#define NVIC_ICPR_UART_IRQn_Pos   (8UL)

NVIC ICPR: UART_IRQn (Bit 8)

Definition at line 2405 of file DA14680BA.h.

◆ NVIC_ICPR_USB_IRQn_Msk

#define NVIC_ICPR_USB_IRQn_Msk   (0x200000UL)

NVIC ICPR: USB_IRQn (Bitfield-Mask: 0x01)

Definition at line 2432 of file DA14680BA.h.

◆ NVIC_ICPR_USB_IRQn_Pos

#define NVIC_ICPR_USB_IRQn_Pos   (21UL)

NVIC ICPR: USB_IRQn (Bit 21)

Definition at line 2431 of file DA14680BA.h.

◆ NVIC_ICPR_VBUS_IRQn_Msk

#define NVIC_ICPR_VBUS_IRQn_Msk   (0x2000000UL)

NVIC ICPR: VBUS_IRQn (Bitfield-Mask: 0x01)

Definition at line 2440 of file DA14680BA.h.

◆ NVIC_ICPR_VBUS_IRQn_Pos

#define NVIC_ICPR_VBUS_IRQn_Pos   (25UL)

NVIC ICPR: VBUS_IRQn (Bit 25)

Definition at line 2439 of file DA14680BA.h.

◆ NVIC_ICPR_WKUP_GPIO_IRQn_Msk

#define NVIC_ICPR_WKUP_GPIO_IRQn_Msk   (0x20000UL)

NVIC ICPR: WKUP_GPIO_IRQn (Bitfield-Mask: 0x01)

Definition at line 2424 of file DA14680BA.h.

◆ NVIC_ICPR_WKUP_GPIO_IRQn_Pos

#define NVIC_ICPR_WKUP_GPIO_IRQn_Pos   (17UL)

NVIC ICPR: WKUP_GPIO_IRQn (Bit 17)

Definition at line 2423 of file DA14680BA.h.

◆ NVIC_ICPR_XTAL16RDY_IRQn_Msk

#define NVIC_ICPR_XTAL16RDY_IRQn_Msk   (0x40000000UL)

NVIC ICPR: XTAL16RDY_IRQn (Bitfield-Mask: 0x01)

Definition at line 2450 of file DA14680BA.h.

◆ NVIC_ICPR_XTAL16RDY_IRQn_Pos

#define NVIC_ICPR_XTAL16RDY_IRQn_Pos   (30UL)

NVIC ICPR: XTAL16RDY_IRQn (Bit 30)

Definition at line 2449 of file DA14680BA.h.

◆ NVIC_IPR0_BLE_GEN_IRQn_prio_Msk

#define NVIC_IPR0_BLE_GEN_IRQn_prio_Msk   (0xff00UL)

NVIC IPR0: BLE_GEN_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2458 of file DA14680BA.h.

◆ NVIC_IPR0_BLE_GEN_IRQn_prio_Pos

#define NVIC_IPR0_BLE_GEN_IRQn_prio_Pos   (8UL)

NVIC IPR0: BLE_GEN_IRQn_prio (Bit 8)

Definition at line 2457 of file DA14680BA.h.

◆ NVIC_IPR0_BLE_WAKEUP_LP_IRQn_prio_Msk

#define NVIC_IPR0_BLE_WAKEUP_LP_IRQn_prio_Msk   (0xffUL)

NVIC IPR0: BLE_WAKEUP_LP_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2456 of file DA14680BA.h.

◆ NVIC_IPR0_BLE_WAKEUP_LP_IRQn_prio_Pos

#define NVIC_IPR0_BLE_WAKEUP_LP_IRQn_prio_Pos   (0UL)

NVIC IPR0: BLE_WAKEUP_LP_IRQn_prio (Bit 0)

Definition at line 2455 of file DA14680BA.h.

◆ NVIC_IPR0_FTDF_GEN_IRQn_prio_Msk

#define NVIC_IPR0_FTDF_GEN_IRQn_prio_Msk   (0xff000000UL)

NVIC IPR0: FTDF_GEN_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2462 of file DA14680BA.h.

◆ NVIC_IPR0_FTDF_GEN_IRQn_prio_Pos

#define NVIC_IPR0_FTDF_GEN_IRQn_prio_Pos   (24UL)

NVIC IPR0: FTDF_GEN_IRQn_prio (Bit 24)

Definition at line 2461 of file DA14680BA.h.

◆ NVIC_IPR0_FTDF_WAKEUP_IRQn_prio_Msk

#define NVIC_IPR0_FTDF_WAKEUP_IRQn_prio_Msk   (0xff0000UL)

NVIC IPR0: FTDF_WAKEUP_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2460 of file DA14680BA.h.

◆ NVIC_IPR0_FTDF_WAKEUP_IRQn_prio_Pos

#define NVIC_IPR0_FTDF_WAKEUP_IRQn_prio_Pos   (16UL)

NVIC IPR0: FTDF_WAKEUP_IRQn_prio (Bit 16)

Definition at line 2459 of file DA14680BA.h.

◆ NVIC_IPR1_COEX_IRQn_prio_Msk

#define NVIC_IPR1_COEX_IRQn_prio_Msk   (0xff00UL)

NVIC IPR1: COEX_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2468 of file DA14680BA.h.

◆ NVIC_IPR1_COEX_IRQn_prio_Pos

#define NVIC_IPR1_COEX_IRQn_prio_Pos   (8UL)

NVIC IPR1: COEX_IRQn_prio (Bit 8)

Definition at line 2467 of file DA14680BA.h.

◆ NVIC_IPR1_CRYPTO_IRQn_prio_Msk

#define NVIC_IPR1_CRYPTO_IRQn_prio_Msk   (0xff0000UL)

NVIC IPR1: CRYPTO_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2470 of file DA14680BA.h.

◆ NVIC_IPR1_CRYPTO_IRQn_prio_Pos

#define NVIC_IPR1_CRYPTO_IRQn_prio_Pos   (16UL)

NVIC IPR1: CRYPTO_IRQn_prio (Bit 16)

Definition at line 2469 of file DA14680BA.h.

◆ NVIC_IPR1_MRM_IRQn_prio_Msk

#define NVIC_IPR1_MRM_IRQn_prio_Msk   (0xff000000UL)

NVIC IPR1: MRM_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2472 of file DA14680BA.h.

◆ NVIC_IPR1_MRM_IRQn_prio_Pos

#define NVIC_IPR1_MRM_IRQn_prio_Pos   (24UL)

NVIC IPR1: MRM_IRQn_prio (Bit 24)

Definition at line 2471 of file DA14680BA.h.

◆ NVIC_IPR1_RFCAL_IRQn_prio_Msk

#define NVIC_IPR1_RFCAL_IRQn_prio_Msk   (0xffUL)

NVIC IPR1: RFCAL_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2466 of file DA14680BA.h.

◆ NVIC_IPR1_RFCAL_IRQn_prio_Pos

#define NVIC_IPR1_RFCAL_IRQn_prio_Pos   (0UL)

NVIC IPR1: RFCAL_IRQn_prio (Bit 0)

Definition at line 2465 of file DA14680BA.h.

◆ NVIC_IPR2_I2C2_IRQn_prio_Msk

#define NVIC_IPR2_I2C2_IRQn_prio_Msk   (0xff000000UL)

NVIC IPR2: I2C2_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2482 of file DA14680BA.h.

◆ NVIC_IPR2_I2C2_IRQn_prio_Pos

#define NVIC_IPR2_I2C2_IRQn_prio_Pos   (24UL)

NVIC IPR2: I2C2_IRQn_prio (Bit 24)

Definition at line 2481 of file DA14680BA.h.

◆ NVIC_IPR2_I2C_IRQn_prio_Msk

#define NVIC_IPR2_I2C_IRQn_prio_Msk   (0xff0000UL)

NVIC IPR2: I2C_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2480 of file DA14680BA.h.

◆ NVIC_IPR2_I2C_IRQn_prio_Pos

#define NVIC_IPR2_I2C_IRQn_prio_Pos   (16UL)

NVIC IPR2: I2C_IRQn_prio (Bit 16)

Definition at line 2479 of file DA14680BA.h.

◆ NVIC_IPR2_UART2_IRQn_prio_Msk

#define NVIC_IPR2_UART2_IRQn_prio_Msk   (0xff00UL)

NVIC IPR2: UART2_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2478 of file DA14680BA.h.

◆ NVIC_IPR2_UART2_IRQn_prio_Pos

#define NVIC_IPR2_UART2_IRQn_prio_Pos   (8UL)

NVIC IPR2: UART2_IRQn_prio (Bit 8)

Definition at line 2477 of file DA14680BA.h.

◆ NVIC_IPR2_UART_IRQn_prio_Msk

#define NVIC_IPR2_UART_IRQn_prio_Msk   (0xffUL)

NVIC IPR2: UART_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2476 of file DA14680BA.h.

◆ NVIC_IPR2_UART_IRQn_prio_Pos

#define NVIC_IPR2_UART_IRQn_prio_Pos   (0UL)

NVIC IPR2: UART_IRQn_prio (Bit 0)

Definition at line 2475 of file DA14680BA.h.

◆ NVIC_IPR3_ADC_IRQn_prio_Msk

#define NVIC_IPR3_ADC_IRQn_prio_Msk   (0xff0000UL)

NVIC IPR3: ADC_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2490 of file DA14680BA.h.

◆ NVIC_IPR3_ADC_IRQn_prio_Pos

#define NVIC_IPR3_ADC_IRQn_prio_Pos   (16UL)

NVIC IPR3: ADC_IRQn_prio (Bit 16)

Definition at line 2489 of file DA14680BA.h.

◆ NVIC_IPR3_KEYBRD_IRQn_prio_Msk

#define NVIC_IPR3_KEYBRD_IRQn_prio_Msk   (0xff000000UL)

NVIC IPR3: KEYBRD_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2492 of file DA14680BA.h.

◆ NVIC_IPR3_KEYBRD_IRQn_prio_Pos

#define NVIC_IPR3_KEYBRD_IRQn_prio_Pos   (24UL)

NVIC IPR3: KEYBRD_IRQn_prio (Bit 24)

Definition at line 2491 of file DA14680BA.h.

◆ NVIC_IPR3_SPI2_IRQn_prio_Msk

#define NVIC_IPR3_SPI2_IRQn_prio_Msk   (0xff00UL)

NVIC IPR3: SPI2_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2488 of file DA14680BA.h.

◆ NVIC_IPR3_SPI2_IRQn_prio_Pos

#define NVIC_IPR3_SPI2_IRQn_prio_Pos   (8UL)

NVIC IPR3: SPI2_IRQn_prio (Bit 8)

Definition at line 2487 of file DA14680BA.h.

◆ NVIC_IPR3_SPI_IRQn_prio_Msk

#define NVIC_IPR3_SPI_IRQn_prio_Msk   (0xffUL)

NVIC IPR3: SPI_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2486 of file DA14680BA.h.

◆ NVIC_IPR3_SPI_IRQn_prio_Pos

#define NVIC_IPR3_SPI_IRQn_prio_Pos   (0UL)

NVIC IPR3: SPI_IRQn_prio (Bit 0)

Definition at line 2485 of file DA14680BA.h.

◆ NVIC_IPR4_IRGEN_IRQn_prio_Msk

#define NVIC_IPR4_IRGEN_IRQn_prio_Msk   (0xffUL)

NVIC IPR4: IRGEN_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2496 of file DA14680BA.h.

◆ NVIC_IPR4_IRGEN_IRQn_prio_Pos

#define NVIC_IPR4_IRGEN_IRQn_prio_Pos   (0UL)

NVIC IPR4: IRGEN_IRQn_prio (Bit 0)

Definition at line 2495 of file DA14680BA.h.

◆ NVIC_IPR4_SWTIM0_IRQn_prio_Msk

#define NVIC_IPR4_SWTIM0_IRQn_prio_Msk   (0xff0000UL)

NVIC IPR4: SWTIM0_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2500 of file DA14680BA.h.

◆ NVIC_IPR4_SWTIM0_IRQn_prio_Pos

#define NVIC_IPR4_SWTIM0_IRQn_prio_Pos   (16UL)

NVIC IPR4: SWTIM0_IRQn_prio (Bit 16)

Definition at line 2499 of file DA14680BA.h.

◆ NVIC_IPR4_SWTIM1_IRQn_prio_Msk

#define NVIC_IPR4_SWTIM1_IRQn_prio_Msk   (0xff000000UL)

NVIC IPR4: SWTIM1_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2502 of file DA14680BA.h.

◆ NVIC_IPR4_SWTIM1_IRQn_prio_Pos

#define NVIC_IPR4_SWTIM1_IRQn_prio_Pos   (24UL)

NVIC IPR4: SWTIM1_IRQn_prio (Bit 24)

Definition at line 2501 of file DA14680BA.h.

◆ NVIC_IPR4_WKUP_GPIO_IRQn_prio_Msk

#define NVIC_IPR4_WKUP_GPIO_IRQn_prio_Msk   (0xff00UL)

NVIC IPR4: WKUP_GPIO_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2498 of file DA14680BA.h.

◆ NVIC_IPR4_WKUP_GPIO_IRQn_prio_Pos

#define NVIC_IPR4_WKUP_GPIO_IRQn_prio_Pos   (8UL)

NVIC IPR4: WKUP_GPIO_IRQn_prio (Bit 8)

Definition at line 2497 of file DA14680BA.h.

◆ NVIC_IPR5_PCM_IRQn_prio_Msk

#define NVIC_IPR5_PCM_IRQn_prio_Msk   (0xff0000UL)

NVIC IPR5: PCM_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2510 of file DA14680BA.h.

◆ NVIC_IPR5_PCM_IRQn_prio_Pos

#define NVIC_IPR5_PCM_IRQn_prio_Pos   (16UL)

NVIC IPR5: PCM_IRQn_prio (Bit 16)

Definition at line 2509 of file DA14680BA.h.

◆ NVIC_IPR5_QUADEC_IRQn_prio_Msk

#define NVIC_IPR5_QUADEC_IRQn_prio_Msk   (0xffUL)

NVIC IPR5: QUADEC_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2506 of file DA14680BA.h.

◆ NVIC_IPR5_QUADEC_IRQn_prio_Pos

#define NVIC_IPR5_QUADEC_IRQn_prio_Pos   (0UL)

NVIC IPR5: QUADEC_IRQn_prio (Bit 0)

Definition at line 2505 of file DA14680BA.h.

◆ NVIC_IPR5_SRC_IN_IRQn_prio_Msk

#define NVIC_IPR5_SRC_IN_IRQn_prio_Msk   (0xff000000UL)

NVIC IPR5: SRC_IN_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2512 of file DA14680BA.h.

◆ NVIC_IPR5_SRC_IN_IRQn_prio_Pos

#define NVIC_IPR5_SRC_IN_IRQn_prio_Pos   (24UL)

NVIC IPR5: SRC_IN_IRQn_prio (Bit 24)

Definition at line 2511 of file DA14680BA.h.

◆ NVIC_IPR5_USB_IRQn_prio_Msk

#define NVIC_IPR5_USB_IRQn_prio_Msk   (0xff00UL)

NVIC IPR5: USB_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2508 of file DA14680BA.h.

◆ NVIC_IPR5_USB_IRQn_prio_Pos

#define NVIC_IPR5_USB_IRQn_prio_Pos   (8UL)

NVIC IPR5: USB_IRQn_prio (Bit 8)

Definition at line 2507 of file DA14680BA.h.

◆ NVIC_IPR6_DMA_IRQn_prio_Msk

#define NVIC_IPR6_DMA_IRQn_prio_Msk   (0xff0000UL)

NVIC IPR6: DMA_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2520 of file DA14680BA.h.

◆ NVIC_IPR6_DMA_IRQn_prio_Pos

#define NVIC_IPR6_DMA_IRQn_prio_Pos   (16UL)

NVIC IPR6: DMA_IRQn_prio (Bit 16)

Definition at line 2519 of file DA14680BA.h.

◆ NVIC_IPR6_RF_DIAG_IRQn_prio_Msk

#define NVIC_IPR6_RF_DIAG_IRQn_prio_Msk   (0xff000000UL)

NVIC IPR6: RF_DIAG_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2522 of file DA14680BA.h.

◆ NVIC_IPR6_RF_DIAG_IRQn_prio_Pos

#define NVIC_IPR6_RF_DIAG_IRQn_prio_Pos   (24UL)

NVIC IPR6: RF_DIAG_IRQn_prio (Bit 24)

Definition at line 2521 of file DA14680BA.h.

◆ NVIC_IPR6_SRC_OUT_IRQn_prio_Msk

#define NVIC_IPR6_SRC_OUT_IRQn_prio_Msk   (0xffUL)

NVIC IPR6: SRC_OUT_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2516 of file DA14680BA.h.

◆ NVIC_IPR6_SRC_OUT_IRQn_prio_Pos

#define NVIC_IPR6_SRC_OUT_IRQn_prio_Pos   (0UL)

NVIC IPR6: SRC_OUT_IRQn_prio (Bit 0)

Definition at line 2515 of file DA14680BA.h.

◆ NVIC_IPR6_VBUS_IRQn_prio_Msk

#define NVIC_IPR6_VBUS_IRQn_prio_Msk   (0xff00UL)

NVIC IPR6: VBUS_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2518 of file DA14680BA.h.

◆ NVIC_IPR6_VBUS_IRQn_prio_Pos

#define NVIC_IPR6_VBUS_IRQn_prio_Pos   (8UL)

NVIC IPR6: VBUS_IRQn_prio (Bit 8)

Definition at line 2517 of file DA14680BA.h.

◆ NVIC_IPR7_DCDC_IRQn_prio_Msk

#define NVIC_IPR7_DCDC_IRQn_prio_Msk   (0xff00UL)

NVIC IPR7: DCDC_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2528 of file DA14680BA.h.

◆ NVIC_IPR7_DCDC_IRQn_prio_Pos

#define NVIC_IPR7_DCDC_IRQn_prio_Pos   (8UL)

NVIC IPR7: DCDC_IRQn_prio (Bit 8)

Definition at line 2527 of file DA14680BA.h.

◆ NVIC_IPR7_RESERVED31_IRQn_DONT_USE_Msk

#define NVIC_IPR7_RESERVED31_IRQn_DONT_USE_Msk   (0xff000000UL)

NVIC IPR7: RESERVED31_IRQn_DONT_USE (Bitfield-Mask: 0xff)

Definition at line 2532 of file DA14680BA.h.

◆ NVIC_IPR7_RESERVED31_IRQn_DONT_USE_Pos

#define NVIC_IPR7_RESERVED31_IRQn_DONT_USE_Pos   (24UL)

NVIC IPR7: RESERVED31_IRQn_DONT_USE (Bit 24)

Definition at line 2531 of file DA14680BA.h.

◆ NVIC_IPR7_TRNG_IRQn_prio_Msk

#define NVIC_IPR7_TRNG_IRQn_prio_Msk   (0xffUL)

NVIC IPR7: TRNG_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2526 of file DA14680BA.h.

◆ NVIC_IPR7_TRNG_IRQn_prio_Pos

#define NVIC_IPR7_TRNG_IRQn_prio_Pos   (0UL)

NVIC IPR7: TRNG_IRQn_prio (Bit 0)

Definition at line 2525 of file DA14680BA.h.

◆ NVIC_IPR7_XTAL16RDY_IRQn_prio_Msk

#define NVIC_IPR7_XTAL16RDY_IRQn_prio_Msk   (0xff0000UL)

NVIC IPR7: XTAL16RDY_IRQn_prio (Bitfield-Mask: 0xff)

Definition at line 2530 of file DA14680BA.h.

◆ NVIC_IPR7_XTAL16RDY_IRQn_prio_Pos

#define NVIC_IPR7_XTAL16RDY_IRQn_prio_Pos   (16UL)

NVIC IPR7: XTAL16RDY_IRQn_prio (Bit 16)

Definition at line 2529 of file DA14680BA.h.

◆ NVIC_ISER_ADC_IRQn_Msk

#define NVIC_ISER_ADC_IRQn_Msk   (0x4000UL)

NVIC ISER: ADC_IRQn (Bitfield-Mask: 0x01)

Definition at line 2220 of file DA14680BA.h.

◆ NVIC_ISER_ADC_IRQn_Pos

#define NVIC_ISER_ADC_IRQn_Pos   (14UL)

NVIC ISER: ADC_IRQn (Bit 14)

Definition at line 2219 of file DA14680BA.h.

◆ NVIC_ISER_BLE_GEN_IRQn_Msk

#define NVIC_ISER_BLE_GEN_IRQn_Msk   (0x2UL)

NVIC ISER: BLE_GEN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2194 of file DA14680BA.h.

◆ NVIC_ISER_BLE_GEN_IRQn_Pos

#define NVIC_ISER_BLE_GEN_IRQn_Pos   (1UL)

NVIC ISER: BLE_GEN_IRQn (Bit 1)

Definition at line 2193 of file DA14680BA.h.

◆ NVIC_ISER_BLE_WAKEUP_LP_IRQn_Msk

#define NVIC_ISER_BLE_WAKEUP_LP_IRQn_Msk   (0x1UL)

NVIC ISER: BLE_WAKEUP_LP_IRQn (Bitfield-Mask: 0x01)

Definition at line 2192 of file DA14680BA.h.

◆ NVIC_ISER_BLE_WAKEUP_LP_IRQn_Pos

#define NVIC_ISER_BLE_WAKEUP_LP_IRQn_Pos   (0UL)

NVIC ISER: BLE_WAKEUP_LP_IRQn (Bit 0)

Definition at line 2191 of file DA14680BA.h.

◆ NVIC_ISER_COEX_IRQn_Msk

#define NVIC_ISER_COEX_IRQn_Msk   (0x20UL)

NVIC ISER: COEX_IRQn (Bitfield-Mask: 0x01)

Definition at line 2202 of file DA14680BA.h.

◆ NVIC_ISER_COEX_IRQn_Pos

#define NVIC_ISER_COEX_IRQn_Pos   (5UL)

NVIC ISER: COEX_IRQn (Bit 5)

Definition at line 2201 of file DA14680BA.h.

◆ NVIC_ISER_CRYPTO_IRQn_Msk

#define NVIC_ISER_CRYPTO_IRQn_Msk   (0x40UL)

NVIC ISER: CRYPTO_IRQn (Bitfield-Mask: 0x01)

Definition at line 2204 of file DA14680BA.h.

◆ NVIC_ISER_CRYPTO_IRQn_Pos

#define NVIC_ISER_CRYPTO_IRQn_Pos   (6UL)

NVIC ISER: CRYPTO_IRQn (Bit 6)

Definition at line 2203 of file DA14680BA.h.

◆ NVIC_ISER_DCDC_IRQn_Msk

#define NVIC_ISER_DCDC_IRQn_Msk   (0x20000000UL)

NVIC ISER: DCDC_IRQn (Bitfield-Mask: 0x01)

Definition at line 2250 of file DA14680BA.h.

◆ NVIC_ISER_DCDC_IRQn_Pos

#define NVIC_ISER_DCDC_IRQn_Pos   (29UL)

NVIC ISER: DCDC_IRQn (Bit 29)

Definition at line 2249 of file DA14680BA.h.

◆ NVIC_ISER_DMA_IRQn_Msk

#define NVIC_ISER_DMA_IRQn_Msk   (0x4000000UL)

NVIC ISER: DMA_IRQn (Bitfield-Mask: 0x01)

Definition at line 2244 of file DA14680BA.h.

◆ NVIC_ISER_DMA_IRQn_Pos

#define NVIC_ISER_DMA_IRQn_Pos   (26UL)

NVIC ISER: DMA_IRQn (Bit 26)

Definition at line 2243 of file DA14680BA.h.

◆ NVIC_ISER_FTDF_GEN_IRQn_Msk

#define NVIC_ISER_FTDF_GEN_IRQn_Msk   (0x8UL)

NVIC ISER: FTDF_GEN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2198 of file DA14680BA.h.

◆ NVIC_ISER_FTDF_GEN_IRQn_Pos

#define NVIC_ISER_FTDF_GEN_IRQn_Pos   (3UL)

NVIC ISER: FTDF_GEN_IRQn (Bit 3)

Definition at line 2197 of file DA14680BA.h.

◆ NVIC_ISER_FTDF_WAKEUP_IRQn_Msk

#define NVIC_ISER_FTDF_WAKEUP_IRQn_Msk   (0x4UL)

NVIC ISER: FTDF_WAKEUP_IRQn (Bitfield-Mask: 0x01)

Definition at line 2196 of file DA14680BA.h.

◆ NVIC_ISER_FTDF_WAKEUP_IRQn_Pos

#define NVIC_ISER_FTDF_WAKEUP_IRQn_Pos   (2UL)

NVIC ISER: FTDF_WAKEUP_IRQn (Bit 2)

Definition at line 2195 of file DA14680BA.h.

◆ NVIC_ISER_I2C2_IRQn_Msk

#define NVIC_ISER_I2C2_IRQn_Msk   (0x800UL)

NVIC ISER: I2C2_IRQn (Bitfield-Mask: 0x01)

Definition at line 2214 of file DA14680BA.h.

◆ NVIC_ISER_I2C2_IRQn_Pos

#define NVIC_ISER_I2C2_IRQn_Pos   (11UL)

NVIC ISER: I2C2_IRQn (Bit 11)

Definition at line 2213 of file DA14680BA.h.

◆ NVIC_ISER_I2C_IRQn_Msk

#define NVIC_ISER_I2C_IRQn_Msk   (0x400UL)

NVIC ISER: I2C_IRQn (Bitfield-Mask: 0x01)

Definition at line 2212 of file DA14680BA.h.

◆ NVIC_ISER_I2C_IRQn_Pos

#define NVIC_ISER_I2C_IRQn_Pos   (10UL)

NVIC ISER: I2C_IRQn (Bit 10)

Definition at line 2211 of file DA14680BA.h.

◆ NVIC_ISER_IRGEN_IRQn_Msk

#define NVIC_ISER_IRGEN_IRQn_Msk   (0x10000UL)

NVIC ISER: IRGEN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2224 of file DA14680BA.h.

◆ NVIC_ISER_IRGEN_IRQn_Pos

#define NVIC_ISER_IRGEN_IRQn_Pos   (16UL)

NVIC ISER: IRGEN_IRQn (Bit 16)

Definition at line 2223 of file DA14680BA.h.

◆ NVIC_ISER_KEYBRD_IRQn_Msk

#define NVIC_ISER_KEYBRD_IRQn_Msk   (0x8000UL)

NVIC ISER: KEYBRD_IRQn (Bitfield-Mask: 0x01)

Definition at line 2222 of file DA14680BA.h.

◆ NVIC_ISER_KEYBRD_IRQn_Pos

#define NVIC_ISER_KEYBRD_IRQn_Pos   (15UL)

NVIC ISER: KEYBRD_IRQn (Bit 15)

Definition at line 2221 of file DA14680BA.h.

◆ NVIC_ISER_MRM_IRQn_Msk

#define NVIC_ISER_MRM_IRQn_Msk   (0x80UL)

NVIC ISER: MRM_IRQn (Bitfield-Mask: 0x01)

Definition at line 2206 of file DA14680BA.h.

◆ NVIC_ISER_MRM_IRQn_Pos

#define NVIC_ISER_MRM_IRQn_Pos   (7UL)

NVIC ISER: MRM_IRQn (Bit 7)

Definition at line 2205 of file DA14680BA.h.

◆ NVIC_ISER_PCM_IRQn_Msk

#define NVIC_ISER_PCM_IRQn_Msk   (0x400000UL)

NVIC ISER: PCM_IRQn (Bitfield-Mask: 0x01)

Definition at line 2236 of file DA14680BA.h.

◆ NVIC_ISER_PCM_IRQn_Pos

#define NVIC_ISER_PCM_IRQn_Pos   (22UL)

NVIC ISER: PCM_IRQn (Bit 22)

Definition at line 2235 of file DA14680BA.h.

◆ NVIC_ISER_QUADEC_IRQn_Msk

#define NVIC_ISER_QUADEC_IRQn_Msk   (0x100000UL)

NVIC ISER: QUADEC_IRQn (Bitfield-Mask: 0x01)

Definition at line 2232 of file DA14680BA.h.

◆ NVIC_ISER_QUADEC_IRQn_Pos

#define NVIC_ISER_QUADEC_IRQn_Pos   (20UL)

NVIC ISER: QUADEC_IRQn (Bit 20)

Definition at line 2231 of file DA14680BA.h.

◆ NVIC_ISER_RF_DIAG_IRQn_Msk

#define NVIC_ISER_RF_DIAG_IRQn_Msk   (0x8000000UL)

NVIC ISER: RF_DIAG_IRQn (Bitfield-Mask: 0x01)

Definition at line 2246 of file DA14680BA.h.

◆ NVIC_ISER_RF_DIAG_IRQn_Pos

#define NVIC_ISER_RF_DIAG_IRQn_Pos   (27UL)

NVIC ISER: RF_DIAG_IRQn (Bit 27)

Definition at line 2245 of file DA14680BA.h.

◆ NVIC_ISER_RFCAL_IRQn_Msk

#define NVIC_ISER_RFCAL_IRQn_Msk   (0x10UL)

NVIC ISER: RFCAL_IRQn (Bitfield-Mask: 0x01)

Definition at line 2200 of file DA14680BA.h.

◆ NVIC_ISER_RFCAL_IRQn_Pos

#define NVIC_ISER_RFCAL_IRQn_Pos   (4UL)

NVIC ISER: RFCAL_IRQn (Bit 4)

Definition at line 2199 of file DA14680BA.h.

◆ NVIC_ISER_Rsvd__irq__n_Msk

#define NVIC_ISER_Rsvd__irq__n_Msk   (0x80000000UL)

NVIC ISER: Rsvd__irq__n (Bitfield-Mask: 0x01)

Definition at line 2254 of file DA14680BA.h.

◆ NVIC_ISER_Rsvd__irq__n_Pos

#define NVIC_ISER_Rsvd__irq__n_Pos   (31UL)

NVIC ISER: Rsvd__irq__n (Bit 31)

Definition at line 2253 of file DA14680BA.h.

◆ NVIC_ISER_SPI2_IRQn_Msk

#define NVIC_ISER_SPI2_IRQn_Msk   (0x2000UL)

NVIC ISER: SPI2_IRQn (Bitfield-Mask: 0x01)

Definition at line 2218 of file DA14680BA.h.

◆ NVIC_ISER_SPI2_IRQn_Pos

#define NVIC_ISER_SPI2_IRQn_Pos   (13UL)

NVIC ISER: SPI2_IRQn (Bit 13)

Definition at line 2217 of file DA14680BA.h.

◆ NVIC_ISER_SPI_IRQn_Msk

#define NVIC_ISER_SPI_IRQn_Msk   (0x1000UL)

NVIC ISER: SPI_IRQn (Bitfield-Mask: 0x01)

Definition at line 2216 of file DA14680BA.h.

◆ NVIC_ISER_SPI_IRQn_Pos

#define NVIC_ISER_SPI_IRQn_Pos   (12UL)

NVIC ISER: SPI_IRQn (Bit 12)

Definition at line 2215 of file DA14680BA.h.

◆ NVIC_ISER_SRC_IN_IRQn_Msk

#define NVIC_ISER_SRC_IN_IRQn_Msk   (0x800000UL)

NVIC ISER: SRC_IN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2238 of file DA14680BA.h.

◆ NVIC_ISER_SRC_IN_IRQn_Pos

#define NVIC_ISER_SRC_IN_IRQn_Pos   (23UL)

NVIC ISER: SRC_IN_IRQn (Bit 23)

Definition at line 2237 of file DA14680BA.h.

◆ NVIC_ISER_SRC_OUT_IRQn_Msk

#define NVIC_ISER_SRC_OUT_IRQn_Msk   (0x1000000UL)

NVIC ISER: SRC_OUT_IRQn (Bitfield-Mask: 0x01)

Definition at line 2240 of file DA14680BA.h.

◆ NVIC_ISER_SRC_OUT_IRQn_Pos

#define NVIC_ISER_SRC_OUT_IRQn_Pos   (24UL)

NVIC ISER: SRC_OUT_IRQn (Bit 24)

Definition at line 2239 of file DA14680BA.h.

◆ NVIC_ISER_SWTIM0_IRQn_Msk

#define NVIC_ISER_SWTIM0_IRQn_Msk   (0x40000UL)

NVIC ISER: SWTIM0_IRQn (Bitfield-Mask: 0x01)

Definition at line 2228 of file DA14680BA.h.

◆ NVIC_ISER_SWTIM0_IRQn_Pos

#define NVIC_ISER_SWTIM0_IRQn_Pos   (18UL)

NVIC ISER: SWTIM0_IRQn (Bit 18)

Definition at line 2227 of file DA14680BA.h.

◆ NVIC_ISER_SWTIM1_IRQn_Msk

#define NVIC_ISER_SWTIM1_IRQn_Msk   (0x80000UL)

NVIC ISER: SWTIM1_IRQn (Bitfield-Mask: 0x01)

Definition at line 2230 of file DA14680BA.h.

◆ NVIC_ISER_SWTIM1_IRQn_Pos

#define NVIC_ISER_SWTIM1_IRQn_Pos   (19UL)

NVIC ISER: SWTIM1_IRQn (Bit 19)

Definition at line 2229 of file DA14680BA.h.

◆ NVIC_ISER_TRNG_IRQn_Msk

#define NVIC_ISER_TRNG_IRQn_Msk   (0x10000000UL)

NVIC ISER: TRNG_IRQn (Bitfield-Mask: 0x01)

Definition at line 2248 of file DA14680BA.h.

◆ NVIC_ISER_TRNG_IRQn_Pos

#define NVIC_ISER_TRNG_IRQn_Pos   (28UL)

NVIC ISER: TRNG_IRQn (Bit 28)

Definition at line 2247 of file DA14680BA.h.

◆ NVIC_ISER_UART2_IRQn_Msk

#define NVIC_ISER_UART2_IRQn_Msk   (0x200UL)

NVIC ISER: UART2_IRQn (Bitfield-Mask: 0x01)

Definition at line 2210 of file DA14680BA.h.

◆ NVIC_ISER_UART2_IRQn_Pos

#define NVIC_ISER_UART2_IRQn_Pos   (9UL)

NVIC ISER: UART2_IRQn (Bit 9)

Definition at line 2209 of file DA14680BA.h.

◆ NVIC_ISER_UART_IRQn_Msk

#define NVIC_ISER_UART_IRQn_Msk   (0x100UL)

NVIC ISER: UART_IRQn (Bitfield-Mask: 0x01)

Definition at line 2208 of file DA14680BA.h.

◆ NVIC_ISER_UART_IRQn_Pos

#define NVIC_ISER_UART_IRQn_Pos   (8UL)

NVIC ISER: UART_IRQn (Bit 8)

Definition at line 2207 of file DA14680BA.h.

◆ NVIC_ISER_USB_IRQn_Msk

#define NVIC_ISER_USB_IRQn_Msk   (0x200000UL)

NVIC ISER: USB_IRQn (Bitfield-Mask: 0x01)

Definition at line 2234 of file DA14680BA.h.

◆ NVIC_ISER_USB_IRQn_Pos

#define NVIC_ISER_USB_IRQn_Pos   (21UL)

NVIC ISER: USB_IRQn (Bit 21)

Definition at line 2233 of file DA14680BA.h.

◆ NVIC_ISER_VBUS_IRQn_Msk

#define NVIC_ISER_VBUS_IRQn_Msk   (0x2000000UL)

NVIC ISER: VBUS_IRQn (Bitfield-Mask: 0x01)

Definition at line 2242 of file DA14680BA.h.

◆ NVIC_ISER_VBUS_IRQn_Pos

#define NVIC_ISER_VBUS_IRQn_Pos   (25UL)

NVIC ISER: VBUS_IRQn (Bit 25)

Definition at line 2241 of file DA14680BA.h.

◆ NVIC_ISER_WKUP_GPIO_IRQn_Msk

#define NVIC_ISER_WKUP_GPIO_IRQn_Msk   (0x20000UL)

NVIC ISER: WKUP_GPIO_IRQn (Bitfield-Mask: 0x01)

Definition at line 2226 of file DA14680BA.h.

◆ NVIC_ISER_WKUP_GPIO_IRQn_Pos

#define NVIC_ISER_WKUP_GPIO_IRQn_Pos   (17UL)

NVIC ISER: WKUP_GPIO_IRQn (Bit 17)

Definition at line 2225 of file DA14680BA.h.

◆ NVIC_ISER_XTAL16RDY_IRQn_Msk

#define NVIC_ISER_XTAL16RDY_IRQn_Msk   (0x40000000UL)

NVIC ISER: XTAL16RDY_IRQn (Bitfield-Mask: 0x01)

Definition at line 2252 of file DA14680BA.h.

◆ NVIC_ISER_XTAL16RDY_IRQn_Pos

#define NVIC_ISER_XTAL16RDY_IRQn_Pos   (30UL)

NVIC ISER: XTAL16RDY_IRQn (Bit 30)

Definition at line 2251 of file DA14680BA.h.

◆ NVIC_ISPR_ADC_IRQn_Msk

#define NVIC_ISPR_ADC_IRQn_Msk   (0x4000UL)

NVIC ISPR: ADC_IRQn (Bitfield-Mask: 0x01)

Definition at line 2352 of file DA14680BA.h.

◆ NVIC_ISPR_ADC_IRQn_Pos

#define NVIC_ISPR_ADC_IRQn_Pos   (14UL)

NVIC ISPR: ADC_IRQn (Bit 14)

Definition at line 2351 of file DA14680BA.h.

◆ NVIC_ISPR_BLE_GEN_IRQn_Msk

#define NVIC_ISPR_BLE_GEN_IRQn_Msk   (0x2UL)

NVIC ISPR: BLE_GEN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2326 of file DA14680BA.h.

◆ NVIC_ISPR_BLE_GEN_IRQn_Pos

#define NVIC_ISPR_BLE_GEN_IRQn_Pos   (1UL)

NVIC ISPR: BLE_GEN_IRQn (Bit 1)

Definition at line 2325 of file DA14680BA.h.

◆ NVIC_ISPR_BLE_WAKEUP_LP_IRQn_Msk

#define NVIC_ISPR_BLE_WAKEUP_LP_IRQn_Msk   (0x1UL)

NVIC ISPR: BLE_WAKEUP_LP_IRQn (Bitfield-Mask: 0x01)

Definition at line 2324 of file DA14680BA.h.

◆ NVIC_ISPR_BLE_WAKEUP_LP_IRQn_Pos

#define NVIC_ISPR_BLE_WAKEUP_LP_IRQn_Pos   (0UL)

NVIC ISPR: BLE_WAKEUP_LP_IRQn (Bit 0)

Definition at line 2323 of file DA14680BA.h.

◆ NVIC_ISPR_COEX_IRQn_Msk

#define NVIC_ISPR_COEX_IRQn_Msk   (0x20UL)

NVIC ISPR: COEX_IRQn (Bitfield-Mask: 0x01)

Definition at line 2334 of file DA14680BA.h.

◆ NVIC_ISPR_COEX_IRQn_Pos

#define NVIC_ISPR_COEX_IRQn_Pos   (5UL)

NVIC ISPR: COEX_IRQn (Bit 5)

Definition at line 2333 of file DA14680BA.h.

◆ NVIC_ISPR_CRYPTO_IRQn_Msk

#define NVIC_ISPR_CRYPTO_IRQn_Msk   (0x40UL)

NVIC ISPR: CRYPTO_IRQn (Bitfield-Mask: 0x01)

Definition at line 2336 of file DA14680BA.h.

◆ NVIC_ISPR_CRYPTO_IRQn_Pos

#define NVIC_ISPR_CRYPTO_IRQn_Pos   (6UL)

NVIC ISPR: CRYPTO_IRQn (Bit 6)

Definition at line 2335 of file DA14680BA.h.

◆ NVIC_ISPR_DCDC_IRQn_Msk

#define NVIC_ISPR_DCDC_IRQn_Msk   (0x20000000UL)

NVIC ISPR: DCDC_IRQn (Bitfield-Mask: 0x01)

Definition at line 2382 of file DA14680BA.h.

◆ NVIC_ISPR_DCDC_IRQn_Pos

#define NVIC_ISPR_DCDC_IRQn_Pos   (29UL)

NVIC ISPR: DCDC_IRQn (Bit 29)

Definition at line 2381 of file DA14680BA.h.

◆ NVIC_ISPR_DMA_IRQn_Msk

#define NVIC_ISPR_DMA_IRQn_Msk   (0x4000000UL)

NVIC ISPR: DMA_IRQn (Bitfield-Mask: 0x01)

Definition at line 2376 of file DA14680BA.h.

◆ NVIC_ISPR_DMA_IRQn_Pos

#define NVIC_ISPR_DMA_IRQn_Pos   (26UL)

NVIC ISPR: DMA_IRQn (Bit 26)

Definition at line 2375 of file DA14680BA.h.

◆ NVIC_ISPR_FTDF_GEN_IRQn_Msk

#define NVIC_ISPR_FTDF_GEN_IRQn_Msk   (0x8UL)

NVIC ISPR: FTDF_GEN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2330 of file DA14680BA.h.

◆ NVIC_ISPR_FTDF_GEN_IRQn_Pos

#define NVIC_ISPR_FTDF_GEN_IRQn_Pos   (3UL)

NVIC ISPR: FTDF_GEN_IRQn (Bit 3)

Definition at line 2329 of file DA14680BA.h.

◆ NVIC_ISPR_FTDF_WAKEUP_IRQn_Msk

#define NVIC_ISPR_FTDF_WAKEUP_IRQn_Msk   (0x4UL)

NVIC ISPR: FTDF_WAKEUP_IRQn (Bitfield-Mask: 0x01)

Definition at line 2328 of file DA14680BA.h.

◆ NVIC_ISPR_FTDF_WAKEUP_IRQn_Pos

#define NVIC_ISPR_FTDF_WAKEUP_IRQn_Pos   (2UL)

NVIC ISPR: FTDF_WAKEUP_IRQn (Bit 2)

Definition at line 2327 of file DA14680BA.h.

◆ NVIC_ISPR_I2C2_IRQn_Msk

#define NVIC_ISPR_I2C2_IRQn_Msk   (0x800UL)

NVIC ISPR: I2C2_IRQn (Bitfield-Mask: 0x01)

Definition at line 2346 of file DA14680BA.h.

◆ NVIC_ISPR_I2C2_IRQn_Pos

#define NVIC_ISPR_I2C2_IRQn_Pos   (11UL)

NVIC ISPR: I2C2_IRQn (Bit 11)

Definition at line 2345 of file DA14680BA.h.

◆ NVIC_ISPR_I2C_IRQn_Msk

#define NVIC_ISPR_I2C_IRQn_Msk   (0x400UL)

NVIC ISPR: I2C_IRQn (Bitfield-Mask: 0x01)

Definition at line 2344 of file DA14680BA.h.

◆ NVIC_ISPR_I2C_IRQn_Pos

#define NVIC_ISPR_I2C_IRQn_Pos   (10UL)

NVIC ISPR: I2C_IRQn (Bit 10)

Definition at line 2343 of file DA14680BA.h.

◆ NVIC_ISPR_IRGEN_IRQn_Msk

#define NVIC_ISPR_IRGEN_IRQn_Msk   (0x10000UL)

NVIC ISPR: IRGEN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2356 of file DA14680BA.h.

◆ NVIC_ISPR_IRGEN_IRQn_Pos

#define NVIC_ISPR_IRGEN_IRQn_Pos   (16UL)

NVIC ISPR: IRGEN_IRQn (Bit 16)

Definition at line 2355 of file DA14680BA.h.

◆ NVIC_ISPR_KEYBRD_IRQn_Msk

#define NVIC_ISPR_KEYBRD_IRQn_Msk   (0x8000UL)

NVIC ISPR: KEYBRD_IRQn (Bitfield-Mask: 0x01)

Definition at line 2354 of file DA14680BA.h.

◆ NVIC_ISPR_KEYBRD_IRQn_Pos

#define NVIC_ISPR_KEYBRD_IRQn_Pos   (15UL)

NVIC ISPR: KEYBRD_IRQn (Bit 15)

Definition at line 2353 of file DA14680BA.h.

◆ NVIC_ISPR_MRM_IRQn_Msk

#define NVIC_ISPR_MRM_IRQn_Msk   (0x80UL)

NVIC ISPR: MRM_IRQn (Bitfield-Mask: 0x01)

Definition at line 2338 of file DA14680BA.h.

◆ NVIC_ISPR_MRM_IRQn_Pos

#define NVIC_ISPR_MRM_IRQn_Pos   (7UL)

NVIC ISPR: MRM_IRQn (Bit 7)

Definition at line 2337 of file DA14680BA.h.

◆ NVIC_ISPR_PCM_IRQn_Msk

#define NVIC_ISPR_PCM_IRQn_Msk   (0x400000UL)

NVIC ISPR: PCM_IRQn (Bitfield-Mask: 0x01)

Definition at line 2368 of file DA14680BA.h.

◆ NVIC_ISPR_PCM_IRQn_Pos

#define NVIC_ISPR_PCM_IRQn_Pos   (22UL)

NVIC ISPR: PCM_IRQn (Bit 22)

Definition at line 2367 of file DA14680BA.h.

◆ NVIC_ISPR_QUADEC_IRQn_Msk

#define NVIC_ISPR_QUADEC_IRQn_Msk   (0x100000UL)

NVIC ISPR: QUADEC_IRQn (Bitfield-Mask: 0x01)

Definition at line 2364 of file DA14680BA.h.

◆ NVIC_ISPR_QUADEC_IRQn_Pos

#define NVIC_ISPR_QUADEC_IRQn_Pos   (20UL)

NVIC ISPR: QUADEC_IRQn (Bit 20)

Definition at line 2363 of file DA14680BA.h.

◆ NVIC_ISPR_RF_DIAG_IRQn_Msk

#define NVIC_ISPR_RF_DIAG_IRQn_Msk   (0x8000000UL)

NVIC ISPR: RF_DIAG_IRQn (Bitfield-Mask: 0x01)

Definition at line 2378 of file DA14680BA.h.

◆ NVIC_ISPR_RF_DIAG_IRQn_Pos

#define NVIC_ISPR_RF_DIAG_IRQn_Pos   (27UL)

NVIC ISPR: RF_DIAG_IRQn (Bit 27)

Definition at line 2377 of file DA14680BA.h.

◆ NVIC_ISPR_RFCAL_IRQn_Msk

#define NVIC_ISPR_RFCAL_IRQn_Msk   (0x10UL)

NVIC ISPR: RFCAL_IRQn (Bitfield-Mask: 0x01)

Definition at line 2332 of file DA14680BA.h.

◆ NVIC_ISPR_RFCAL_IRQn_Pos

#define NVIC_ISPR_RFCAL_IRQn_Pos   (4UL)

NVIC ISPR: RFCAL_IRQn (Bit 4)

Definition at line 2331 of file DA14680BA.h.

◆ NVIC_ISPR_Rsvd__irq__n_Msk

#define NVIC_ISPR_Rsvd__irq__n_Msk   (0x80000000UL)

NVIC ISPR: Rsvd__irq__n (Bitfield-Mask: 0x01)

Definition at line 2386 of file DA14680BA.h.

◆ NVIC_ISPR_Rsvd__irq__n_Pos

#define NVIC_ISPR_Rsvd__irq__n_Pos   (31UL)

NVIC ISPR: Rsvd__irq__n (Bit 31)

Definition at line 2385 of file DA14680BA.h.

◆ NVIC_ISPR_SPI2_IRQn_Msk

#define NVIC_ISPR_SPI2_IRQn_Msk   (0x2000UL)

NVIC ISPR: SPI2_IRQn (Bitfield-Mask: 0x01)

Definition at line 2350 of file DA14680BA.h.

◆ NVIC_ISPR_SPI2_IRQn_Pos

#define NVIC_ISPR_SPI2_IRQn_Pos   (13UL)

NVIC ISPR: SPI2_IRQn (Bit 13)

Definition at line 2349 of file DA14680BA.h.

◆ NVIC_ISPR_SPI_IRQn_Msk

#define NVIC_ISPR_SPI_IRQn_Msk   (0x1000UL)

NVIC ISPR: SPI_IRQn (Bitfield-Mask: 0x01)

Definition at line 2348 of file DA14680BA.h.

◆ NVIC_ISPR_SPI_IRQn_Pos

#define NVIC_ISPR_SPI_IRQn_Pos   (12UL)

NVIC ISPR: SPI_IRQn (Bit 12)

Definition at line 2347 of file DA14680BA.h.

◆ NVIC_ISPR_SRC_IN_IRQn_Msk

#define NVIC_ISPR_SRC_IN_IRQn_Msk   (0x800000UL)

NVIC ISPR: SRC_IN_IRQn (Bitfield-Mask: 0x01)

Definition at line 2370 of file DA14680BA.h.

◆ NVIC_ISPR_SRC_IN_IRQn_Pos

#define NVIC_ISPR_SRC_IN_IRQn_Pos   (23UL)

NVIC ISPR: SRC_IN_IRQn (Bit 23)

Definition at line 2369 of file DA14680BA.h.

◆ NVIC_ISPR_SRC_OUT_IRQn_Msk

#define NVIC_ISPR_SRC_OUT_IRQn_Msk   (0x1000000UL)

NVIC ISPR: SRC_OUT_IRQn (Bitfield-Mask: 0x01)

Definition at line 2372 of file DA14680BA.h.

◆ NVIC_ISPR_SRC_OUT_IRQn_Pos

#define NVIC_ISPR_SRC_OUT_IRQn_Pos   (24UL)

NVIC ISPR: SRC_OUT_IRQn (Bit 24)

Definition at line 2371 of file DA14680BA.h.

◆ NVIC_ISPR_SWTIM0_IRQn_Msk

#define NVIC_ISPR_SWTIM0_IRQn_Msk   (0x40000UL)

NVIC ISPR: SWTIM0_IRQn (Bitfield-Mask: 0x01)

Definition at line 2360 of file DA14680BA.h.

◆ NVIC_ISPR_SWTIM0_IRQn_Pos

#define NVIC_ISPR_SWTIM0_IRQn_Pos   (18UL)

NVIC ISPR: SWTIM0_IRQn (Bit 18)

Definition at line 2359 of file DA14680BA.h.

◆ NVIC_ISPR_SWTIM1_IRQn_Msk

#define NVIC_ISPR_SWTIM1_IRQn_Msk   (0x80000UL)

NVIC ISPR: SWTIM1_IRQn (Bitfield-Mask: 0x01)

Definition at line 2362 of file DA14680BA.h.

◆ NVIC_ISPR_SWTIM1_IRQn_Pos

#define NVIC_ISPR_SWTIM1_IRQn_Pos   (19UL)

NVIC ISPR: SWTIM1_IRQn (Bit 19)

Definition at line 2361 of file DA14680BA.h.

◆ NVIC_ISPR_TRNG_IRQn_Msk

#define NVIC_ISPR_TRNG_IRQn_Msk   (0x10000000UL)

NVIC ISPR: TRNG_IRQn (Bitfield-Mask: 0x01)

Definition at line 2380 of file DA14680BA.h.

◆ NVIC_ISPR_TRNG_IRQn_Pos

#define NVIC_ISPR_TRNG_IRQn_Pos   (28UL)

NVIC ISPR: TRNG_IRQn (Bit 28)

Definition at line 2379 of file DA14680BA.h.

◆ NVIC_ISPR_UART2_IRQn_Msk

#define NVIC_ISPR_UART2_IRQn_Msk   (0x200UL)

NVIC ISPR: UART2_IRQn (Bitfield-Mask: 0x01)

Definition at line 2342 of file DA14680BA.h.

◆ NVIC_ISPR_UART2_IRQn_Pos

#define NVIC_ISPR_UART2_IRQn_Pos   (9UL)

NVIC ISPR: UART2_IRQn (Bit 9)

Definition at line 2341 of file DA14680BA.h.

◆ NVIC_ISPR_UART_IRQn_Msk

#define NVIC_ISPR_UART_IRQn_Msk   (0x100UL)

NVIC ISPR: UART_IRQn (Bitfield-Mask: 0x01)

Definition at line 2340 of file DA14680BA.h.

◆ NVIC_ISPR_UART_IRQn_Pos

#define NVIC_ISPR_UART_IRQn_Pos   (8UL)

NVIC ISPR: UART_IRQn (Bit 8)

Definition at line 2339 of file DA14680BA.h.

◆ NVIC_ISPR_USB_IRQn_Msk

#define NVIC_ISPR_USB_IRQn_Msk   (0x200000UL)

NVIC ISPR: USB_IRQn (Bitfield-Mask: 0x01)

Definition at line 2366 of file DA14680BA.h.

◆ NVIC_ISPR_USB_IRQn_Pos

#define NVIC_ISPR_USB_IRQn_Pos   (21UL)

NVIC ISPR: USB_IRQn (Bit 21)

Definition at line 2365 of file DA14680BA.h.

◆ NVIC_ISPR_VBUS_IRQn_Msk

#define NVIC_ISPR_VBUS_IRQn_Msk   (0x2000000UL)

NVIC ISPR: VBUS_IRQn (Bitfield-Mask: 0x01)

Definition at line 2374 of file DA14680BA.h.

◆ NVIC_ISPR_VBUS_IRQn_Pos

#define NVIC_ISPR_VBUS_IRQn_Pos   (25UL)

NVIC ISPR: VBUS_IRQn (Bit 25)

Definition at line 2373 of file DA14680BA.h.

◆ NVIC_ISPR_WKUP_GPIO_IRQn_Msk

#define NVIC_ISPR_WKUP_GPIO_IRQn_Msk   (0x20000UL)

NVIC ISPR: WKUP_GPIO_IRQn (Bitfield-Mask: 0x01)

Definition at line 2358 of file DA14680BA.h.

◆ NVIC_ISPR_WKUP_GPIO_IRQn_Pos

#define NVIC_ISPR_WKUP_GPIO_IRQn_Pos   (17UL)

NVIC ISPR: WKUP_GPIO_IRQn (Bit 17)

Definition at line 2357 of file DA14680BA.h.

◆ NVIC_ISPR_XTAL16RDY_IRQn_Msk

#define NVIC_ISPR_XTAL16RDY_IRQn_Msk   (0x40000000UL)

NVIC ISPR: XTAL16RDY_IRQn (Bitfield-Mask: 0x01)

Definition at line 2384 of file DA14680BA.h.

◆ NVIC_ISPR_XTAL16RDY_IRQn_Pos

#define NVIC_ISPR_XTAL16RDY_IRQn_Pos   (30UL)

NVIC ISPR: XTAL16RDY_IRQn (Bit 30)

Definition at line 2383 of file DA14680BA.h.

◆ OTPC

#define OTPC   ((OTPC_Type *) OTPC_BASE)

Definition at line 12095 of file DA14680BA.h.

◆ OTPC_BASE

#define OTPC_BASE   0x07F40000UL

Definition at line 12050 of file DA14680BA.h.

◆ OTPC_OTPC_AHBADR_REG_OTPC_AHBADR_Msk

#define OTPC_OTPC_AHBADR_REG_OTPC_AHBADR_Msk   (0xfffffffcUL)

OTPC OTPC_AHBADR_REG: OTPC_AHBADR (Bitfield-Mask: 0x3fffffff)

Definition at line 8686 of file DA14680BA.h.

◆ OTPC_OTPC_AHBADR_REG_OTPC_AHBADR_Pos

#define OTPC_OTPC_AHBADR_REG_OTPC_AHBADR_Pos   (2UL)

OTPC OTPC_AHBADR_REG: OTPC_AHBADR (Bit 2)

Definition at line 8685 of file DA14680BA.h.

◆ OTPC_OTPC_CELADR_REG_OTPC_CELADR_LV_Msk

#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_LV_Msk   (0x3fff0000UL)

OTPC OTPC_CELADR_REG: OTPC_CELADR_LV (Bitfield-Mask: 0x3fff)

Definition at line 8692 of file DA14680BA.h.

◆ OTPC_OTPC_CELADR_REG_OTPC_CELADR_LV_Pos

#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_LV_Pos   (16UL)

OTPC OTPC_CELADR_REG: OTPC_CELADR_LV (Bit 16)

Definition at line 8691 of file DA14680BA.h.

◆ OTPC_OTPC_CELADR_REG_OTPC_CELADR_Msk

#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_Msk   (0x3fffUL)

OTPC OTPC_CELADR_REG: OTPC_CELADR (Bitfield-Mask: 0x3fff)

Definition at line 8690 of file DA14680BA.h.

◆ OTPC_OTPC_CELADR_REG_OTPC_CELADR_Pos

#define OTPC_OTPC_CELADR_REG_OTPC_CELADR_Pos   (0UL)

OTPC OTPC_CELADR_REG: OTPC_CELADR (Bit 0)

Definition at line 8689 of file DA14680BA.h.

◆ OTPC_OTPC_FFPRT_REG_OTPC_FFPRT_Msk

#define OTPC_OTPC_FFPRT_REG_OTPC_FFPRT_Msk   (0xffffffffUL)

OTPC OTPC_FFPRT_REG: OTPC_FFPRT (Bitfield-Mask: 0xffffffff)

Definition at line 8700 of file DA14680BA.h.

◆ OTPC_OTPC_FFPRT_REG_OTPC_FFPRT_Pos

#define OTPC_OTPC_FFPRT_REG_OTPC_FFPRT_Pos   (0UL)

OTPC OTPC_FFPRT_REG: OTPC_FFPRT (Bit 0)

Definition at line 8699 of file DA14680BA.h.

◆ OTPC_OTPC_FFRD_REG_OTPC_FFRD_Msk

#define OTPC_OTPC_FFRD_REG_OTPC_FFRD_Msk   (0xffffffffUL)

OTPC OTPC_FFRD_REG: OTPC_FFRD (Bitfield-Mask: 0xffffffff)

Definition at line 8704 of file DA14680BA.h.

◆ OTPC_OTPC_FFRD_REG_OTPC_FFRD_Pos

#define OTPC_OTPC_FFRD_REG_OTPC_FFRD_Pos   (0UL)

OTPC OTPC_FFRD_REG: OTPC_FFRD (Bit 0)

Definition at line 8703 of file DA14680BA.h.

◆ OTPC_OTPC_MODE_REG_OTPC_MODE_ERR_RESP_DIS_Msk

#define OTPC_OTPC_MODE_REG_OTPC_MODE_ERR_RESP_DIS_Msk   (0x40UL)

OTPC OTPC_MODE_REG: OTPC_MODE_ERR_RESP_DIS (Bitfield-Mask: 0x01)

Definition at line 8648 of file DA14680BA.h.

◆ OTPC_OTPC_MODE_REG_OTPC_MODE_ERR_RESP_DIS_Pos

#define OTPC_OTPC_MODE_REG_OTPC_MODE_ERR_RESP_DIS_Pos   (6UL)

OTPC OTPC_MODE_REG: OTPC_MODE_ERR_RESP_DIS (Bit 6)

Definition at line 8647 of file DA14680BA.h.

◆ OTPC_OTPC_MODE_REG_OTPC_MODE_FIFO_FLUSH_Msk

#define OTPC_OTPC_MODE_REG_OTPC_MODE_FIFO_FLUSH_Msk   (0x20UL)

OTPC OTPC_MODE_REG: OTPC_MODE_FIFO_FLUSH (Bitfield-Mask: 0x01)

Definition at line 8646 of file DA14680BA.h.

◆ OTPC_OTPC_MODE_REG_OTPC_MODE_FIFO_FLUSH_Pos

#define OTPC_OTPC_MODE_REG_OTPC_MODE_FIFO_FLUSH_Pos   (5UL)

OTPC OTPC_MODE_REG: OTPC_MODE_FIFO_FLUSH (Bit 5)

Definition at line 8645 of file DA14680BA.h.

◆ OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Msk

#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Msk   (0x7UL)

OTPC OTPC_MODE_REG: OTPC_MODE_MODE (Bitfield-Mask: 0x07)

Definition at line 8642 of file DA14680BA.h.

◆ OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Pos

#define OTPC_OTPC_MODE_REG_OTPC_MODE_MODE_Pos   (0UL)

OTPC OTPC_MODE_REG: OTPC_MODE_MODE (Bit 0)

Definition at line 8641 of file DA14680BA.h.

◆ OTPC_OTPC_MODE_REG_OTPC_MODE_RLD_RR_REQ_Msk

#define OTPC_OTPC_MODE_REG_OTPC_MODE_RLD_RR_REQ_Msk   (0x200UL)

OTPC OTPC_MODE_REG: OTPC_MODE_RLD_RR_REQ (Bitfield-Mask: 0x01)

Definition at line 8652 of file DA14680BA.h.

◆ OTPC_OTPC_MODE_REG_OTPC_MODE_RLD_RR_REQ_Pos

#define OTPC_OTPC_MODE_REG_OTPC_MODE_RLD_RR_REQ_Pos   (9UL)

OTPC OTPC_MODE_REG: OTPC_MODE_RLD_RR_REQ (Bit 9)

Definition at line 8651 of file DA14680BA.h.

◆ OTPC_OTPC_MODE_REG_OTPC_MODE_USE_DMA_Msk

#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_DMA_Msk   (0x10UL)

OTPC OTPC_MODE_REG: OTPC_MODE_USE_DMA (Bitfield-Mask: 0x01)

Definition at line 8644 of file DA14680BA.h.

◆ OTPC_OTPC_MODE_REG_OTPC_MODE_USE_DMA_Pos

#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_DMA_Pos   (4UL)

OTPC OTPC_MODE_REG: OTPC_MODE_USE_DMA (Bit 4)

Definition at line 8643 of file DA14680BA.h.

◆ OTPC_OTPC_MODE_REG_OTPC_MODE_USE_SP_ROWS_Msk

#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_SP_ROWS_Msk   (0x100UL)

OTPC OTPC_MODE_REG: OTPC_MODE_USE_SP_ROWS (Bitfield-Mask: 0x01)

Definition at line 8650 of file DA14680BA.h.

◆ OTPC_OTPC_MODE_REG_OTPC_MODE_USE_SP_ROWS_Pos

#define OTPC_OTPC_MODE_REG_OTPC_MODE_USE_SP_ROWS_Pos   (8UL)

OTPC OTPC_MODE_REG: OTPC_MODE_USE_SP_ROWS (Bit 8)

Definition at line 8649 of file DA14680BA.h.

◆ OTPC_OTPC_NWORDS_REG_OTPC_NWORDS_Msk

#define OTPC_OTPC_NWORDS_REG_OTPC_NWORDS_Msk   (0x3fffUL)

OTPC OTPC_NWORDS_REG: OTPC_NWORDS (Bitfield-Mask: 0x3fff)

Definition at line 8696 of file DA14680BA.h.

◆ OTPC_OTPC_NWORDS_REG_OTPC_NWORDS_Pos

#define OTPC_OTPC_NWORDS_REG_OTPC_NWORDS_Pos   (0UL)

OTPC OTPC_NWORDS_REG: OTPC_NWORDS (Bit 0)

Definition at line 8695 of file DA14680BA.h.

◆ OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PRETRY_Msk

#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PRETRY_Msk   (0x4000UL)

OTPC OTPC_PCTRL_REG: OTPC_PCTRL_PRETRY (Bitfield-Mask: 0x01)

Definition at line 8658 of file DA14680BA.h.

◆ OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PRETRY_Pos

#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PRETRY_Pos   (14UL)

OTPC OTPC_PCTRL_REG: OTPC_PCTRL_PRETRY (Bit 14)

Definition at line 8657 of file DA14680BA.h.

◆ OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PSTART_Msk

#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PSTART_Msk   (0x8000UL)

OTPC OTPC_PCTRL_REG: OTPC_PCTRL_PSTART (Bitfield-Mask: 0x01)

Definition at line 8660 of file DA14680BA.h.

◆ OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PSTART_Pos

#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_PSTART_Pos   (15UL)

OTPC OTPC_PCTRL_REG: OTPC_PCTRL_PSTART (Bit 15)

Definition at line 8659 of file DA14680BA.h.

◆ OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_WADDR_Msk

#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_WADDR_Msk   (0x1fffUL)

OTPC OTPC_PCTRL_REG: OTPC_PCTRL_WADDR (Bitfield-Mask: 0x1fff)

Definition at line 8656 of file DA14680BA.h.

◆ OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_WADDR_Pos

#define OTPC_OTPC_PCTRL_REG_OTPC_PCTRL_WADDR_Pos   (0UL)

OTPC OTPC_PCTRL_REG: OTPC_PCTRL_WADDR (Bit 0)

Definition at line 8655 of file DA14680BA.h.

◆ OTPC_OTPC_PWORDH_REG_OTPC_PWORDH_Msk

#define OTPC_OTPC_PWORDH_REG_OTPC_PWORDH_Msk   (0xffffffffUL)

OTPC OTPC_PWORDH_REG: OTPC_PWORDH (Bitfield-Mask: 0xffffffff)

Definition at line 8712 of file DA14680BA.h.

◆ OTPC_OTPC_PWORDH_REG_OTPC_PWORDH_Pos

#define OTPC_OTPC_PWORDH_REG_OTPC_PWORDH_Pos   (0UL)

OTPC OTPC_PWORDH_REG: OTPC_PWORDH (Bit 0)

Definition at line 8711 of file DA14680BA.h.

◆ OTPC_OTPC_PWORDL_REG_OTPC_PWORDL_Msk

#define OTPC_OTPC_PWORDL_REG_OTPC_PWORDL_Msk   (0xffffffffUL)

OTPC OTPC_PWORDL_REG: OTPC_PWORDL (Bitfield-Mask: 0xffffffff)

Definition at line 8708 of file DA14680BA.h.

◆ OTPC_OTPC_PWORDL_REG_OTPC_PWORDL_Pos

#define OTPC_OTPC_PWORDL_REG_OTPC_PWORDL_Pos   (0UL)

OTPC OTPC_PWORDL_REG: OTPC_PWORDL (Bit 0)

Definition at line 8707 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_ARDY_Msk

#define OTPC_OTPC_STAT_REG_OTPC_STAT_ARDY_Msk   (0x40UL)

OTPC OTPC_STAT_REG: OTPC_STAT_ARDY (Bitfield-Mask: 0x01)

Definition at line 8676 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_ARDY_Pos

#define OTPC_OTPC_STAT_REG_OTPC_STAT_ARDY_Pos   (6UL)

OTPC OTPC_STAT_REG: OTPC_STAT_ARDY (Bit 6)

Definition at line 8675 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_FWORDS_Msk

#define OTPC_OTPC_STAT_REG_OTPC_STAT_FWORDS_Msk   (0xf00UL)

OTPC OTPC_STAT_REG: OTPC_STAT_FWORDS (Bitfield-Mask: 0x0f)

Definition at line 8680 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_FWORDS_Pos

#define OTPC_OTPC_STAT_REG_OTPC_STAT_FWORDS_Pos   (8UL)

OTPC OTPC_STAT_REG: OTPC_STAT_FWORDS (Bit 8)

Definition at line 8679 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_NWORDS_Msk

#define OTPC_OTPC_STAT_REG_OTPC_STAT_NWORDS_Msk   (0x3fff0000UL)

OTPC OTPC_STAT_REG: OTPC_STAT_NWORDS (Bitfield-Mask: 0x3fff)

Definition at line 8682 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_NWORDS_Pos

#define OTPC_OTPC_STAT_REG_OTPC_STAT_NWORDS_Pos   (16UL)

OTPC OTPC_STAT_REG: OTPC_STAT_NWORDS (Bit 16)

Definition at line 8681 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_COR_Msk

#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_COR_Msk   (0x4UL)

OTPC OTPC_STAT_REG: OTPC_STAT_PERR_COR (Bitfield-Mask: 0x01)

Definition at line 8668 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_COR_Pos

#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_COR_Pos   (2UL)

OTPC OTPC_STAT_REG: OTPC_STAT_PERR_COR (Bit 2)

Definition at line 8667 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_UNC_Msk

#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_UNC_Msk   (0x2UL)

OTPC OTPC_STAT_REG: OTPC_STAT_PERR_UNC (Bitfield-Mask: 0x01)

Definition at line 8666 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_UNC_Pos

#define OTPC_OTPC_STAT_REG_OTPC_STAT_PERR_UNC_Pos   (1UL)

OTPC OTPC_STAT_REG: OTPC_STAT_PERR_UNC (Bit 1)

Definition at line 8665 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Msk

#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Msk   (0x1UL)

OTPC OTPC_STAT_REG: OTPC_STAT_PRDY (Bitfield-Mask: 0x01)

Definition at line 8664 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Pos

#define OTPC_OTPC_STAT_REG_OTPC_STAT_PRDY_Pos   (0UL)

OTPC OTPC_STAT_REG: OTPC_STAT_PRDY (Bit 0)

Definition at line 8663 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_PZERO_Msk

#define OTPC_OTPC_STAT_REG_OTPC_STAT_PZERO_Msk   (0x8UL)

OTPC OTPC_STAT_REG: OTPC_STAT_PZERO (Bitfield-Mask: 0x01)

Definition at line 8670 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_PZERO_Pos

#define OTPC_OTPC_STAT_REG_OTPC_STAT_PZERO_Pos   (3UL)

OTPC OTPC_STAT_REG: OTPC_STAT_PZERO (Bit 3)

Definition at line 8669 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_RERROR_Msk

#define OTPC_OTPC_STAT_REG_OTPC_STAT_RERROR_Msk   (0x80UL)

OTPC OTPC_STAT_REG: OTPC_STAT_RERROR (Bitfield-Mask: 0x01)

Definition at line 8678 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_RERROR_Pos

#define OTPC_OTPC_STAT_REG_OTPC_STAT_RERROR_Pos   (7UL)

OTPC OTPC_STAT_REG: OTPC_STAT_RERROR (Bit 7)

Definition at line 8677 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_TERROR_Msk

#define OTPC_OTPC_STAT_REG_OTPC_STAT_TERROR_Msk   (0x20UL)

OTPC OTPC_STAT_REG: OTPC_STAT_TERROR (Bitfield-Mask: 0x01)

Definition at line 8674 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_TERROR_Pos

#define OTPC_OTPC_STAT_REG_OTPC_STAT_TERROR_Pos   (5UL)

OTPC OTPC_STAT_REG: OTPC_STAT_TERROR (Bit 5)

Definition at line 8673 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_TRDY_Msk

#define OTPC_OTPC_STAT_REG_OTPC_STAT_TRDY_Msk   (0x10UL)

OTPC OTPC_STAT_REG: OTPC_STAT_TRDY (Bitfield-Mask: 0x01)

Definition at line 8672 of file DA14680BA.h.

◆ OTPC_OTPC_STAT_REG_OTPC_STAT_TRDY_Pos

#define OTPC_OTPC_STAT_REG_OTPC_STAT_TRDY_Pos   (4UL)

OTPC OTPC_STAT_REG: OTPC_STAT_TRDY (Bit 4)

Definition at line 8671 of file DA14680BA.h.

◆ OTPC_OTPC_TEST_REG_OTPC_SECDED_COR_DIS_Msk

#define OTPC_OTPC_TEST_REG_OTPC_SECDED_COR_DIS_Msk   (0x1UL)

OTPC OTPC_TEST_REG: OTPC_SECDED_COR_DIS (Bitfield-Mask: 0x01)

Definition at line 8738 of file DA14680BA.h.

◆ OTPC_OTPC_TEST_REG_OTPC_SECDED_COR_DIS_Pos

#define OTPC_OTPC_TEST_REG_OTPC_SECDED_COR_DIS_Pos   (0UL)

OTPC OTPC_TEST_REG: OTPC_SECDED_COR_DIS (Bit 0)

Definition at line 8737 of file DA14680BA.h.

◆ OTPC_OTPC_TEST_REG_OTPC_SECDED_RAW_ECC_Msk

#define OTPC_OTPC_TEST_REG_OTPC_SECDED_RAW_ECC_Msk   (0xff0000UL)

OTPC OTPC_TEST_REG: OTPC_SECDED_RAW_ECC (Bitfield-Mask: 0xff)

Definition at line 8740 of file DA14680BA.h.

◆ OTPC_OTPC_TEST_REG_OTPC_SECDED_RAW_ECC_Pos

#define OTPC_OTPC_TEST_REG_OTPC_SECDED_RAW_ECC_Pos   (16UL)

OTPC OTPC_TEST_REG: OTPC_SECDED_RAW_ECC (Bit 16)

Definition at line 8739 of file DA14680BA.h.

◆ OTPC_OTPC_TEST_REG_OTPC_SECDED_STAT_Msk

#define OTPC_OTPC_TEST_REG_OTPC_SECDED_STAT_Msk   (0x3000000UL)

OTPC OTPC_TEST_REG: OTPC_SECDED_STAT (Bitfield-Mask: 0x03)

Definition at line 8742 of file DA14680BA.h.

◆ OTPC_OTPC_TEST_REG_OTPC_SECDED_STAT_Pos

#define OTPC_OTPC_TEST_REG_OTPC_SECDED_STAT_Pos   (24UL)

OTPC OTPC_TEST_REG: OTPC_SECDED_STAT (Bit 24)

Definition at line 8741 of file DA14680BA.h.

◆ OTPC_OTPC_TEST_REG_OTPC_USED_RR_Msk

#define OTPC_OTPC_TEST_REG_OTPC_USED_RR_Msk   (0x4000000UL)

OTPC OTPC_TEST_REG: OTPC_USED_RR (Bitfield-Mask: 0x01)

Definition at line 8744 of file DA14680BA.h.

◆ OTPC_OTPC_TEST_REG_OTPC_USED_RR_Pos

#define OTPC_OTPC_TEST_REG_OTPC_USED_RR_Pos   (26UL)

OTPC OTPC_TEST_REG: OTPC_USED_RR (Bit 26)

Definition at line 8743 of file DA14680BA.h.

◆ OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Msk

#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Msk   (0x3f0000UL)

OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_1US (Bitfield-Mask: 0x3f)

Definition at line 8720 of file DA14680BA.h.

◆ OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos

#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_1US_Pos   (16UL)

OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_1US (Bit 16)

Definition at line 8719 of file DA14680BA.h.

◆ OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Msk

#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Msk   (0x78000000UL)

OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_200NS (Bitfield-Mask: 0x0f)

Definition at line 8724 of file DA14680BA.h.

◆ OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos

#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_200NS_Pos   (27UL)

OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_200NS (Bit 27)

Definition at line 8723 of file DA14680BA.h.

◆ OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Msk

#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Msk   (0x80000000UL)

OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_25NS (Bitfield-Mask: 0x01)

Definition at line 8726 of file DA14680BA.h.

◆ OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos

#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_25NS_Pos   (31UL)

OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_25NS (Bit 31)

Definition at line 8725 of file DA14680BA.h.

◆ OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Msk

#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Msk   (0x7c00000UL)

OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_500NS (Bitfield-Mask: 0x1f)

Definition at line 8722 of file DA14680BA.h.

◆ OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos

#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_500NS_Pos   (22UL)

OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_500NS (Bit 22)

Definition at line 8721 of file DA14680BA.h.

◆ OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Msk

#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Msk   (0xffUL)

OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_CADX (Bitfield-Mask: 0xff)

Definition at line 8716 of file DA14680BA.h.

◆ OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos

#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_CADX_Pos   (0UL)

OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_CADX (Bit 0)

Definition at line 8715 of file DA14680BA.h.

◆ OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Msk

#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Msk   (0xff00UL)

OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_PW (Bitfield-Mask: 0xff)

Definition at line 8718 of file DA14680BA.h.

◆ OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos

#define OTPC_OTPC_TIM1_REG_OTPC_TIM1_CC_T_PW_Pos   (8UL)

OTPC OTPC_TIM1_REG: OTPC_TIM1_CC_T_PW (Bit 8)

Definition at line 8717 of file DA14680BA.h.

◆ OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_STBY_THR_Msk

#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_STBY_THR_Msk   (0x3ffUL)

OTPC OTPC_TIM2_REG: OTPC_TIM2_CC_STBY_THR (Bitfield-Mask: 0x3ff)

Definition at line 8730 of file DA14680BA.h.

◆ OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_STBY_THR_Pos

#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_STBY_THR_Pos   (0UL)

OTPC OTPC_TIM2_REG: OTPC_TIM2_CC_STBY_THR (Bit 0)

Definition at line 8729 of file DA14680BA.h.

◆ OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_T_BCHK_Msk

#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_T_BCHK_Msk   (0x7f0000UL)

OTPC OTPC_TIM2_REG: OTPC_TIM2_CC_T_BCHK (Bitfield-Mask: 0x7f)

Definition at line 8732 of file DA14680BA.h.

◆ OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_T_BCHK_Pos

#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_CC_T_BCHK_Pos   (16UL)

OTPC OTPC_TIM2_REG: OTPC_TIM2_CC_T_BCHK (Bit 16)

Definition at line 8731 of file DA14680BA.h.

◆ OTPC_OTPC_TIM2_REG_OTPC_TIM2_RDENL_PROT_Msk

#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_RDENL_PROT_Msk   (0x800000UL)

OTPC OTPC_TIM2_REG: OTPC_TIM2_RDENL_PROT (Bitfield-Mask: 0x01)

Definition at line 8734 of file DA14680BA.h.

◆ OTPC_OTPC_TIM2_REG_OTPC_TIM2_RDENL_PROT_Pos

#define OTPC_OTPC_TIM2_REG_OTPC_TIM2_RDENL_PROT_Pos   (23UL)

OTPC OTPC_TIM2_REG: OTPC_TIM2_RDENL_PROT (Bit 23)

Definition at line 8733 of file DA14680BA.h.

◆ PATCH

#define PATCH   ((PATCH_Type *) PATCH_BASE)

Definition at line 12096 of file DA14680BA.h.

◆ PATCH_BASE

#define PATCH_BASE   0x40050000UL

Definition at line 12051 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR0_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR0_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8768 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR0_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR0_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8767 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR0_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR0_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8766 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR0_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR0_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR0_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8765 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR10_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR10_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8828 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR10_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR10_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8827 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR10_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR10_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8826 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR10_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR10_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR10_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8825 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR11_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR11_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8834 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR11_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR11_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8833 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR11_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR11_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8832 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR11_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR11_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR11_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8831 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR12_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR12_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8840 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR12_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR12_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8839 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR12_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR12_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8838 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR12_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR12_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR12_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8837 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR13_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR13_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8846 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR13_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR13_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8845 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR13_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR13_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8844 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR13_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR13_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR13_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8843 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR14_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR14_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8852 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR14_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR14_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8851 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR14_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR14_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8850 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR14_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR14_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR14_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8849 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR15_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR15_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8858 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR15_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR15_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8857 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR15_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR15_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8856 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR15_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR15_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR15_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8855 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR16_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR16_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8864 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR16_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR16_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8863 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR16_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR16_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8862 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR16_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR16_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR16_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8861 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR17_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR17_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8870 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR17_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR17_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8869 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR17_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR17_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8868 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR17_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR17_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR17_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8867 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR18_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR18_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8876 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR18_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR18_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8875 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR18_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR18_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8874 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR18_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR18_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR18_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8873 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR19_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR19_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8882 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR19_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR19_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8881 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR19_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR19_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8880 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR19_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR19_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR19_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8879 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR1_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR1_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8774 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR1_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR1_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8773 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR1_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR1_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8772 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR1_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR1_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR1_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8771 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR20_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR20_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8888 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR20_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR20_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8887 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR20_REG_PATCH_ADDR_D_Msk

#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)

PATCH PATCH_ADDR20_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff)

Definition at line 8886 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR20_REG_PATCH_ADDR_D_Pos

#define PATCH_PATCH_ADDR20_REG_PATCH_ADDR_D_Pos   (2UL)

PATCH PATCH_ADDR20_REG: PATCH_ADDR_D (Bit 2)

Definition at line 8885 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR21_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR21_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8898 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR21_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR21_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8897 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR21_REG_PATCH_ADDR_D_Msk

#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)

PATCH PATCH_ADDR21_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff)

Definition at line 8896 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR21_REG_PATCH_ADDR_D_Pos

#define PATCH_PATCH_ADDR21_REG_PATCH_ADDR_D_Pos   (2UL)

PATCH PATCH_ADDR21_REG: PATCH_ADDR_D (Bit 2)

Definition at line 8895 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR22_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR22_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8908 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR22_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR22_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8907 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR22_REG_PATCH_ADDR_D_Msk

#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)

PATCH PATCH_ADDR22_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff)

Definition at line 8906 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR22_REG_PATCH_ADDR_D_Pos

#define PATCH_PATCH_ADDR22_REG_PATCH_ADDR_D_Pos   (2UL)

PATCH PATCH_ADDR22_REG: PATCH_ADDR_D (Bit 2)

Definition at line 8905 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR23_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR23_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8918 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR23_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR23_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8917 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR23_REG_PATCH_ADDR_D_Msk

#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)

PATCH PATCH_ADDR23_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff)

Definition at line 8916 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR23_REG_PATCH_ADDR_D_Pos

#define PATCH_PATCH_ADDR23_REG_PATCH_ADDR_D_Pos   (2UL)

PATCH PATCH_ADDR23_REG: PATCH_ADDR_D (Bit 2)

Definition at line 8915 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR24_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR24_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8928 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR24_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR24_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8927 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR24_REG_PATCH_ADDR_D_Msk

#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)

PATCH PATCH_ADDR24_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff)

Definition at line 8926 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR24_REG_PATCH_ADDR_D_Pos

#define PATCH_PATCH_ADDR24_REG_PATCH_ADDR_D_Pos   (2UL)

PATCH PATCH_ADDR24_REG: PATCH_ADDR_D (Bit 2)

Definition at line 8925 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR25_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR25_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8938 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR25_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR25_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8937 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR25_REG_PATCH_ADDR_D_Msk

#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)

PATCH PATCH_ADDR25_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff)

Definition at line 8936 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR25_REG_PATCH_ADDR_D_Pos

#define PATCH_PATCH_ADDR25_REG_PATCH_ADDR_D_Pos   (2UL)

PATCH PATCH_ADDR25_REG: PATCH_ADDR_D (Bit 2)

Definition at line 8935 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR26_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR26_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8948 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR26_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR26_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8947 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR26_REG_PATCH_ADDR_D_Msk

#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)

PATCH PATCH_ADDR26_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff)

Definition at line 8946 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR26_REG_PATCH_ADDR_D_Pos

#define PATCH_PATCH_ADDR26_REG_PATCH_ADDR_D_Pos   (2UL)

PATCH PATCH_ADDR26_REG: PATCH_ADDR_D (Bit 2)

Definition at line 8945 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR27_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR27_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8958 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR27_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR27_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8957 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR27_REG_PATCH_ADDR_D_Msk

#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_D_Msk   (0x1fffcUL)

PATCH PATCH_ADDR27_REG: PATCH_ADDR_D (Bitfield-Mask: 0x7fff)

Definition at line 8956 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR27_REG_PATCH_ADDR_D_Pos

#define PATCH_PATCH_ADDR27_REG_PATCH_ADDR_D_Pos   (2UL)

PATCH PATCH_ADDR27_REG: PATCH_ADDR_D (Bit 2)

Definition at line 8955 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR2_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR2_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8780 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR2_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR2_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8779 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR2_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR2_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8778 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR2_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR2_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR2_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8777 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR3_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR3_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8786 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR3_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR3_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8785 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR3_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR3_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8784 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR3_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR3_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR3_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8783 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR4_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR4_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8792 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR4_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR4_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8791 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR4_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR4_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8790 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR4_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR4_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR4_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8789 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR5_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR5_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8798 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR5_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR5_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8797 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR5_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR5_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8796 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR5_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR5_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR5_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8795 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR6_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR6_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8804 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR6_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR6_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8803 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR6_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR6_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8802 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR6_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR6_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR6_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8801 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR7_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR7_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8810 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR7_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR7_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8809 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR7_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR7_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8808 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR7_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR7_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR7_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8807 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR8_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR8_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8816 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR8_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR8_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8815 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR8_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR8_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8814 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR8_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR8_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR8_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8813 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR9_REG_PATCH_ADDR_19_Msk

#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_19_Msk   (0x80000UL)

PATCH PATCH_ADDR9_REG: PATCH_ADDR_19 (Bitfield-Mask: 0x01)

Definition at line 8822 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR9_REG_PATCH_ADDR_19_Pos

#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_19_Pos   (19UL)

PATCH PATCH_ADDR9_REG: PATCH_ADDR_19 (Bit 19)

Definition at line 8821 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR9_REG_PATCH_ADDR_C_Msk

#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_C_Msk   (0x1fffeUL)

PATCH PATCH_ADDR9_REG: PATCH_ADDR_C (Bitfield-Mask: 0xffff)

Definition at line 8820 of file DA14680BA.h.

◆ PATCH_PATCH_ADDR9_REG_PATCH_ADDR_C_Pos

#define PATCH_PATCH_ADDR9_REG_PATCH_ADDR_C_Pos   (1UL)

PATCH PATCH_ADDR9_REG: PATCH_ADDR_C (Bit 1)

Definition at line 8819 of file DA14680BA.h.

◆ PATCH_PATCH_DATA20_REG_PATCH_DATA_Msk

#define PATCH_PATCH_DATA20_REG_PATCH_DATA_Msk   (0xffffffffUL)

PATCH PATCH_DATA20_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff)

Definition at line 8892 of file DA14680BA.h.

◆ PATCH_PATCH_DATA20_REG_PATCH_DATA_Pos

#define PATCH_PATCH_DATA20_REG_PATCH_DATA_Pos   (0UL)

PATCH PATCH_DATA20_REG: PATCH_DATA (Bit 0)

Definition at line 8891 of file DA14680BA.h.

◆ PATCH_PATCH_DATA21_REG_PATCH_DATA_Msk

#define PATCH_PATCH_DATA21_REG_PATCH_DATA_Msk   (0xffffffffUL)

PATCH PATCH_DATA21_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff)

Definition at line 8902 of file DA14680BA.h.

◆ PATCH_PATCH_DATA21_REG_PATCH_DATA_Pos

#define PATCH_PATCH_DATA21_REG_PATCH_DATA_Pos   (0UL)

PATCH PATCH_DATA21_REG: PATCH_DATA (Bit 0)

Definition at line 8901 of file DA14680BA.h.

◆ PATCH_PATCH_DATA22_REG_PATCH_DATA_Msk

#define PATCH_PATCH_DATA22_REG_PATCH_DATA_Msk   (0xffffffffUL)

PATCH PATCH_DATA22_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff)

Definition at line 8912 of file DA14680BA.h.

◆ PATCH_PATCH_DATA22_REG_PATCH_DATA_Pos

#define PATCH_PATCH_DATA22_REG_PATCH_DATA_Pos   (0UL)

PATCH PATCH_DATA22_REG: PATCH_DATA (Bit 0)

Definition at line 8911 of file DA14680BA.h.

◆ PATCH_PATCH_DATA23_REG_PATCH_DATA_Msk

#define PATCH_PATCH_DATA23_REG_PATCH_DATA_Msk   (0xffffffffUL)

PATCH PATCH_DATA23_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff)

Definition at line 8922 of file DA14680BA.h.

◆ PATCH_PATCH_DATA23_REG_PATCH_DATA_Pos

#define PATCH_PATCH_DATA23_REG_PATCH_DATA_Pos   (0UL)

PATCH PATCH_DATA23_REG: PATCH_DATA (Bit 0)

Definition at line 8921 of file DA14680BA.h.

◆ PATCH_PATCH_DATA24_REG_PATCH_DATA_Msk

#define PATCH_PATCH_DATA24_REG_PATCH_DATA_Msk   (0xffffffffUL)

PATCH PATCH_DATA24_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff)

Definition at line 8932 of file DA14680BA.h.

◆ PATCH_PATCH_DATA24_REG_PATCH_DATA_Pos

#define PATCH_PATCH_DATA24_REG_PATCH_DATA_Pos   (0UL)

PATCH PATCH_DATA24_REG: PATCH_DATA (Bit 0)

Definition at line 8931 of file DA14680BA.h.

◆ PATCH_PATCH_DATA25_REG_PATCH_DATA_Msk

#define PATCH_PATCH_DATA25_REG_PATCH_DATA_Msk   (0xffffffffUL)

PATCH PATCH_DATA25_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff)

Definition at line 8942 of file DA14680BA.h.

◆ PATCH_PATCH_DATA25_REG_PATCH_DATA_Pos

#define PATCH_PATCH_DATA25_REG_PATCH_DATA_Pos   (0UL)

PATCH PATCH_DATA25_REG: PATCH_DATA (Bit 0)

Definition at line 8941 of file DA14680BA.h.

◆ PATCH_PATCH_DATA26_REG_PATCH_DATA_Msk

#define PATCH_PATCH_DATA26_REG_PATCH_DATA_Msk   (0xffffffffUL)

PATCH PATCH_DATA26_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff)

Definition at line 8952 of file DA14680BA.h.

◆ PATCH_PATCH_DATA26_REG_PATCH_DATA_Pos

#define PATCH_PATCH_DATA26_REG_PATCH_DATA_Pos   (0UL)

PATCH PATCH_DATA26_REG: PATCH_DATA (Bit 0)

Definition at line 8951 of file DA14680BA.h.

◆ PATCH_PATCH_DATA27_REG_PATCH_DATA_Msk

#define PATCH_PATCH_DATA27_REG_PATCH_DATA_Msk   (0xffffffffUL)

PATCH PATCH_DATA27_REG: PATCH_DATA (Bitfield-Mask: 0xffffffff)

Definition at line 8962 of file DA14680BA.h.

◆ PATCH_PATCH_DATA27_REG_PATCH_DATA_Pos

#define PATCH_PATCH_DATA27_REG_PATCH_DATA_Pos   (0UL)

PATCH PATCH_DATA27_REG: PATCH_DATA (Bit 0)

Definition at line 8961 of file DA14680BA.h.

◆ PATCH_PATCH_VALID_REG_PATCH_VALID_Msk

#define PATCH_PATCH_VALID_REG_PATCH_VALID_Msk   (0xfffffffUL)

PATCH PATCH_VALID_REG: PATCH_VALID (Bitfield-Mask: 0xfffffff)

Definition at line 8754 of file DA14680BA.h.

◆ PATCH_PATCH_VALID_REG_PATCH_VALID_Pos

#define PATCH_PATCH_VALID_REG_PATCH_VALID_Pos   (0UL)

PATCH PATCH_VALID_REG: PATCH_VALID (Bit 0)

Definition at line 8753 of file DA14680BA.h.

◆ PATCH_PATCH_VALID_RESET_REG_PATCH_VALID_Msk

#define PATCH_PATCH_VALID_RESET_REG_PATCH_VALID_Msk   (0xfffffffUL)

PATCH PATCH_VALID_RESET_REG: PATCH_VALID (Bitfield-Mask: 0xfffffff)

Definition at line 8762 of file DA14680BA.h.

◆ PATCH_PATCH_VALID_RESET_REG_PATCH_VALID_Pos

#define PATCH_PATCH_VALID_RESET_REG_PATCH_VALID_Pos   (0UL)

PATCH PATCH_VALID_RESET_REG: PATCH_VALID (Bit 0)

Definition at line 8761 of file DA14680BA.h.

◆ PATCH_PATCH_VALID_SET_REG_PATCH_VALID_Msk

#define PATCH_PATCH_VALID_SET_REG_PATCH_VALID_Msk   (0xfffffffUL)

PATCH PATCH_VALID_SET_REG: PATCH_VALID (Bitfield-Mask: 0xfffffff)

Definition at line 8758 of file DA14680BA.h.

◆ PATCH_PATCH_VALID_SET_REG_PATCH_VALID_Pos

#define PATCH_PATCH_VALID_SET_REG_PATCH_VALID_Pos   (0UL)

PATCH PATCH_VALID_SET_REG: PATCH_VALID (Bit 0)

Definition at line 8757 of file DA14680BA.h.

◆ PLLDIG

#define PLLDIG   ((PLLDIG_Type *) PLLDIG_BASE)

Definition at line 12097 of file DA14680BA.h.

◆ PLLDIG_BASE

#define PLLDIG_BASE   0x50002D00UL

Definition at line 12052 of file DA14680BA.h.

◆ PLLDIG_RF_BMCW_REG_CN_SEL_Msk

#define PLLDIG_RF_BMCW_REG_CN_SEL_Msk   (0x80UL)

PLLDIG RF_BMCW_REG: CN_SEL (Bitfield-Mask: 0x01)

Definition at line 9086 of file DA14680BA.h.

◆ PLLDIG_RF_BMCW_REG_CN_SEL_Pos

#define PLLDIG_RF_BMCW_REG_CN_SEL_Pos   (7UL)

PLLDIG RF_BMCW_REG: CN_SEL (Bit 7)

Definition at line 9085 of file DA14680BA.h.

◆ PLLDIG_RF_BMCW_REG_CN_WR_Msk

#define PLLDIG_RF_BMCW_REG_CN_WR_Msk   (0x3fUL)

PLLDIG RF_BMCW_REG: CN_WR (Bitfield-Mask: 0x3f)

Definition at line 9082 of file DA14680BA.h.

◆ PLLDIG_RF_BMCW_REG_CN_WR_Pos

#define PLLDIG_RF_BMCW_REG_CN_WR_Pos   (0UL)

PLLDIG RF_BMCW_REG: CN_WR (Bit 0)

Definition at line 9081 of file DA14680BA.h.

◆ PLLDIG_RF_BMCW_REG_HSI_SEL_Msk

#define PLLDIG_RF_BMCW_REG_HSI_SEL_Msk   (0x100UL)

PLLDIG RF_BMCW_REG: HSI_SEL (Bitfield-Mask: 0x01)

Definition at line 9088 of file DA14680BA.h.

◆ PLLDIG_RF_BMCW_REG_HSI_SEL_Pos

#define PLLDIG_RF_BMCW_REG_HSI_SEL_Pos   (8UL)

PLLDIG RF_BMCW_REG: HSI_SEL (Bit 8)

Definition at line 9087 of file DA14680BA.h.

◆ PLLDIG_RF_BMCW_REG_HSI_WR_Msk

#define PLLDIG_RF_BMCW_REG_HSI_WR_Msk   (0x40UL)

PLLDIG RF_BMCW_REG: HSI_WR (Bitfield-Mask: 0x01)

Definition at line 9084 of file DA14680BA.h.

◆ PLLDIG_RF_BMCW_REG_HSI_WR_Pos

#define PLLDIG_RF_BMCW_REG_HSI_WR_Pos   (6UL)

PLLDIG RF_BMCW_REG: HSI_WR (Bit 6)

Definition at line 9083 of file DA14680BA.h.

◆ PLLDIG_RF_CALCAP1_REG_VCO_CALCAP_LOW_Msk

#define PLLDIG_RF_CALCAP1_REG_VCO_CALCAP_LOW_Msk   (0xffffUL)

PLLDIG RF_CALCAP1_REG: VCO_CALCAP_LOW (Bitfield-Mask: 0xffff)

Definition at line 9126 of file DA14680BA.h.

◆ PLLDIG_RF_CALCAP1_REG_VCO_CALCAP_LOW_Pos

#define PLLDIG_RF_CALCAP1_REG_VCO_CALCAP_LOW_Pos   (0UL)

PLLDIG RF_CALCAP1_REG: VCO_CALCAP_LOW (Bit 0)

Definition at line 9125 of file DA14680BA.h.

◆ PLLDIG_RF_CALCAP2_REG_VCO_CALCAP_HIGH_Msk

#define PLLDIG_RF_CALCAP2_REG_VCO_CALCAP_HIGH_Msk   (0x3UL)

PLLDIG RF_CALCAP2_REG: VCO_CALCAP_HIGH (Bitfield-Mask: 0x03)

Definition at line 9130 of file DA14680BA.h.

◆ PLLDIG_RF_CALCAP2_REG_VCO_CALCAP_HIGH_Pos

#define PLLDIG_RF_CALCAP2_REG_VCO_CALCAP_HIGH_Pos   (0UL)

PLLDIG RF_CALCAP2_REG: VCO_CALCAP_HIGH (Bit 0)

Definition at line 9129 of file DA14680BA.h.

◆ PLLDIG_RF_CALTRIM_STEP1_REG_MDSTATE_RD_Msk

#define PLLDIG_RF_CALTRIM_STEP1_REG_MDSTATE_RD_Msk   (0xffffUL)

PLLDIG RF_CALTRIM_STEP1_REG: MDSTATE_RD (Bitfield-Mask: 0xffff)

Definition at line 9144 of file DA14680BA.h.

◆ PLLDIG_RF_CALTRIM_STEP1_REG_MDSTATE_RD_Pos

#define PLLDIG_RF_CALTRIM_STEP1_REG_MDSTATE_RD_Pos   (0UL)

PLLDIG RF_CALTRIM_STEP1_REG: MDSTATE_RD (Bit 0)

Definition at line 9143 of file DA14680BA.h.

◆ PLLDIG_RF_CALTRIM_STEP2_REG_MDSTATE_RD_Msk

#define PLLDIG_RF_CALTRIM_STEP2_REG_MDSTATE_RD_Msk   (0xffffUL)

PLLDIG RF_CALTRIM_STEP2_REG: MDSTATE_RD (Bitfield-Mask: 0xffff)

Definition at line 9148 of file DA14680BA.h.

◆ PLLDIG_RF_CALTRIM_STEP2_REG_MDSTATE_RD_Pos

#define PLLDIG_RF_CALTRIM_STEP2_REG_MDSTATE_RD_Pos   (0UL)

PLLDIG RF_CALTRIM_STEP2_REG: MDSTATE_RD (Bit 0)

Definition at line 9147 of file DA14680BA.h.

◆ PLLDIG_RF_CALTRIM_STEP3_REG_MDSTATE_RD_Msk

#define PLLDIG_RF_CALTRIM_STEP3_REG_MDSTATE_RD_Msk   (0xffffUL)

PLLDIG RF_CALTRIM_STEP3_REG: MDSTATE_RD (Bitfield-Mask: 0xffff)

Definition at line 9152 of file DA14680BA.h.

◆ PLLDIG_RF_CALTRIM_STEP3_REG_MDSTATE_RD_Pos

#define PLLDIG_RF_CALTRIM_STEP3_REG_MDSTATE_RD_Pos   (0UL)

PLLDIG RF_CALTRIM_STEP3_REG: MDSTATE_RD (Bit 0)

Definition at line 9151 of file DA14680BA.h.

◆ PLLDIG_RF_CALTRIM_STEP4_REG_MDSTATE_RD_Msk

#define PLLDIG_RF_CALTRIM_STEP4_REG_MDSTATE_RD_Msk   (0xffffUL)

PLLDIG RF_CALTRIM_STEP4_REG: MDSTATE_RD (Bitfield-Mask: 0xffff)

Definition at line 9156 of file DA14680BA.h.

◆ PLLDIG_RF_CALTRIM_STEP4_REG_MDSTATE_RD_Pos

#define PLLDIG_RF_CALTRIM_STEP4_REG_MDSTATE_RD_Pos   (0UL)

PLLDIG RF_CALTRIM_STEP4_REG: MDSTATE_RD (Bit 0)

Definition at line 9155 of file DA14680BA.h.

◆ PLLDIG_RF_FTDF_PHYATTR_REG_FTDF_PHYATTR_Msk

#define PLLDIG_RF_FTDF_PHYATTR_REG_FTDF_PHYATTR_Msk   (0xffffUL)

PLLDIG RF_FTDF_PHYATTR_REG: FTDF_PHYATTR (Bitfield-Mask: 0xffff)

Definition at line 9140 of file DA14680BA.h.

◆ PLLDIG_RF_FTDF_PHYATTR_REG_FTDF_PHYATTR_Pos

#define PLLDIG_RF_FTDF_PHYATTR_REG_FTDF_PHYATTR_Pos   (0UL)

PLLDIG RF_FTDF_PHYATTR_REG: FTDF_PHYATTR (Bit 0)

Definition at line 9139 of file DA14680BA.h.

◆ PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_GAUSSDAC_Msk

#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_GAUSSDAC_Msk   (0x3fUL)

PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_GAUSSDAC (Bitfield-Mask: 0x3f)

Definition at line 9092 of file DA14680BA.h.

◆ PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_GAUSSDAC_Pos

#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_GAUSSDAC_Pos   (0UL)

PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_GAUSSDAC (Bit 0)

Definition at line 9091 of file DA14680BA.h.

◆ PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_TXDAC_Msk

#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_TXDAC_Msk   (0xfc0UL)

PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_TXDAC (Bitfield-Mask: 0x3f)

Definition at line 9094 of file DA14680BA.h.

◆ PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_TXDAC_Pos

#define PLLDIG_RF_KMOD_ALPHA_BLE_REG_KMOD_ALPHA_TXDAC_Pos   (6UL)

PLLDIG RF_KMOD_ALPHA_BLE_REG: KMOD_ALPHA_TXDAC (Bit 6)

Definition at line 9093 of file DA14680BA.h.

◆ PLLDIG_RF_KMOD_ALPHA_FTDF_REG_KMOD_ALPHA_FTDF_Msk

#define PLLDIG_RF_KMOD_ALPHA_FTDF_REG_KMOD_ALPHA_FTDF_Msk   (0x3fUL)

PLLDIG RF_KMOD_ALPHA_FTDF_REG: KMOD_ALPHA_FTDF (Bitfield-Mask: 0x3f)

Definition at line 9098 of file DA14680BA.h.

◆ PLLDIG_RF_KMOD_ALPHA_FTDF_REG_KMOD_ALPHA_FTDF_Pos

#define PLLDIG_RF_KMOD_ALPHA_FTDF_REG_KMOD_ALPHA_FTDF_Pos   (0UL)

PLLDIG RF_KMOD_ALPHA_FTDF_REG: KMOD_ALPHA_FTDF (Bit 0)

Definition at line 9097 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL0_REG_MGAIN_COMP_VAL_Msk

#define PLLDIG_RF_MGAIN_COMP_VAL0_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)

PLLDIG RF_MGAIN_COMP_VAL0_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f)

Definition at line 9204 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL0_REG_MGAIN_COMP_VAL_Pos

#define PLLDIG_RF_MGAIN_COMP_VAL0_REG_MGAIN_COMP_VAL_Pos   (0UL)

PLLDIG RF_MGAIN_COMP_VAL0_REG: MGAIN_COMP_VAL (Bit 0)

Definition at line 9203 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL1_REG_MGAIN_COMP_VAL_Msk

#define PLLDIG_RF_MGAIN_COMP_VAL1_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)

PLLDIG RF_MGAIN_COMP_VAL1_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f)

Definition at line 9208 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL1_REG_MGAIN_COMP_VAL_Pos

#define PLLDIG_RF_MGAIN_COMP_VAL1_REG_MGAIN_COMP_VAL_Pos   (0UL)

PLLDIG RF_MGAIN_COMP_VAL1_REG: MGAIN_COMP_VAL (Bit 0)

Definition at line 9207 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL2_REG_MGAIN_COMP_VAL_Msk

#define PLLDIG_RF_MGAIN_COMP_VAL2_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)

PLLDIG RF_MGAIN_COMP_VAL2_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f)

Definition at line 9212 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL2_REG_MGAIN_COMP_VAL_Pos

#define PLLDIG_RF_MGAIN_COMP_VAL2_REG_MGAIN_COMP_VAL_Pos   (0UL)

PLLDIG RF_MGAIN_COMP_VAL2_REG: MGAIN_COMP_VAL (Bit 0)

Definition at line 9211 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL3_REG_MGAIN_COMP_VAL_Msk

#define PLLDIG_RF_MGAIN_COMP_VAL3_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)

PLLDIG RF_MGAIN_COMP_VAL3_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f)

Definition at line 9216 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL3_REG_MGAIN_COMP_VAL_Pos

#define PLLDIG_RF_MGAIN_COMP_VAL3_REG_MGAIN_COMP_VAL_Pos   (0UL)

PLLDIG RF_MGAIN_COMP_VAL3_REG: MGAIN_COMP_VAL (Bit 0)

Definition at line 9215 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL4_REG_MGAIN_COMP_VAL_Msk

#define PLLDIG_RF_MGAIN_COMP_VAL4_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)

PLLDIG RF_MGAIN_COMP_VAL4_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f)

Definition at line 9220 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL4_REG_MGAIN_COMP_VAL_Pos

#define PLLDIG_RF_MGAIN_COMP_VAL4_REG_MGAIN_COMP_VAL_Pos   (0UL)

PLLDIG RF_MGAIN_COMP_VAL4_REG: MGAIN_COMP_VAL (Bit 0)

Definition at line 9219 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL5_REG_MGAIN_COMP_VAL_Msk

#define PLLDIG_RF_MGAIN_COMP_VAL5_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)

PLLDIG RF_MGAIN_COMP_VAL5_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f)

Definition at line 9224 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL5_REG_MGAIN_COMP_VAL_Pos

#define PLLDIG_RF_MGAIN_COMP_VAL5_REG_MGAIN_COMP_VAL_Pos   (0UL)

PLLDIG RF_MGAIN_COMP_VAL5_REG: MGAIN_COMP_VAL (Bit 0)

Definition at line 9223 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL6_REG_MGAIN_COMP_VAL_Msk

#define PLLDIG_RF_MGAIN_COMP_VAL6_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)

PLLDIG RF_MGAIN_COMP_VAL6_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f)

Definition at line 9228 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL6_REG_MGAIN_COMP_VAL_Pos

#define PLLDIG_RF_MGAIN_COMP_VAL6_REG_MGAIN_COMP_VAL_Pos   (0UL)

PLLDIG RF_MGAIN_COMP_VAL6_REG: MGAIN_COMP_VAL (Bit 0)

Definition at line 9227 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL7_REG_MGAIN_COMP_VAL_Msk

#define PLLDIG_RF_MGAIN_COMP_VAL7_REG_MGAIN_COMP_VAL_Msk   (0x1fUL)

PLLDIG RF_MGAIN_COMP_VAL7_REG: MGAIN_COMP_VAL (Bitfield-Mask: 0x1f)

Definition at line 9232 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_COMP_VAL7_REG_MGAIN_COMP_VAL_Pos

#define PLLDIG_RF_MGAIN_COMP_VAL7_REG_MGAIN_COMP_VAL_Pos   (0UL)

PLLDIG RF_MGAIN_COMP_VAL7_REG: MGAIN_COMP_VAL (Bit 0)

Definition at line 9231 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_MODE_SEL_Msk

#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_MODE_SEL_Msk   (0x80UL)

PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_MODE_SEL (Bitfield-Mask: 0x01)

Definition at line 9068 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_MODE_SEL_Pos

#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_MODE_SEL_Pos   (7UL)

PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_MODE_SEL (Bit 7)

Definition at line 9067 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_TRANSMIT_LENGTH_Msk

#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_TRANSMIT_LENGTH_Msk   (0x7fUL)

PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_TRANSMIT_LENGTH (Bitfield-Mask: 0x7f)

Definition at line 9066 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_TRANSMIT_LENGTH_Pos

#define PLLDIG_RF_MGAIN_CTRL2_REG_MGAIN_TRANSMIT_LENGTH_Pos   (0UL)

PLLDIG RF_MGAIN_CTRL2_REG: MGAIN_TRANSMIT_LENGTH (Bit 0)

Definition at line 9065 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL2_REG_MSK_GAINCAL_LONG_Msk

#define PLLDIG_RF_MGAIN_CTRL2_REG_MSK_GAINCAL_LONG_Msk   (0x100UL)

PLLDIG RF_MGAIN_CTRL2_REG: MSK_GAINCAL_LONG (Bitfield-Mask: 0x01)

Definition at line 9070 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL2_REG_MSK_GAINCAL_LONG_Pos

#define PLLDIG_RF_MGAIN_CTRL2_REG_MSK_GAINCAL_LONG_Pos   (8UL)

PLLDIG RF_MGAIN_CTRL2_REG: MSK_GAINCAL_LONG (Bit 8)

Definition at line 9069 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL3_REG_GFSK_GAIN_OFFSET_Msk

#define PLLDIG_RF_MGAIN_CTRL3_REG_GFSK_GAIN_OFFSET_Msk   (0xffUL)

PLLDIG RF_MGAIN_CTRL3_REG: GFSK_GAIN_OFFSET (Bitfield-Mask: 0xff)

Definition at line 9160 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL3_REG_GFSK_GAIN_OFFSET_Pos

#define PLLDIG_RF_MGAIN_CTRL3_REG_GFSK_GAIN_OFFSET_Pos   (0UL)

PLLDIG RF_MGAIN_CTRL3_REG: GFSK_GAIN_OFFSET (Bit 0)

Definition at line 9159 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_BLE_REG_BLE_TESTPAT_GEN_Msk

#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_BLE_TESTPAT_GEN_Msk   (0x200UL)

PLLDIG RF_MGAIN_CTRL_BLE_REG: BLE_TESTPAT_GEN (Bitfield-Mask: 0x01)

Definition at line 9050 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_BLE_REG_BLE_TESTPAT_GEN_Pos

#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_BLE_TESTPAT_GEN_Pos   (9UL)

PLLDIG RF_MGAIN_CTRL_BLE_REG: BLE_TESTPAT_GEN (Bit 9)

Definition at line 9049 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_SEL_Msk

#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_SEL_Msk   (0x100UL)

PLLDIG RF_MGAIN_CTRL_BLE_REG: GAUSS_GAIN_SEL (Bitfield-Mask: 0x01)

Definition at line 9048 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_SEL_Pos

#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_SEL_Pos   (8UL)

PLLDIG RF_MGAIN_CTRL_BLE_REG: GAUSS_GAIN_SEL (Bit 8)

Definition at line 9047 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_WR_Msk

#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_WR_Msk   (0xffUL)

PLLDIG RF_MGAIN_CTRL_BLE_REG: GAUSS_GAIN_WR (Bitfield-Mask: 0xff)

Definition at line 9046 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_WR_Pos

#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_GAUSS_GAIN_WR_Pos   (0UL)

PLLDIG RF_MGAIN_CTRL_BLE_REG: GAUSS_GAIN_WR (Bit 0)

Definition at line 9045 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_AVER_Msk

#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_AVER_Msk   (0x1800UL)

PLLDIG RF_MGAIN_CTRL_BLE_REG: MGAIN_AVER (Bitfield-Mask: 0x03)

Definition at line 9054 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_AVER_Pos

#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_AVER_Pos   (11UL)

PLLDIG RF_MGAIN_CTRL_BLE_REG: MGAIN_AVER (Bit 11)

Definition at line 9053 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_CMP_INV_Msk

#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_CMP_INV_Msk   (0x400UL)

PLLDIG RF_MGAIN_CTRL_BLE_REG: MGAIN_CMP_INV (Bitfield-Mask: 0x01)

Definition at line 9052 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_CMP_INV_Pos

#define PLLDIG_RF_MGAIN_CTRL_BLE_REG_MGAIN_CMP_INV_Pos   (10UL)

PLLDIG RF_MGAIN_CTRL_BLE_REG: MGAIN_CMP_INV (Bit 10)

Definition at line 9051 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_OFFSET_Msk

#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_OFFSET_Msk   (0xff00UL)

PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_OFFSET (Bitfield-Mask: 0xff)

Definition at line 9062 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_OFFSET_Pos

#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_OFFSET_Pos   (8UL)

PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_OFFSET (Bit 8)

Definition at line 9061 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Msk

#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Msk   (0x80UL)

PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_SEL (Bitfield-Mask: 0x01)

Definition at line 9060 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Pos

#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_SEL_Pos   (7UL)

PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_SEL (Bit 7)

Definition at line 9059 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_WR_Msk

#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_WR_Msk   (0x7fUL)

PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_WR (Bitfield-Mask: 0x7f)

Definition at line 9058 of file DA14680BA.h.

◆ PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_WR_Pos

#define PLLDIG_RF_MGAIN_CTRL_FTDF_REG_MSK_GAIN_WR_Pos   (0UL)

PLLDIG RF_MGAIN_CTRL_FTDF_REG: MSK_GAIN_WR (Bit 0)

Definition at line 9057 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CHIPH_REG_MSK_CHIPH_Msk

#define PLLDIG_RF_MSKMOD_CHIPH_REG_MSK_CHIPH_Msk   (0xffffUL)

PLLDIG RF_MSKMOD_CHIPH_REG: MSK_CHIPH (Bitfield-Mask: 0xffff)

Definition at line 9194 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CHIPH_REG_MSK_CHIPH_Pos

#define PLLDIG_RF_MSKMOD_CHIPH_REG_MSK_CHIPH_Pos   (0UL)

PLLDIG RF_MSKMOD_CHIPH_REG: MSK_CHIPH (Bit 0)

Definition at line 9193 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CHIPL_REG_MSK_CHIPL_Msk

#define PLLDIG_RF_MSKMOD_CHIPL_REG_MSK_CHIPL_Msk   (0xffffUL)

PLLDIG RF_MSKMOD_CHIPL_REG: MSK_CHIPL (Bitfield-Mask: 0xffff)

Definition at line 9190 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CHIPL_REG_MSK_CHIPL_Pos

#define PLLDIG_RF_MSKMOD_CHIPL_REG_MSK_CHIPL_Pos   (0UL)

PLLDIG RF_MSKMOD_CHIPL_REG: MSK_CHIPL (Bit 0)

Definition at line 9189 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_ALW_EN_Msk

#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_ALW_EN_Msk   (0x40UL)

PLLDIG RF_MSKMOD_CTRL1_REG: MSK_ALW_EN (Bitfield-Mask: 0x01)

Definition at line 9182 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_ALW_EN_Pos

#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_ALW_EN_Pos   (6UL)

PLLDIG RF_MSKMOD_CTRL1_REG: MSK_ALW_EN (Bit 6)

Definition at line 9181 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Msk

#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Msk   (0x100UL)

PLLDIG RF_MSKMOD_CTRL1_REG: MSK_BYPASS_PHASE (Bitfield-Mask: 0x01)

Definition at line 9186 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Pos

#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_BYPASS_PHASE_Pos   (8UL)

PLLDIG RF_MSKMOD_CTRL1_REG: MSK_BYPASS_PHASE (Bit 8)

Definition at line 9185 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_TX_SEL_Msk

#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_TX_SEL_Msk   (0x20UL)

PLLDIG RF_MSKMOD_CTRL1_REG: MSK_TX_SEL (Bitfield-Mask: 0x01)

Definition at line 9180 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_TX_SEL_Pos

#define PLLDIG_RF_MSKMOD_CTRL1_REG_MSK_TX_SEL_Pos   (5UL)

PLLDIG RF_MSKMOD_CTRL1_REG: MSK_TX_SEL (Bit 5)

Definition at line 9179 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DATA_Msk

#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DATA_Msk   (0xfUL)

PLLDIG RF_MSKMOD_CTRL1_REG: TX_DATA (Bitfield-Mask: 0x0f)

Definition at line 9176 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DATA_Pos

#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_DATA_Pos   (0UL)

PLLDIG RF_MSKMOD_CTRL1_REG: TX_DATA (Bit 0)

Definition at line 9175 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Msk

#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Msk   (0x80UL)

PLLDIG RF_MSKMOD_CTRL1_REG: TX_MOD_FROM_GPIO (Bitfield-Mask: 0x01)

Definition at line 9184 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Pos

#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_MOD_FROM_GPIO_Pos   (7UL)

PLLDIG RF_MSKMOD_CTRL1_REG: TX_MOD_FROM_GPIO (Bit 7)

Definition at line 9183 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CTRL1_REG_TX_VALID_Msk

#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_VALID_Msk   (0x10UL)

PLLDIG RF_MSKMOD_CTRL1_REG: TX_VALID (Bitfield-Mask: 0x01)

Definition at line 9178 of file DA14680BA.h.

◆ PLLDIG_RF_MSKMOD_CTRL1_REG_TX_VALID_Pos

#define PLLDIG_RF_MSKMOD_CTRL1_REG_TX_VALID_Pos   (4UL)

PLLDIG RF_MSKMOD_CTRL1_REG: TX_VALID (Bit 4)

Definition at line 9177 of file DA14680BA.h.

◆ PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_PLL96M_Msk

#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_PLL96M_Msk   (0xff00UL)

PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_PLL96M (Bitfield-Mask: 0xff)

Definition at line 9136 of file DA14680BA.h.

◆ PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_PLL96M_Pos

#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_PLL96M_Pos   (8UL)

PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_PLL96M (Bit 8)

Definition at line 9135 of file DA14680BA.h.

◆ PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_XTAL16M_Msk

#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_XTAL16M_Msk   (0xffUL)

PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_XTAL16M (Bitfield-Mask: 0xff)

Definition at line 9134 of file DA14680BA.h.

◆ PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_XTAL16M_Pos

#define PLLDIG_RF_NMD_OFFSET_REG_NMD_OFFSET_XTAL16M_Pos   (0UL)

PLLDIG RF_NMD_OFFSET_REG: NMD_OFFSET_XTAL16M (Bit 0)

Definition at line 9133 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_CTRL_REG_FTDF_LOWPASS_EN_Msk

#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_LOWPASS_EN_Msk   (0x8UL)

PLLDIG RF_PULSE_CTRL_REG: FTDF_LOWPASS_EN (Bitfield-Mask: 0x01)

Definition at line 9272 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_CTRL_REG_FTDF_LOWPASS_EN_Pos

#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_LOWPASS_EN_Pos   (3UL)

PLLDIG RF_PULSE_CTRL_REG: FTDF_LOWPASS_EN (Bit 3)

Definition at line 9271 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GAIN_Msk

#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GAIN_Msk   (0xf0UL)

PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GAIN (Bitfield-Mask: 0x0f)

Definition at line 9274 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GAIN_Pos

#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GAIN_Pos   (4UL)

PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GAIN (Bit 4)

Definition at line 9273 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GATE_Msk

#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GATE_Msk   (0x6UL)

PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GATE (Bitfield-Mask: 0x03)

Definition at line 9270 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GATE_Pos

#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_GATE_Pos   (1UL)

PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_GATE (Bit 1)

Definition at line 9269 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_SEL_Msk

#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_SEL_Msk   (0x1UL)

PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_SEL (Bitfield-Mask: 0x01)

Definition at line 9268 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_SEL_Pos

#define PLLDIG_RF_PULSE_CTRL_REG_FTDF_PULSE_SEL_Pos   (0UL)

PLLDIG RF_PULSE_CTRL_REG: FTDF_PULSE_SEL (Bit 0)

Definition at line 9267 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_0_REG_FTDF_PULSE_VAL_Msk

#define PLLDIG_RF_PULSE_TBL_0_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)

PLLDIG RF_PULSE_TBL_0_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff)

Definition at line 9236 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_0_REG_FTDF_PULSE_VAL_Pos

#define PLLDIG_RF_PULSE_TBL_0_REG_FTDF_PULSE_VAL_Pos   (0UL)

PLLDIG RF_PULSE_TBL_0_REG: FTDF_PULSE_VAL (Bit 0)

Definition at line 9235 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_1_REG_FTDF_PULSE_VAL_Msk

#define PLLDIG_RF_PULSE_TBL_1_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)

PLLDIG RF_PULSE_TBL_1_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff)

Definition at line 9240 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_1_REG_FTDF_PULSE_VAL_Pos

#define PLLDIG_RF_PULSE_TBL_1_REG_FTDF_PULSE_VAL_Pos   (0UL)

PLLDIG RF_PULSE_TBL_1_REG: FTDF_PULSE_VAL (Bit 0)

Definition at line 9239 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_2_REG_FTDF_PULSE_VAL_Msk

#define PLLDIG_RF_PULSE_TBL_2_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)

PLLDIG RF_PULSE_TBL_2_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff)

Definition at line 9244 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_2_REG_FTDF_PULSE_VAL_Pos

#define PLLDIG_RF_PULSE_TBL_2_REG_FTDF_PULSE_VAL_Pos   (0UL)

PLLDIG RF_PULSE_TBL_2_REG: FTDF_PULSE_VAL (Bit 0)

Definition at line 9243 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_3_REG_FTDF_PULSE_VAL_Msk

#define PLLDIG_RF_PULSE_TBL_3_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)

PLLDIG RF_PULSE_TBL_3_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff)

Definition at line 9248 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_3_REG_FTDF_PULSE_VAL_Pos

#define PLLDIG_RF_PULSE_TBL_3_REG_FTDF_PULSE_VAL_Pos   (0UL)

PLLDIG RF_PULSE_TBL_3_REG: FTDF_PULSE_VAL (Bit 0)

Definition at line 9247 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_4_REG_FTDF_PULSE_VAL_Msk

#define PLLDIG_RF_PULSE_TBL_4_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)

PLLDIG RF_PULSE_TBL_4_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff)

Definition at line 9252 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_4_REG_FTDF_PULSE_VAL_Pos

#define PLLDIG_RF_PULSE_TBL_4_REG_FTDF_PULSE_VAL_Pos   (0UL)

PLLDIG RF_PULSE_TBL_4_REG: FTDF_PULSE_VAL (Bit 0)

Definition at line 9251 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_5_REG_FTDF_PULSE_VAL_Msk

#define PLLDIG_RF_PULSE_TBL_5_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)

PLLDIG RF_PULSE_TBL_5_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff)

Definition at line 9256 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_5_REG_FTDF_PULSE_VAL_Pos

#define PLLDIG_RF_PULSE_TBL_5_REG_FTDF_PULSE_VAL_Pos   (0UL)

PLLDIG RF_PULSE_TBL_5_REG: FTDF_PULSE_VAL (Bit 0)

Definition at line 9255 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_6_REG_FTDF_PULSE_VAL_Msk

#define PLLDIG_RF_PULSE_TBL_6_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)

PLLDIG RF_PULSE_TBL_6_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff)

Definition at line 9260 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_6_REG_FTDF_PULSE_VAL_Pos

#define PLLDIG_RF_PULSE_TBL_6_REG_FTDF_PULSE_VAL_Pos   (0UL)

PLLDIG RF_PULSE_TBL_6_REG: FTDF_PULSE_VAL (Bit 0)

Definition at line 9259 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_7_REG_FTDF_PULSE_VAL_Msk

#define PLLDIG_RF_PULSE_TBL_7_REG_FTDF_PULSE_VAL_Msk   (0x7ffUL)

PLLDIG RF_PULSE_TBL_7_REG: FTDF_PULSE_VAL (Bitfield-Mask: 0x7ff)

Definition at line 9264 of file DA14680BA.h.

◆ PLLDIG_RF_PULSE_TBL_7_REG_FTDF_PULSE_VAL_Pos

#define PLLDIG_RF_PULSE_TBL_7_REG_FTDF_PULSE_VAL_Pos   (0UL)

PLLDIG RF_PULSE_TBL_7_REG: FTDF_PULSE_VAL (Bit 0)

Definition at line 9263 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CHANNEL_ZERO_Msk

#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CHANNEL_ZERO_Msk   (0xfffUL)

PLLDIG RF_SYNTH_CTRL1_BLE_REG: CHANNEL_ZERO (Bitfield-Mask: 0xfff)

Definition at line 8972 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CHANNEL_ZERO_Pos

#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CHANNEL_ZERO_Pos   (0UL)

PLLDIG RF_SYNTH_CTRL1_BLE_REG: CHANNEL_ZERO (Bit 0)

Definition at line 8971 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CS_Msk

#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CS_Msk   (0x2000UL)

PLLDIG RF_SYNTH_CTRL1_BLE_REG: CS (Bitfield-Mask: 0x01)

Definition at line 8976 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CS_Pos

#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_CS_Pos   (13UL)

PLLDIG RF_SYNTH_CTRL1_BLE_REG: CS (Bit 13)

Definition at line 8975 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_BLE_REG_PLL_HSI_POL_Msk

#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_PLL_HSI_POL_Msk   (0x4000UL)

PLLDIG RF_SYNTH_CTRL1_BLE_REG: PLL_HSI_POL (Bitfield-Mask: 0x01)

Definition at line 8978 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_BLE_REG_PLL_HSI_POL_Pos

#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_PLL_HSI_POL_Pos   (14UL)

PLLDIG RF_SYNTH_CTRL1_BLE_REG: PLL_HSI_POL (Bit 14)

Definition at line 8977 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_BLE_REG_SGN_Msk

#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_SGN_Msk   (0x1000UL)

PLLDIG RF_SYNTH_CTRL1_BLE_REG: SGN (Bitfield-Mask: 0x01)

Definition at line 8974 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_BLE_REG_SGN_Pos

#define PLLDIG_RF_SYNTH_CTRL1_BLE_REG_SGN_Pos   (12UL)

PLLDIG RF_SYNTH_CTRL1_BLE_REG: SGN (Bit 12)

Definition at line 8973 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CHANNEL_ZERO_Msk

#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CHANNEL_ZERO_Msk   (0xfffUL)

PLLDIG RF_SYNTH_CTRL1_FTDF_REG: CHANNEL_ZERO (Bitfield-Mask: 0xfff)

Definition at line 8982 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CHANNEL_ZERO_Pos

#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CHANNEL_ZERO_Pos   (0UL)

PLLDIG RF_SYNTH_CTRL1_FTDF_REG: CHANNEL_ZERO (Bit 0)

Definition at line 8981 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CS_Msk

#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CS_Msk   (0x2000UL)

PLLDIG RF_SYNTH_CTRL1_FTDF_REG: CS (Bitfield-Mask: 0x01)

Definition at line 8986 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CS_Pos

#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_CS_Pos   (13UL)

PLLDIG RF_SYNTH_CTRL1_FTDF_REG: CS (Bit 13)

Definition at line 8985 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_PLL_HSI_POL_Msk

#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_PLL_HSI_POL_Msk   (0x4000UL)

PLLDIG RF_SYNTH_CTRL1_FTDF_REG: PLL_HSI_POL (Bitfield-Mask: 0x01)

Definition at line 8988 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_PLL_HSI_POL_Pos

#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_PLL_HSI_POL_Pos   (14UL)

PLLDIG RF_SYNTH_CTRL1_FTDF_REG: PLL_HSI_POL (Bit 14)

Definition at line 8987 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_SGN_Msk

#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_SGN_Msk   (0x1000UL)

PLLDIG RF_SYNTH_CTRL1_FTDF_REG: SGN (Bitfield-Mask: 0x01)

Definition at line 8984 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_SGN_Pos

#define PLLDIG_RF_SYNTH_CTRL1_FTDF_REG_SGN_Pos   (12UL)

PLLDIG RF_SYNTH_CTRL1_FTDF_REG: SGN (Bit 12)

Definition at line 8983 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BLE_DAC_SEL_Msk

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BLE_DAC_SEL_Msk   (0x2000UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: BLE_DAC_SEL (Bitfield-Mask: 0x01)

Definition at line 9010 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BLE_DAC_SEL_Pos

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BLE_DAC_SEL_Pos   (13UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: BLE_DAC_SEL (Bit 13)

Definition at line 9009 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BT_SEL_Msk

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BT_SEL_Msk   (0x1000UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: BT_SEL (Bitfield-Mask: 0x01)

Definition at line 9008 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BT_SEL_Pos

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_BT_SEL_Pos   (12UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: BT_SEL (Bit 12)

Definition at line 9007 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_EO_PACKET_DIS_Msk

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_EO_PACKET_DIS_Msk   (0x800UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: EO_PACKET_DIS (Bitfield-Mask: 0x01)

Definition at line 9006 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_EO_PACKET_DIS_Pos

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_EO_PACKET_DIS_Pos   (11UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: EO_PACKET_DIS (Bit 11)

Definition at line 9005 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_86_Msk

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_86_Msk   (0x200UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_86 (Bitfield-Mask: 0x01)

Definition at line 9002 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_86_Pos

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_86_Pos   (9UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_86 (Bit 9)

Definition at line 9001 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_DELAY_Msk

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_DELAY_Msk   (0xc0UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_DELAY (Bitfield-Mask: 0x03)

Definition at line 8998 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_DELAY_Pos

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_DELAY_Pos   (6UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_DELAY (Bit 6)

Definition at line 8997 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_INV_Msk

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_INV_Msk   (0x100UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_INV (Bitfield-Mask: 0x01)

Definition at line 9000 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_INV_Pos

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_GAUSS_INV_Pos   (8UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: GAUSS_INV (Bit 8)

Definition at line 8999 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_MODINDEX_Msk

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_MODINDEX_Msk   (0x30UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: MODINDEX (Bitfield-Mask: 0x03)

Definition at line 8996 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_MODINDEX_Pos

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_MODINDEX_Pos   (4UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: MODINDEX (Bit 4)

Definition at line 8995 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_RX_Msk

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_RX_Msk   (0x3UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: SD_ORDER_RX (Bitfield-Mask: 0x03)

Definition at line 8992 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_RX_Pos

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_RX_Pos   (0UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: SD_ORDER_RX (Bit 0)

Definition at line 8991 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_TX_Msk

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_TX_Msk   (0xcUL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: SD_ORDER_TX (Bitfield-Mask: 0x03)

Definition at line 8994 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_TX_Pos

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_SD_ORDER_TX_Pos   (2UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: SD_ORDER_TX (Bit 2)

Definition at line 8993 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_TXDATA_INV_Msk

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_TXDATA_INV_Msk   (0x400UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: TXDATA_INV (Bitfield-Mask: 0x01)

Definition at line 9004 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_BLE_REG_TXDATA_INV_Pos

#define PLLDIG_RF_SYNTH_CTRL2_BLE_REG_TXDATA_INV_Pos   (10UL)

PLLDIG RF_SYNTH_CTRL2_BLE_REG: TXDATA_INV (Bit 10)

Definition at line 9003 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_GAUSS_INV_Msk

#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_GAUSS_INV_Msk   (0x100UL)

PLLDIG RF_SYNTH_CTRL2_FTDF_REG: GAUSS_INV (Bitfield-Mask: 0x01)

Definition at line 9022 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_GAUSS_INV_Pos

#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_GAUSS_INV_Pos   (8UL)

PLLDIG RF_SYNTH_CTRL2_FTDF_REG: GAUSS_INV (Bit 8)

Definition at line 9021 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_MODINDEX_Msk

#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_MODINDEX_Msk   (0x30UL)

PLLDIG RF_SYNTH_CTRL2_FTDF_REG: MODINDEX (Bitfield-Mask: 0x03)

Definition at line 9018 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_MODINDEX_Pos

#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_MODINDEX_Pos   (4UL)

PLLDIG RF_SYNTH_CTRL2_FTDF_REG: MODINDEX (Bit 4)

Definition at line 9017 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_RX_Msk

#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_RX_Msk   (0x3UL)

PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_RX (Bitfield-Mask: 0x03)

Definition at line 9014 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_RX_Pos

#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_RX_Pos   (0UL)

PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_RX (Bit 0)

Definition at line 9013 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_TX_Msk

#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_TX_Msk   (0xcUL)

PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_TX (Bitfield-Mask: 0x03)

Definition at line 9016 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_TX_Pos

#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_SD_ORDER_TX_Pos   (2UL)

PLLDIG RF_SYNTH_CTRL2_FTDF_REG: SD_ORDER_TX (Bit 2)

Definition at line 9015 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDAC_DELAY_Msk

#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDAC_DELAY_Msk   (0x40UL)

PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDAC_DELAY (Bitfield-Mask: 0x01)

Definition at line 9020 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDAC_DELAY_Pos

#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDAC_DELAY_Pos   (6UL)

PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDAC_DELAY (Bit 6)

Definition at line 9019 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDATA_INV_Msk

#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDATA_INV_Msk   (0x400UL)

PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDATA_INV (Bitfield-Mask: 0x01)

Definition at line 9024 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDATA_INV_Pos

#define PLLDIG_RF_SYNTH_CTRL2_FTDF_REG_TXDATA_INV_Pos   (10UL)

PLLDIG RF_SYNTH_CTRL2_FTDF_REG: TXDATA_INV (Bit 10)

Definition at line 9023 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_SEL_Msk

#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_SEL_Msk   (0x4000UL)

PLLDIG RF_SYNTH_CTRL3_REG: MODVAL_SEL (Bitfield-Mask: 0x01)

Definition at line 9030 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_SEL_Pos

#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_SEL_Pos   (14UL)

PLLDIG RF_SYNTH_CTRL3_REG: MODVAL_SEL (Bit 14)

Definition at line 9029 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_WR_Msk

#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_WR_Msk   (0x3fffUL)

PLLDIG RF_SYNTH_CTRL3_REG: MODVAL_WR (Bitfield-Mask: 0x3fff)

Definition at line 9028 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_WR_Pos

#define PLLDIG_RF_SYNTH_CTRL3_REG_MODVAL_WR_Pos   (0UL)

PLLDIG RF_SYNTH_CTRL3_REG: MODVAL_WR (Bit 0)

Definition at line 9027 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL3_REG_ZIF_MODE_EN_Msk

#define PLLDIG_RF_SYNTH_CTRL3_REG_ZIF_MODE_EN_Msk   (0x8000UL)

PLLDIG RF_SYNTH_CTRL3_REG: ZIF_MODE_EN (Bitfield-Mask: 0x01)

Definition at line 9032 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_CTRL3_REG_ZIF_MODE_EN_Pos

#define PLLDIG_RF_SYNTH_CTRL3_REG_ZIF_MODE_EN_Pos   (15UL)

PLLDIG RF_SYNTH_CTRL3_REG: ZIF_MODE_EN (Bit 15)

Definition at line 9031 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT2_BLE_REG_CN_CAL_RD_Msk

#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_CN_CAL_RD_Msk   (0x3f00UL)

PLLDIG RF_SYNTH_RESULT2_BLE_REG: CN_CAL_RD (Bitfield-Mask: 0x3f)

Definition at line 9114 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT2_BLE_REG_CN_CAL_RD_Pos

#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_CN_CAL_RD_Pos   (8UL)

PLLDIG RF_SYNTH_RESULT2_BLE_REG: CN_CAL_RD (Bit 8)

Definition at line 9113 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT2_BLE_REG_GAUSS_GAIN_RD_Msk

#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_GAUSS_GAIN_RD_Msk   (0xffUL)

PLLDIG RF_SYNTH_RESULT2_BLE_REG: GAUSS_GAIN_RD (Bitfield-Mask: 0xff)

Definition at line 9112 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT2_BLE_REG_GAUSS_GAIN_RD_Pos

#define PLLDIG_RF_SYNTH_RESULT2_BLE_REG_GAUSS_GAIN_RD_Pos   (0UL)

PLLDIG RF_SYNTH_RESULT2_BLE_REG: GAUSS_GAIN_RD (Bit 0)

Definition at line 9111 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_RD_Msk

#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_RD_Msk   (0xffUL)

PLLDIG RF_SYNTH_RESULT2_FTDF_REG: MSK_GAIN_RD (Bitfield-Mask: 0xff)

Definition at line 9118 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_RD_Pos

#define PLLDIG_RF_SYNTH_RESULT2_FTDF_REG_MSK_GAIN_RD_Pos   (0UL)

PLLDIG RF_SYNTH_RESULT2_FTDF_REG: MSK_GAIN_RD (Bit 0)

Definition at line 9117 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT3_FTDF_REG_CN_CAL_FTDF_RD_Msk

#define PLLDIG_RF_SYNTH_RESULT3_FTDF_REG_CN_CAL_FTDF_RD_Msk   (0x3fUL)

PLLDIG RF_SYNTH_RESULT3_FTDF_REG: CN_CAL_FTDF_RD (Bitfield-Mask: 0x3f)

Definition at line 9122 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT3_FTDF_REG_CN_CAL_FTDF_RD_Pos

#define PLLDIG_RF_SYNTH_RESULT3_FTDF_REG_CN_CAL_FTDF_RD_Pos   (0UL)

PLLDIG RF_SYNTH_RESULT3_FTDF_REG: CN_CAL_FTDF_RD (Bit 0)

Definition at line 9121 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT_BLE_REG_GAUSS_GAIN_CAL_RD_Msk

#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_GAUSS_GAIN_CAL_RD_Msk   (0xffUL)

PLLDIG RF_SYNTH_RESULT_BLE_REG: GAUSS_GAIN_CAL_RD (Bitfield-Mask: 0xff)

Definition at line 9102 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT_BLE_REG_GAUSS_GAIN_CAL_RD_Pos

#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_GAUSS_GAIN_CAL_RD_Pos   (0UL)

PLLDIG RF_SYNTH_RESULT_BLE_REG: GAUSS_GAIN_CAL_RD (Bit 0)

Definition at line 9101 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT_BLE_REG_VCO_FREQTRIM_RD_Msk

#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_VCO_FREQTRIM_RD_Msk   (0xf00UL)

PLLDIG RF_SYNTH_RESULT_BLE_REG: VCO_FREQTRIM_RD (Bitfield-Mask: 0x0f)

Definition at line 9104 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT_BLE_REG_VCO_FREQTRIM_RD_Pos

#define PLLDIG_RF_SYNTH_RESULT_BLE_REG_VCO_FREQTRIM_RD_Pos   (8UL)

PLLDIG RF_SYNTH_RESULT_BLE_REG: VCO_FREQTRIM_RD (Bit 8)

Definition at line 9103 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT_FTDF_REG_MSK_GAIN_CAL_RD_Msk

#define PLLDIG_RF_SYNTH_RESULT_FTDF_REG_MSK_GAIN_CAL_RD_Msk   (0x7fUL)

PLLDIG RF_SYNTH_RESULT_FTDF_REG: MSK_GAIN_CAL_RD (Bitfield-Mask: 0x7f)

Definition at line 9108 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_RESULT_FTDF_REG_MSK_GAIN_CAL_RD_Pos

#define PLLDIG_RF_SYNTH_RESULT_FTDF_REG_MSK_GAIN_CAL_RD_Pos   (0UL)

PLLDIG RF_SYNTH_RESULT_FTDF_REG: MSK_GAIN_CAL_RD (Bit 0)

Definition at line 9107 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_SPARE_REG_SPARE_Msk

#define PLLDIG_RF_SYNTH_SPARE_REG_SPARE_Msk   (0xffUL)

PLLDIG RF_SYNTH_SPARE_REG: SPARE (Bitfield-Mask: 0xff)

Definition at line 9172 of file DA14680BA.h.

◆ PLLDIG_RF_SYNTH_SPARE_REG_SPARE_Pos

#define PLLDIG_RF_SYNTH_SPARE_REG_SPARE_Pos   (0UL)

PLLDIG RF_SYNTH_SPARE_REG: SPARE (Bit 0)

Definition at line 9171 of file DA14680BA.h.

◆ PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_SEL_Msk

#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_SEL_Msk   (0x100UL)

PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_SEL (Bitfield-Mask: 0x01)

Definition at line 9200 of file DA14680BA.h.

◆ PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_SEL_Pos

#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_SEL_Pos   (8UL)

PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_SEL (Bit 8)

Definition at line 9199 of file DA14680BA.h.

◆ PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_WR_Msk

#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_WR_Msk   (0xffUL)

PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_WR (Bitfield-Mask: 0xff)

Definition at line 9198 of file DA14680BA.h.

◆ PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_WR_Pos

#define PLLDIG_RF_TXDAC_TEST_REG_RF_TXDAC_TEST_WR_Pos   (0UL)

PLLDIG RF_TXDAC_TEST_REG: RF_TXDAC_TEST_WR (Bit 0)

Definition at line 9197 of file DA14680BA.h.

◆ PLLDIG_RF_VCO_CALCAP_BIT14_REG_VCO_CALCAP_BIT14_Msk

#define PLLDIG_RF_VCO_CALCAP_BIT14_REG_VCO_CALCAP_BIT14_Msk   (0xffffUL)

PLLDIG RF_VCO_CALCAP_BIT14_REG: VCO_CALCAP_BIT14 (Bitfield-Mask: 0xffff)

Definition at line 9074 of file DA14680BA.h.

◆ PLLDIG_RF_VCO_CALCAP_BIT14_REG_VCO_CALCAP_BIT14_Pos

#define PLLDIG_RF_VCO_CALCAP_BIT14_REG_VCO_CALCAP_BIT14_Pos   (0UL)

PLLDIG RF_VCO_CALCAP_BIT14_REG: VCO_CALCAP_BIT14 (Bit 0)

Definition at line 9073 of file DA14680BA.h.

◆ PLLDIG_RF_VCO_CALCAP_BIT15_REG_VCO_CALCAP_BIT15_Msk

#define PLLDIG_RF_VCO_CALCAP_BIT15_REG_VCO_CALCAP_BIT15_Msk   (0xffffUL)

PLLDIG RF_VCO_CALCAP_BIT15_REG: VCO_CALCAP_BIT15 (Bitfield-Mask: 0xffff)

Definition at line 9078 of file DA14680BA.h.

◆ PLLDIG_RF_VCO_CALCAP_BIT15_REG_VCO_CALCAP_BIT15_Pos

#define PLLDIG_RF_VCO_CALCAP_BIT15_REG_VCO_CALCAP_BIT15_Pos   (0UL)

PLLDIG RF_VCO_CALCAP_BIT15_REG: VCO_CALCAP_BIT15 (Bit 0)

Definition at line 9077 of file DA14680BA.h.

◆ PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_EN_Msk

#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_EN_Msk   (0x1UL)

PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_EN (Bitfield-Mask: 0x01)

Definition at line 9164 of file DA14680BA.h.

◆ PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_EN_Pos

#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_EN_Pos   (0UL)

PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_EN (Bit 0)

Definition at line 9163 of file DA14680BA.h.

◆ PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_LEN_Msk

#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_LEN_Msk   (0xfeUL)

PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_LEN (Bitfield-Mask: 0x7f)

Definition at line 9166 of file DA14680BA.h.

◆ PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_LEN_Pos

#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_LEN_Pos   (1UL)

PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_LEN (Bit 1)

Definition at line 9165 of file DA14680BA.h.

◆ PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_UPPER_RD_Msk

#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_UPPER_RD_Msk   (0x700UL)

PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_UPPER_RD (Bitfield-Mask: 0x07)

Definition at line 9168 of file DA14680BA.h.

◆ PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_UPPER_RD_Pos

#define PLLDIG_RF_VCO_FREQ_EST_REG_VCO_FREQ_EST_UPPER_RD_Pos   (8UL)

PLLDIG RF_VCO_FREQ_EST_REG: VCO_FREQ_EST_UPPER_RD (Bit 8)

Definition at line 9167 of file DA14680BA.h.

◆ PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_SEL_Msk

#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_SEL_Msk   (0x30UL)

PLLDIG RF_VCOCAL_CTRL_REG: VCO_FREQTRIM_SEL (Bitfield-Mask: 0x03)

Definition at line 9038 of file DA14680BA.h.

◆ PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_SEL_Pos

#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_SEL_Pos   (4UL)

PLLDIG RF_VCOCAL_CTRL_REG: VCO_FREQTRIM_SEL (Bit 4)

Definition at line 9037 of file DA14680BA.h.

◆ PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_WR_Msk

#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_WR_Msk   (0xfUL)

PLLDIG RF_VCOCAL_CTRL_REG: VCO_FREQTRIM_WR (Bitfield-Mask: 0x0f)

Definition at line 9036 of file DA14680BA.h.

◆ PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_WR_Pos

#define PLLDIG_RF_VCOCAL_CTRL_REG_VCO_FREQTRIM_WR_Pos   (0UL)

PLLDIG RF_VCOCAL_CTRL_REG: VCO_FREQTRIM_WR (Bit 0)

Definition at line 9035 of file DA14680BA.h.

◆ PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_MD_STATE_DLY_SEL_Msk

#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_MD_STATE_DLY_SEL_Msk   (0x100UL)

PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_MD_STATE_DLY_SEL (Bitfield-Mask: 0x01)

Definition at line 9042 of file DA14680BA.h.

◆ PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_MD_STATE_DLY_SEL_Pos

#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_MD_STATE_DLY_SEL_Pos   (8UL)

PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_MD_STATE_DLY_SEL (Bit 8)

Definition at line 9041 of file DA14680BA.h.

◆ PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_PERIOD_Msk

#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_PERIOD_Msk   (0xc0UL)

PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_PERIOD (Bitfield-Mask: 0x03)

Definition at line 9040 of file DA14680BA.h.

◆ PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_PERIOD_Pos

#define PLLDIG_RF_VCOCAL_CTRL_REG_VCOCAL_PERIOD_Pos   (6UL)

PLLDIG RF_VCOCAL_CTRL_REG: VCOCAL_PERIOD (Bit 6)

Definition at line 9039 of file DA14680BA.h.

◆ QSPIC

#define QSPIC   ((QSPIC_Type *) QSPIC_BASE)

Definition at line 12098 of file DA14680BA.h.

◆ QSPIC_BASE

#define QSPIC_BASE   0x0C000000UL

Definition at line 12053 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Msk

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Msk   (0x10000UL)

QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_EN (Bitfield-Mask: 0x01)

Definition at line 9418 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Pos

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Pos   (16UL)

QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_EN (Bit 16)

Definition at line 9417 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Msk

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Msk   (0x20000UL)

QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_SZ (Bitfield-Mask: 0x01)

Definition at line 9420 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Pos

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Pos   (17UL)

QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_SZ (Bit 17)

Definition at line 9419 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk   (0xc0000UL)

QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_TX_MD (Bitfield-Mask: 0x03)

Definition at line 9422 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos   (18UL)

QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_TX_MD (Bit 18)

Definition at line 9421 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Msk

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Msk   (0xffffUL)

QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_WRD (Bitfield-Mask: 0xffff)

Definition at line 9416 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Pos

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Pos   (0UL)

QSPIC QSPIC_BURSTBRK_REG: QSPIC_BRK_WRD (Bit 0)

Definition at line 9415 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk   (0x100000UL)

QSPIC QSPIC_BURSTBRK_REG: QSPIC_SEC_HF_DS (Bitfield-Mask: 0x01)

Definition at line 9424 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos   (20UL)

QSPIC QSPIC_BURSTBRK_REG: QSPIC_SEC_HF_DS (Bit 20)

Definition at line 9423 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk   (0xc000000UL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_ADR_TX_MD (Bitfield-Mask: 0x03)

Definition at line 9334 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos   (26UL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_ADR_TX_MD (Bit 26)

Definition at line 9333 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk   (0xc0000000UL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_DMY_TX_MD (Bitfield-Mask: 0x03)

Definition at line 9338 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos   (30UL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_DMY_TX_MD (Bit 30)

Definition at line 9337 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk   (0xff0000UL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_EXT_BYTE (Bitfield-Mask: 0xff)

Definition at line 9330 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos   (16UL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_EXT_BYTE (Bit 16)

Definition at line 9329 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk   (0x30000000UL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_EXT_TX_MD (Bitfield-Mask: 0x03)

Definition at line 9336 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos   (28UL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_EXT_TX_MD (Bit 28)

Definition at line 9335 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Msk   (0xffUL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST (Bitfield-Mask: 0xff)

Definition at line 9326 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Pos   (0UL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST (Bit 0)

Definition at line 9325 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk   (0x3000000UL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST_TX_MD (Bitfield-Mask: 0x03)

Definition at line 9332 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos   (24UL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST_TX_MD (Bit 24)

Definition at line 9331 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Msk   (0xff00UL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST_WB (Bitfield-Mask: 0xff)

Definition at line 9328 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Pos   (8UL)

QSPIC QSPIC_BURSTCMDA_REG: QSPIC_INST_WB (Bit 8)

Definition at line 9327 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk   (0x7000UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_CS_HIGH_MIN (Bitfield-Mask: 0x07)

Definition at line 9358 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos   (12UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_CS_HIGH_MIN (Bit 12)

Definition at line 9357 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk   (0x3UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DAT_RX_MD (Bitfield-Mask: 0x03)

Definition at line 9342 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos   (0UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DAT_RX_MD (Bit 0)

Definition at line 9341 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk   (0x8000UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DMY_FORCE (Bitfield-Mask: 0x01)

Definition at line 9360 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos   (15UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DMY_FORCE (Bit 15)

Definition at line 9359 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk   (0x30UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DMY_NUM (Bitfield-Mask: 0x03)

Definition at line 9348 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos   (4UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_DMY_NUM (Bit 4)

Definition at line 9347 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk   (0x4UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_EXT_BYTE_EN (Bitfield-Mask: 0x01)

Definition at line 9344 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos   (2UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_EXT_BYTE_EN (Bit 2)

Definition at line 9343 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk   (0x8UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_EXT_HF_DS (Bitfield-Mask: 0x01)

Definition at line 9346 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos   (3UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_EXT_HF_DS (Bit 3)

Definition at line 9345 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Msk   (0x40UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_INST_MD (Bitfield-Mask: 0x01)

Definition at line 9350 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Pos   (6UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_INST_MD (Bit 6)

Definition at line 9349 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk   (0x300UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_LEN (Bitfield-Mask: 0x03)

Definition at line 9354 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos   (8UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_LEN (Bit 8)

Definition at line 9353 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk   (0x80UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_MD (Bitfield-Mask: 0x01)

Definition at line 9352 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos   (7UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_MD (Bit 7)

Definition at line 9351 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk   (0xc00UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_SIZE (Bitfield-Mask: 0x03)

Definition at line 9356 of file DA14680BA.h.

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos   (10UL)

QSPIC QSPIC_BURSTCMDB_REG: QSPIC_WRAP_SIZE (Bit 10)

Definition at line 9355 of file DA14680BA.h.

◆ QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Msk

#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Msk   (0xffffffffUL)

QSPIC QSPIC_CHCKERASE_REG: QSPIC_CHCKERASE (Bitfield-Mask: 0xffffffff)

Definition at line 9444 of file DA14680BA.h.

◆ QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Pos

#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Pos   (0UL)

QSPIC QSPIC_CHCKERASE_REG: QSPIC_CHCKERASE (Bit 0)

Definition at line 9443 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk   (0x10UL)

QSPIC QSPIC_CTRLBUS_REG: QSPIC_DIS_CS (Bitfield-Mask: 0x01)

Definition at line 9292 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Pos

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Pos   (4UL)

QSPIC QSPIC_CTRLBUS_REG: QSPIC_DIS_CS (Bit 4)

Definition at line 9291 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk   (0x8UL)

QSPIC QSPIC_CTRLBUS_REG: QSPIC_EN_CS (Bitfield-Mask: 0x01)

Definition at line 9290 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Pos

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Pos   (3UL)

QSPIC QSPIC_CTRLBUS_REG: QSPIC_EN_CS (Bit 3)

Definition at line 9289 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Msk

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Msk   (0x2UL)

QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_DUAL (Bitfield-Mask: 0x01)

Definition at line 9286 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Pos

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Pos   (1UL)

QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_DUAL (Bit 1)

Definition at line 9285 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Msk

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Msk   (0x4UL)

QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_QUAD (Bitfield-Mask: 0x01)

Definition at line 9288 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Pos

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Pos   (2UL)

QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_QUAD (Bit 2)

Definition at line 9287 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk   (0x1UL)

QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_SINGLE (Bitfield-Mask: 0x01)

Definition at line 9284 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos   (0UL)

QSPIC QSPIC_CTRLBUS_REG: QSPIC_SET_SINGLE (Bit 0)

Definition at line 9283 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk   (0x1UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_AUTO_MD (Bitfield-Mask: 0x01)

Definition at line 9296 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Pos   (0UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_AUTO_MD (Bit 0)

Definition at line 9295 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Msk   (0x2UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_CLK_MD (Bitfield-Mask: 0x01)

Definition at line 9298 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Pos   (1UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_CLK_MD (Bit 1)

Definition at line 9297 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Msk   (0x1000UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_FORCENSEQ_EN (Bitfield-Mask: 0x01)

Definition at line 9316 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Pos   (12UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_FORCENSEQ_EN (Bit 12)

Definition at line 9315 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Msk   (0x40UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_HRDY_MD (Bitfield-Mask: 0x01)

Definition at line 9308 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Pos   (6UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_HRDY_MD (Bit 6)

Definition at line 9307 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Msk   (0x10UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO2_DAT (Bitfield-Mask: 0x01)

Definition at line 9304 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Pos   (4UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO2_DAT (Bit 4)

Definition at line 9303 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk   (0x4UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO2_OEN (Bitfield-Mask: 0x01)

Definition at line 9300 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Pos   (2UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO2_OEN (Bit 2)

Definition at line 9299 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Msk   (0x20UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO3_DAT (Bitfield-Mask: 0x01)

Definition at line 9306 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Pos   (5UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO3_DAT (Bit 5)

Definition at line 9305 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Msk   (0x8UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO3_OEN (Bitfield-Mask: 0x01)

Definition at line 9302 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Pos   (3UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_IO3_OEN (Bit 3)

Definition at line 9301 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk   (0xe00UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_PCLK_MD (Bitfield-Mask: 0x07)

Definition at line 9314 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos   (9UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_PCLK_MD (Bit 9)

Definition at line 9313 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk   (0x100UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_RPIPE_EN (Bitfield-Mask: 0x01)

Definition at line 9312 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos   (8UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_RPIPE_EN (Bit 8)

Definition at line 9311 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Msk   (0x80UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_RXD_NEG (Bitfield-Mask: 0x01)

Definition at line 9310 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Pos   (7UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_RXD_NEG (Bit 7)

Definition at line 9309 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Msk   (0x2000UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_USE_32BA (Bitfield-Mask: 0x01)

Definition at line 9318 of file DA14680BA.h.

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Pos   (13UL)

QSPIC QSPIC_CTRLMODE_REG: QSPIC_USE_32BA (Bit 13)

Definition at line 9317 of file DA14680BA.h.

◆ QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk

#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk   (0xffffffffUL)

QSPIC QSPIC_DUMMYDATA_REG: QSPIC_DUMMYDATA (Bitfield-Mask: 0xffffffff)

Definition at line 9376 of file DA14680BA.h.

◆ QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos

#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos   (0UL)

QSPIC QSPIC_DUMMYDATA_REG: QSPIC_DUMMYDATA (Bit 0)

Definition at line 9375 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Msk

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Msk   (0xffUL)

QSPIC QSPIC_ERASECMDA_REG: QSPIC_ERS_INST (Bitfield-Mask: 0xff)

Definition at line 9388 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Pos

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Pos   (0UL)

QSPIC QSPIC_ERASECMDA_REG: QSPIC_ERS_INST (Bit 0)

Definition at line 9387 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Msk

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Msk   (0xff000000UL)

QSPIC QSPIC_ERASECMDA_REG: QSPIC_RES_INST (Bitfield-Mask: 0xff)

Definition at line 9394 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Pos

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Pos   (24UL)

QSPIC QSPIC_ERASECMDA_REG: QSPIC_RES_INST (Bit 24)

Definition at line 9393 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Msk

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Msk   (0xff0000UL)

QSPIC QSPIC_ERASECMDA_REG: QSPIC_SUS_INST (Bitfield-Mask: 0xff)

Definition at line 9392 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Pos

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Pos   (16UL)

QSPIC QSPIC_ERASECMDA_REG: QSPIC_SUS_INST (Bit 16)

Definition at line 9391 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Msk

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Msk   (0xff00UL)

QSPIC QSPIC_ERASECMDA_REG: QSPIC_WEN_INST (Bitfield-Mask: 0xff)

Definition at line 9390 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Pos

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Pos   (8UL)

QSPIC QSPIC_ERASECMDA_REG: QSPIC_WEN_INST (Bit 8)

Definition at line 9389 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk   (0x300UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_EAD_TX_MD (Bitfield-Mask: 0x03)

Definition at line 9406 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos   (8UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_EAD_TX_MD (Bit 8)

Definition at line 9405 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk   (0x7c00UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERS_CS_HI (Bitfield-Mask: 0x1f)

Definition at line 9408 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos   (10UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERS_CS_HI (Bit 10)

Definition at line 9407 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk   (0x3UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERS_TX_MD (Bitfield-Mask: 0x03)

Definition at line 9398 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos   (0UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERS_TX_MD (Bit 0)

Definition at line 9397 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk   (0xf0000UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERSRES_HLD (Bitfield-Mask: 0x0f)

Definition at line 9410 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos   (16UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_ERSRES_HLD (Bit 16)

Definition at line 9409 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk   (0xc0UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_RES_TX_MD (Bitfield-Mask: 0x03)

Definition at line 9404 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos   (6UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_RES_TX_MD (Bit 6)

Definition at line 9403 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk   (0x3f000000UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_RESSUS_DLY (Bitfield-Mask: 0x3f)

Definition at line 9412 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos   (24UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_RESSUS_DLY (Bit 24)

Definition at line 9411 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk   (0x30UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_SUS_TX_MD (Bitfield-Mask: 0x03)

Definition at line 9402 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos   (4UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_SUS_TX_MD (Bit 4)

Definition at line 9401 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk   (0xcUL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_WEN_TX_MD (Bitfield-Mask: 0x03)

Definition at line 9400 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos   (2UL)

QSPIC QSPIC_ERASECMDB_REG: QSPIC_WEN_TX_MD (Bit 2)

Definition at line 9399 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Msk

#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Msk   (0x1000000UL)

QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERASE_EN (Bitfield-Mask: 0x01)

Definition at line 9382 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Pos

#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Pos   (24UL)

QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERASE_EN (Bit 24)

Definition at line 9381 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk

#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk   (0xfffff0UL)

QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERS_ADDR (Bitfield-Mask: 0xfffff)

Definition at line 9380 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos

#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos   (4UL)

QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERS_ADDR (Bit 4)

Definition at line 9379 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Msk

#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Msk   (0xe000000UL)

QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERS_STATE (Bitfield-Mask: 0x07)

Definition at line 9384 of file DA14680BA.h.

◆ QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Pos

#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Pos   (25UL)

QSPIC QSPIC_ERASECTRL_REG: QSPIC_ERS_STATE (Bit 25)

Definition at line 9383 of file DA14680BA.h.

◆ QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Msk

#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Msk   (0x6UL)

QSPIC QSPIC_GP_REG: QSPIC_PADS_DRV (Bitfield-Mask: 0x03)

Definition at line 9448 of file DA14680BA.h.

◆ QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Pos

#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Pos   (1UL)

QSPIC QSPIC_GP_REG: QSPIC_PADS_DRV (Bit 1)

Definition at line 9447 of file DA14680BA.h.

◆ QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Msk

#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Msk   (0x18UL)

QSPIC QSPIC_GP_REG: QSPIC_PADS_SLEW (Bitfield-Mask: 0x03)

Definition at line 9450 of file DA14680BA.h.

◆ QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Pos

#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Pos   (3UL)

QSPIC QSPIC_GP_REG: QSPIC_PADS_SLEW (Bit 3)

Definition at line 9449 of file DA14680BA.h.

◆ QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Msk

#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Msk   (0xffffffffUL)

QSPIC QSPIC_READDATA_REG: QSPIC_READDATA (Bitfield-Mask: 0xffffffff)

Definition at line 9372 of file DA14680BA.h.

◆ QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Pos

#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Pos   (0UL)

QSPIC QSPIC_READDATA_REG: QSPIC_READDATA (Bit 0)

Definition at line 9371 of file DA14680BA.h.

◆ QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Msk

#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Msk   (0xffffffffUL)

QSPIC QSPIC_RECVDATA_REG: QSPIC_RECVDATA (Bitfield-Mask: 0xffffffff)

Definition at line 9322 of file DA14680BA.h.

◆ QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Pos

#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Pos   (0UL)

QSPIC QSPIC_RECVDATA_REG: QSPIC_RECVDATA (Bit 0)

Definition at line 9321 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Msk

#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Msk   (0x1UL)

QSPIC QSPIC_STATUS_REG: QSPIC_BUSY (Bitfield-Mask: 0x01)

Definition at line 9364 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Pos

#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Pos   (0UL)

QSPIC QSPIC_STATUS_REG: QSPIC_BUSY (Bit 0)

Definition at line 9363 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Msk   (0x7000UL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_BUSY_POS (Bitfield-Mask: 0x07)

Definition at line 9434 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Pos   (12UL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_BUSY_POS (Bit 12)

Definition at line 9433 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk   (0x8000UL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_BUSY_VAL (Bitfield-Mask: 0x01)

Definition at line 9436 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos   (15UL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_BUSY_VAL (Bit 15)

Definition at line 9435 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk   (0x3f0000UL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_RESSTS_DLY (Bitfield-Mask: 0x3f)

Definition at line 9438 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos   (16UL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_RESSTS_DLY (Bit 16)

Definition at line 9437 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk   (0xffUL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_INST (Bitfield-Mask: 0xff)

Definition at line 9428 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos   (0UL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_INST (Bit 0)

Definition at line 9427 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk   (0xc00UL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_RX_MD (Bitfield-Mask: 0x03)

Definition at line 9432 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos   (10UL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_RX_MD (Bit 10)

Definition at line 9431 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk   (0x300UL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_TX_MD (Bitfield-Mask: 0x03)

Definition at line 9430 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos   (8UL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_RSTAT_TX_MD (Bit 8)

Definition at line 9429 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk   (0x400000UL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_STSDLY_SEL (Bitfield-Mask: 0x01)

Definition at line 9440 of file DA14680BA.h.

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos   (22UL)

QSPIC QSPIC_STATUSCMD_REG: QSPIC_STSDLY_SEL (Bit 22)

Definition at line 9439 of file DA14680BA.h.

◆ QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Msk

#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Msk   (0xffffffffUL)

QSPIC QSPIC_UCODE_START: QSPIC_UCODE_X (Bitfield-Mask: 0xffffffff)

Definition at line 9454 of file DA14680BA.h.

◆ QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Pos

#define QSPIC_QSPIC_UCODE_START_QSPIC_UCODE_X_Pos   (0UL)

QSPIC QSPIC_UCODE_START: QSPIC_UCODE_X (Bit 0)

Definition at line 9453 of file DA14680BA.h.

◆ QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Msk

#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Msk   (0xffffffffUL)

QSPIC QSPIC_WRITEDATA_REG: QSPIC_WRITEDATA (Bitfield-Mask: 0xffffffff)

Definition at line 9368 of file DA14680BA.h.

◆ QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Pos

#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Pos   (0UL)

QSPIC QSPIC_WRITEDATA_REG: QSPIC_WRITEDATA (Bit 0)

Definition at line 9367 of file DA14680BA.h.

◆ QUAD

#define QUAD   ((QUAD_Type *) QUAD_BASE)

Definition at line 12099 of file DA14680BA.h.

◆ QUAD_BASE

#define QUAD_BASE   0x50001A00UL

Definition at line 12054 of file DA14680BA.h.

◆ QUAD_QDEC_CLOCKDIV_REG_clock_divider_Msk

#define QUAD_QDEC_CLOCKDIV_REG_clock_divider_Msk   (0x3ffUL)

QUAD QDEC_CLOCKDIV_REG: clock_divider (Bitfield-Mask: 0x3ff)

Definition at line 9492 of file DA14680BA.h.

◆ QUAD_QDEC_CLOCKDIV_REG_clock_divider_Pos

#define QUAD_QDEC_CLOCKDIV_REG_clock_divider_Pos   (0UL)

QUAD QDEC_CLOCKDIV_REG: clock_divider (Bit 0)

Definition at line 9491 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_CHX_PORT_EN_Msk

#define QUAD_QDEC_CTRL_REG_CHX_PORT_EN_Msk   (0x400UL)

QUAD QDEC_CTRL_REG: CHX_PORT_EN (Bitfield-Mask: 0x01)

Definition at line 9472 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_CHX_PORT_EN_Pos

#define QUAD_QDEC_CTRL_REG_CHX_PORT_EN_Pos   (10UL)

QUAD QDEC_CTRL_REG: CHX_PORT_EN (Bit 10)

Definition at line 9471 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_CHY_PORT_EN_Msk

#define QUAD_QDEC_CTRL_REG_CHY_PORT_EN_Msk   (0x800UL)

QUAD QDEC_CTRL_REG: CHY_PORT_EN (Bitfield-Mask: 0x01)

Definition at line 9474 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_CHY_PORT_EN_Pos

#define QUAD_QDEC_CTRL_REG_CHY_PORT_EN_Pos   (11UL)

QUAD QDEC_CTRL_REG: CHY_PORT_EN (Bit 11)

Definition at line 9473 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_CHZ_PORT_EN_Msk

#define QUAD_QDEC_CTRL_REG_CHZ_PORT_EN_Msk   (0x1000UL)

QUAD QDEC_CTRL_REG: CHZ_PORT_EN (Bitfield-Mask: 0x01)

Definition at line 9476 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_CHZ_PORT_EN_Pos

#define QUAD_QDEC_CTRL_REG_CHZ_PORT_EN_Pos   (12UL)

QUAD QDEC_CTRL_REG: CHZ_PORT_EN (Bit 12)

Definition at line 9475 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_QD_IRQ_CLR_Msk

#define QUAD_QDEC_CTRL_REG_QD_IRQ_CLR_Msk   (0x2UL)

QUAD QDEC_CTRL_REG: QD_IRQ_CLR (Bitfield-Mask: 0x01)

Definition at line 9466 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_QD_IRQ_CLR_Pos

#define QUAD_QDEC_CTRL_REG_QD_IRQ_CLR_Pos   (1UL)

QUAD QDEC_CTRL_REG: QD_IRQ_CLR (Bit 1)

Definition at line 9465 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_QD_IRQ_MASK_Msk

#define QUAD_QDEC_CTRL_REG_QD_IRQ_MASK_Msk   (0x1UL)

QUAD QDEC_CTRL_REG: QD_IRQ_MASK (Bitfield-Mask: 0x01)

Definition at line 9464 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_QD_IRQ_MASK_Pos

#define QUAD_QDEC_CTRL_REG_QD_IRQ_MASK_Pos   (0UL)

QUAD QDEC_CTRL_REG: QD_IRQ_MASK (Bit 0)

Definition at line 9463 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_QD_IRQ_STATUS_Msk

#define QUAD_QDEC_CTRL_REG_QD_IRQ_STATUS_Msk   (0x4UL)

QUAD QDEC_CTRL_REG: QD_IRQ_STATUS (Bitfield-Mask: 0x01)

Definition at line 9468 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_QD_IRQ_STATUS_Pos

#define QUAD_QDEC_CTRL_REG_QD_IRQ_STATUS_Pos   (2UL)

QUAD QDEC_CTRL_REG: QD_IRQ_STATUS (Bit 2)

Definition at line 9467 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_QD_IRQ_THRES_Msk

#define QUAD_QDEC_CTRL_REG_QD_IRQ_THRES_Msk   (0x3f8UL)

QUAD QDEC_CTRL_REG: QD_IRQ_THRES (Bitfield-Mask: 0x7f)

Definition at line 9470 of file DA14680BA.h.

◆ QUAD_QDEC_CTRL_REG_QD_IRQ_THRES_Pos

#define QUAD_QDEC_CTRL_REG_QD_IRQ_THRES_Pos   (3UL)

QUAD QDEC_CTRL_REG: QD_IRQ_THRES (Bit 3)

Definition at line 9469 of file DA14680BA.h.

◆ QUAD_QDEC_XCNT_REG_X_counter_Msk

#define QUAD_QDEC_XCNT_REG_X_counter_Msk   (0xffffUL)

QUAD QDEC_XCNT_REG: X_counter (Bitfield-Mask: 0xffff)

Definition at line 9480 of file DA14680BA.h.

◆ QUAD_QDEC_XCNT_REG_X_counter_Pos

#define QUAD_QDEC_XCNT_REG_X_counter_Pos   (0UL)

QUAD QDEC_XCNT_REG: X_counter (Bit 0)

Definition at line 9479 of file DA14680BA.h.

◆ QUAD_QDEC_YCNT_REG_Y_counter_Msk

#define QUAD_QDEC_YCNT_REG_Y_counter_Msk   (0xffffUL)

QUAD QDEC_YCNT_REG: Y_counter (Bitfield-Mask: 0xffff)

Definition at line 9484 of file DA14680BA.h.

◆ QUAD_QDEC_YCNT_REG_Y_counter_Pos

#define QUAD_QDEC_YCNT_REG_Y_counter_Pos   (0UL)

QUAD QDEC_YCNT_REG: Y_counter (Bit 0)

Definition at line 9483 of file DA14680BA.h.

◆ QUAD_QDEC_ZCNT_REG_Z_counter_Msk

#define QUAD_QDEC_ZCNT_REG_Z_counter_Msk   (0xffffUL)

QUAD QDEC_ZCNT_REG: Z_counter (Bitfield-Mask: 0xffff)

Definition at line 9488 of file DA14680BA.h.

◆ QUAD_QDEC_ZCNT_REG_Z_counter_Pos

#define QUAD_QDEC_ZCNT_REG_Z_counter_Pos   (0UL)

QUAD QDEC_ZCNT_REG: Z_counter (Bit 0)

Definition at line 9487 of file DA14680BA.h.

◆ RFCU

#define RFCU   ((RFCU_Type *) RFCU_BASE)

Definition at line 12100 of file DA14680BA.h.

◆ RFCU_BASE

#define RFCU_BASE   0x50002000UL

Definition at line 12055 of file DA14680BA.h.

◆ RFCU_POWER

#define RFCU_POWER   ((RFCU_POWER_Type *) RFCU_POWER_BASE)

Definition at line 12101 of file DA14680BA.h.

◆ RFCU_POWER_BASE

#define RFCU_POWER_BASE   0x50002200UL

Definition at line 12056 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_BIAS_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_BIAS_EN_Msk   (0x1000UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_CP_BIAS_EN (Bitfield-Mask: 0x01)

Definition at line 10610 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_BIAS_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_BIAS_EN_Pos   (12UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_CP_BIAS_EN (Bit 12)

Definition at line 10609 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_SWITCH_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_SWITCH_EN_Msk   (0x400UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_CP_SWITCH_EN (Bitfield-Mask: 0x01)

Definition at line 10606 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_SWITCH_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_CP_SWITCH_EN_Pos   (10UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_CP_SWITCH_EN (Bit 10)

Definition at line 10605 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFF_LDO_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFF_LDO_EN_Msk   (0x10UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_IFF_LDO_EN (Bitfield-Mask: 0x01)

Definition at line 10594 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFF_LDO_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFF_LDO_EN_Pos   (4UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_IFF_LDO_EN (Bit 4)

Definition at line 10593 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFFADC_LDO_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFFADC_LDO_EN_Msk   (0x20UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_IFFADC_LDO_EN (Bitfield-Mask: 0x01)

Definition at line 10596 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFFADC_LDO_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_IFFADC_LDO_EN_Pos   (5UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_IFFADC_LDO_EN (Bit 5)

Definition at line 10595 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CGM_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CGM_EN_Msk   (0x4UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_CGM_EN (Bitfield-Mask: 0x01)

Definition at line 10590 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CGM_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CGM_EN_Pos   (2UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_CGM_EN (Bit 2)

Definition at line 10589 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CORE_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CORE_EN_Msk   (0x2UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_CORE_EN (Bitfield-Mask: 0x01)

Definition at line 10588 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CORE_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_CORE_EN_Pos   (1UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_CORE_EN (Bit 1)

Definition at line 10587 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_EN_Msk   (0x1UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_LDO_EN (Bitfield-Mask: 0x01)

Definition at line 10586 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_EN_Pos   (0UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_LDO_EN (Bit 0)

Definition at line 10585 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_ZERO_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_ZERO_Msk   (0x2000UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_LDO_ZERO (Bitfield-Mask: 0x01)

Definition at line 10612 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_ZERO_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_LNA_LDO_ZERO_Pos   (13UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_LNA_LDO_ZERO (Bit 13)

Definition at line 10611 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MD_LDO_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MD_LDO_EN_Msk   (0x80UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_MD_LDO_EN (Bitfield-Mask: 0x01)

Definition at line 10600 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MD_LDO_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MD_LDO_EN_Pos   (7UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_MD_LDO_EN (Bit 7)

Definition at line 10599 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MIX_LDO_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MIX_LDO_EN_Msk   (0x8UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_MIX_LDO_EN (Bitfield-Mask: 0x01)

Definition at line 10592 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MIX_LDO_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_MIX_LDO_EN_Pos   (3UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_MIX_LDO_EN (Bit 3)

Definition at line 10591 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_EN_Msk   (0x8000UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_EN (Bitfield-Mask: 0x01)

Definition at line 10616 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_EN_Pos   (15UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_EN (Bit 15)

Definition at line 10615 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_LDO_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_LDO_EN_Msk   (0x200UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_LDO_EN (Bitfield-Mask: 0x01)

Definition at line 10604 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_LDO_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_LDO_EN_Pos   (9UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_LDO_EN (Bit 9)

Definition at line 10603 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_RAMP_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_RAMP_EN_Msk   (0x4000UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_RAMP_EN (Bitfield-Mask: 0x01)

Definition at line 10614 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_RAMP_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PA_RAMP_EN_Pos   (14UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PA_RAMP_EN (Bit 14)

Definition at line 10613 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PFD_LDO_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PFD_LDO_EN_Msk   (0x100UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PFD_LDO_EN (Bitfield-Mask: 0x01)

Definition at line 10602 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PFD_LDO_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_PFD_LDO_EN_Pos   (8UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_PFD_LDO_EN (Bit 8)

Definition at line 10601 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_BIAS_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_BIAS_EN_Msk   (0x800UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_VCO_BIAS_EN (Bitfield-Mask: 0x01)

Definition at line 10608 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_BIAS_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_BIAS_EN_Pos   (11UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_VCO_BIAS_EN (Bit 11)

Definition at line 10607 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_LDO_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_LDO_EN_Msk   (0x40UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_VCO_LDO_EN (Bitfield-Mask: 0x01)

Definition at line 10598 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_LDO_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN1_REG_ALW_EN_VCO_LDO_EN_Pos   (6UL)

RFCU_POWER RF_ALWAYS_EN1_REG: ALW_EN_VCO_LDO_EN (Bit 6)

Definition at line 10597 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_ADC_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_ADC_EN_Msk   (0x4UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_ADC_EN (Bitfield-Mask: 0x01)

Definition at line 10624 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_ADC_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_ADC_EN_Pos   (2UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_ADC_EN (Bit 2)

Definition at line 10623 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_BIAS_SH_OPEN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_BIAS_SH_OPEN_Msk   (0x1000UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_CP_BIAS_SH_OPEN (Bitfield-Mask: 0x01)

Definition at line 10644 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_BIAS_SH_OPEN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_BIAS_SH_OPEN_Pos   (12UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_CP_BIAS_SH_OPEN (Bit 12)

Definition at line 10643 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_EN_Msk   (0x20UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_CP_EN (Bitfield-Mask: 0x01)

Definition at line 10630 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_CP_EN_Pos   (5UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_CP_EN (Bit 5)

Definition at line 10629 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_DIV2_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_DIV2_EN_Msk   (0x800UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_DIV2_EN (Bitfield-Mask: 0x01)

Definition at line 10642 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_DIV2_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_DIV2_EN_Pos   (11UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_DIV2_EN (Bit 11)

Definition at line 10641 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_BIAS_SH_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_BIAS_SH_Msk   (0x8000UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_GAUSS_BIAS_SH (Bitfield-Mask: 0x01)

Definition at line 10650 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_BIAS_SH_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_BIAS_SH_Pos   (15UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_GAUSS_BIAS_SH (Bit 15)

Definition at line 10649 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_EN_Msk   (0x80UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_GAUSS_EN (Bitfield-Mask: 0x01)

Definition at line 10634 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_GAUSS_EN_Pos   (7UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_GAUSS_EN (Bit 7)

Definition at line 10633 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFF_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFF_EN_Msk   (0x2UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_IFF_EN (Bitfield-Mask: 0x01)

Definition at line 10622 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFF_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFF_EN_Pos   (1UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_IFF_EN (Bit 1)

Definition at line 10621 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFFMIX_BIAS_SH_OPEN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFFMIX_BIAS_SH_OPEN_Msk   (0x4000UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_IFFMIX_BIAS_SH_OPEN (Bitfield-Mask: 0x01)

Definition at line 10648 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFFMIX_BIAS_SH_OPEN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_IFFMIX_BIAS_SH_OPEN_Pos   (14UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_IFFMIX_BIAS_SH_OPEN (Bit 14)

Definition at line 10647 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_MD_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_MD_EN_Msk   (0x10UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_LOBUF_MD_EN (Bitfield-Mask: 0x01)

Definition at line 10628 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_MD_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_MD_EN_Pos   (4UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_LOBUF_MD_EN (Bit 4)

Definition at line 10627 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_PA_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_PA_EN_Msk   (0x200UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_LOBUF_PA_EN (Bitfield-Mask: 0x01)

Definition at line 10638 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_PA_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_LOBUF_PA_EN_Pos   (9UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_LOBUF_PA_EN (Bit 9)

Definition at line 10637 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_MIX_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_MIX_EN_Msk   (0x1UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_MIX_EN (Bitfield-Mask: 0x01)

Definition at line 10620 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_MIX_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_MIX_EN_Pos   (0UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_MIX_EN (Bit 0)

Definition at line 10619 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_PDF_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_PDF_EN_Msk   (0x40UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_PDF_EN (Bitfield-Mask: 0x01)

Definition at line 10632 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_PDF_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_PDF_EN_Pos   (6UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_PDF_EN (Bit 6)

Definition at line 10631 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RFIO_TXRX_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RFIO_TXRX_Msk   (0x100UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_RFIO_TXRX (Bitfield-Mask: 0x01)

Definition at line 10636 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RFIO_TXRX_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RFIO_TXRX_Pos   (8UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_RFIO_TXRX (Bit 8)

Definition at line 10635 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RXIQ_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RXIQ_EN_Msk   (0x400UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_RXIQ_EN (Bitfield-Mask: 0x01)

Definition at line 10640 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RXIQ_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_RXIQ_EN_Pos   (10UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_RXIQ_EN (Bit 10)

Definition at line 10639 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_BIAS_SH_OPEN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_BIAS_SH_OPEN_Msk   (0x2000UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_VCO_BIAS_SH_OPEN (Bitfield-Mask: 0x01)

Definition at line 10646 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_BIAS_SH_OPEN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_BIAS_SH_OPEN_Pos   (13UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_VCO_BIAS_SH_OPEN (Bit 13)

Definition at line 10645 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_EN_Msk   (0x8UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_VCO_EN (Bitfield-Mask: 0x01)

Definition at line 10626 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN2_REG_ALW_EN_VCO_EN_Pos   (3UL)

RFCU_POWER RF_ALWAYS_EN2_REG: ALW_EN_VCO_EN (Bit 3)

Definition at line 10625 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_ADC_CLK_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_ADC_CLK_EN_Msk   (0x800UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_ADC_CLK_EN (Bitfield-Mask: 0x01)

Definition at line 10676 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_ADC_CLK_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_ADC_CLK_EN_Pos   (11UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_ADC_CLK_EN (Bit 11)

Definition at line 10675 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_CAL_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_CAL_EN_Msk   (0x20UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_CAL_EN (Bitfield-Mask: 0x01)

Definition at line 10664 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_CAL_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_CAL_EN_Pos   (5UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_CAL_EN (Bit 5)

Definition at line 10663 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_DEM_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_DEM_EN_Msk   (0x8UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_DEM_EN (Bitfield-Mask: 0x01)

Definition at line 10660 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_DEM_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_DEM_EN_Pos   (3UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_DEM_EN (Bit 3)

Definition at line 10659 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RADIO_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RADIO_EN_Msk   (0x400UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_RADIO_EN (Bitfield-Mask: 0x01)

Definition at line 10674 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RADIO_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RADIO_EN_Pos   (10UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_RADIO_EN (Bit 10)

Definition at line 10673 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RFIO_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RFIO_EN_Msk   (0x80UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_RFIO_EN (Bitfield-Mask: 0x01)

Definition at line 10668 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RFIO_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_RFIO_EN_Pos   (7UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_RFIO_EN (Bit 7)

Definition at line 10667 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_ZERO_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_ZERO_EN_Msk   (0x10UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_ZERO_EN (Bitfield-Mask: 0x01)

Definition at line 10662 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_ZERO_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_LDO_ZERO_EN_Pos   (4UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_LDO_ZERO_EN (Bit 4)

Definition at line 10661 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_MIX_BIAS_SH_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_MIX_BIAS_SH_Msk   (0x1UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_MIX_BIAS_SH (Bitfield-Mask: 0x01)

Definition at line 10654 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_MIX_BIAS_SH_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_MIX_BIAS_SH_Pos   (0UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_MIX_BIAS_SH (Bit 0)

Definition at line 10653 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLL_DIG_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLL_DIG_EN_Msk   (0x2UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_PLL_DIG_EN (Bitfield-Mask: 0x01)

Definition at line 10656 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLL_DIG_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLL_DIG_EN_Pos   (1UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_PLL_DIG_EN (Bit 1)

Definition at line 10655 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLLCLOSED_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLLCLOSED_EN_Msk   (0x4UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_PLLCLOSED_EN (Bitfield-Mask: 0x01)

Definition at line 10658 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLLCLOSED_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_PLLCLOSED_EN_Pos   (2UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_PLLCLOSED_EN (Bit 2)

Definition at line 10657 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_EN_Msk   (0x100UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_RFIO_BIAS_EN (Bitfield-Mask: 0x01)

Definition at line 10670 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_EN_Pos   (8UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_RFIO_BIAS_EN (Bit 8)

Definition at line 10669 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_SH_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_SH_Msk   (0x200UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_RFIO_BIAS_SH (Bitfield-Mask: 0x01)

Definition at line 10672 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_SH_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_RFIO_BIAS_SH_Pos   (9UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_RFIO_BIAS_SH (Bit 9)

Definition at line 10671 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE2_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE2_EN_Msk   (0x4000UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_SPARE2_EN (Bitfield-Mask: 0x01)

Definition at line 10682 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE2_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE2_EN_Pos   (14UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_SPARE2_EN (Bit 14)

Definition at line 10681 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE3_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE3_EN_Msk   (0x8000UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_SPARE3_EN (Bitfield-Mask: 0x01)

Definition at line 10684 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE3_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_SPARE3_EN_Pos   (15UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_SPARE3_EN (Bit 15)

Definition at line 10683 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TDC_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TDC_EN_Msk   (0x40UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TDC_EN (Bitfield-Mask: 0x01)

Definition at line 10666 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TDC_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TDC_EN_Pos   (6UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TDC_EN (Bit 6)

Definition at line 10665 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TR_PWRM_OFF_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TR_PWRM_OFF_EN_Msk   (0x1000UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TR_PWRM_OFF_EN (Bitfield-Mask: 0x01)

Definition at line 10678 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TR_PWRM_OFF_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TR_PWRM_OFF_EN_Pos   (12UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TR_PWRM_OFF_EN (Bit 12)

Definition at line 10677 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TXDAC_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TXDAC_EN_Msk   (0x2000UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TXDAC_EN (Bitfield-Mask: 0x01)

Definition at line 10680 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TXDAC_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN3_REG_ALW_EN_TXDAC_EN_Pos   (13UL)

RFCU_POWER RF_ALWAYS_EN3_REG: ALW_EN_TXDAC_EN (Bit 13)

Definition at line 10679 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_DEM_FTDF_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_DEM_FTDF_EN_Msk   (0x2UL)

RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_DEM_FTDF_EN (Bitfield-Mask: 0x01)

Definition at line 10690 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_DEM_FTDF_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_DEM_FTDF_EN_Pos   (1UL)

RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_DEM_FTDF_EN (Bit 1)

Definition at line 10689 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_SPARE4_EN_Msk

#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_SPARE4_EN_Msk   (0x1UL)

RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_SPARE4_EN (Bitfield-Mask: 0x01)

Definition at line 10688 of file DA14680BA.h.

◆ RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_SPARE4_EN_Pos

#define RFCU_POWER_RF_ALWAYS_EN4_REG_ALW_EN_SPARE4_EN_Pos   (0UL)

RFCU_POWER RF_ALWAYS_EN4_REG: ALW_EN_SPARE4_EN (Bit 0)

Definition at line 10687 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_10_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_10_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10456 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_10_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_10_REG: RESET_OFFSET (Bit 8)

Definition at line 10455 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_10_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_10_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10454 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_10_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_10_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_10_REG: SET_OFFSET (Bit 0)

Definition at line 10453 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_11_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_11_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10462 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_11_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_11_REG: RESET_OFFSET (Bit 8)

Definition at line 10461 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_11_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_11_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10460 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_11_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_11_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_11_REG: SET_OFFSET (Bit 0)

Definition at line 10459 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_12_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_12_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10468 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_12_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_12_REG: RESET_OFFSET (Bit 8)

Definition at line 10467 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_12_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_12_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10466 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_12_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_12_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_12_REG: SET_OFFSET (Bit 0)

Definition at line 10465 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_13_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_13_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10474 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_13_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_13_REG: RESET_OFFSET (Bit 8)

Definition at line 10473 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_13_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_13_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10472 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_13_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_13_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_13_REG: SET_OFFSET (Bit 0)

Definition at line 10471 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_14_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_14_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10480 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_14_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_14_REG: RESET_OFFSET (Bit 8)

Definition at line 10479 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_14_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_14_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10478 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_14_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_14_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_14_REG: SET_OFFSET (Bit 0)

Definition at line 10477 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_15_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_15_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10486 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_15_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_15_REG: RESET_OFFSET (Bit 8)

Definition at line 10485 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_15_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_15_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10484 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_15_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_15_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_15_REG: SET_OFFSET (Bit 0)

Definition at line 10483 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_16_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_16_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10492 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_16_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_16_REG: RESET_OFFSET (Bit 8)

Definition at line 10491 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_16_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_16_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10490 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_16_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_16_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_16_REG: SET_OFFSET (Bit 0)

Definition at line 10489 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_17_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_17_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10498 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_17_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_17_REG: RESET_OFFSET (Bit 8)

Definition at line 10497 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_17_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_17_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10496 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_17_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_17_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_17_REG: SET_OFFSET (Bit 0)

Definition at line 10495 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_18_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_18_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10504 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_18_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_18_REG: RESET_OFFSET (Bit 8)

Definition at line 10503 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_18_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_18_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10502 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_18_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_18_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_18_REG: SET_OFFSET (Bit 0)

Definition at line 10501 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_19_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_19_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10510 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_19_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_19_REG: RESET_OFFSET (Bit 8)

Definition at line 10509 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_19_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_19_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10508 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_19_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_19_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_19_REG: SET_OFFSET (Bit 0)

Definition at line 10507 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_1_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_1_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10402 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_1_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_1_REG: RESET_OFFSET (Bit 8)

Definition at line 10401 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_1_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_1_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10400 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_1_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_1_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_1_REG: SET_OFFSET (Bit 0)

Definition at line 10399 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_20_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_20_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10516 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_20_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_20_REG: RESET_OFFSET (Bit 8)

Definition at line 10515 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_20_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_20_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10514 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_20_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_20_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_20_REG: SET_OFFSET (Bit 0)

Definition at line 10513 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_21_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_21_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10522 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_21_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_21_REG: RESET_OFFSET (Bit 8)

Definition at line 10521 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_21_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_21_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10520 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_21_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_21_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_21_REG: SET_OFFSET (Bit 0)

Definition at line 10519 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_22_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_22_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10528 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_22_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_22_REG: RESET_OFFSET (Bit 8)

Definition at line 10527 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_22_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_22_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10526 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_22_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_22_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_22_REG: SET_OFFSET (Bit 0)

Definition at line 10525 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_23_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_23_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10534 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_23_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_23_REG: RESET_OFFSET (Bit 8)

Definition at line 10533 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_23_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_23_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10532 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_23_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_23_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_23_REG: SET_OFFSET (Bit 0)

Definition at line 10531 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_24_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_24_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10540 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_24_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_24_REG: RESET_OFFSET (Bit 8)

Definition at line 10539 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_24_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_24_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10538 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_24_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_24_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_24_REG: SET_OFFSET (Bit 0)

Definition at line 10537 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_25_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_25_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10546 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_25_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_25_REG: RESET_OFFSET (Bit 8)

Definition at line 10545 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_25_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_25_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10544 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_25_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_25_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_25_REG: SET_OFFSET (Bit 0)

Definition at line 10543 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_26_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_26_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10552 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_26_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_26_REG: RESET_OFFSET (Bit 8)

Definition at line 10551 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_26_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_26_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10550 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_26_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_26_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_26_REG: SET_OFFSET (Bit 0)

Definition at line 10549 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_27_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_27_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10558 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_27_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_27_REG: RESET_OFFSET (Bit 8)

Definition at line 10557 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_27_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_27_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10556 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_27_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_27_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_27_REG: SET_OFFSET (Bit 0)

Definition at line 10555 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_28_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_28_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10564 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_28_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_28_REG: RESET_OFFSET (Bit 8)

Definition at line 10563 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_28_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_28_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10562 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_28_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_28_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_28_REG: SET_OFFSET (Bit 0)

Definition at line 10561 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_29_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_29_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10570 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_29_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_29_REG: RESET_OFFSET (Bit 8)

Definition at line 10569 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_29_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_29_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10568 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_29_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_29_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_29_REG: SET_OFFSET (Bit 0)

Definition at line 10567 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_2_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_2_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10408 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_2_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_2_REG: RESET_OFFSET (Bit 8)

Definition at line 10407 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_2_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_2_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10406 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_2_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_2_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_2_REG: SET_OFFSET (Bit 0)

Definition at line 10405 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_30_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_30_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10576 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_30_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_30_REG: RESET_OFFSET (Bit 8)

Definition at line 10575 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_30_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_30_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10574 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_30_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_30_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_30_REG: SET_OFFSET (Bit 0)

Definition at line 10573 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_31_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_31_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10582 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_31_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_31_REG: RESET_OFFSET (Bit 8)

Definition at line 10581 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_31_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_31_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10580 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_31_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_31_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_31_REG: SET_OFFSET (Bit 0)

Definition at line 10579 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_3_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_3_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10414 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_3_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_3_REG: RESET_OFFSET (Bit 8)

Definition at line 10413 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_3_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_3_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10412 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_3_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_3_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_3_REG: SET_OFFSET (Bit 0)

Definition at line 10411 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_4_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_4_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10420 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_4_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_4_REG: RESET_OFFSET (Bit 8)

Definition at line 10419 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_4_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_4_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10418 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_4_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_4_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_4_REG: SET_OFFSET (Bit 0)

Definition at line 10417 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_5_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_5_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10426 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_5_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_5_REG: RESET_OFFSET (Bit 8)

Definition at line 10425 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_5_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_5_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10424 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_5_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_5_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_5_REG: SET_OFFSET (Bit 0)

Definition at line 10423 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_6_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_6_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10432 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_6_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_6_REG: RESET_OFFSET (Bit 8)

Definition at line 10431 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_6_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_6_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10430 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_6_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_6_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_6_REG: SET_OFFSET (Bit 0)

Definition at line 10429 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_7_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_7_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10438 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_7_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_7_REG: RESET_OFFSET (Bit 8)

Definition at line 10437 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_7_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_7_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10436 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_7_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_7_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_7_REG: SET_OFFSET (Bit 0)

Definition at line 10435 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_8_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_8_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10444 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_8_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_8_REG: RESET_OFFSET (Bit 8)

Definition at line 10443 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_8_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_8_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10442 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_8_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_8_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_8_REG: SET_OFFSET (Bit 0)

Definition at line 10441 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_9_REG_RESET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_RESET_OFFSET_Msk   (0xff00UL)

RFCU_POWER RF_CNTRL_TIMER_9_REG: RESET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10450 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_9_REG_RESET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_RESET_OFFSET_Pos   (8UL)

RFCU_POWER RF_CNTRL_TIMER_9_REG: RESET_OFFSET (Bit 8)

Definition at line 10449 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_9_REG_SET_OFFSET_Msk

#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_SET_OFFSET_Msk   (0xffUL)

RFCU_POWER RF_CNTRL_TIMER_9_REG: SET_OFFSET (Bitfield-Mask: 0xff)

Definition at line 10448 of file DA14680BA.h.

◆ RFCU_POWER_RF_CNTRL_TIMER_9_REG_SET_OFFSET_Pos

#define RFCU_POWER_RF_CNTRL_TIMER_9_REG_SET_OFFSET_Pos   (0UL)

RFCU_POWER RF_CNTRL_TIMER_9_REG: SET_OFFSET (Bit 0)

Definition at line 10447 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10028 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_rx (Bit 0)

Definition at line 10027 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10030 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG0_REG_lna_ldo_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG0_REG: lna_ldo_en_dcf_tx (Bit 5)

Definition at line 10029 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10088 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_rx (Bit 0)

Definition at line 10087 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10090 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG10_REG_cp_switch_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG10_REG: cp_switch_en_dcf_tx (Bit 5)

Definition at line 10089 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10094 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_rx (Bit 0)

Definition at line 10093 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10096 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG11_REG_vco_bias_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG11_REG: vco_bias_en_dcf_tx (Bit 5)

Definition at line 10095 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10100 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_rx (Bit 0)

Definition at line 10099 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10102 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG12_REG_cp_bias_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG12_REG: cp_bias_en_dcf_tx (Bit 5)

Definition at line 10101 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10106 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_rx (Bit 0)

Definition at line 10105 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10108 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG13_REG_lna_ldo_zero_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG13_REG: lna_ldo_zero_dcf_tx (Bit 5)

Definition at line 10107 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10112 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_rx (Bit 0)

Definition at line 10111 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10114 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG14_REG_pa_ramp_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG14_REG: pa_ramp_en_dcf_tx (Bit 5)

Definition at line 10113 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10118 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_rx (Bit 0)

Definition at line 10117 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10120 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG15_REG_pa_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG15_REG: pa_en_dcf_tx (Bit 5)

Definition at line 10119 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10124 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_rx (Bit 0)

Definition at line 10123 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10126 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG16_REG_mix_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG16_REG: mix_en_dcf_tx (Bit 5)

Definition at line 10125 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10130 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_rx (Bit 0)

Definition at line 10129 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10132 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG17_REG_iff_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG17_REG: iff_en_dcf_tx (Bit 5)

Definition at line 10131 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10136 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_rx (Bit 0)

Definition at line 10135 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10138 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG18_REG_adc_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG18_REG: adc_en_dcf_tx (Bit 5)

Definition at line 10137 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10142 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_rx (Bit 0)

Definition at line 10141 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10144 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG19_REG_vco_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG19_REG: vco_en_dcf_tx (Bit 5)

Definition at line 10143 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10034 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_rx (Bit 0)

Definition at line 10033 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10036 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG1_REG_lna_core_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG1_REG: lna_core_en_dcf_tx (Bit 5)

Definition at line 10035 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10148 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_rx (Bit 0)

Definition at line 10147 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10150 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG20_REG_lobuf_md_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG20_REG: lobuf_md_en_dcf_tx (Bit 5)

Definition at line 10149 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10154 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_rx (Bit 0)

Definition at line 10153 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10156 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG21_REG_cp_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG21_REG: cp_en_dcf_tx (Bit 5)

Definition at line 10155 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10160 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_rx (Bit 0)

Definition at line 10159 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10162 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG22_REG_pfd_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG22_REG: pfd_en_dcf_tx (Bit 5)

Definition at line 10161 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG23_BLE_REG: gauss_en_ble_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10166 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG23_BLE_REG: gauss_en_ble_dcf_rx (Bit 0)

Definition at line 10165 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG23_BLE_REG: gauss_en_ble_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10168 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG23_BLE_REG_gauss_en_ble_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG23_BLE_REG: gauss_en_ble_dcf_tx (Bit 5)

Definition at line 10167 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10328 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_rx (Bit 0)

Definition at line 10327 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10330 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG23_FTDF_REG_gauss_en_ftdf_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG23_FTDF_REG: gauss_en_ftdf_dcf_tx (Bit 5)

Definition at line 10329 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10172 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_rx (Bit 0)

Definition at line 10171 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10174 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG24_BLE_REG_rfio_txrx_ble_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG24_BLE_REG: rfio_txrx_ble_dcf_tx (Bit 5)

Definition at line 10173 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10334 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_rx (Bit 0)

Definition at line 10333 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10336 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG24_FTDF_REG_rfio_txrx_ftdf_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG24_FTDF_REG: rfio_txrx_ftdf_dcf_tx (Bit 5)

Definition at line 10335 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10178 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_rx (Bit 0)

Definition at line 10177 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10180 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG25_REG_lobuf_pa_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG25_REG: lobuf_pa_en_dcf_tx (Bit 5)

Definition at line 10179 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10184 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_rx (Bit 0)

Definition at line 10183 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10186 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG26_REG_lobuf_rxiq_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG26_REG: lobuf_rxiq_en_dcf_tx (Bit 5)

Definition at line 10185 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10190 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_rx (Bit 0)

Definition at line 10189 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10192 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG27_REG_div2_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG27_REG: div2_en_dcf_tx (Bit 5)

Definition at line 10191 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10196 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_rx (Bit 0)

Definition at line 10195 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10198 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG28_REG_cp_bias_sh_open_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG28_REG: cp_bias_sh_open_dcf_tx (Bit 5)

Definition at line 10197 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10202 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_rx (Bit 0)

Definition at line 10201 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10204 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG29_REG_vco_bias_sh_open_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG29_REG: vco_bias_sh_open_dcf_tx (Bit 5)

Definition at line 10203 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10040 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_rx (Bit 0)

Definition at line 10039 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10042 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG2_REG_lna_cgm_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG2_REG: lna_cgm_en_dcf_tx (Bit 5)

Definition at line 10041 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10208 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_rx (Bit 0)

Definition at line 10207 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10210 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG30_REG_iffmix_bias_sh_open_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG30_REG: iffmix_bias_sh_open_dcf_tx (Bit 5)

Definition at line 10209 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10214 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_rx (Bit 0)

Definition at line 10213 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10216 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG31_BLE_REG_gauss_bias_sh_ble_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG31_BLE_REG: gauss_bias_sh_ble_dcf_tx (Bit 5)

Definition at line 10215 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10340 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_rx (Bit 0)

Definition at line 10339 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10342 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG31_FTDF_REG_gauss_bias_sh_ftdf_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG31_FTDF_REG: gauss_bias_sh_ftdf_dcf_tx (Bit 5)

Definition at line 10341 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10220 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_rx (Bit 0)

Definition at line 10219 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10222 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG32_REG_mix_bias_sh_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG32_REG: mix_bias_sh_dcf_tx (Bit 5)

Definition at line 10221 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10226 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_rx (Bit 0)

Definition at line 10225 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10228 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG33_REG_pll_dig_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG33_REG: pll_dig_en_dcf_tx (Bit 5)

Definition at line 10227 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10232 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_rx (Bit 0)

Definition at line 10231 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10234 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG34_REG_pllclosed_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG34_REG: pllclosed_en_dcf_tx (Bit 5)

Definition at line 10233 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10238 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_rx (Bit 0)

Definition at line 10237 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10240 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG35_BLE_REG_dem_en_ble_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG35_BLE_REG: dem_en_ble_dcf_tx (Bit 5)

Definition at line 10239 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10346 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_rx (Bit 0)

Definition at line 10345 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10348 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG35_FTDF_REG_dem_en_ftdf_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG35_FTDF_REG: dem_en_ftdf_dcf_tx (Bit 5)

Definition at line 10347 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10244 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_rx (Bit 0)

Definition at line 10243 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10246 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG36_REG_ldo_zero_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG36_REG: ldo_zero_en_dcf_tx (Bit 5)

Definition at line 10245 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG37_BLE_REG: cal_en_ble_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10250 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG37_BLE_REG: cal_en_ble_dcf_rx (Bit 0)

Definition at line 10249 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG37_BLE_REG: cal_en_ble_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10252 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG37_BLE_REG_cal_en_ble_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG37_BLE_REG: cal_en_ble_dcf_tx (Bit 5)

Definition at line 10251 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10352 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_rx (Bit 0)

Definition at line 10351 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10354 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG37_FTDF_REG_cal_en_ftdf_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG37_FTDF_REG: cal_en_ftdf_dcf_tx (Bit 5)

Definition at line 10353 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10256 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_rx (Bit 0)

Definition at line 10255 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10258 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG38_BLE_REG_tdc_en_ble_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG38_BLE_REG: tdc_en_ble_dcf_tx (Bit 5)

Definition at line 10257 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10358 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_rx (Bit 0)

Definition at line 10357 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10360 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG38_FTDF_REG_tdc_en_ftdf_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG38_FTDF_REG: tdc_en_ftdf_dcf_tx (Bit 5)

Definition at line 10359 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10262 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_rx (Bit 0)

Definition at line 10261 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10264 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG39_REG_ldo_rfio_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG39_REG: ldo_rfio_en_dcf_tx (Bit 5)

Definition at line 10263 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10046 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_rx (Bit 0)

Definition at line 10045 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10048 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG3_REG_mix_ldo_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG3_REG: mix_ldo_en_dcf_tx (Bit 5)

Definition at line 10047 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10268 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_rx (Bit 0)

Definition at line 10267 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10270 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG40_REG_rfio_bias_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG40_REG: rfio_bias_en_dcf_tx (Bit 5)

Definition at line 10269 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10274 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_rx (Bit 0)

Definition at line 10273 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10276 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG41_REG_rfio_bias_sh_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG41_REG: rfio_bias_sh_dcf_tx (Bit 5)

Definition at line 10275 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10280 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_rx (Bit 0)

Definition at line 10279 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10282 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG42_REG_ldo_radio_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG42_REG: ldo_radio_en_dcf_tx (Bit 5)

Definition at line 10281 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10286 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_rx (Bit 0)

Definition at line 10285 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10288 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG43_REG_adc_clk_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG43_REG: adc_clk_en_dcf_tx (Bit 5)

Definition at line 10287 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG44_BLE_REG: tr_pwm_off_en_ble_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10292 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG44_BLE_REG: tr_pwm_off_en_ble_dcf_rx (Bit 0)

Definition at line 10291 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG44_BLE_REG: tr_pwm_off_en_ble_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10294 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG44_BLE_REG_tr_pwm_off_en_ble_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG44_BLE_REG: tr_pwm_off_en_ble_dcf_tx (Bit 5)

Definition at line 10293 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10364 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_rx (Bit 0)

Definition at line 10363 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10366 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG44_FTDF_REG_tr_pwm_off_en_ftdf_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG44_FTDF_REG: tr_pwm_off_en_ftdf_dcf_tx (Bit 5)

Definition at line 10365 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG45_BLE_REG: txdac_en_ble_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10298 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG45_BLE_REG: txdac_en_ble_dcf_rx (Bit 0)

Definition at line 10297 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG45_BLE_REG: txdac_en_ble_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10300 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG45_BLE_REG_txdac_en_ble_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG45_BLE_REG: txdac_en_ble_dcf_tx (Bit 5)

Definition at line 10299 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG45_FTDF_REG: txdac_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10370 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG45_FTDF_REG: txdac_en_ftdf_dcf_rx (Bit 0)

Definition at line 10369 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG45_FTDF_REG: txdac_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10372 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG45_FTDF_REG_txdac_en_ftdf_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG45_FTDF_REG: txdac_en_ftdf_dcf_tx (Bit 5)

Definition at line 10371 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dem_dcparcal_en_ble_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dem_dcparcal_en_ble_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: dem_dcparcal_en_ble_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10304 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dem_dcparcal_en_ble_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_dem_dcparcal_en_ble_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: dem_dcparcal_en_ble_dcf_rx (Bit 0)

Definition at line 10303 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_spare2_en_ble_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_spare2_en_ble_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: spare2_en_ble_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10306 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_spare2_en_ble_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG46_BLE_REG_spare2_en_ble_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG46_BLE_REG: spare2_en_ble_dcf_tx (Bit 5)

Definition at line 10305 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dem_dcparcal_en_ftdf_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dem_dcparcal_en_ftdf_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: dem_dcparcal_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10376 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dem_dcparcal_en_ftdf_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_dem_dcparcal_en_ftdf_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: dem_dcparcal_en_ftdf_dcf_rx (Bit 0)

Definition at line 10375 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_spare2_en_ftdf_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_spare2_en_ftdf_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: spare2_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10378 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_spare2_en_ftdf_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG46_FTDF_REG_spare2_en_ftdf_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG46_FTDF_REG: spare2_en_ftdf_dcf_tx (Bit 5)

Definition at line 10377 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_dem_agcunfreeze_en_ble_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_dem_agcunfreeze_en_ble_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: dem_agcunfreeze_en_ble_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10310 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_dem_agcunfreeze_en_ble_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_dem_agcunfreeze_en_ble_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: dem_agcunfreeze_en_ble_dcf_rx (Bit 0)

Definition at line 10309 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_spare3_en_ble_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_spare3_en_ble_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: spare3_en_ble_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10312 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_spare3_en_ble_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG47_BLE_REG_spare3_en_ble_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG47_BLE_REG: spare3_en_ble_dcf_tx (Bit 5)

Definition at line 10311 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_dem_agcunfreeze_en_ftdf_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_dem_agcunfreeze_en_ftdf_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: dem_agcunfreeze_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10382 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_dem_agcunfreeze_en_ftdf_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_dem_agcunfreeze_en_ftdf_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: dem_agcunfreeze_en_ftdf_dcf_rx (Bit 0)

Definition at line 10381 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_spare3_en_ftdf_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_spare3_en_ftdf_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: spare3_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10384 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_spare3_en_ftdf_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG47_FTDF_REG_spare3_en_ftdf_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG47_FTDF_REG: spare3_en_ftdf_dcf_tx (Bit 5)

Definition at line 10383 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_dem_sigdetect_en_ble_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_dem_sigdetect_en_ble_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: dem_sigdetect_en_ble_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10316 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_dem_sigdetect_en_ble_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_dem_sigdetect_en_ble_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: dem_sigdetect_en_ble_dcf_rx (Bit 0)

Definition at line 10315 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_spare4_en_ble_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_spare4_en_ble_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: spare4_en_ble_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10318 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_spare4_en_ble_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG48_BLE_REG_spare4_en_ble_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG48_BLE_REG: spare4_en_ble_dcf_tx (Bit 5)

Definition at line 10317 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_dem_sigdetect_en_ftdf_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_dem_sigdetect_en_ftdf_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: dem_sigdetect_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10388 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_dem_sigdetect_en_ftdf_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_dem_sigdetect_en_ftdf_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: dem_sigdetect_en_ftdf_dcf_rx (Bit 0)

Definition at line 10387 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_spare4_en_ftdf_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_spare4_en_ftdf_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: spare4_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10390 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_spare4_en_ftdf_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG48_FTDF_REG_spare4_en_ftdf_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG48_FTDF_REG: spare4_en_ftdf_dcf_tx (Bit 5)

Definition at line 10389 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10322 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_rx (Bit 0)

Definition at line 10321 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10324 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG49_BLE_REG_dem_ftdf_en_ble_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG49_BLE_REG: dem_ftdf_en_ble_dcf_tx (Bit 5)

Definition at line 10323 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG49_FTDF_REG: dem_ftdf_en_ftdf_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10394 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG49_FTDF_REG: dem_ftdf_en_ftdf_dcf_rx (Bit 0)

Definition at line 10393 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG49_FTDF_REG: dem_ftdf_en_ftdf_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10396 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG49_FTDF_REG_dem_ftdf_en_ftdf_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG49_FTDF_REG: dem_ftdf_en_ftdf_dcf_tx (Bit 5)

Definition at line 10395 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10052 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_rx (Bit 0)

Definition at line 10051 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10054 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG4_REG_iff_ldo_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG4_REG: iff_ldo_en_dcf_tx (Bit 5)

Definition at line 10053 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10058 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_rx (Bit 0)

Definition at line 10057 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10060 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG5_REG_iffadc_ldo_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG5_REG: iffadc_ldo_en_dcf_tx (Bit 5)

Definition at line 10059 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10064 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_rx (Bit 0)

Definition at line 10063 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10066 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG6_REG_vco_ldo_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG6_REG: vco_ldo_en_dcf_tx (Bit 5)

Definition at line 10065 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10070 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_rx (Bit 0)

Definition at line 10069 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10072 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG7_REG_md_ldo_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG7_REG: md_ldo_en_dcf_tx (Bit 5)

Definition at line 10071 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10076 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_rx (Bit 0)

Definition at line 10075 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10078 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG8_REG_pfd_ldo_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG8_REG: pfd_ldo_en_dcf_tx (Bit 5)

Definition at line 10077 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_rx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_rx_Msk   (0x1fUL)

RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_rx (Bitfield-Mask: 0x1f)

Definition at line 10082 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_rx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_rx_Pos   (0UL)

RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_rx (Bit 0)

Definition at line 10081 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_tx_Msk

#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_tx_Msk   (0x3e0UL)

RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_tx (Bitfield-Mask: 0x1f)

Definition at line 10084 of file DA14680BA.h.

◆ RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_tx_Pos

#define RFCU_POWER_RF_ENABLE_CONFIG9_REG_pa_ldo_en_dcf_tx_Pos   (5UL)

RFCU_POWER RF_ENABLE_CONFIG9_REG: pa_ldo_en_dcf_tx (Bit 5)

Definition at line 10083 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_RX_Msk

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_RX_Msk   (0x1UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_RX (Bitfield-Mask: 0x01)

Definition at line 10694 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_RX_Pos

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_RX_Pos   (0UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_RX (Bit 0)

Definition at line 10693 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_TX_Msk

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_TX_Msk   (0x2UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_TX (Bitfield-Mask: 0x01)

Definition at line 10696 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_TX_Pos

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT0_TX_Pos   (1UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT0_TX (Bit 1)

Definition at line 10695 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_RX_Msk

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_RX_Msk   (0x4UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_RX (Bitfield-Mask: 0x01)

Definition at line 10698 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_RX_Pos

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_RX_Pos   (2UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_RX (Bit 2)

Definition at line 10697 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_TX_Msk

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_TX_Msk   (0x8UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_TX (Bitfield-Mask: 0x01)

Definition at line 10700 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_TX_Pos

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT1_TX_Pos   (3UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT1_TX (Bit 3)

Definition at line 10699 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_RX_Msk

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_RX_Msk   (0x10UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_RX (Bitfield-Mask: 0x01)

Definition at line 10702 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_RX_Pos

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_RX_Pos   (4UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_RX (Bit 4)

Definition at line 10701 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_TX_Msk

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_TX_Msk   (0x20UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_TX (Bitfield-Mask: 0x01)

Definition at line 10704 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_TX_Pos

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT2_TX_Pos   (5UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT2_TX (Bit 5)

Definition at line 10703 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Msk

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Msk   (0x40UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_RX (Bitfield-Mask: 0x01)

Definition at line 10706 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Pos

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_RX_Pos   (6UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_RX (Bit 6)

Definition at line 10705 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Msk

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Msk   (0x80UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_TX (Bitfield-Mask: 0x01)

Definition at line 10708 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Pos

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT3_TX_Pos   (7UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT3_TX (Bit 7)

Definition at line 10707 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_RX_Msk

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_RX_Msk   (0x100UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_RX (Bitfield-Mask: 0x01)

Definition at line 10710 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_RX_Pos

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_RX_Pos   (8UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_RX (Bit 8)

Definition at line 10709 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_TX_Msk

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_TX_Msk   (0x200UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_TX (Bitfield-Mask: 0x01)

Definition at line 10712 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_TX_Pos

#define RFCU_POWER_RF_PORT_EN_BLE_REG_RF_PORT4_TX_Pos   (9UL)

RFCU_POWER RF_PORT_EN_BLE_REG: RF_PORT4_TX (Bit 9)

Definition at line 10711 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_RX_Msk

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_RX_Msk   (0x1UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_RX (Bitfield-Mask: 0x01)

Definition at line 10716 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_RX_Pos

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_RX_Pos   (0UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_RX (Bit 0)

Definition at line 10715 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_TX_Msk

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_TX_Msk   (0x2UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_TX (Bitfield-Mask: 0x01)

Definition at line 10718 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_TX_Pos

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT0_TX_Pos   (1UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT0_TX (Bit 1)

Definition at line 10717 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_RX_Msk

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_RX_Msk   (0x4UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_RX (Bitfield-Mask: 0x01)

Definition at line 10720 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_RX_Pos

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_RX_Pos   (2UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_RX (Bit 2)

Definition at line 10719 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_TX_Msk

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_TX_Msk   (0x8UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_TX (Bitfield-Mask: 0x01)

Definition at line 10722 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_TX_Pos

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT1_TX_Pos   (3UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT1_TX (Bit 3)

Definition at line 10721 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_RX_Msk

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_RX_Msk   (0x10UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_RX (Bitfield-Mask: 0x01)

Definition at line 10724 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_RX_Pos

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_RX_Pos   (4UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_RX (Bit 4)

Definition at line 10723 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_TX_Msk

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_TX_Msk   (0x20UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_TX (Bitfield-Mask: 0x01)

Definition at line 10726 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_TX_Pos

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT2_TX_Pos   (5UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT2_TX (Bit 5)

Definition at line 10725 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Msk

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Msk   (0x40UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_RX (Bitfield-Mask: 0x01)

Definition at line 10728 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Pos

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_RX_Pos   (6UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_RX (Bit 6)

Definition at line 10727 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Msk

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Msk   (0x80UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_TX (Bitfield-Mask: 0x01)

Definition at line 10730 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Pos

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT3_TX_Pos   (7UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT3_TX (Bit 7)

Definition at line 10729 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_RX_Msk

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_RX_Msk   (0x100UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_RX (Bitfield-Mask: 0x01)

Definition at line 10732 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_RX_Pos

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_RX_Pos   (8UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_RX (Bit 8)

Definition at line 10731 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_TX_Msk

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_TX_Msk   (0x200UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_TX (Bitfield-Mask: 0x01)

Definition at line 10734 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_TX_Pos

#define RFCU_POWER_RF_PORT_EN_FTDF_REG_RF_PORT4_TX_Pos   (9UL)

RFCU_POWER RF_PORT_EN_FTDF_REG: RF_PORT4_TX (Bit 9)

Definition at line 10733 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_POL_REG_RF_PORT0_POL_Msk

#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT0_POL_Msk   (0x1UL)

RFCU_POWER RF_PORT_POL_REG: RF_PORT0_POL (Bitfield-Mask: 0x01)

Definition at line 10738 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_POL_REG_RF_PORT0_POL_Pos

#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT0_POL_Pos   (0UL)

RFCU_POWER RF_PORT_POL_REG: RF_PORT0_POL (Bit 0)

Definition at line 10737 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_POL_REG_RF_PORT1_POL_Msk

#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT1_POL_Msk   (0x2UL)

RFCU_POWER RF_PORT_POL_REG: RF_PORT1_POL (Bitfield-Mask: 0x01)

Definition at line 10740 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_POL_REG_RF_PORT1_POL_Pos

#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT1_POL_Pos   (1UL)

RFCU_POWER RF_PORT_POL_REG: RF_PORT1_POL (Bit 1)

Definition at line 10739 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_POL_REG_RF_PORT2_POL_Msk

#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT2_POL_Msk   (0x4UL)

RFCU_POWER RF_PORT_POL_REG: RF_PORT2_POL (Bitfield-Mask: 0x01)

Definition at line 10742 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_POL_REG_RF_PORT2_POL_Pos

#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT2_POL_Pos   (2UL)

RFCU_POWER RF_PORT_POL_REG: RF_PORT2_POL (Bit 2)

Definition at line 10741 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_POL_REG_RF_PORT3_POL_Msk

#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT3_POL_Msk   (0x8UL)

RFCU_POWER RF_PORT_POL_REG: RF_PORT3_POL (Bitfield-Mask: 0x01)

Definition at line 10744 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_POL_REG_RF_PORT3_POL_Pos

#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT3_POL_Pos   (3UL)

RFCU_POWER RF_PORT_POL_REG: RF_PORT3_POL (Bit 3)

Definition at line 10743 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_POL_REG_RF_PORT4_POL_Msk

#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT4_POL_Msk   (0x10UL)

RFCU_POWER RF_PORT_POL_REG: RF_PORT4_POL (Bitfield-Mask: 0x01)

Definition at line 10746 of file DA14680BA.h.

◆ RFCU_POWER_RF_PORT_POL_REG_RF_PORT4_POL_Pos

#define RFCU_POWER_RF_PORT_POL_REG_RF_PORT4_POL_Pos   (4UL)

RFCU_POWER RF_PORT_POL_REG: RF_PORT4_POL (Bit 4)

Definition at line 10745 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL1_REG_ADC_DC_OFFSET_SEL_Msk

#define RFCU_RF_ADC_CTRL1_REG_ADC_DC_OFFSET_SEL_Msk   (0x1UL)

RFCU RF_ADC_CTRL1_REG: ADC_DC_OFFSET_SEL (Bitfield-Mask: 0x01)

Definition at line 9686 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL1_REG_ADC_DC_OFFSET_SEL_Pos

#define RFCU_RF_ADC_CTRL1_REG_ADC_DC_OFFSET_SEL_Pos   (0UL)

RFCU RF_ADC_CTRL1_REG: ADC_DC_OFFSET_SEL (Bit 0)

Definition at line 9685 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL1_REG_ADC_MUTE_Msk

#define RFCU_RF_ADC_CTRL1_REG_ADC_MUTE_Msk   (0x2000UL)

RFCU RF_ADC_CTRL1_REG: ADC_MUTE (Bitfield-Mask: 0x01)

Definition at line 9688 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL1_REG_ADC_MUTE_Pos

#define RFCU_RF_ADC_CTRL1_REG_ADC_MUTE_Pos   (13UL)

RFCU RF_ADC_CTRL1_REG: ADC_MUTE (Bit 13)

Definition at line 9687 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL1_REG_ADC_SIGN_Msk

#define RFCU_RF_ADC_CTRL1_REG_ADC_SIGN_Msk   (0x4000UL)

RFCU RF_ADC_CTRL1_REG: ADC_SIGN (Bitfield-Mask: 0x01)

Definition at line 9690 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL1_REG_ADC_SIGN_Pos

#define RFCU_RF_ADC_CTRL1_REG_ADC_SIGN_Pos   (14UL)

RFCU RF_ADC_CTRL1_REG: ADC_SIGN (Bit 14)

Definition at line 9689 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL2_REG_ADC_OFFN_I_WR_Msk

#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFN_I_WR_Msk   (0xff00UL)

RFCU RF_ADC_CTRL2_REG: ADC_OFFN_I_WR (Bitfield-Mask: 0xff)

Definition at line 9696 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL2_REG_ADC_OFFN_I_WR_Pos

#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFN_I_WR_Pos   (8UL)

RFCU RF_ADC_CTRL2_REG: ADC_OFFN_I_WR (Bit 8)

Definition at line 9695 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL2_REG_ADC_OFFP_I_WR_Msk

#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFP_I_WR_Msk   (0xffUL)

RFCU RF_ADC_CTRL2_REG: ADC_OFFP_I_WR (Bitfield-Mask: 0xff)

Definition at line 9694 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL2_REG_ADC_OFFP_I_WR_Pos

#define RFCU_RF_ADC_CTRL2_REG_ADC_OFFP_I_WR_Pos   (0UL)

RFCU RF_ADC_CTRL2_REG: ADC_OFFP_I_WR (Bit 0)

Definition at line 9693 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL3_REG_ADC_OFFN_Q_WR_Msk

#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFN_Q_WR_Msk   (0xff00UL)

RFCU RF_ADC_CTRL3_REG: ADC_OFFN_Q_WR (Bitfield-Mask: 0xff)

Definition at line 9702 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL3_REG_ADC_OFFN_Q_WR_Pos

#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFN_Q_WR_Pos   (8UL)

RFCU RF_ADC_CTRL3_REG: ADC_OFFN_Q_WR (Bit 8)

Definition at line 9701 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL3_REG_ADC_OFFP_Q_WR_Msk

#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFP_Q_WR_Msk   (0xffUL)

RFCU RF_ADC_CTRL3_REG: ADC_OFFP_Q_WR (Bitfield-Mask: 0xff)

Definition at line 9700 of file DA14680BA.h.

◆ RFCU_RF_ADC_CTRL3_REG_ADC_OFFP_Q_WR_Pos

#define RFCU_RF_ADC_CTRL3_REG_ADC_OFFP_Q_WR_Pos   (0UL)

RFCU RF_ADC_CTRL3_REG: ADC_OFFP_Q_WR (Bit 0)

Definition at line 9699 of file DA14680BA.h.

◆ RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFN_I_RD_Msk

#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFN_I_RD_Msk   (0xff00UL)

RFCU RF_ADCI_DC_OFFSET_REG: ADC_OFFN_I_RD (Bitfield-Mask: 0xff)

Definition at line 9612 of file DA14680BA.h.

◆ RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFN_I_RD_Pos

#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFN_I_RD_Pos   (8UL)

RFCU RF_ADCI_DC_OFFSET_REG: ADC_OFFN_I_RD (Bit 8)

Definition at line 9611 of file DA14680BA.h.

◆ RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFP_I_RD_Msk

#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFP_I_RD_Msk   (0xffUL)

RFCU RF_ADCI_DC_OFFSET_REG: ADC_OFFP_I_RD (Bitfield-Mask: 0xff)

Definition at line 9610 of file DA14680BA.h.

◆ RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFP_I_RD_Pos

#define RFCU_RF_ADCI_DC_OFFSET_REG_ADC_OFFP_I_RD_Pos   (0UL)

RFCU RF_ADCI_DC_OFFSET_REG: ADC_OFFP_I_RD (Bit 0)

Definition at line 9609 of file DA14680BA.h.

◆ RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFN_Q_RD_Msk

#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFN_Q_RD_Msk   (0xff00UL)

RFCU RF_ADCQ_DC_OFFSET_REG: ADC_OFFN_Q_RD (Bitfield-Mask: 0xff)

Definition at line 9618 of file DA14680BA.h.

◆ RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFN_Q_RD_Pos

#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFN_Q_RD_Pos   (8UL)

RFCU RF_ADCQ_DC_OFFSET_REG: ADC_OFFN_Q_RD (Bit 8)

Definition at line 9617 of file DA14680BA.h.

◆ RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFP_Q_RD_Msk

#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFP_Q_RD_Msk   (0xffUL)

RFCU RF_ADCQ_DC_OFFSET_REG: ADC_OFFP_Q_RD (Bitfield-Mask: 0xff)

Definition at line 9616 of file DA14680BA.h.

◆ RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFP_Q_RD_Pos

#define RFCU_RF_ADCQ_DC_OFFSET_REG_ADC_OFFP_Q_RD_Pos   (0UL)

RFCU RF_ADCQ_DC_OFFSET_REG: ADC_OFFP_Q_RD (Bit 0)

Definition at line 9615 of file DA14680BA.h.

◆ RFCU_RF_AGC_EXT1_LUT_REG_AGC_EXT_LUT_Msk

#define RFCU_RF_AGC_EXT1_LUT_REG_AGC_EXT_LUT_Msk   (0x3ffUL)

RFCU RF_AGC_EXT1_LUT_REG: AGC_EXT_LUT (Bitfield-Mask: 0x3ff)

Definition at line 9566 of file DA14680BA.h.

◆ RFCU_RF_AGC_EXT1_LUT_REG_AGC_EXT_LUT_Pos

#define RFCU_RF_AGC_EXT1_LUT_REG_AGC_EXT_LUT_Pos   (0UL)

RFCU RF_AGC_EXT1_LUT_REG: AGC_EXT_LUT (Bit 0)

Definition at line 9565 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_BLE_REG_CP_BIAS_BLE_SET_Msk

#define RFCU_RF_BIAS_CTRL1_BLE_REG_CP_BIAS_BLE_SET_Msk   (0xf0UL)

RFCU RF_BIAS_CTRL1_BLE_REG: CP_BIAS_BLE_SET (Bitfield-Mask: 0x0f)

Definition at line 9652 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_BLE_REG_CP_BIAS_BLE_SET_Pos

#define RFCU_RF_BIAS_CTRL1_BLE_REG_CP_BIAS_BLE_SET_Pos   (4UL)

RFCU RF_BIAS_CTRL1_BLE_REG: CP_BIAS_BLE_SET (Bit 4)

Definition at line 9651 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_BLE_REG_IFF_BIAS_BLE_SET_Msk

#define RFCU_RF_BIAS_CTRL1_BLE_REG_IFF_BIAS_BLE_SET_Msk   (0xf000UL)

RFCU RF_BIAS_CTRL1_BLE_REG: IFF_BIAS_BLE_SET (Bitfield-Mask: 0x0f)

Definition at line 9656 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_BLE_REG_IFF_BIAS_BLE_SET_Pos

#define RFCU_RF_BIAS_CTRL1_BLE_REG_IFF_BIAS_BLE_SET_Pos   (12UL)

RFCU RF_BIAS_CTRL1_BLE_REG: IFF_BIAS_BLE_SET (Bit 12)

Definition at line 9655 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_BLE_REG_MIX_BIAS_BLE_SET_Msk

#define RFCU_RF_BIAS_CTRL1_BLE_REG_MIX_BIAS_BLE_SET_Msk   (0xfUL)

RFCU RF_BIAS_CTRL1_BLE_REG: MIX_BIAS_BLE_SET (Bitfield-Mask: 0x0f)

Definition at line 9650 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_BLE_REG_MIX_BIAS_BLE_SET_Pos

#define RFCU_RF_BIAS_CTRL1_BLE_REG_MIX_BIAS_BLE_SET_Pos   (0UL)

RFCU RF_BIAS_CTRL1_BLE_REG: MIX_BIAS_BLE_SET (Bit 0)

Definition at line 9649 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_BLE_REG_VCO_BIAS_BLE_SET_Msk

#define RFCU_RF_BIAS_CTRL1_BLE_REG_VCO_BIAS_BLE_SET_Msk   (0xf00UL)

RFCU RF_BIAS_CTRL1_BLE_REG: VCO_BIAS_BLE_SET (Bitfield-Mask: 0x0f)

Definition at line 9654 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_BLE_REG_VCO_BIAS_BLE_SET_Pos

#define RFCU_RF_BIAS_CTRL1_BLE_REG_VCO_BIAS_BLE_SET_Pos   (8UL)

RFCU RF_BIAS_CTRL1_BLE_REG: VCO_BIAS_BLE_SET (Bit 8)

Definition at line 9653 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_FTDF_REG_CP_BIAS_FTDF_SET_Msk

#define RFCU_RF_BIAS_CTRL1_FTDF_REG_CP_BIAS_FTDF_SET_Msk   (0xf0UL)

RFCU RF_BIAS_CTRL1_FTDF_REG: CP_BIAS_FTDF_SET (Bitfield-Mask: 0x0f)

Definition at line 9662 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_FTDF_REG_CP_BIAS_FTDF_SET_Pos

#define RFCU_RF_BIAS_CTRL1_FTDF_REG_CP_BIAS_FTDF_SET_Pos   (4UL)

RFCU RF_BIAS_CTRL1_FTDF_REG: CP_BIAS_FTDF_SET (Bit 4)

Definition at line 9661 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_FTDF_REG_IFF_BIAS_FTDF_SET_Msk

#define RFCU_RF_BIAS_CTRL1_FTDF_REG_IFF_BIAS_FTDF_SET_Msk   (0xf000UL)

RFCU RF_BIAS_CTRL1_FTDF_REG: IFF_BIAS_FTDF_SET (Bitfield-Mask: 0x0f)

Definition at line 9666 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_FTDF_REG_IFF_BIAS_FTDF_SET_Pos

#define RFCU_RF_BIAS_CTRL1_FTDF_REG_IFF_BIAS_FTDF_SET_Pos   (12UL)

RFCU RF_BIAS_CTRL1_FTDF_REG: IFF_BIAS_FTDF_SET (Bit 12)

Definition at line 9665 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_FTDF_REG_MIX_BIAS_FTDF_SET_Msk

#define RFCU_RF_BIAS_CTRL1_FTDF_REG_MIX_BIAS_FTDF_SET_Msk   (0xfUL)

RFCU RF_BIAS_CTRL1_FTDF_REG: MIX_BIAS_FTDF_SET (Bitfield-Mask: 0x0f)

Definition at line 9660 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_FTDF_REG_MIX_BIAS_FTDF_SET_Pos

#define RFCU_RF_BIAS_CTRL1_FTDF_REG_MIX_BIAS_FTDF_SET_Pos   (0UL)

RFCU RF_BIAS_CTRL1_FTDF_REG: MIX_BIAS_FTDF_SET (Bit 0)

Definition at line 9659 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_FTDF_REG_VCO_BIAS_FTDF_SET_Msk

#define RFCU_RF_BIAS_CTRL1_FTDF_REG_VCO_BIAS_FTDF_SET_Msk   (0xf00UL)

RFCU RF_BIAS_CTRL1_FTDF_REG: VCO_BIAS_FTDF_SET (Bitfield-Mask: 0x0f)

Definition at line 9664 of file DA14680BA.h.

◆ RFCU_RF_BIAS_CTRL1_FTDF_REG_VCO_BIAS_FTDF_SET_Pos

#define RFCU_RF_BIAS_CTRL1_FTDF_REG_VCO_BIAS_FTDF_SET_Pos   (8UL)

RFCU RF_BIAS_CTRL1_FTDF_REG: VCO_BIAS_FTDF_SET (Bit 8)

Definition at line 9663 of file DA14680BA.h.

◆ RFCU_RF_CAL_CTRL_REG_DC_OFFSET_CAL_DIS_Msk

#define RFCU_RF_CAL_CTRL_REG_DC_OFFSET_CAL_DIS_Msk   (0x10UL)

RFCU RF_CAL_CTRL_REG: DC_OFFSET_CAL_DIS (Bitfield-Mask: 0x01)

Definition at line 9600 of file DA14680BA.h.

◆ RFCU_RF_CAL_CTRL_REG_DC_OFFSET_CAL_DIS_Pos

#define RFCU_RF_CAL_CTRL_REG_DC_OFFSET_CAL_DIS_Pos   (4UL)

RFCU RF_CAL_CTRL_REG: DC_OFFSET_CAL_DIS (Bit 4)

Definition at line 9599 of file DA14680BA.h.

◆ RFCU_RF_CAL_CTRL_REG_EO_CAL_Msk

#define RFCU_RF_CAL_CTRL_REG_EO_CAL_Msk   (0x2UL)

RFCU RF_CAL_CTRL_REG: EO_CAL (Bitfield-Mask: 0x01)

Definition at line 9594 of file DA14680BA.h.

◆ RFCU_RF_CAL_CTRL_REG_EO_CAL_Pos

#define RFCU_RF_CAL_CTRL_REG_EO_CAL_Pos   (1UL)

RFCU RF_CAL_CTRL_REG: EO_CAL (Bit 1)

Definition at line 9593 of file DA14680BA.h.

◆ RFCU_RF_CAL_CTRL_REG_IFF_CAL_DIS_Msk

#define RFCU_RF_CAL_CTRL_REG_IFF_CAL_DIS_Msk   (0x8UL)

RFCU RF_CAL_CTRL_REG: IFF_CAL_DIS (Bitfield-Mask: 0x01)

Definition at line 9598 of file DA14680BA.h.

◆ RFCU_RF_CAL_CTRL_REG_IFF_CAL_DIS_Pos

#define RFCU_RF_CAL_CTRL_REG_IFF_CAL_DIS_Pos   (3UL)

RFCU RF_CAL_CTRL_REG: IFF_CAL_DIS (Bit 3)

Definition at line 9597 of file DA14680BA.h.

◆ RFCU_RF_CAL_CTRL_REG_MGAIN_CAL_DIS_Msk

#define RFCU_RF_CAL_CTRL_REG_MGAIN_CAL_DIS_Msk   (0x4UL)

RFCU RF_CAL_CTRL_REG: MGAIN_CAL_DIS (Bitfield-Mask: 0x01)

Definition at line 9596 of file DA14680BA.h.

◆ RFCU_RF_CAL_CTRL_REG_MGAIN_CAL_DIS_Pos

#define RFCU_RF_CAL_CTRL_REG_MGAIN_CAL_DIS_Pos   (2UL)

RFCU RF_CAL_CTRL_REG: MGAIN_CAL_DIS (Bit 2)

Definition at line 9595 of file DA14680BA.h.

◆ RFCU_RF_CAL_CTRL_REG_SO_CAL_Msk

#define RFCU_RF_CAL_CTRL_REG_SO_CAL_Msk   (0x1UL)

RFCU RF_CAL_CTRL_REG: SO_CAL (Bitfield-Mask: 0x01)

Definition at line 9592 of file DA14680BA.h.

◆ RFCU_RF_CAL_CTRL_REG_SO_CAL_Pos

#define RFCU_RF_CAL_CTRL_REG_SO_CAL_Pos   (0UL)

RFCU RF_CAL_CTRL_REG: SO_CAL (Bit 0)

Definition at line 9591 of file DA14680BA.h.

◆ RFCU_RF_CAL_CTRL_REG_VCO_CAL_DIS_Msk

#define RFCU_RF_CAL_CTRL_REG_VCO_CAL_DIS_Msk   (0x20UL)

RFCU RF_CAL_CTRL_REG: VCO_CAL_DIS (Bitfield-Mask: 0x01)

Definition at line 9602 of file DA14680BA.h.

◆ RFCU_RF_CAL_CTRL_REG_VCO_CAL_DIS_Pos

#define RFCU_RF_CAL_CTRL_REG_VCO_CAL_DIS_Pos   (5UL)

RFCU RF_CAL_CTRL_REG: VCO_CAL_DIS (Bit 5)

Definition at line 9601 of file DA14680BA.h.

◆ RFCU_RF_CALSTATE_REG_CALSTATE_Msk

#define RFCU_RF_CALSTATE_REG_CALSTATE_Msk   (0xfUL)

RFCU RF_CALSTATE_REG: CALSTATE (Bitfield-Mask: 0x0f)

Definition at line 9570 of file DA14680BA.h.

◆ RFCU_RF_CALSTATE_REG_CALSTATE_Pos

#define RFCU_RF_CALSTATE_REG_CALSTATE_Pos   (0UL)

RFCU RF_CALSTATE_REG: CALSTATE (Bit 0)

Definition at line 9569 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_RX_Msk

#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_RX_Msk   (0xf00UL)

RFCU RF_CP_CTRL_BLE_REG: CP_CUR_BLE_RX (Bitfield-Mask: 0x0f)

Definition at line 9750 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_RX_Pos

#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_RX_Pos   (8UL)

RFCU RF_CP_CTRL_BLE_REG: CP_CUR_BLE_RX (Bit 8)

Definition at line 9749 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_TX_Msk

#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_TX_Msk   (0xf000UL)

RFCU RF_CP_CTRL_BLE_REG: CP_CUR_BLE_TX (Bitfield-Mask: 0x0f)

Definition at line 9752 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_TX_Pos

#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_BLE_TX_Pos   (12UL)

RFCU RF_CP_CTRL_BLE_REG: CP_CUR_BLE_TX (Bit 12)

Definition at line 9751 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_RX_Msk

#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_RX_Msk   (0xfUL)

RFCU RF_CP_CTRL_BLE_REG: CP_CUR_SET_BLE_RX (Bitfield-Mask: 0x0f)

Definition at line 9746 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_RX_Pos

#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_RX_Pos   (0UL)

RFCU RF_CP_CTRL_BLE_REG: CP_CUR_SET_BLE_RX (Bit 0)

Definition at line 9745 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_TX_Msk

#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_TX_Msk   (0xf0UL)

RFCU RF_CP_CTRL_BLE_REG: CP_CUR_SET_BLE_TX (Bitfield-Mask: 0x0f)

Definition at line 9748 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_TX_Pos

#define RFCU_RF_CP_CTRL_BLE_REG_CP_CUR_SET_BLE_TX_Pos   (4UL)

RFCU RF_CP_CTRL_BLE_REG: CP_CUR_SET_BLE_TX (Bit 4)

Definition at line 9747 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_RX_Msk

#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_RX_Msk   (0xf00UL)

RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_FTDF_RX (Bitfield-Mask: 0x0f)

Definition at line 9760 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_RX_Pos

#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_RX_Pos   (8UL)

RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_FTDF_RX (Bit 8)

Definition at line 9759 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_TX_Msk

#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_TX_Msk   (0xf000UL)

RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_FTDF_TX (Bitfield-Mask: 0x0f)

Definition at line 9762 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_TX_Pos

#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_FTDF_TX_Pos   (12UL)

RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_FTDF_TX (Bit 12)

Definition at line 9761 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_RX_Msk

#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_RX_Msk   (0xfUL)

RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_SET_FTDF_RX (Bitfield-Mask: 0x0f)

Definition at line 9756 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_RX_Pos

#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_RX_Pos   (0UL)

RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_SET_FTDF_RX (Bit 0)

Definition at line 9755 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_TX_Msk

#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_TX_Msk   (0xf0UL)

RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_SET_FTDF_TX (Bitfield-Mask: 0x0f)

Definition at line 9758 of file DA14680BA.h.

◆ RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_TX_Pos

#define RFCU_RF_CP_CTRL_FTDF_REG_CP_CUR_SET_FTDF_TX_Pos   (4UL)

RFCU RF_CP_CTRL_FTDF_REG: CP_CUR_SET_FTDF_TX (Bit 4)

Definition at line 9757 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_0_Msk

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_0_Msk   (0x38UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_BSEL_0 (Bitfield-Mask: 0x07)

Definition at line 9524 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_0_Pos

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_0_Pos   (3UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_BSEL_0 (Bit 3)

Definition at line 9523 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_1_Msk

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_1_Msk   (0x3800UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_BSEL_1 (Bitfield-Mask: 0x07)

Definition at line 9532 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_1_Pos

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_BSEL_1_Pos   (11UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_BSEL_1 (Bit 11)

Definition at line 9531 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_0_Msk

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_0_Msk   (0x40UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_EDGE_0 (Bitfield-Mask: 0x01)

Definition at line 9526 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_0_Pos

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_0_Pos   (6UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_EDGE_0 (Bit 6)

Definition at line 9525 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_1_Msk

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_1_Msk   (0x4000UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_EDGE_1 (Bitfield-Mask: 0x01)

Definition at line 9534 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_1_Pos

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_EDGE_1_Pos   (14UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_EDGE_1 (Bit 14)

Definition at line 9533 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_0_Msk

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_0_Msk   (0x1UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_MASK_0 (Bitfield-Mask: 0x01)

Definition at line 9520 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_0_Pos

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_0_Pos   (0UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_MASK_0 (Bit 0)

Definition at line 9519 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_1_Msk

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_1_Msk   (0x100UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_MASK_1 (Bitfield-Mask: 0x01)

Definition at line 9528 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_1_Pos

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_MASK_1_Pos   (8UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_MASK_1 (Bit 8)

Definition at line 9527 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_0_Msk

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_0_Msk   (0x6UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_WSEL_0 (Bitfield-Mask: 0x03)

Definition at line 9522 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_0_Pos

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_0_Pos   (1UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_WSEL_0 (Bit 1)

Definition at line 9521 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_1_Msk

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_1_Msk   (0x600UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_WSEL_1 (Bitfield-Mask: 0x03)

Definition at line 9530 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_1_Pos

#define RFCU_RF_DIAGIRQ01_REG_DIAGIRQ_WSEL_1_Pos   (9UL)

RFCU RF_DIAGIRQ01_REG: DIAGIRQ_WSEL_1 (Bit 9)

Definition at line 9529 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_2_Msk

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_2_Msk   (0x38UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_BSEL_2 (Bitfield-Mask: 0x07)

Definition at line 9542 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_2_Pos

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_2_Pos   (3UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_BSEL_2 (Bit 3)

Definition at line 9541 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_3_Msk

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_3_Msk   (0x3800UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_BSEL_3 (Bitfield-Mask: 0x07)

Definition at line 9550 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_3_Pos

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_BSEL_3_Pos   (11UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_BSEL_3 (Bit 11)

Definition at line 9549 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_2_Msk

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_2_Msk   (0x40UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_EDGE_2 (Bitfield-Mask: 0x01)

Definition at line 9544 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_2_Pos

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_2_Pos   (6UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_EDGE_2 (Bit 6)

Definition at line 9543 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_3_Msk

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_3_Msk   (0x4000UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_EDGE_3 (Bitfield-Mask: 0x01)

Definition at line 9552 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_3_Pos

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_EDGE_3_Pos   (14UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_EDGE_3 (Bit 14)

Definition at line 9551 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_2_Msk

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_2_Msk   (0x1UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_MASK_2 (Bitfield-Mask: 0x01)

Definition at line 9538 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_2_Pos

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_2_Pos   (0UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_MASK_2 (Bit 0)

Definition at line 9537 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_3_Msk

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_3_Msk   (0x100UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_MASK_3 (Bitfield-Mask: 0x01)

Definition at line 9546 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_3_Pos

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_MASK_3_Pos   (8UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_MASK_3 (Bit 8)

Definition at line 9545 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_2_Msk

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_2_Msk   (0x6UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_WSEL_2 (Bitfield-Mask: 0x03)

Definition at line 9540 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_2_Pos

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_2_Pos   (1UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_WSEL_2 (Bit 1)

Definition at line 9539 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_3_Msk

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_3_Msk   (0x600UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_WSEL_3 (Bitfield-Mask: 0x03)

Definition at line 9548 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_3_Pos

#define RFCU_RF_DIAGIRQ23_REG_DIAGIRQ_WSEL_3_Pos   (9UL)

RFCU RF_DIAGIRQ23_REG: DIAGIRQ_WSEL_3 (Bit 9)

Definition at line 9547 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_0_Msk

#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_0_Msk   (0x1UL)

RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_0 (Bitfield-Mask: 0x01)

Definition at line 9556 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_0_Pos

#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_0_Pos   (0UL)

RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_0 (Bit 0)

Definition at line 9555 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_1_Msk

#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_1_Msk   (0x2UL)

RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_1 (Bitfield-Mask: 0x01)

Definition at line 9558 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_1_Pos

#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_1_Pos   (1UL)

RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_1 (Bit 1)

Definition at line 9557 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_2_Msk

#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_2_Msk   (0x4UL)

RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_2 (Bitfield-Mask: 0x01)

Definition at line 9560 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_2_Pos

#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_2_Pos   (2UL)

RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_2 (Bit 2)

Definition at line 9559 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_3_Msk

#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_3_Msk   (0x8UL)

RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_3 (Bitfield-Mask: 0x01)

Definition at line 9562 of file DA14680BA.h.

◆ RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_3_Pos

#define RFCU_RF_DIAGIRQ_STAT_REG_DIAGIRQ_STAT_3_Pos   (3UL)

RFCU RF_DIAGIRQ_STAT_REG: DIAGIRQ_STAT_3 (Bit 3)

Definition at line 9561 of file DA14680BA.h.

◆ RFCU_RF_DIV_IQ_RX_REG_DIV2_IQ_TRIM_RX_SPARE_Msk

#define RFCU_RF_DIV_IQ_RX_REG_DIV2_IQ_TRIM_RX_SPARE_Msk   (0x100UL)

RFCU RF_DIV_IQ_RX_REG: DIV2_IQ_TRIM_RX_SPARE (Bitfield-Mask: 0x01)

Definition at line 9956 of file DA14680BA.h.

◆ RFCU_RF_DIV_IQ_RX_REG_DIV2_IQ_TRIM_RX_SPARE_Pos

#define RFCU_RF_DIV_IQ_RX_REG_DIV2_IQ_TRIM_RX_SPARE_Pos   (8UL)

RFCU RF_DIV_IQ_RX_REG: DIV2_IQ_TRIM_RX_SPARE (Bit 8)

Definition at line 9955 of file DA14680BA.h.

◆ RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFN_TRIM_RX_Msk

#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFN_TRIM_RX_Msk   (0xfUL)

RFCU RF_DIV_IQ_RX_REG: DIV2_OFFN_TRIM_RX (Bitfield-Mask: 0x0f)

Definition at line 9952 of file DA14680BA.h.

◆ RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFN_TRIM_RX_Pos

#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFN_TRIM_RX_Pos   (0UL)

RFCU RF_DIV_IQ_RX_REG: DIV2_OFFN_TRIM_RX (Bit 0)

Definition at line 9951 of file DA14680BA.h.

◆ RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFP_TRIM_RX_Msk

#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFP_TRIM_RX_Msk   (0xf0UL)

RFCU RF_DIV_IQ_RX_REG: DIV2_OFFP_TRIM_RX (Bitfield-Mask: 0x0f)

Definition at line 9954 of file DA14680BA.h.

◆ RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFP_TRIM_RX_Pos

#define RFCU_RF_DIV_IQ_RX_REG_DIV2_OFFP_TRIM_RX_Pos   (4UL)

RFCU RF_DIV_IQ_RX_REG: DIV2_OFFP_TRIM_RX (Bit 4)

Definition at line 9953 of file DA14680BA.h.

◆ RFCU_RF_DIV_IQ_TX_REG_DIV2_IQ_TRIM_TX_SPARE_Msk

#define RFCU_RF_DIV_IQ_TX_REG_DIV2_IQ_TRIM_TX_SPARE_Msk   (0x100UL)

RFCU RF_DIV_IQ_TX_REG: DIV2_IQ_TRIM_TX_SPARE (Bitfield-Mask: 0x01)

Definition at line 9964 of file DA14680BA.h.

◆ RFCU_RF_DIV_IQ_TX_REG_DIV2_IQ_TRIM_TX_SPARE_Pos

#define RFCU_RF_DIV_IQ_TX_REG_DIV2_IQ_TRIM_TX_SPARE_Pos   (8UL)

RFCU RF_DIV_IQ_TX_REG: DIV2_IQ_TRIM_TX_SPARE (Bit 8)

Definition at line 9963 of file DA14680BA.h.

◆ RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFN_TRIM_TX_Msk

#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFN_TRIM_TX_Msk   (0xfUL)

RFCU RF_DIV_IQ_TX_REG: DIV2_OFFN_TRIM_TX (Bitfield-Mask: 0x0f)

Definition at line 9960 of file DA14680BA.h.

◆ RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFN_TRIM_TX_Pos

#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFN_TRIM_TX_Pos   (0UL)

RFCU RF_DIV_IQ_TX_REG: DIV2_OFFN_TRIM_TX (Bit 0)

Definition at line 9959 of file DA14680BA.h.

◆ RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFP_TRIM_TX_Msk

#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFP_TRIM_TX_Msk   (0xf0UL)

RFCU RF_DIV_IQ_TX_REG: DIV2_OFFP_TRIM_TX (Bitfield-Mask: 0x0f)

Definition at line 9962 of file DA14680BA.h.

◆ RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFP_TRIM_TX_Pos

#define RFCU_RF_DIV_IQ_TX_REG_DIV2_OFFP_TRIM_TX_Pos   (4UL)

RFCU RF_DIV_IQ_TX_REG: DIV2_OFFP_TRIM_TX (Bit 4)

Definition at line 9961 of file DA14680BA.h.

◆ RFCU_RF_IFF_CAL_CAP_STAT_REG_IF_CAL_CAP_RD_Msk

#define RFCU_RF_IFF_CAL_CAP_STAT_REG_IF_CAL_CAP_RD_Msk   (0x1fUL)

RFCU RF_IFF_CAL_CAP_STAT_REG: IF_CAL_CAP_RD (Bitfield-Mask: 0x1f)

Definition at line 10008 of file DA14680BA.h.

◆ RFCU_RF_IFF_CAL_CAP_STAT_REG_IF_CAL_CAP_RD_Pos

#define RFCU_RF_IFF_CAL_CAP_STAT_REG_IF_CAL_CAP_RD_Pos   (0UL)

RFCU RF_IFF_CAL_CAP_STAT_REG: IF_CAL_CAP_RD (Bit 0)

Definition at line 10007 of file DA14680BA.h.

◆ RFCU_RF_IFF_CC_BLE_SET1_REG_IF_CAL_CAP_WR_Msk

#define RFCU_RF_IFF_CC_BLE_SET1_REG_IF_CAL_CAP_WR_Msk   (0x1fUL)

RFCU RF_IFF_CC_BLE_SET1_REG: IF_CAL_CAP_WR (Bitfield-Mask: 0x1f)

Definition at line 9992 of file DA14680BA.h.

◆ RFCU_RF_IFF_CC_BLE_SET1_REG_IF_CAL_CAP_WR_Pos

#define RFCU_RF_IFF_CC_BLE_SET1_REG_IF_CAL_CAP_WR_Pos   (0UL)

RFCU RF_IFF_CC_BLE_SET1_REG: IF_CAL_CAP_WR (Bit 0)

Definition at line 9991 of file DA14680BA.h.

◆ RFCU_RF_IFF_CC_BLE_SET2_REG_IF_CAL_CAP_WR_Msk

#define RFCU_RF_IFF_CC_BLE_SET2_REG_IF_CAL_CAP_WR_Msk   (0x1fUL)

RFCU RF_IFF_CC_BLE_SET2_REG: IF_CAL_CAP_WR (Bitfield-Mask: 0x1f)

Definition at line 9996 of file DA14680BA.h.

◆ RFCU_RF_IFF_CC_BLE_SET2_REG_IF_CAL_CAP_WR_Pos

#define RFCU_RF_IFF_CC_BLE_SET2_REG_IF_CAL_CAP_WR_Pos   (0UL)

RFCU RF_IFF_CC_BLE_SET2_REG: IF_CAL_CAP_WR (Bit 0)

Definition at line 9995 of file DA14680BA.h.

◆ RFCU_RF_IFF_CC_FTDF_SET1_REG_IF_CAL_CAP_WR_Msk

#define RFCU_RF_IFF_CC_FTDF_SET1_REG_IF_CAL_CAP_WR_Msk   (0x1fUL)

RFCU RF_IFF_CC_FTDF_SET1_REG: IF_CAL_CAP_WR (Bitfield-Mask: 0x1f)

Definition at line 10000 of file DA14680BA.h.

◆ RFCU_RF_IFF_CC_FTDF_SET1_REG_IF_CAL_CAP_WR_Pos

#define RFCU_RF_IFF_CC_FTDF_SET1_REG_IF_CAL_CAP_WR_Pos   (0UL)

RFCU RF_IFF_CC_FTDF_SET1_REG: IF_CAL_CAP_WR (Bit 0)

Definition at line 9999 of file DA14680BA.h.

◆ RFCU_RF_IFF_CC_FTDF_SET2_REG_IF_CAL_CAP_WR_Msk

#define RFCU_RF_IFF_CC_FTDF_SET2_REG_IF_CAL_CAP_WR_Msk   (0x1fUL)

RFCU RF_IFF_CC_FTDF_SET2_REG: IF_CAL_CAP_WR (Bitfield-Mask: 0x1f)

Definition at line 10004 of file DA14680BA.h.

◆ RFCU_RF_IFF_CC_FTDF_SET2_REG_IF_CAL_CAP_WR_Pos

#define RFCU_RF_IFF_CC_FTDF_SET2_REG_IF_CAL_CAP_WR_Pos   (0UL)

RFCU RF_IFF_CC_FTDF_SET2_REG: IF_CAL_CAP_WR (Bit 0)

Definition at line 10003 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_IF_CAL_CAP_Msk

#define RFCU_RF_IFF_CTRL1_REG_IF_CAL_CAP_Msk   (0x1fUL)

RFCU RF_IFF_CTRL1_REG: IF_CAL_CAP (Bitfield-Mask: 0x1f)

Definition at line 9670 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_IF_CAL_CAP_Pos

#define RFCU_RF_IFF_CTRL1_REG_IF_CAL_CAP_Pos   (0UL)

RFCU RF_IFF_CTRL1_REG: IF_CAL_CAP (Bit 0)

Definition at line 9669 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_IF_MUTE_Msk

#define RFCU_RF_IFF_CTRL1_REG_IF_MUTE_Msk   (0x20UL)

RFCU RF_IFF_CTRL1_REG: IF_MUTE (Bitfield-Mask: 0x01)

Definition at line 9672 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_IF_MUTE_Pos

#define RFCU_RF_IFF_CTRL1_REG_IF_MUTE_Pos   (5UL)

RFCU RF_IFF_CTRL1_REG: IF_MUTE (Bit 5)

Definition at line 9671 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_IF_SEL_SET2_GT_Msk

#define RFCU_RF_IFF_CTRL1_REG_IF_SEL_SET2_GT_Msk   (0xf00UL)

RFCU RF_IFF_CTRL1_REG: IF_SEL_SET2_GT (Bitfield-Mask: 0x0f)

Definition at line 9678 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_IF_SEL_SET2_GT_Pos

#define RFCU_RF_IFF_CTRL1_REG_IF_SEL_SET2_GT_Pos   (8UL)

RFCU RF_IFF_CTRL1_REG: IF_SEL_SET2_GT (Bit 8)

Definition at line 9677 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_IF_SELECT_FSM_Msk

#define RFCU_RF_IFF_CTRL1_REG_IF_SELECT_FSM_Msk   (0x1000UL)

RFCU RF_IFF_CTRL1_REG: IF_SELECT_FSM (Bitfield-Mask: 0x01)

Definition at line 9680 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_IF_SELECT_FSM_Pos

#define RFCU_RF_IFF_CTRL1_REG_IF_SELECT_FSM_Pos   (12UL)

RFCU RF_IFF_CTRL1_REG: IF_SELECT_FSM (Bit 12)

Definition at line 9679 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_IFF_COMPLEX_DIS_Msk

#define RFCU_RF_IFF_CTRL1_REG_IFF_COMPLEX_DIS_Msk   (0x2000UL)

RFCU RF_IFF_CTRL1_REG: IFF_COMPLEX_DIS (Bitfield-Mask: 0x01)

Definition at line 9682 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_IFF_COMPLEX_DIS_Pos

#define RFCU_RF_IFF_CTRL1_REG_IFF_COMPLEX_DIS_Pos   (13UL)

RFCU RF_IFF_CTRL1_REG: IFF_COMPLEX_DIS (Bit 13)

Definition at line 9681 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_IFF_DCOC_DAC_DIS_Msk

#define RFCU_RF_IFF_CTRL1_REG_IFF_DCOC_DAC_DIS_Msk   (0x40UL)

RFCU RF_IFF_CTRL1_REG: IFF_DCOC_DAC_DIS (Bitfield-Mask: 0x01)

Definition at line 9674 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_IFF_DCOC_DAC_DIS_Pos

#define RFCU_RF_IFF_CTRL1_REG_IFF_DCOC_DAC_DIS_Pos   (6UL)

RFCU RF_IFF_CTRL1_REG: IFF_DCOC_DAC_DIS (Bit 6)

Definition at line 9673 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_RO_TO_PINS_Msk

#define RFCU_RF_IFF_CTRL1_REG_RO_TO_PINS_Msk   (0x80UL)

RFCU RF_IFF_CTRL1_REG: RO_TO_PINS (Bitfield-Mask: 0x01)

Definition at line 9676 of file DA14680BA.h.

◆ RFCU_RF_IFF_CTRL1_REG_RO_TO_PINS_Pos

#define RFCU_RF_IFF_CTRL1_REG_RO_TO_PINS_Pos   (7UL)

RFCU RF_IFF_CTRL1_REG: RO_TO_PINS (Bit 7)

Definition at line 9675 of file DA14680BA.h.

◆ RFCU_RF_IFF_RESULT_REG_IF_CAL_CAP_RD_Msk

#define RFCU_RF_IFF_RESULT_REG_IF_CAL_CAP_RD_Msk   (0x1fUL)

RFCU RF_IFF_RESULT_REG: IF_CAL_CAP_RD (Bitfield-Mask: 0x1f)

Definition at line 9988 of file DA14680BA.h.

◆ RFCU_RF_IFF_RESULT_REG_IF_CAL_CAP_RD_Pos

#define RFCU_RF_IFF_RESULT_REG_IF_CAL_CAP_RD_Pos   (0UL)

RFCU RF_IFF_RESULT_REG: IF_CAL_CAP_RD (Bit 0)

Definition at line 9987 of file DA14680BA.h.

◆ RFCU_RF_IO_CTRL1_REG_RFIO_TRIM1_CAP_Msk

#define RFCU_RF_IO_CTRL1_REG_RFIO_TRIM1_CAP_Msk   (0xffUL)

RFCU RF_IO_CTRL1_REG: RFIO_TRIM1_CAP (Bitfield-Mask: 0xff)

Definition at line 9840 of file DA14680BA.h.

◆ RFCU_RF_IO_CTRL1_REG_RFIO_TRIM1_CAP_Pos

#define RFCU_RF_IO_CTRL1_REG_RFIO_TRIM1_CAP_Pos   (0UL)

RFCU RF_IO_CTRL1_REG: RFIO_TRIM1_CAP (Bit 0)

Definition at line 9839 of file DA14680BA.h.

◆ RFCU_RF_IRQ_CTRL_REG_EO_CAL_CLEAR_Msk

#define RFCU_RF_IRQ_CTRL_REG_EO_CAL_CLEAR_Msk   (0x1UL)

RFCU RF_IRQ_CTRL_REG: EO_CAL_CLEAR (Bitfield-Mask: 0x01)

Definition at line 9606 of file DA14680BA.h.

◆ RFCU_RF_IRQ_CTRL_REG_EO_CAL_CLEAR_Pos

#define RFCU_RF_IRQ_CTRL_REG_EO_CAL_CLEAR_Pos   (0UL)

RFCU RF_IRQ_CTRL_REG: EO_CAL_CLEAR (Bit 0)

Definition at line 9605 of file DA14680BA.h.

◆ RFCU_RF_LF_CAL_CAP_STAT_REG_LF_CAL_CAP_RD_Msk

#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_CAL_CAP_RD_Msk   (0x1fUL)

RFCU RF_LF_CAL_CAP_STAT_REG: LF_CAL_CAP_RD (Bitfield-Mask: 0x1f)

Definition at line 10016 of file DA14680BA.h.

◆ RFCU_RF_LF_CAL_CAP_STAT_REG_LF_CAL_CAP_RD_Pos

#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_CAL_CAP_RD_Pos   (0UL)

RFCU RF_LF_CAL_CAP_STAT_REG: LF_CAL_CAP_RD (Bit 0)

Definition at line 10015 of file DA14680BA.h.

◆ RFCU_RF_LF_CAL_CAP_STAT_REG_LF_SHORT_R4_RD_Msk

#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_SHORT_R4_RD_Msk   (0x20UL)

RFCU RF_LF_CAL_CAP_STAT_REG: LF_SHORT_R4_RD (Bitfield-Mask: 0x01)

Definition at line 10018 of file DA14680BA.h.

◆ RFCU_RF_LF_CAL_CAP_STAT_REG_LF_SHORT_R4_RD_Pos

#define RFCU_RF_LF_CAL_CAP_STAT_REG_LF_SHORT_R4_RD_Pos   (5UL)

RFCU RF_LF_CAL_CAP_STAT_REG: LF_SHORT_R4_RD (Bit 5)

Definition at line 10017 of file DA14680BA.h.

◆ RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_SEL_Msk

#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_SEL_Msk   (0x20UL)

RFCU RF_LF_CTRL_REG: LF_CAL_CAP_SEL (Bitfield-Mask: 0x01)

Definition at line 9816 of file DA14680BA.h.

◆ RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_SEL_Pos

#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_SEL_Pos   (5UL)

RFCU RF_LF_CTRL_REG: LF_CAL_CAP_SEL (Bit 5)

Definition at line 9815 of file DA14680BA.h.

◆ RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_BLE_Msk

#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_BLE_Msk   (0x1fUL)

RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_BLE (Bitfield-Mask: 0x1f)

Definition at line 9814 of file DA14680BA.h.

◆ RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_BLE_Pos

#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_BLE_Pos   (0UL)

RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_BLE (Bit 0)

Definition at line 9813 of file DA14680BA.h.

◆ RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_FTDF_Msk

#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_FTDF_Msk   (0x1f00UL)

RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_FTDF (Bitfield-Mask: 0x1f)

Definition at line 9822 of file DA14680BA.h.

◆ RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_FTDF_Pos

#define RFCU_RF_LF_CTRL_REG_LF_CAL_CAP_WR_FTDF_Pos   (8UL)

RFCU RF_LF_CTRL_REG: LF_CAL_CAP_WR_FTDF (Bit 8)

Definition at line 9821 of file DA14680BA.h.

◆ RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_BLE_Msk

#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_BLE_Msk   (0x40UL)

RFCU RF_LF_CTRL_REG: LF_SHORT_R4_BLE (Bitfield-Mask: 0x01)

Definition at line 9818 of file DA14680BA.h.

◆ RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_BLE_Pos

#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_BLE_Pos   (6UL)

RFCU RF_LF_CTRL_REG: LF_SHORT_R4_BLE (Bit 6)

Definition at line 9817 of file DA14680BA.h.

◆ RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_FTDF_Msk

#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_FTDF_Msk   (0x80UL)

RFCU RF_LF_CTRL_REG: LF_SHORT_R4_FTDF (Bitfield-Mask: 0x01)

Definition at line 9820 of file DA14680BA.h.

◆ RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_FTDF_Pos

#define RFCU_RF_LF_CTRL_REG_LF_SHORT_R4_FTDF_Pos   (7UL)

RFCU RF_LF_CTRL_REG: LF_SHORT_R4_FTDF (Bit 7)

Definition at line 9819 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_RX_Msk

#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_RX_Msk   (0xf00UL)

RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_BLE_RX (Bitfield-Mask: 0x0f)

Definition at line 9770 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_RX_Pos

#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_RX_Pos   (8UL)

RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_BLE_RX (Bit 8)

Definition at line 9769 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_TX_Msk

#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_TX_Msk   (0xf000UL)

RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_BLE_TX (Bitfield-Mask: 0x0f)

Definition at line 9772 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_TX_Pos

#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_BLE_TX_Pos   (12UL)

RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_BLE_TX (Bit 12)

Definition at line 9771 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_RX_Msk

#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_RX_Msk   (0xfUL)

RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_SET_BLE_RX (Bitfield-Mask: 0x0f)

Definition at line 9766 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_RX_Pos

#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_RX_Pos   (0UL)

RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_SET_BLE_RX (Bit 0)

Definition at line 9765 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_TX_Msk

#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_TX_Msk   (0xf0UL)

RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_SET_BLE_TX (Bitfield-Mask: 0x0f)

Definition at line 9768 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_TX_Pos

#define RFCU_RF_LF_RES_CTRL_BLE_REG_LF_RES_SET_BLE_TX_Pos   (4UL)

RFCU RF_LF_RES_CTRL_BLE_REG: LF_RES_SET_BLE_TX (Bit 4)

Definition at line 9767 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_RX_Msk

#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_RX_Msk   (0xf00UL)

RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_FTDF_RX (Bitfield-Mask: 0x0f)

Definition at line 9780 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_RX_Pos

#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_RX_Pos   (8UL)

RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_FTDF_RX (Bit 8)

Definition at line 9779 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_TX_Msk

#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_TX_Msk   (0xf000UL)

RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_FTDF_TX (Bitfield-Mask: 0x0f)

Definition at line 9782 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_TX_Pos

#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_FTDF_TX_Pos   (12UL)

RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_FTDF_TX (Bit 12)

Definition at line 9781 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_RX_Msk

#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_RX_Msk   (0xfUL)

RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_SET_FTDF_RX (Bitfield-Mask: 0x0f)

Definition at line 9776 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_RX_Pos

#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_RX_Pos   (0UL)

RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_SET_FTDF_RX (Bit 0)

Definition at line 9775 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_TX_Msk

#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_TX_Msk   (0xf0UL)

RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_SET_FTDF_TX (Bitfield-Mask: 0x0f)

Definition at line 9778 of file DA14680BA.h.

◆ RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_TX_Pos

#define RFCU_RF_LF_RES_CTRL_FTDF_REG_LF_RES_SET_FTDF_TX_Pos   (4UL)

RFCU RF_LF_RES_CTRL_FTDF_REG: LF_RES_SET_FTDF_TX (Bit 4)

Definition at line 9777 of file DA14680BA.h.

◆ RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_HF_Msk

#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_HF_Msk   (0xfc0UL)

RFCU RF_LNA_CTRL1_REG: LNA_TRIM_CD_HF (Bitfield-Mask: 0x3f)

Definition at line 9846 of file DA14680BA.h.

◆ RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_HF_Pos

#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_HF_Pos   (6UL)

RFCU RF_LNA_CTRL1_REG: LNA_TRIM_CD_HF (Bit 6)

Definition at line 9845 of file DA14680BA.h.

◆ RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_LF_Msk

#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_LF_Msk   (0x3fUL)

RFCU RF_LNA_CTRL1_REG: LNA_TRIM_CD_LF (Bitfield-Mask: 0x3f)

Definition at line 9844 of file DA14680BA.h.

◆ RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_LF_Pos

#define RFCU_RF_LNA_CTRL1_REG_LNA_TRIM_CD_LF_Pos   (0UL)

RFCU RF_LNA_CTRL1_REG: LNA_TRIM_CD_LF (Bit 0)

Definition at line 9843 of file DA14680BA.h.

◆ RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_HI_Msk

#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_HI_Msk   (0x3fUL)

RFCU RF_LNA_CTRL2_REG: LNA_TRIM_GM_HI (Bitfield-Mask: 0x3f)

Definition at line 9850 of file DA14680BA.h.

◆ RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_HI_Pos

#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_HI_Pos   (0UL)

RFCU RF_LNA_CTRL2_REG: LNA_TRIM_GM_HI (Bit 0)

Definition at line 9849 of file DA14680BA.h.

◆ RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_LO_Msk

#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_LO_Msk   (0xfc0UL)

RFCU RF_LNA_CTRL2_REG: LNA_TRIM_GM_LO (Bitfield-Mask: 0x3f)

Definition at line 9852 of file DA14680BA.h.

◆ RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_LO_Pos

#define RFCU_RF_LNA_CTRL2_REG_LNA_TRIM_GM_LO_Pos   (6UL)

RFCU RF_LNA_CTRL2_REG: LNA_TRIM_GM_LO (Bit 6)

Definition at line 9851 of file DA14680BA.h.

◆ RFCU_RF_LNA_CTRL3_REG_LNA_TRIM_CGS_Msk

#define RFCU_RF_LNA_CTRL3_REG_LNA_TRIM_CGS_Msk   (0x1fUL)

RFCU RF_LNA_CTRL3_REG: LNA_TRIM_CGS (Bitfield-Mask: 0x1f)

Definition at line 9856 of file DA14680BA.h.

◆ RFCU_RF_LNA_CTRL3_REG_LNA_TRIM_CGS_Pos

#define RFCU_RF_LNA_CTRL3_REG_LNA_TRIM_CGS_Pos   (0UL)

RFCU RF_LNA_CTRL3_REG: LNA_TRIM_CGS (Bit 0)

Definition at line 9855 of file DA14680BA.h.

◆ RFCU_RF_LO_IQ_TRIM_REG_RF_LO_IQ_TRIM_Msk

#define RFCU_RF_LO_IQ_TRIM_REG_RF_LO_IQ_TRIM_Msk   (0xffffUL)

RFCU RF_LO_IQ_TRIM_REG: RF_LO_IQ_TRIM (Bitfield-Mask: 0xffff)

Definition at line 9968 of file DA14680BA.h.

◆ RFCU_RF_LO_IQ_TRIM_REG_RF_LO_IQ_TRIM_Pos

#define RFCU_RF_LO_IQ_TRIM_REG_RF_LO_IQ_TRIM_Pos   (0UL)

RFCU RF_LO_IQ_TRIM_REG: RF_LO_IQ_TRIM (Bit 0)

Definition at line 9967 of file DA14680BA.h.

◆ RFCU_RF_MGC_CTRL_REG_GAUSS_DAC_CTRL_Msk

#define RFCU_RF_MGC_CTRL_REG_GAUSS_DAC_CTRL_Msk   (0xcUL)

RFCU RF_MGC_CTRL_REG: GAUSS_DAC_CTRL (Bitfield-Mask: 0x03)

Definition at line 9720 of file DA14680BA.h.

◆ RFCU_RF_MGC_CTRL_REG_GAUSS_DAC_CTRL_Pos

#define RFCU_RF_MGC_CTRL_REG_GAUSS_DAC_CTRL_Pos   (2UL)

RFCU RF_MGC_CTRL_REG: GAUSS_DAC_CTRL (Bit 2)

Definition at line 9719 of file DA14680BA.h.

◆ RFCU_RF_MGC_CTRL_REG_MGC_GAIN_SET_Msk

#define RFCU_RF_MGC_CTRL_REG_MGC_GAIN_SET_Msk   (0x1UL)

RFCU RF_MGC_CTRL_REG: MGC_GAIN_SET (Bitfield-Mask: 0x01)

Definition at line 9716 of file DA14680BA.h.

◆ RFCU_RF_MGC_CTRL_REG_MGC_GAIN_SET_Pos

#define RFCU_RF_MGC_CTRL_REG_MGC_GAIN_SET_Pos   (0UL)

RFCU RF_MGC_CTRL_REG: MGC_GAIN_SET (Bit 0)

Definition at line 9715 of file DA14680BA.h.

◆ RFCU_RF_MGC_CTRL_REG_MGC_POLE_SW_Msk

#define RFCU_RF_MGC_CTRL_REG_MGC_POLE_SW_Msk   (0x2UL)

RFCU RF_MGC_CTRL_REG: MGC_POLE_SW (Bitfield-Mask: 0x01)

Definition at line 9718 of file DA14680BA.h.

◆ RFCU_RF_MGC_CTRL_REG_MGC_POLE_SW_Pos

#define RFCU_RF_MGC_CTRL_REG_MGC_POLE_SW_Pos   (1UL)

RFCU RF_MGC_CTRL_REG: MGC_POLE_SW (Bit 1)

Definition at line 9717 of file DA14680BA.h.

◆ RFCU_RF_MIX_CAL_CAP_STAT_REG_MIX_CAL_CAP_RD_Msk

#define RFCU_RF_MIX_CAL_CAP_STAT_REG_MIX_CAL_CAP_RD_Msk   (0x1fUL)

RFCU RF_MIX_CAL_CAP_STAT_REG: MIX_CAL_CAP_RD (Bitfield-Mask: 0x1f)

Definition at line 10012 of file DA14680BA.h.

◆ RFCU_RF_MIX_CAL_CAP_STAT_REG_MIX_CAL_CAP_RD_Pos

#define RFCU_RF_MIX_CAL_CAP_STAT_REG_MIX_CAL_CAP_RD_Pos   (0UL)

RFCU RF_MIX_CAL_CAP_STAT_REG: MIX_CAL_CAP_RD (Bit 0)

Definition at line 10011 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_SPARE_BLE_Msk

#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_SPARE_BLE_Msk   (0xf000UL)

RFCU RF_MIXER_CTRL1_BLE_REG: MIX_SPARE_BLE (Bitfield-Mask: 0x0f)

Definition at line 9792 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_SPARE_BLE_Pos

#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_SPARE_BLE_Pos   (12UL)

RFCU RF_MIXER_CTRL1_BLE_REG: MIX_SPARE_BLE (Bit 12)

Definition at line 9791 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_GMBIAS_BLE_Msk

#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_GMBIAS_BLE_Msk   (0xfUL)

RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_GMBIAS_BLE (Bitfield-Mask: 0x0f)

Definition at line 9786 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_GMBIAS_BLE_Pos

#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_GMBIAS_BLE_Pos   (0UL)

RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_GMBIAS_BLE (Bit 0)

Definition at line 9785 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_IBIAS_BLE_Msk

#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_IBIAS_BLE_Msk   (0xf0UL)

RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_IBIAS_BLE (Bitfield-Mask: 0x0f)

Definition at line 9788 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_IBIAS_BLE_Pos

#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_IBIAS_BLE_Pos   (4UL)

RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_IBIAS_BLE (Bit 4)

Definition at line 9787 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_VCM_BLE_Msk

#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_VCM_BLE_Msk   (0xf00UL)

RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_VCM_BLE (Bitfield-Mask: 0x0f)

Definition at line 9790 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_VCM_BLE_Pos

#define RFCU_RF_MIXER_CTRL1_BLE_REG_MIX_TRIM_VCM_BLE_Pos   (8UL)

RFCU RF_MIXER_CTRL1_BLE_REG: MIX_TRIM_VCM_BLE (Bit 8)

Definition at line 9789 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_SPARE_Msk

#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_SPARE_Msk   (0xf000UL)

RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_SPARE (Bitfield-Mask: 0x0f)

Definition at line 9802 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_SPARE_Pos

#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_SPARE_Pos   (12UL)

RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_SPARE (Bit 12)

Definition at line 9801 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_GMBIAS_FTDF_Msk

#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_GMBIAS_FTDF_Msk   (0xfUL)

RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_GMBIAS_FTDF (Bitfield-Mask: 0x0f)

Definition at line 9796 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_GMBIAS_FTDF_Pos

#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_GMBIAS_FTDF_Pos   (0UL)

RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_GMBIAS_FTDF (Bit 0)

Definition at line 9795 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_IBIAS_FTDF_Msk

#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_IBIAS_FTDF_Msk   (0xf0UL)

RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_IBIAS_FTDF (Bitfield-Mask: 0x0f)

Definition at line 9798 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_IBIAS_FTDF_Pos

#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_IBIAS_FTDF_Pos   (4UL)

RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_IBIAS_FTDF (Bit 4)

Definition at line 9797 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_VCM_FTDF_Msk

#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_VCM_FTDF_Msk   (0xf00UL)

RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_VCM_FTDF (Bitfield-Mask: 0x0f)

Definition at line 9800 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_VCM_FTDF_Pos

#define RFCU_RF_MIXER_CTRL1_FTDF_REG_MIX_TRIM_VCM_FTDF_Pos   (8UL)

RFCU RF_MIXER_CTRL1_FTDF_REG: MIX_TRIM_VCM_FTDF (Bit 8)

Definition at line 9799 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_BLE_Msk

#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_BLE_Msk   (0x1fUL)

RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_BLE (Bitfield-Mask: 0x1f)

Definition at line 9806 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_BLE_Pos

#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_BLE_Pos   (0UL)

RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_BLE (Bit 0)

Definition at line 9805 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_FTDF_Msk

#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_FTDF_Msk   (0x7c0UL)

RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_FTDF (Bitfield-Mask: 0x1f)

Definition at line 9810 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_FTDF_Pos

#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_CAP_WR_FTDF_Pos   (6UL)

RFCU RF_MIXER_CTRL2_REG: MIX_CAL_CAP_WR_FTDF (Bit 6)

Definition at line 9809 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_SELECT_Msk

#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_SELECT_Msk   (0x20UL)

RFCU RF_MIXER_CTRL2_REG: MIX_CAL_SELECT (Bitfield-Mask: 0x01)

Definition at line 9808 of file DA14680BA.h.

◆ RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_SELECT_Pos

#define RFCU_RF_MIXER_CTRL2_REG_MIX_CAL_SELECT_Pos   (5UL)

RFCU RF_MIXER_CTRL2_REG: MIX_CAL_SELECT (Bit 5)

Definition at line 9807 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_CN_FTDF_TIMES2_Msk

#define RFCU_RF_OVERRULE_REG_CN_FTDF_TIMES2_Msk   (0x4000UL)

RFCU RF_OVERRULE_REG: CN_FTDF_TIMES2 (Bitfield-Mask: 0x01)

Definition at line 9516 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_CN_FTDF_TIMES2_Pos

#define RFCU_RF_OVERRULE_REG_CN_FTDF_TIMES2_Pos   (14UL)

RFCU RF_OVERRULE_REG: CN_FTDF_TIMES2 (Bit 14)

Definition at line 9515 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_GAUSS_DAC_SEL_Msk

#define RFCU_RF_OVERRULE_REG_GAUSS_DAC_SEL_Msk   (0x3000UL)

RFCU RF_OVERRULE_REG: GAUSS_DAC_SEL (Bitfield-Mask: 0x03)

Definition at line 9514 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_GAUSS_DAC_SEL_Pos

#define RFCU_RF_OVERRULE_REG_GAUSS_DAC_SEL_Pos   (12UL)

RFCU RF_OVERRULE_REG: GAUSS_DAC_SEL (Bit 12)

Definition at line 9513 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_IFF_FTDF_OVR_Msk

#define RFCU_RF_OVERRULE_REG_IFF_FTDF_OVR_Msk   (0xc0UL)

RFCU RF_OVERRULE_REG: IFF_FTDF_OVR (Bitfield-Mask: 0x03)

Definition at line 9508 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_IFF_FTDF_OVR_Pos

#define RFCU_RF_OVERRULE_REG_IFF_FTDF_OVR_Pos   (6UL)

RFCU RF_OVERRULE_REG: IFF_FTDF_OVR (Bit 6)

Definition at line 9507 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_MIX_FTDF_OVR_Msk

#define RFCU_RF_OVERRULE_REG_MIX_FTDF_OVR_Msk   (0x300UL)

RFCU RF_OVERRULE_REG: MIX_FTDF_OVR (Bitfield-Mask: 0x03)

Definition at line 9510 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_MIX_FTDF_OVR_Pos

#define RFCU_RF_OVERRULE_REG_MIX_FTDF_OVR_Pos   (8UL)

RFCU RF_OVERRULE_REG: MIX_FTDF_OVR (Bit 8)

Definition at line 9509 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_RF_MODE_OVR_Msk

#define RFCU_RF_OVERRULE_REG_RF_MODE_OVR_Msk   (0x30UL)

RFCU RF_OVERRULE_REG: RF_MODE_OVR (Bitfield-Mask: 0x03)

Definition at line 9506 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_RF_MODE_OVR_Pos

#define RFCU_RF_OVERRULE_REG_RF_MODE_OVR_Pos   (4UL)

RFCU RF_OVERRULE_REG: RF_MODE_OVR (Bit 4)

Definition at line 9505 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_RX_EN_OVR_Msk

#define RFCU_RF_OVERRULE_REG_RX_EN_OVR_Msk   (0xcUL)

RFCU RF_OVERRULE_REG: RX_EN_OVR (Bitfield-Mask: 0x03)

Definition at line 9504 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_RX_EN_OVR_Pos

#define RFCU_RF_OVERRULE_REG_RX_EN_OVR_Pos   (2UL)

RFCU RF_OVERRULE_REG: RX_EN_OVR (Bit 2)

Definition at line 9503 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_TX_EN_OVR_Msk

#define RFCU_RF_OVERRULE_REG_TX_EN_OVR_Msk   (0x3UL)

RFCU RF_OVERRULE_REG: TX_EN_OVR (Bitfield-Mask: 0x03)

Definition at line 9502 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_TX_EN_OVR_Pos

#define RFCU_RF_OVERRULE_REG_TX_EN_OVR_Pos   (0UL)

RFCU RF_OVERRULE_REG: TX_EN_OVR (Bit 0)

Definition at line 9501 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_TXDAC_SEL_Msk

#define RFCU_RF_OVERRULE_REG_TXDAC_SEL_Msk   (0xc00UL)

RFCU RF_OVERRULE_REG: TXDAC_SEL (Bitfield-Mask: 0x03)

Definition at line 9512 of file DA14680BA.h.

◆ RFCU_RF_OVERRULE_REG_TXDAC_SEL_Pos

#define RFCU_RF_OVERRULE_REG_TXDAC_SEL_Pos   (10UL)

RFCU RF_OVERRULE_REG: TXDAC_SEL (Bit 10)

Definition at line 9511 of file DA14680BA.h.

◆ RFCU_RF_PA_CTRL_REG_LEVEL_LDO_RFPA_Msk

#define RFCU_RF_PA_CTRL_REG_LEVEL_LDO_RFPA_Msk   (0x7800UL)

RFCU RF_PA_CTRL_REG: LEVEL_LDO_RFPA (Bitfield-Mask: 0x0f)

Definition at line 9712 of file DA14680BA.h.

◆ RFCU_RF_PA_CTRL_REG_LEVEL_LDO_RFPA_Pos

#define RFCU_RF_PA_CTRL_REG_LEVEL_LDO_RFPA_Pos   (11UL)

RFCU RF_PA_CTRL_REG: LEVEL_LDO_RFPA (Bit 11)

Definition at line 9711 of file DA14680BA.h.

◆ RFCU_RF_PA_CTRL_REG_PA_FAST_DISCHARGE_EN_Msk

#define RFCU_RF_PA_CTRL_REG_PA_FAST_DISCHARGE_EN_Msk   (0x200UL)

RFCU RF_PA_CTRL_REG: PA_FAST_DISCHARGE_EN (Bitfield-Mask: 0x01)

Definition at line 9710 of file DA14680BA.h.

◆ RFCU_RF_PA_CTRL_REG_PA_FAST_DISCHARGE_EN_Pos

#define RFCU_RF_PA_CTRL_REG_PA_FAST_DISCHARGE_EN_Pos   (9UL)

RFCU RF_PA_CTRL_REG: PA_FAST_DISCHARGE_EN (Bit 9)

Definition at line 9709 of file DA14680BA.h.

◆ RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_DOWN_Msk

#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_DOWN_Msk   (0x60UL)

RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_DOWN (Bitfield-Mask: 0x03)

Definition at line 9706 of file DA14680BA.h.

◆ RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_DOWN_Pos

#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_DOWN_Pos   (5UL)

RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_DOWN (Bit 5)

Definition at line 9705 of file DA14680BA.h.

◆ RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_UP_Msk

#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_UP_Msk   (0x180UL)

RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_UP (Bitfield-Mask: 0x03)

Definition at line 9708 of file DA14680BA.h.

◆ RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_UP_Pos

#define RFCU_RF_PA_CTRL_REG_PA_RAMPSPEED_UP_Pos   (7UL)

RFCU RF_PA_CTRL_REG: PA_RAMPSPEED_UP (Bit 7)

Definition at line 9707 of file DA14680BA.h.

◆ RFCU_RF_PFD_CTRL_REG_FIXED_CUR_EN_Msk

#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_EN_Msk   (0x4UL)

RFCU RF_PFD_CTRL_REG: FIXED_CUR_EN (Bitfield-Mask: 0x01)

Definition at line 9740 of file DA14680BA.h.

◆ RFCU_RF_PFD_CTRL_REG_FIXED_CUR_EN_Pos

#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_EN_Pos   (2UL)

RFCU RF_PFD_CTRL_REG: FIXED_CUR_EN (Bit 2)

Definition at line 9739 of file DA14680BA.h.

◆ RFCU_RF_PFD_CTRL_REG_FIXED_CUR_SET_Msk

#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_SET_Msk   (0x3UL)

RFCU RF_PFD_CTRL_REG: FIXED_CUR_SET (Bitfield-Mask: 0x03)

Definition at line 9738 of file DA14680BA.h.

◆ RFCU_RF_PFD_CTRL_REG_FIXED_CUR_SET_Pos

#define RFCU_RF_PFD_CTRL_REG_FIXED_CUR_SET_Pos   (0UL)

RFCU RF_PFD_CTRL_REG: FIXED_CUR_SET (Bit 0)

Definition at line 9737 of file DA14680BA.h.

◆ RFCU_RF_PFD_CTRL_REG_PFD_POLARITY_Msk

#define RFCU_RF_PFD_CTRL_REG_PFD_POLARITY_Msk   (0x8UL)

RFCU RF_PFD_CTRL_REG: PFD_POLARITY (Bitfield-Mask: 0x01)

Definition at line 9742 of file DA14680BA.h.

◆ RFCU_RF_PFD_CTRL_REG_PFD_POLARITY_Pos

#define RFCU_RF_PFD_CTRL_REG_PFD_POLARITY_Pos   (3UL)

RFCU RF_PFD_CTRL_REG: PFD_POLARITY (Bit 3)

Definition at line 9741 of file DA14680BA.h.

◆ RFCU_RF_REF_OSC_BLE_REG_CNT_CLK_Msk

#define RFCU_RF_REF_OSC_BLE_REG_CNT_CLK_Msk   (0x7fc0UL)

RFCU RF_REF_OSC_BLE_REG: CNT_CLK (Bitfield-Mask: 0x1ff)

Definition at line 9582 of file DA14680BA.h.

◆ RFCU_RF_REF_OSC_BLE_REG_CNT_CLK_Pos

#define RFCU_RF_REF_OSC_BLE_REG_CNT_CLK_Pos   (6UL)

RFCU RF_REF_OSC_BLE_REG: CNT_CLK (Bit 6)

Definition at line 9581 of file DA14680BA.h.

◆ RFCU_RF_REF_OSC_BLE_REG_CNT_RO_Msk

#define RFCU_RF_REF_OSC_BLE_REG_CNT_RO_Msk   (0x3fUL)

RFCU RF_REF_OSC_BLE_REG: CNT_RO (Bitfield-Mask: 0x3f)

Definition at line 9580 of file DA14680BA.h.

◆ RFCU_RF_REF_OSC_BLE_REG_CNT_RO_Pos

#define RFCU_RF_REF_OSC_BLE_REG_CNT_RO_Pos   (0UL)

RFCU RF_REF_OSC_BLE_REG: CNT_RO (Bit 0)

Definition at line 9579 of file DA14680BA.h.

◆ RFCU_RF_REF_OSC_FTDF_REG_CNT_CLK_Msk

#define RFCU_RF_REF_OSC_FTDF_REG_CNT_CLK_Msk   (0x7fc0UL)

RFCU RF_REF_OSC_FTDF_REG: CNT_CLK (Bitfield-Mask: 0x1ff)

Definition at line 9588 of file DA14680BA.h.

◆ RFCU_RF_REF_OSC_FTDF_REG_CNT_CLK_Pos

#define RFCU_RF_REF_OSC_FTDF_REG_CNT_CLK_Pos   (6UL)

RFCU RF_REF_OSC_FTDF_REG: CNT_CLK (Bit 6)

Definition at line 9587 of file DA14680BA.h.

◆ RFCU_RF_REF_OSC_FTDF_REG_CNT_RO_Msk

#define RFCU_RF_REF_OSC_FTDF_REG_CNT_RO_Msk   (0x3fUL)

RFCU RF_REF_OSC_FTDF_REG: CNT_RO (Bitfield-Mask: 0x3f)

Definition at line 9586 of file DA14680BA.h.

◆ RFCU_RF_REF_OSC_FTDF_REG_CNT_RO_Pos

#define RFCU_RF_REF_OSC_FTDF_REG_CNT_RO_Pos   (0UL)

RFCU RF_REF_OSC_FTDF_REG: CNT_RO (Bit 0)

Definition at line 9585 of file DA14680BA.h.

◆ RFCU_RF_SCAN_FEEDBACK_REG_CP_CUR_Msk

#define RFCU_RF_SCAN_FEEDBACK_REG_CP_CUR_Msk   (0xf0UL)

RFCU RF_SCAN_FEEDBACK_REG: CP_CUR (Bitfield-Mask: 0x0f)

Definition at line 9576 of file DA14680BA.h.

◆ RFCU_RF_SCAN_FEEDBACK_REG_CP_CUR_Pos

#define RFCU_RF_SCAN_FEEDBACK_REG_CP_CUR_Pos   (4UL)

RFCU RF_SCAN_FEEDBACK_REG: CP_CUR (Bit 4)

Definition at line 9575 of file DA14680BA.h.

◆ RFCU_RF_SCAN_FEEDBACK_REG_LF_RES_Msk

#define RFCU_RF_SCAN_FEEDBACK_REG_LF_RES_Msk   (0xfUL)

RFCU RF_SCAN_FEEDBACK_REG: LF_RES (Bitfield-Mask: 0x0f)

Definition at line 9574 of file DA14680BA.h.

◆ RFCU_RF_SCAN_FEEDBACK_REG_LF_RES_Pos

#define RFCU_RF_SCAN_FEEDBACK_REG_LF_RES_Pos   (0UL)

RFCU RF_SCAN_FEEDBACK_REG: LF_RES (Bit 0)

Definition at line 9573 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_BLE_REG_RF_GDAC_CUR_SET_Msk

#define RFCU_RF_SPARE1_BLE_REG_RF_GDAC_CUR_SET_Msk   (0x30UL)

RFCU RF_SPARE1_BLE_REG: RF_GDAC_CUR_SET (Bitfield-Mask: 0x03)

Definition at line 9630 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_BLE_REG_RF_GDAC_CUR_SET_Pos

#define RFCU_RF_SPARE1_BLE_REG_RF_GDAC_CUR_SET_Pos   (4UL)

RFCU RF_SPARE1_BLE_REG: RF_GDAC_CUR_SET (Bit 4)

Definition at line 9629 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_BLE_REG_RF_SPARE_REG_Msk

#define RFCU_RF_SPARE1_BLE_REG_RF_SPARE_REG_Msk   (0xffc0UL)

RFCU RF_SPARE1_BLE_REG: RF_SPARE_REG (Bitfield-Mask: 0x3ff)

Definition at line 9632 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_BLE_REG_RF_SPARE_REG_Pos

#define RFCU_RF_SPARE1_BLE_REG_RF_SPARE_REG_Pos   (6UL)

RFCU RF_SPARE1_BLE_REG: RF_SPARE_REG (Bit 6)

Definition at line 9631 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_BLE_REG_RF_TXDAC_CLK_POL_SEL_Msk

#define RFCU_RF_SPARE1_BLE_REG_RF_TXDAC_CLK_POL_SEL_Msk   (0x8UL)

RFCU RF_SPARE1_BLE_REG: RF_TXDAC_CLK_POL_SEL (Bitfield-Mask: 0x01)

Definition at line 9628 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_BLE_REG_RF_TXDAC_CLK_POL_SEL_Pos

#define RFCU_RF_SPARE1_BLE_REG_RF_TXDAC_CLK_POL_SEL_Pos   (3UL)

RFCU RF_SPARE1_BLE_REG: RF_TXDAC_CLK_POL_SEL (Bit 3)

Definition at line 9627 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_BLE_REG_RF_VTUNE_TO_ADC_TEST_EN_Msk

#define RFCU_RF_SPARE1_BLE_REG_RF_VTUNE_TO_ADC_TEST_EN_Msk   (0x4UL)

RFCU RF_SPARE1_BLE_REG: RF_VTUNE_TO_ADC_TEST_EN (Bitfield-Mask: 0x01)

Definition at line 9626 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_BLE_REG_RF_VTUNE_TO_ADC_TEST_EN_Pos

#define RFCU_RF_SPARE1_BLE_REG_RF_VTUNE_TO_ADC_TEST_EN_Pos   (2UL)

RFCU RF_SPARE1_BLE_REG: RF_VTUNE_TO_ADC_TEST_EN (Bit 2)

Definition at line 9625 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_BLE_REG_RF_XTAL_PLL_DXTAL16_TEST_Msk

#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_PLL_DXTAL16_TEST_Msk   (0x2UL)

RFCU RF_SPARE1_BLE_REG: RF_XTAL_PLL_DXTAL16_TEST (Bitfield-Mask: 0x01)

Definition at line 9624 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_BLE_REG_RF_XTAL_PLL_DXTAL16_TEST_Pos

#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_PLL_DXTAL16_TEST_Pos   (1UL)

RFCU RF_SPARE1_BLE_REG: RF_XTAL_PLL_DXTAL16_TEST (Bit 1)

Definition at line 9623 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_BLE_REG_RF_XTAL_RFCLK_TEST_Msk

#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_RFCLK_TEST_Msk   (0x1UL)

RFCU RF_SPARE1_BLE_REG: RF_XTAL_RFCLK_TEST (Bitfield-Mask: 0x01)

Definition at line 9622 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_BLE_REG_RF_XTAL_RFCLK_TEST_Pos

#define RFCU_RF_SPARE1_BLE_REG_RF_XTAL_RFCLK_TEST_Pos   (0UL)

RFCU RF_SPARE1_BLE_REG: RF_XTAL_RFCLK_TEST (Bit 0)

Definition at line 9621 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_FTDF_REG_RF_GDAC_CUR_SET_Msk

#define RFCU_RF_SPARE1_FTDF_REG_RF_GDAC_CUR_SET_Msk   (0x30UL)

RFCU RF_SPARE1_FTDF_REG: RF_GDAC_CUR_SET (Bitfield-Mask: 0x03)

Definition at line 9644 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_FTDF_REG_RF_GDAC_CUR_SET_Pos

#define RFCU_RF_SPARE1_FTDF_REG_RF_GDAC_CUR_SET_Pos   (4UL)

RFCU RF_SPARE1_FTDF_REG: RF_GDAC_CUR_SET (Bit 4)

Definition at line 9643 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_FTDF_REG_RF_SPARE_REG_Msk

#define RFCU_RF_SPARE1_FTDF_REG_RF_SPARE_REG_Msk   (0xffc0UL)

RFCU RF_SPARE1_FTDF_REG: RF_SPARE_REG (Bitfield-Mask: 0x3ff)

Definition at line 9646 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_FTDF_REG_RF_SPARE_REG_Pos

#define RFCU_RF_SPARE1_FTDF_REG_RF_SPARE_REG_Pos   (6UL)

RFCU RF_SPARE1_FTDF_REG: RF_SPARE_REG (Bit 6)

Definition at line 9645 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_FTDF_REG_RF_TXDAC_CLK_POL_SEL_Msk

#define RFCU_RF_SPARE1_FTDF_REG_RF_TXDAC_CLK_POL_SEL_Msk   (0x8UL)

RFCU RF_SPARE1_FTDF_REG: RF_TXDAC_CLK_POL_SEL (Bitfield-Mask: 0x01)

Definition at line 9642 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_FTDF_REG_RF_TXDAC_CLK_POL_SEL_Pos

#define RFCU_RF_SPARE1_FTDF_REG_RF_TXDAC_CLK_POL_SEL_Pos   (3UL)

RFCU RF_SPARE1_FTDF_REG: RF_TXDAC_CLK_POL_SEL (Bit 3)

Definition at line 9641 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_FTDF_REG_RF_VTUNE_TO_ADC_TEST_EN_Msk

#define RFCU_RF_SPARE1_FTDF_REG_RF_VTUNE_TO_ADC_TEST_EN_Msk   (0x4UL)

RFCU RF_SPARE1_FTDF_REG: RF_VTUNE_TO_ADC_TEST_EN (Bitfield-Mask: 0x01)

Definition at line 9640 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_FTDF_REG_RF_VTUNE_TO_ADC_TEST_EN_Pos

#define RFCU_RF_SPARE1_FTDF_REG_RF_VTUNE_TO_ADC_TEST_EN_Pos   (2UL)

RFCU RF_SPARE1_FTDF_REG: RF_VTUNE_TO_ADC_TEST_EN (Bit 2)

Definition at line 9639 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_PLL_DXTAL16_TEST_Msk

#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_PLL_DXTAL16_TEST_Msk   (0x2UL)

RFCU RF_SPARE1_FTDF_REG: RF_XTAL_PLL_DXTAL16_TEST (Bitfield-Mask: 0x01)

Definition at line 9638 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_PLL_DXTAL16_TEST_Pos

#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_PLL_DXTAL16_TEST_Pos   (1UL)

RFCU RF_SPARE1_FTDF_REG: RF_XTAL_PLL_DXTAL16_TEST (Bit 1)

Definition at line 9637 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_RFCLK_TEST_Msk

#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_RFCLK_TEST_Msk   (0x1UL)

RFCU RF_SPARE1_FTDF_REG: RF_XTAL_RFCLK_TEST (Bitfield-Mask: 0x01)

Definition at line 9636 of file DA14680BA.h.

◆ RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_RFCLK_TEST_Pos

#define RFCU_RF_SPARE1_FTDF_REG_RF_XTAL_RFCLK_TEST_Pos   (0UL)

RFCU RF_SPARE1_FTDF_REG: RF_XTAL_RFCLK_TEST (Bit 0)

Definition at line 9635 of file DA14680BA.h.

◆ RFCU_RF_TDC_CTRL_REG_CAL_PH_1_Msk

#define RFCU_RF_TDC_CTRL_REG_CAL_PH_1_Msk   (0x100UL)

RFCU RF_TDC_CTRL_REG: CAL_PH_1 (Bitfield-Mask: 0x01)

Definition at line 9830 of file DA14680BA.h.

◆ RFCU_RF_TDC_CTRL_REG_CAL_PH_1_Pos

#define RFCU_RF_TDC_CTRL_REG_CAL_PH_1_Pos   (8UL)

RFCU RF_TDC_CTRL_REG: CAL_PH_1 (Bit 8)

Definition at line 9829 of file DA14680BA.h.

◆ RFCU_RF_TDC_CTRL_REG_CAL_PH_2_Msk

#define RFCU_RF_TDC_CTRL_REG_CAL_PH_2_Msk   (0x200UL)

RFCU RF_TDC_CTRL_REG: CAL_PH_2 (Bitfield-Mask: 0x01)

Definition at line 9832 of file DA14680BA.h.

◆ RFCU_RF_TDC_CTRL_REG_CAL_PH_2_Pos

#define RFCU_RF_TDC_CTRL_REG_CAL_PH_2_Pos   (9UL)

RFCU RF_TDC_CTRL_REG: CAL_PH_2 (Bit 9)

Definition at line 9831 of file DA14680BA.h.

◆ RFCU_RF_TDC_CTRL_REG_CTRL_FAST_Msk

#define RFCU_RF_TDC_CTRL_REG_CTRL_FAST_Msk   (0xfUL)

RFCU RF_TDC_CTRL_REG: CTRL_FAST (Bitfield-Mask: 0x0f)

Definition at line 9826 of file DA14680BA.h.

◆ RFCU_RF_TDC_CTRL_REG_CTRL_FAST_Pos

#define RFCU_RF_TDC_CTRL_REG_CTRL_FAST_Pos   (0UL)

RFCU RF_TDC_CTRL_REG: CTRL_FAST (Bit 0)

Definition at line 9825 of file DA14680BA.h.

◆ RFCU_RF_TDC_CTRL_REG_CTRL_SLOW_Msk

#define RFCU_RF_TDC_CTRL_REG_CTRL_SLOW_Msk   (0xf0UL)

RFCU RF_TDC_CTRL_REG: CTRL_SLOW (Bitfield-Mask: 0x0f)

Definition at line 9828 of file DA14680BA.h.

◆ RFCU_RF_TDC_CTRL_REG_CTRL_SLOW_Pos

#define RFCU_RF_TDC_CTRL_REG_CTRL_SLOW_Pos   (4UL)

RFCU RF_TDC_CTRL_REG: CTRL_SLOW (Bit 4)

Definition at line 9827 of file DA14680BA.h.

◆ RFCU_RF_TDC_CTRL_REG_REF_CTRL_Msk

#define RFCU_RF_TDC_CTRL_REG_REF_CTRL_Msk   (0xc00UL)

RFCU RF_TDC_CTRL_REG: REF_CTRL (Bitfield-Mask: 0x03)

Definition at line 9834 of file DA14680BA.h.

◆ RFCU_RF_TDC_CTRL_REG_REF_CTRL_Pos

#define RFCU_RF_TDC_CTRL_REG_REF_CTRL_Pos   (10UL)

RFCU RF_TDC_CTRL_REG: REF_CTRL (Bit 10)

Definition at line 9833 of file DA14680BA.h.

◆ RFCU_RF_TDC_CTRL_REG_TDC_CONNECT_Msk

#define RFCU_RF_TDC_CTRL_REG_TDC_CONNECT_Msk   (0x1000UL)

RFCU RF_TDC_CTRL_REG: TDC_CONNECT (Bitfield-Mask: 0x01)

Definition at line 9836 of file DA14680BA.h.

◆ RFCU_RF_TDC_CTRL_REG_TDC_CONNECT_Pos

#define RFCU_RF_TDC_CTRL_REG_TDC_CONNECT_Pos   (12UL)

RFCU RF_TDC_CTRL_REG: TDC_CONNECT (Bit 12)

Definition at line 9835 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_BLE_REG_TX_POWER_SET_Msk

#define RFCU_RF_TX_PWR_BLE_REG_TX_POWER_SET_Msk   (0x7UL)

RFCU RF_TX_PWR_BLE_REG: TX_POWER_SET (Bitfield-Mask: 0x07)

Definition at line 9870 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_BLE_REG_TX_POWER_SET_Pos

#define RFCU_RF_TX_PWR_BLE_REG_TX_POWER_SET_Pos   (0UL)

RFCU RF_TX_PWR_BLE_REG: TX_POWER_SET (Bit 0)

Definition at line 9869 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_FTDF_REG_TX_POWER_SET_Msk

#define RFCU_RF_TX_PWR_FTDF_REG_TX_POWER_SET_Msk   (0x7UL)

RFCU RF_TX_PWR_FTDF_REG: TX_POWER_SET (Bitfield-Mask: 0x07)

Definition at line 9944 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_FTDF_REG_TX_POWER_SET_Pos

#define RFCU_RF_TX_PWR_FTDF_REG_TX_POWER_SET_Pos   (0UL)

RFCU RF_TX_PWR_FTDF_REG: TX_POWER_SET (Bit 0)

Definition at line 9943 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_IO_CTRL1_REG_Msk

#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)

RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03)

Definition at line 9874 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_IO_CTRL1_REG_Pos

#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)

RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)

Definition at line 9873 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk

#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)

RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f)

Definition at line 9878 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos

#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)

RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)

Definition at line 9877 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_PA_CTRL_REG_Msk

#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)

RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f)

Definition at line 9876 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_PA_CTRL_REG_Pos

#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)

RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)

Definition at line 9875 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk

#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)

RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01)

Definition at line 9880 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos

#define RFCU_RF_TX_PWR_LUT_1_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)

RFCU RF_TX_PWR_LUT_1_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11)

Definition at line 9879 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_IO_CTRL1_REG_Msk

#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)

RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03)

Definition at line 9884 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_IO_CTRL1_REG_Pos

#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)

RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)

Definition at line 9883 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk

#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)

RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f)

Definition at line 9888 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos

#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)

RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)

Definition at line 9887 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_PA_CTRL_REG_Msk

#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)

RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f)

Definition at line 9886 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_PA_CTRL_REG_Pos

#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)

RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)

Definition at line 9885 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk

#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)

RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01)

Definition at line 9890 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos

#define RFCU_RF_TX_PWR_LUT_2_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)

RFCU RF_TX_PWR_LUT_2_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11)

Definition at line 9889 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_IO_CTRL1_REG_Msk

#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)

RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03)

Definition at line 9894 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_IO_CTRL1_REG_Pos

#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)

RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)

Definition at line 9893 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk

#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)

RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f)

Definition at line 9898 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos

#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)

RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)

Definition at line 9897 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_PA_CTRL_REG_Msk

#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)

RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f)

Definition at line 9896 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_PA_CTRL_REG_Pos

#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)

RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)

Definition at line 9895 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk

#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)

RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01)

Definition at line 9900 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos

#define RFCU_RF_TX_PWR_LUT_3_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)

RFCU RF_TX_PWR_LUT_3_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11)

Definition at line 9899 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_IO_CTRL1_REG_Msk

#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)

RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03)

Definition at line 9904 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_IO_CTRL1_REG_Pos

#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)

RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)

Definition at line 9903 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk

#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)

RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f)

Definition at line 9908 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos

#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)

RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)

Definition at line 9907 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_PA_CTRL_REG_Msk

#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)

RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f)

Definition at line 9906 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_PA_CTRL_REG_Pos

#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)

RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)

Definition at line 9905 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk

#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)

RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01)

Definition at line 9910 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos

#define RFCU_RF_TX_PWR_LUT_4_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)

RFCU RF_TX_PWR_LUT_4_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11)

Definition at line 9909 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_IO_CTRL1_REG_Msk

#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)

RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03)

Definition at line 9914 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_IO_CTRL1_REG_Pos

#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)

RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)

Definition at line 9913 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk

#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)

RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f)

Definition at line 9918 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos

#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)

RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)

Definition at line 9917 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_PA_CTRL_REG_Msk

#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)

RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f)

Definition at line 9916 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_PA_CTRL_REG_Pos

#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)

RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)

Definition at line 9915 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk

#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)

RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01)

Definition at line 9920 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos

#define RFCU_RF_TX_PWR_LUT_5_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)

RFCU RF_TX_PWR_LUT_5_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11)

Definition at line 9919 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_IO_CTRL1_REG_Msk

#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)

RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03)

Definition at line 9924 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_IO_CTRL1_REG_Pos

#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)

RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)

Definition at line 9923 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk

#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)

RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f)

Definition at line 9928 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos

#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)

RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)

Definition at line 9927 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_PA_CTRL_REG_Msk

#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)

RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f)

Definition at line 9926 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_PA_CTRL_REG_Pos

#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)

RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)

Definition at line 9925 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk

#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)

RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01)

Definition at line 9930 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos

#define RFCU_RF_TX_PWR_LUT_6_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)

RFCU RF_TX_PWR_LUT_6_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11)

Definition at line 9929 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Msk

#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Msk   (0x3UL)

RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_IO_CTRL1_REG (Bitfield-Mask: 0x03)

Definition at line 9934 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Pos

#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_IO_CTRL1_REG_Pos   (0UL)

RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_IO_CTRL1_REG (Bit 0)

Definition at line 9933 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk

#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Msk   (0x7c0UL)

RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_LNA_CTRL3_REG (Bitfield-Mask: 0x1f)

Definition at line 9938 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos

#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_LNA_CTRL3_REG_Pos   (6UL)

RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_LNA_CTRL3_REG (Bit 6)

Definition at line 9937 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Msk

#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Msk   (0x3cUL)

RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_PA_CTRL_REG (Bitfield-Mask: 0x0f)

Definition at line 9936 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Pos

#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RF_PA_CTRL_REG_Pos   (2UL)

RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RF_PA_CTRL_REG (Bit 2)

Definition at line 9935 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk

#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Msk   (0x800UL)

RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bitfield-Mask: 0x01)

Definition at line 9940 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos

#define RFCU_RF_TX_PWR_LUT_7_REG_TX_PWR_RFIO_TXRX_DCF_DIS_Pos   (11UL)

RFCU RF_TX_PWR_LUT_7_REG: TX_PWR_RFIO_TXRX_DCF_DIS (Bit 11)

Definition at line 9939 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_RD_REG_RF_TX_PWR_LUT_RD_Msk

#define RFCU_RF_TX_PWR_LUT_RD_REG_RF_TX_PWR_LUT_RD_Msk   (0xfffUL)

RFCU RF_TX_PWR_LUT_RD_REG: RF_TX_PWR_LUT_RD (Bitfield-Mask: 0xfff)

Definition at line 9948 of file DA14680BA.h.

◆ RFCU_RF_TX_PWR_LUT_RD_REG_RF_TX_PWR_LUT_RD_Pos

#define RFCU_RF_TX_PWR_LUT_RD_REG_RF_TX_PWR_LUT_RD_Pos   (0UL)

RFCU RF_TX_PWR_LUT_RD_REG: RF_TX_PWR_LUT_RD (Bit 0)

Definition at line 9947 of file DA14680BA.h.

◆ RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_CAL_CAP_RD_Msk

#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_CAL_CAP_RD_Msk   (0x1fUL)

RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_CAL_CAP_RD (Bitfield-Mask: 0x1f)

Definition at line 9982 of file DA14680BA.h.

◆ RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_CAL_CAP_RD_Pos

#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_CAL_CAP_RD_Pos   (0UL)

RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_CAL_CAP_RD (Bit 0)

Definition at line 9981 of file DA14680BA.h.

◆ RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_FIXED_CAP_ON_RD_Msk

#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_FIXED_CAP_ON_RD_Msk   (0x20UL)

RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_FIXED_CAP_ON_RD (Bitfield-Mask: 0x01)

Definition at line 9984 of file DA14680BA.h.

◆ RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_FIXED_CAP_ON_RD_Pos

#define RFCU_RF_TXDAC_CAL_CAP_STAT_REG_TXDAC_FIXED_CAP_ON_RD_Pos   (5UL)

RFCU RF_TXDAC_CAL_CAP_STAT_REG: TXDAC_FIXED_CAP_ON_RD (Bit 5)

Definition at line 9983 of file DA14680BA.h.

◆ RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_SEL_Msk

#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_SEL_Msk   (0x20UL)

RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_SEL (Bitfield-Mask: 0x01)

Definition at line 9974 of file DA14680BA.h.

◆ RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_SEL_Pos

#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_SEL_Pos   (5UL)

RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_SEL (Bit 5)

Definition at line 9973 of file DA14680BA.h.

◆ RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_BLE_Msk

#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_BLE_Msk   (0x1fUL)

RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_BLE (Bitfield-Mask: 0x1f)

Definition at line 9972 of file DA14680BA.h.

◆ RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_BLE_Pos

#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_BLE_Pos   (0UL)

RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_BLE (Bit 0)

Definition at line 9971 of file DA14680BA.h.

◆ RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_FTDF_Msk

#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_FTDF_Msk   (0xf80UL)

RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_FTDF (Bitfield-Mask: 0x1f)

Definition at line 9978 of file DA14680BA.h.

◆ RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_FTDF_Pos

#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_CAL_CAP_WR_FTDF_Pos   (7UL)

RFCU RF_TXDAC_CTRL_REG: TXDAC_CAL_CAP_WR_FTDF (Bit 7)

Definition at line 9977 of file DA14680BA.h.

◆ RFCU_RF_TXDAC_CTRL_REG_TXDAC_FIXED_CAP_ON_Msk

#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_FIXED_CAP_ON_Msk   (0x40UL)

RFCU RF_TXDAC_CTRL_REG: TXDAC_FIXED_CAP_ON (Bitfield-Mask: 0x01)

Definition at line 9976 of file DA14680BA.h.

◆ RFCU_RF_TXDAC_CTRL_REG_TXDAC_FIXED_CAP_ON_Pos

#define RFCU_RF_TXDAC_CTRL_REG_TXDAC_FIXED_CAP_ON_Pos   (6UL)

RFCU RF_TXDAC_CTRL_REG: TXDAC_FIXED_CAP_ON (Bit 6)

Definition at line 9975 of file DA14680BA.h.

◆ RFCU_RF_VCO_AMP_CTRL1_REG_VCO_AMPL_MODE_Msk

#define RFCU_RF_VCO_AMP_CTRL1_REG_VCO_AMPL_MODE_Msk   (0x7fUL)

RFCU RF_VCO_AMP_CTRL1_REG: VCO_AMPL_MODE (Bitfield-Mask: 0x7f)

Definition at line 9860 of file DA14680BA.h.

◆ RFCU_RF_VCO_AMP_CTRL1_REG_VCO_AMPL_MODE_Pos

#define RFCU_RF_VCO_AMP_CTRL1_REG_VCO_AMPL_MODE_Pos   (0UL)

RFCU RF_VCO_AMP_CTRL1_REG: VCO_AMPL_MODE (Bit 0)

Definition at line 9859 of file DA14680BA.h.

◆ RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_RX_Msk

#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_RX_Msk   (0xff00UL)

RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_RX (Bitfield-Mask: 0xff)

Definition at line 9866 of file DA14680BA.h.

◆ RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_RX_Pos

#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_RX_Pos   (8UL)

RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_RX (Bit 8)

Definition at line 9865 of file DA14680BA.h.

◆ RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_TX_Msk

#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_TX_Msk   (0xffUL)

RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_TX (Bitfield-Mask: 0xff)

Definition at line 9864 of file DA14680BA.h.

◆ RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_TX_Pos

#define RFCU_RF_VCO_AMP_CTRL2_REG_VCO_AMPL_SET_TX_Pos   (0UL)

RFCU RF_VCO_AMP_CTRL2_REG: VCO_AMPL_SET_TX (Bit 0)

Definition at line 9863 of file DA14680BA.h.

◆ RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V0_Msk

#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V0_Msk   (0x3000UL)

RFCU RF_VCOVAR_CTRL_REG: MOD_VAR_V0 (Bitfield-Mask: 0x03)

Definition at line 9732 of file DA14680BA.h.

◆ RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V0_Pos

#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V0_Pos   (12UL)

RFCU RF_VCOVAR_CTRL_REG: MOD_VAR_V0 (Bit 12)

Definition at line 9731 of file DA14680BA.h.

◆ RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V1_Msk

#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V1_Msk   (0xc000UL)

RFCU RF_VCOVAR_CTRL_REG: MOD_VAR_V1 (Bitfield-Mask: 0x03)

Definition at line 9734 of file DA14680BA.h.

◆ RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V1_Pos

#define RFCU_RF_VCOVAR_CTRL_REG_MOD_VAR_V1_Pos   (14UL)

RFCU RF_VCOVAR_CTRL_REG: MOD_VAR_V1 (Bit 14)

Definition at line 9733 of file DA14680BA.h.

◆ RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V0_Msk

#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V0_Msk   (0x7UL)

RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V0 (Bitfield-Mask: 0x07)

Definition at line 9724 of file DA14680BA.h.

◆ RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V0_Pos

#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V0_Pos   (0UL)

RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V0 (Bit 0)

Definition at line 9723 of file DA14680BA.h.

◆ RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V1_Msk

#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V1_Msk   (0x38UL)

RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V1 (Bitfield-Mask: 0x07)

Definition at line 9726 of file DA14680BA.h.

◆ RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V1_Pos

#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V1_Pos   (3UL)

RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V1 (Bit 3)

Definition at line 9725 of file DA14680BA.h.

◆ RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V2_Msk

#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V2_Msk   (0x1c0UL)

RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V2 (Bitfield-Mask: 0x07)

Definition at line 9728 of file DA14680BA.h.

◆ RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V2_Pos

#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V2_Pos   (6UL)

RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V2 (Bit 6)

Definition at line 9727 of file DA14680BA.h.

◆ RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V3_Msk

#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V3_Msk   (0xe00UL)

RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V3 (Bitfield-Mask: 0x07)

Definition at line 9730 of file DA14680BA.h.

◆ RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V3_Pos

#define RFCU_RF_VCOVAR_CTRL_REG_TUNE_VAR_V3_Pos   (9UL)

RFCU RF_VCOVAR_CTRL_REG: TUNE_VAR_V3 (Bit 9)

Definition at line 9729 of file DA14680BA.h.

◆ RFPT

#define RFPT   ((RFPT_Type *) RFPT_BASE)

Definition at line 12102 of file DA14680BA.h.

◆ RFPT_BASE

#define RFPT_BASE   0x50003600UL

Definition at line 12057 of file DA14680BA.h.

◆ RFPT_RFPT_ADDRH_REG_RFPT_ADDRH_Msk

#define RFPT_RFPT_ADDRH_REG_RFPT_ADDRH_Msk   (0x3UL)

RFPT RFPT_ADDRH_REG: RFPT_ADDRH (Bitfield-Mask: 0x03)

Definition at line 10772 of file DA14680BA.h.

◆ RFPT_RFPT_ADDRH_REG_RFPT_ADDRH_Pos

#define RFPT_RFPT_ADDRH_REG_RFPT_ADDRH_Pos   (0UL)

RFPT RFPT_ADDRH_REG: RFPT_ADDRH (Bit 0)

Definition at line 10771 of file DA14680BA.h.

◆ RFPT_RFPT_ADDRL_REG_RFPT_ADDRL_Msk

#define RFPT_RFPT_ADDRL_REG_RFPT_ADDRL_Msk   (0xfffcUL)

RFPT RFPT_ADDRL_REG: RFPT_ADDRL (Bitfield-Mask: 0x3fff)

Definition at line 10768 of file DA14680BA.h.

◆ RFPT_RFPT_ADDRL_REG_RFPT_ADDRL_Pos

#define RFPT_RFPT_ADDRL_REG_RFPT_ADDRL_Pos   (2UL)

RFPT RFPT_ADDRL_REG: RFPT_ADDRL (Bit 2)

Definition at line 10767 of file DA14680BA.h.

◆ RFPT_RFPT_CRV_ADDRH_REG_RFPT_CRV_ADDRH_Msk

#define RFPT_RFPT_CRV_ADDRH_REG_RFPT_CRV_ADDRH_Msk   (0x3UL)

RFPT RFPT_CRV_ADDRH_REG: RFPT_CRV_ADDRH (Bitfield-Mask: 0x03)

Definition at line 10790 of file DA14680BA.h.

◆ RFPT_RFPT_CRV_ADDRH_REG_RFPT_CRV_ADDRH_Pos

#define RFPT_RFPT_CRV_ADDRH_REG_RFPT_CRV_ADDRH_Pos   (0UL)

RFPT RFPT_CRV_ADDRH_REG: RFPT_CRV_ADDRH (Bit 0)

Definition at line 10789 of file DA14680BA.h.

◆ RFPT_RFPT_CRV_ADDRL_REG_RFPT_CRV_ADDRL_Msk

#define RFPT_RFPT_CRV_ADDRL_REG_RFPT_CRV_ADDRL_Msk   (0xfffcUL)

RFPT RFPT_CRV_ADDRL_REG: RFPT_CRV_ADDRL (Bitfield-Mask: 0x3fff)

Definition at line 10786 of file DA14680BA.h.

◆ RFPT_RFPT_CRV_ADDRL_REG_RFPT_CRV_ADDRL_Pos

#define RFPT_RFPT_CRV_ADDRL_REG_RFPT_CRV_ADDRL_Pos   (2UL)

RFPT RFPT_CRV_ADDRL_REG: RFPT_CRV_ADDRL (Bit 2)

Definition at line 10785 of file DA14680BA.h.

◆ RFPT_RFPT_CRV_LEN_REG_RFPT_CRV_LEN_Msk

#define RFPT_RFPT_CRV_LEN_REG_RFPT_CRV_LEN_Msk   (0x7fffUL)

RFPT RFPT_CRV_LEN_REG: RFPT_CRV_LEN (Bitfield-Mask: 0x7fff)

Definition at line 10794 of file DA14680BA.h.

◆ RFPT_RFPT_CRV_LEN_REG_RFPT_CRV_LEN_Pos

#define RFPT_RFPT_CRV_LEN_REG_RFPT_CRV_LEN_Pos   (0UL)

RFPT RFPT_CRV_LEN_REG: RFPT_CRV_LEN (Bit 0)

Definition at line 10793 of file DA14680BA.h.

◆ RFPT_RFPT_CTRL_REG_RFPT_BREQ_FORCE_Msk

#define RFPT_RFPT_CTRL_REG_RFPT_BREQ_FORCE_Msk   (0x20UL)

RFPT RFPT_CTRL_REG: RFPT_BREQ_FORCE (Bitfield-Mask: 0x01)

Definition at line 10764 of file DA14680BA.h.

◆ RFPT_RFPT_CTRL_REG_RFPT_BREQ_FORCE_Pos

#define RFPT_RFPT_CTRL_REG_RFPT_BREQ_FORCE_Pos   (5UL)

RFPT RFPT_CTRL_REG: RFPT_BREQ_FORCE (Bit 5)

Definition at line 10763 of file DA14680BA.h.

◆ RFPT_RFPT_CTRL_REG_RFPT_CIRC_EN_Msk

#define RFPT_RFPT_CTRL_REG_RFPT_CIRC_EN_Msk   (0x10UL)

RFPT RFPT_CTRL_REG: RFPT_CIRC_EN (Bitfield-Mask: 0x01)

Definition at line 10762 of file DA14680BA.h.

◆ RFPT_RFPT_CTRL_REG_RFPT_CIRC_EN_Pos

#define RFPT_RFPT_CTRL_REG_RFPT_CIRC_EN_Pos   (4UL)

RFPT RFPT_CTRL_REG: RFPT_CIRC_EN (Bit 4)

Definition at line 10761 of file DA14680BA.h.

◆ RFPT_RFPT_CTRL_REG_RFPT_PACK_ADC_TYPE_Msk

#define RFPT_RFPT_CTRL_REG_RFPT_PACK_ADC_TYPE_Msk   (0x8UL)

RFPT RFPT_CTRL_REG: RFPT_PACK_ADC_TYPE (Bitfield-Mask: 0x01)

Definition at line 10760 of file DA14680BA.h.

◆ RFPT_RFPT_CTRL_REG_RFPT_PACK_ADC_TYPE_Pos

#define RFPT_RFPT_CTRL_REG_RFPT_PACK_ADC_TYPE_Pos   (3UL)

RFPT RFPT_CTRL_REG: RFPT_PACK_ADC_TYPE (Bit 3)

Definition at line 10759 of file DA14680BA.h.

◆ RFPT_RFPT_CTRL_REG_RFPT_PACK_EN_Msk

#define RFPT_RFPT_CTRL_REG_RFPT_PACK_EN_Msk   (0x1UL)

RFPT RFPT_CTRL_REG: RFPT_PACK_EN (Bitfield-Mask: 0x01)

Definition at line 10756 of file DA14680BA.h.

◆ RFPT_RFPT_CTRL_REG_RFPT_PACK_EN_Pos

#define RFPT_RFPT_CTRL_REG_RFPT_PACK_EN_Pos   (0UL)

RFPT RFPT_CTRL_REG: RFPT_PACK_EN (Bit 0)

Definition at line 10755 of file DA14680BA.h.

◆ RFPT_RFPT_CTRL_REG_RFPT_PACK_SEL_Msk

#define RFPT_RFPT_CTRL_REG_RFPT_PACK_SEL_Msk   (0x6UL)

RFPT RFPT_CTRL_REG: RFPT_PACK_SEL (Bitfield-Mask: 0x03)

Definition at line 10758 of file DA14680BA.h.

◆ RFPT_RFPT_CTRL_REG_RFPT_PACK_SEL_Pos

#define RFPT_RFPT_CTRL_REG_RFPT_PACK_SEL_Pos   (1UL)

RFPT RFPT_CTRL_REG: RFPT_PACK_SEL (Bit 1)

Definition at line 10757 of file DA14680BA.h.

◆ RFPT_RFPT_LEN_REG_RFPT_LEN_Msk

#define RFPT_RFPT_LEN_REG_RFPT_LEN_Msk   (0x7fffUL)

RFPT RFPT_LEN_REG: RFPT_LEN (Bitfield-Mask: 0x7fff)

Definition at line 10776 of file DA14680BA.h.

◆ RFPT_RFPT_LEN_REG_RFPT_LEN_Pos

#define RFPT_RFPT_LEN_REG_RFPT_LEN_Pos   (0UL)

RFPT RFPT_LEN_REG: RFPT_LEN (Bit 0)

Definition at line 10775 of file DA14680BA.h.

◆ RFPT_RFPT_STAT_REG_RFPT_ACTIVE_Msk

#define RFPT_RFPT_STAT_REG_RFPT_ACTIVE_Msk   (0x1UL)

RFPT RFPT_STAT_REG: RFPT_ACTIVE (Bitfield-Mask: 0x01)

Definition at line 10780 of file DA14680BA.h.

◆ RFPT_RFPT_STAT_REG_RFPT_ACTIVE_Pos

#define RFPT_RFPT_STAT_REG_RFPT_ACTIVE_Pos   (0UL)

RFPT RFPT_STAT_REG: RFPT_ACTIVE (Bit 0)

Definition at line 10779 of file DA14680BA.h.

◆ RFPT_RFPT_STAT_REG_RFPT_OFLOW_STK_Msk

#define RFPT_RFPT_STAT_REG_RFPT_OFLOW_STK_Msk   (0x2UL)

RFPT RFPT_STAT_REG: RFPT_OFLOW_STK (Bitfield-Mask: 0x01)

Definition at line 10782 of file DA14680BA.h.

◆ RFPT_RFPT_STAT_REG_RFPT_OFLOW_STK_Pos

#define RFPT_RFPT_STAT_REG_RFPT_OFLOW_STK_Pos   (1UL)

RFPT RFPT_STAT_REG: RFPT_OFLOW_STK (Bit 1)

Definition at line 10781 of file DA14680BA.h.

◆ SPI

#define SPI   ((SPI_Type *) SPI_BASE)

Definition at line 12103 of file DA14680BA.h.

◆ SPI2

#define SPI2   ((SPI2_Type *) SPI2_BASE)

Definition at line 12104 of file DA14680BA.h.

◆ SPI2_BASE

#define SPI2_BASE   0x50001300UL

Definition at line 12059 of file DA14680BA.h.

◆ SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Msk

#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Msk   (0xffffUL)

SPI2 SPI2_CLEAR_INT_REG: SPI_CLEAR_INT (Bitfield-Mask: 0xffff)

Definition at line 10900 of file DA14680BA.h.

◆ SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Pos

#define SPI2_SPI2_CLEAR_INT_REG_SPI_CLEAR_INT_Pos   (0UL)

SPI2 SPI2_CLEAR_INT_REG: SPI_CLEAR_INT (Bit 0)

Definition at line 10899 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG1_SPI_9BIT_VAL_Msk

#define SPI2_SPI2_CTRL_REG1_SPI_9BIT_VAL_Msk   (0x10UL)

SPI2 SPI2_CTRL_REG1: SPI_9BIT_VAL (Bitfield-Mask: 0x01)

Definition at line 10910 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG1_SPI_9BIT_VAL_Pos

#define SPI2_SPI2_CTRL_REG1_SPI_9BIT_VAL_Pos   (4UL)

SPI2 SPI2_CTRL_REG1: SPI_9BIT_VAL (Bit 4)

Definition at line 10909 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG1_SPI_BUSY_Msk

#define SPI2_SPI2_CTRL_REG1_SPI_BUSY_Msk   (0x8UL)

SPI2 SPI2_CTRL_REG1: SPI_BUSY (Bitfield-Mask: 0x01)

Definition at line 10908 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG1_SPI_BUSY_Pos

#define SPI2_SPI2_CTRL_REG1_SPI_BUSY_Pos   (3UL)

SPI2 SPI2_CTRL_REG1: SPI_BUSY (Bit 3)

Definition at line 10907 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG1_SPI_FIFO_MODE_Msk

#define SPI2_SPI2_CTRL_REG1_SPI_FIFO_MODE_Msk   (0x3UL)

SPI2 SPI2_CTRL_REG1: SPI_FIFO_MODE (Bitfield-Mask: 0x03)

Definition at line 10904 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG1_SPI_FIFO_MODE_Pos

#define SPI2_SPI2_CTRL_REG1_SPI_FIFO_MODE_Pos   (0UL)

SPI2 SPI2_CTRL_REG1: SPI_FIFO_MODE (Bit 0)

Definition at line 10903 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG1_SPI_PRIORITY_Msk

#define SPI2_SPI2_CTRL_REG1_SPI_PRIORITY_Msk   (0x4UL)

SPI2 SPI2_CTRL_REG1: SPI_PRIORITY (Bitfield-Mask: 0x01)

Definition at line 10906 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG1_SPI_PRIORITY_Pos

#define SPI2_SPI2_CTRL_REG1_SPI_PRIORITY_Pos   (2UL)

SPI2 SPI2_CTRL_REG1: SPI_PRIORITY (Bit 2)

Definition at line 10905 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_CLK_Msk

#define SPI2_SPI2_CTRL_REG_SPI_CLK_Msk   (0x18UL)

SPI2 SPI2_CTRL_REG: SPI_CLK (Bitfield-Mask: 0x03)

Definition at line 10868 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_CLK_Pos

#define SPI2_SPI2_CTRL_REG_SPI_CLK_Pos   (3UL)

SPI2 SPI2_CTRL_REG: SPI_CLK (Bit 3)

Definition at line 10867 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_DI_Msk

#define SPI2_SPI2_CTRL_REG_SPI_DI_Msk   (0x1000UL)

SPI2 SPI2_CTRL_REG: SPI_DI (Bitfield-Mask: 0x01)

Definition at line 10882 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_DI_Pos

#define SPI2_SPI2_CTRL_REG_SPI_DI_Pos   (12UL)

SPI2 SPI2_CTRL_REG: SPI_DI (Bit 12)

Definition at line 10881 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_DO_Msk

#define SPI2_SPI2_CTRL_REG_SPI_DO_Msk   (0x20UL)

SPI2 SPI2_CTRL_REG: SPI_DO (Bitfield-Mask: 0x01)

Definition at line 10870 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_DO_Pos

#define SPI2_SPI2_CTRL_REG_SPI_DO_Pos   (5UL)

SPI2 SPI2_CTRL_REG: SPI_DO (Bit 5)

Definition at line 10869 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Msk

#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Msk   (0x8000UL)

SPI2 SPI2_CTRL_REG: SPI_EN_CTRL (Bitfield-Mask: 0x01)

Definition at line 10888 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Pos

#define SPI2_SPI2_CTRL_REG_SPI_EN_CTRL_Pos   (15UL)

SPI2 SPI2_CTRL_REG: SPI_EN_CTRL (Bit 15)

Definition at line 10887 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Msk

#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Msk   (0x400UL)

SPI2 SPI2_CTRL_REG: SPI_FORCE_DO (Bitfield-Mask: 0x01)

Definition at line 10878 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Pos

#define SPI2_SPI2_CTRL_REG_SPI_FORCE_DO_Pos   (10UL)

SPI2 SPI2_CTRL_REG: SPI_FORCE_DO (Bit 10)

Definition at line 10877 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Msk

#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Msk   (0x2000UL)

SPI2 SPI2_CTRL_REG: SPI_INT_BIT (Bitfield-Mask: 0x01)

Definition at line 10884 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Pos

#define SPI2_SPI2_CTRL_REG_SPI_INT_BIT_Pos   (13UL)

SPI2 SPI2_CTRL_REG: SPI_INT_BIT (Bit 13)

Definition at line 10883 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_MINT_Msk

#define SPI2_SPI2_CTRL_REG_SPI_MINT_Msk   (0x4000UL)

SPI2 SPI2_CTRL_REG: SPI_MINT (Bitfield-Mask: 0x01)

Definition at line 10886 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_MINT_Pos

#define SPI2_SPI2_CTRL_REG_SPI_MINT_Pos   (14UL)

SPI2 SPI2_CTRL_REG: SPI_MINT (Bit 14)

Definition at line 10885 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_ON_Msk

#define SPI2_SPI2_CTRL_REG_SPI_ON_Msk   (0x1UL)

SPI2 SPI2_CTRL_REG: SPI_ON (Bitfield-Mask: 0x01)

Definition at line 10862 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_ON_Pos

#define SPI2_SPI2_CTRL_REG_SPI_ON_Pos   (0UL)

SPI2 SPI2_CTRL_REG: SPI_ON (Bit 0)

Definition at line 10861 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_PHA_Msk

#define SPI2_SPI2_CTRL_REG_SPI_PHA_Msk   (0x2UL)

SPI2 SPI2_CTRL_REG: SPI_PHA (Bitfield-Mask: 0x01)

Definition at line 10864 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_PHA_Pos

#define SPI2_SPI2_CTRL_REG_SPI_PHA_Pos   (1UL)

SPI2 SPI2_CTRL_REG: SPI_PHA (Bit 1)

Definition at line 10863 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_POL_Msk

#define SPI2_SPI2_CTRL_REG_SPI_POL_Msk   (0x4UL)

SPI2 SPI2_CTRL_REG: SPI_POL (Bitfield-Mask: 0x01)

Definition at line 10866 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_POL_Pos

#define SPI2_SPI2_CTRL_REG_SPI_POL_Pos   (2UL)

SPI2 SPI2_CTRL_REG: SPI_POL (Bit 2)

Definition at line 10865 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_RST_Msk

#define SPI2_SPI2_CTRL_REG_SPI_RST_Msk   (0x200UL)

SPI2 SPI2_CTRL_REG: SPI_RST (Bitfield-Mask: 0x01)

Definition at line 10876 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_RST_Pos

#define SPI2_SPI2_CTRL_REG_SPI_RST_Pos   (9UL)

SPI2 SPI2_CTRL_REG: SPI_RST (Bit 9)

Definition at line 10875 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_SMN_Msk

#define SPI2_SPI2_CTRL_REG_SPI_SMN_Msk   (0x40UL)

SPI2 SPI2_CTRL_REG: SPI_SMN (Bitfield-Mask: 0x01)

Definition at line 10872 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_SMN_Pos

#define SPI2_SPI2_CTRL_REG_SPI_SMN_Pos   (6UL)

SPI2 SPI2_CTRL_REG: SPI_SMN (Bit 6)

Definition at line 10871 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_TXH_Msk

#define SPI2_SPI2_CTRL_REG_SPI_TXH_Msk   (0x800UL)

SPI2 SPI2_CTRL_REG: SPI_TXH (Bitfield-Mask: 0x01)

Definition at line 10880 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_TXH_Pos

#define SPI2_SPI2_CTRL_REG_SPI_TXH_Pos   (11UL)

SPI2 SPI2_CTRL_REG: SPI_TXH (Bit 11)

Definition at line 10879 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_WORD_Msk

#define SPI2_SPI2_CTRL_REG_SPI_WORD_Msk   (0x180UL)

SPI2 SPI2_CTRL_REG: SPI_WORD (Bitfield-Mask: 0x03)

Definition at line 10874 of file DA14680BA.h.

◆ SPI2_SPI2_CTRL_REG_SPI_WORD_Pos

#define SPI2_SPI2_CTRL_REG_SPI_WORD_Pos   (7UL)

SPI2 SPI2_CTRL_REG: SPI_WORD (Bit 7)

Definition at line 10873 of file DA14680BA.h.

◆ SPI2_SPI2_RX_TX_REG0_SPI_DATA0_Msk

#define SPI2_SPI2_RX_TX_REG0_SPI_DATA0_Msk   (0xffffUL)

SPI2 SPI2_RX_TX_REG0: SPI_DATA0 (Bitfield-Mask: 0xffff)

Definition at line 10892 of file DA14680BA.h.

◆ SPI2_SPI2_RX_TX_REG0_SPI_DATA0_Pos

#define SPI2_SPI2_RX_TX_REG0_SPI_DATA0_Pos   (0UL)

SPI2 SPI2_RX_TX_REG0: SPI_DATA0 (Bit 0)

Definition at line 10891 of file DA14680BA.h.

◆ SPI2_SPI2_RX_TX_REG1_SPI_DATA1_Msk

#define SPI2_SPI2_RX_TX_REG1_SPI_DATA1_Msk   (0xffffUL)

SPI2 SPI2_RX_TX_REG1: SPI_DATA1 (Bitfield-Mask: 0xffff)

Definition at line 10896 of file DA14680BA.h.

◆ SPI2_SPI2_RX_TX_REG1_SPI_DATA1_Pos

#define SPI2_SPI2_RX_TX_REG1_SPI_DATA1_Pos   (0UL)

SPI2 SPI2_RX_TX_REG1: SPI_DATA1 (Bit 0)

Definition at line 10895 of file DA14680BA.h.

◆ SPI_BASE

#define SPI_BASE   0x50001200UL

Definition at line 12058 of file DA14680BA.h.

◆ SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Msk

#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Msk   (0xffffUL)

SPI SPI_CLEAR_INT_REG: SPI_CLEAR_INT (Bitfield-Mask: 0xffff)

Definition at line 10842 of file DA14680BA.h.

◆ SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Pos

#define SPI_SPI_CLEAR_INT_REG_SPI_CLEAR_INT_Pos   (0UL)

SPI SPI_CLEAR_INT_REG: SPI_CLEAR_INT (Bit 0)

Definition at line 10841 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG1_SPI_9BIT_VAL_Msk

#define SPI_SPI_CTRL_REG1_SPI_9BIT_VAL_Msk   (0x10UL)

SPI SPI_CTRL_REG1: SPI_9BIT_VAL (Bitfield-Mask: 0x01)

Definition at line 10852 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG1_SPI_9BIT_VAL_Pos

#define SPI_SPI_CTRL_REG1_SPI_9BIT_VAL_Pos   (4UL)

SPI SPI_CTRL_REG1: SPI_9BIT_VAL (Bit 4)

Definition at line 10851 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG1_SPI_BUSY_Msk

#define SPI_SPI_CTRL_REG1_SPI_BUSY_Msk   (0x8UL)

SPI SPI_CTRL_REG1: SPI_BUSY (Bitfield-Mask: 0x01)

Definition at line 10850 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG1_SPI_BUSY_Pos

#define SPI_SPI_CTRL_REG1_SPI_BUSY_Pos   (3UL)

SPI SPI_CTRL_REG1: SPI_BUSY (Bit 3)

Definition at line 10849 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG1_SPI_FIFO_MODE_Msk

#define SPI_SPI_CTRL_REG1_SPI_FIFO_MODE_Msk   (0x3UL)

SPI SPI_CTRL_REG1: SPI_FIFO_MODE (Bitfield-Mask: 0x03)

Definition at line 10846 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG1_SPI_FIFO_MODE_Pos

#define SPI_SPI_CTRL_REG1_SPI_FIFO_MODE_Pos   (0UL)

SPI SPI_CTRL_REG1: SPI_FIFO_MODE (Bit 0)

Definition at line 10845 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG1_SPI_PRIORITY_Msk

#define SPI_SPI_CTRL_REG1_SPI_PRIORITY_Msk   (0x4UL)

SPI SPI_CTRL_REG1: SPI_PRIORITY (Bitfield-Mask: 0x01)

Definition at line 10848 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG1_SPI_PRIORITY_Pos

#define SPI_SPI_CTRL_REG1_SPI_PRIORITY_Pos   (2UL)

SPI SPI_CTRL_REG1: SPI_PRIORITY (Bit 2)

Definition at line 10847 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_CLK_Msk

#define SPI_SPI_CTRL_REG_SPI_CLK_Msk   (0x18UL)

SPI SPI_CTRL_REG: SPI_CLK (Bitfield-Mask: 0x03)

Definition at line 10810 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_CLK_Pos

#define SPI_SPI_CTRL_REG_SPI_CLK_Pos   (3UL)

SPI SPI_CTRL_REG: SPI_CLK (Bit 3)

Definition at line 10809 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_DI_Msk

#define SPI_SPI_CTRL_REG_SPI_DI_Msk   (0x1000UL)

SPI SPI_CTRL_REG: SPI_DI (Bitfield-Mask: 0x01)

Definition at line 10824 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_DI_Pos

#define SPI_SPI_CTRL_REG_SPI_DI_Pos   (12UL)

SPI SPI_CTRL_REG: SPI_DI (Bit 12)

Definition at line 10823 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_DO_Msk

#define SPI_SPI_CTRL_REG_SPI_DO_Msk   (0x20UL)

SPI SPI_CTRL_REG: SPI_DO (Bitfield-Mask: 0x01)

Definition at line 10812 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_DO_Pos

#define SPI_SPI_CTRL_REG_SPI_DO_Pos   (5UL)

SPI SPI_CTRL_REG: SPI_DO (Bit 5)

Definition at line 10811 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_EN_CTRL_Msk

#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Msk   (0x8000UL)

SPI SPI_CTRL_REG: SPI_EN_CTRL (Bitfield-Mask: 0x01)

Definition at line 10830 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_EN_CTRL_Pos

#define SPI_SPI_CTRL_REG_SPI_EN_CTRL_Pos   (15UL)

SPI SPI_CTRL_REG: SPI_EN_CTRL (Bit 15)

Definition at line 10829 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_FORCE_DO_Msk

#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Msk   (0x400UL)

SPI SPI_CTRL_REG: SPI_FORCE_DO (Bitfield-Mask: 0x01)

Definition at line 10820 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_FORCE_DO_Pos

#define SPI_SPI_CTRL_REG_SPI_FORCE_DO_Pos   (10UL)

SPI SPI_CTRL_REG: SPI_FORCE_DO (Bit 10)

Definition at line 10819 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_INT_BIT_Msk

#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Msk   (0x2000UL)

SPI SPI_CTRL_REG: SPI_INT_BIT (Bitfield-Mask: 0x01)

Definition at line 10826 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_INT_BIT_Pos

#define SPI_SPI_CTRL_REG_SPI_INT_BIT_Pos   (13UL)

SPI SPI_CTRL_REG: SPI_INT_BIT (Bit 13)

Definition at line 10825 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_MINT_Msk

#define SPI_SPI_CTRL_REG_SPI_MINT_Msk   (0x4000UL)

SPI SPI_CTRL_REG: SPI_MINT (Bitfield-Mask: 0x01)

Definition at line 10828 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_MINT_Pos

#define SPI_SPI_CTRL_REG_SPI_MINT_Pos   (14UL)

SPI SPI_CTRL_REG: SPI_MINT (Bit 14)

Definition at line 10827 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_ON_Msk

#define SPI_SPI_CTRL_REG_SPI_ON_Msk   (0x1UL)

SPI SPI_CTRL_REG: SPI_ON (Bitfield-Mask: 0x01)

Definition at line 10804 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_ON_Pos

#define SPI_SPI_CTRL_REG_SPI_ON_Pos   (0UL)

SPI SPI_CTRL_REG: SPI_ON (Bit 0)

Definition at line 10803 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_PHA_Msk

#define SPI_SPI_CTRL_REG_SPI_PHA_Msk   (0x2UL)

SPI SPI_CTRL_REG: SPI_PHA (Bitfield-Mask: 0x01)

Definition at line 10806 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_PHA_Pos

#define SPI_SPI_CTRL_REG_SPI_PHA_Pos   (1UL)

SPI SPI_CTRL_REG: SPI_PHA (Bit 1)

Definition at line 10805 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_POL_Msk

#define SPI_SPI_CTRL_REG_SPI_POL_Msk   (0x4UL)

SPI SPI_CTRL_REG: SPI_POL (Bitfield-Mask: 0x01)

Definition at line 10808 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_POL_Pos

#define SPI_SPI_CTRL_REG_SPI_POL_Pos   (2UL)

SPI SPI_CTRL_REG: SPI_POL (Bit 2)

Definition at line 10807 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_RST_Msk

#define SPI_SPI_CTRL_REG_SPI_RST_Msk   (0x200UL)

SPI SPI_CTRL_REG: SPI_RST (Bitfield-Mask: 0x01)

Definition at line 10818 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_RST_Pos

#define SPI_SPI_CTRL_REG_SPI_RST_Pos   (9UL)

SPI SPI_CTRL_REG: SPI_RST (Bit 9)

Definition at line 10817 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_SMN_Msk

#define SPI_SPI_CTRL_REG_SPI_SMN_Msk   (0x40UL)

SPI SPI_CTRL_REG: SPI_SMN (Bitfield-Mask: 0x01)

Definition at line 10814 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_SMN_Pos

#define SPI_SPI_CTRL_REG_SPI_SMN_Pos   (6UL)

SPI SPI_CTRL_REG: SPI_SMN (Bit 6)

Definition at line 10813 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_TXH_Msk

#define SPI_SPI_CTRL_REG_SPI_TXH_Msk   (0x800UL)

SPI SPI_CTRL_REG: SPI_TXH (Bitfield-Mask: 0x01)

Definition at line 10822 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_TXH_Pos

#define SPI_SPI_CTRL_REG_SPI_TXH_Pos   (11UL)

SPI SPI_CTRL_REG: SPI_TXH (Bit 11)

Definition at line 10821 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_WORD_Msk

#define SPI_SPI_CTRL_REG_SPI_WORD_Msk   (0x180UL)

SPI SPI_CTRL_REG: SPI_WORD (Bitfield-Mask: 0x03)

Definition at line 10816 of file DA14680BA.h.

◆ SPI_SPI_CTRL_REG_SPI_WORD_Pos

#define SPI_SPI_CTRL_REG_SPI_WORD_Pos   (7UL)

SPI SPI_CTRL_REG: SPI_WORD (Bit 7)

Definition at line 10815 of file DA14680BA.h.

◆ SPI_SPI_RX_TX_REG0_SPI_DATA0_Msk

#define SPI_SPI_RX_TX_REG0_SPI_DATA0_Msk   (0xffffUL)

SPI SPI_RX_TX_REG0: SPI_DATA0 (Bitfield-Mask: 0xffff)

Definition at line 10834 of file DA14680BA.h.

◆ SPI_SPI_RX_TX_REG0_SPI_DATA0_Pos

#define SPI_SPI_RX_TX_REG0_SPI_DATA0_Pos   (0UL)

SPI SPI_RX_TX_REG0: SPI_DATA0 (Bit 0)

Definition at line 10833 of file DA14680BA.h.

◆ SPI_SPI_RX_TX_REG1_SPI_DATA1_Msk

#define SPI_SPI_RX_TX_REG1_SPI_DATA1_Msk   (0xffffUL)

SPI SPI_RX_TX_REG1: SPI_DATA1 (Bitfield-Mask: 0xffff)

Definition at line 10838 of file DA14680BA.h.

◆ SPI_SPI_RX_TX_REG1_SPI_DATA1_Pos

#define SPI_SPI_RX_TX_REG1_SPI_DATA1_Pos   (0UL)

SPI SPI_RX_TX_REG1: SPI_DATA1 (Bit 0)

Definition at line 10837 of file DA14680BA.h.

◆ TIMER1

#define TIMER1   ((TIMER1_Type *) TIMER1_BASE)

Definition at line 12105 of file DA14680BA.h.

◆ TIMER1_BASE

#define TIMER1_BASE   0x50000200UL

Definition at line 12060 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CAPTURE_GPIO1_REG_CAPTIM_CAPTURE_GPIO1_Msk

#define TIMER1_CAPTIM_CAPTURE_GPIO1_REG_CAPTIM_CAPTURE_GPIO1_Msk   (0xffffUL)

TIMER1 CAPTIM_CAPTURE_GPIO1_REG: CAPTIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffff)

Definition at line 10970 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CAPTURE_GPIO1_REG_CAPTIM_CAPTURE_GPIO1_Pos

#define TIMER1_CAPTIM_CAPTURE_GPIO1_REG_CAPTIM_CAPTURE_GPIO1_Pos   (0UL)

TIMER1 CAPTIM_CAPTURE_GPIO1_REG: CAPTIM_CAPTURE_GPIO1 (Bit 0)

Definition at line 10969 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CAPTURE_GPIO2_REG_CAPTIM_CAPTURE_GPIO2_Msk

#define TIMER1_CAPTIM_CAPTURE_GPIO2_REG_CAPTIM_CAPTURE_GPIO2_Msk   (0xffffUL)

TIMER1 CAPTIM_CAPTURE_GPIO2_REG: CAPTIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffff)

Definition at line 10974 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CAPTURE_GPIO2_REG_CAPTIM_CAPTURE_GPIO2_Pos

#define TIMER1_CAPTIM_CAPTURE_GPIO2_REG_CAPTIM_CAPTURE_GPIO2_Pos   (0UL)

TIMER1 CAPTIM_CAPTURE_GPIO2_REG: CAPTIM_CAPTURE_GPIO2 (Bit 0)

Definition at line 10973 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG_CAPTIM_CAPTURE_HIGH_GPIO1_Msk

#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG_CAPTIM_CAPTURE_HIGH_GPIO1_Msk   (0xffffUL)

TIMER1 CAPTIM_CAPTURE_HIGH_GPIO1_REG: CAPTIM_CAPTURE_HIGH_GPIO1 (Bitfield-Mask: 0xffff)

Definition at line 10998 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG_CAPTIM_CAPTURE_HIGH_GPIO1_Pos

#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO1_REG_CAPTIM_CAPTURE_HIGH_GPIO1_Pos   (0UL)

TIMER1 CAPTIM_CAPTURE_HIGH_GPIO1_REG: CAPTIM_CAPTURE_HIGH_GPIO1 (Bit 0)

Definition at line 10997 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG_CAPTIM_CAPTURE_HIGH_GPIO2_Msk

#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG_CAPTIM_CAPTURE_HIGH_GPIO2_Msk   (0xffffUL)

TIMER1 CAPTIM_CAPTURE_HIGH_GPIO2_REG: CAPTIM_CAPTURE_HIGH_GPIO2 (Bitfield-Mask: 0xffff)

Definition at line 11002 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG_CAPTIM_CAPTURE_HIGH_GPIO2_Pos

#define TIMER1_CAPTIM_CAPTURE_HIGH_GPIO2_REG_CAPTIM_CAPTURE_HIGH_GPIO2_Pos   (0UL)

TIMER1 CAPTIM_CAPTURE_HIGH_GPIO2_REG: CAPTIM_CAPTURE_HIGH_GPIO2 (Bit 0)

Definition at line 11001 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_COUNT_DOWN_EN_Msk

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_COUNT_DOWN_EN_Msk   (0x4UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01)

Definition at line 10924 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_COUNT_DOWN_EN_Pos

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_COUNT_DOWN_EN_Pos   (2UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_COUNT_DOWN_EN (Bit 2)

Definition at line 10923 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_EN_Msk

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_EN_Msk   (0x1UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_EN (Bitfield-Mask: 0x01)

Definition at line 10920 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_EN_Pos

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_EN_Pos   (0UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_EN (Bit 0)

Definition at line 10919 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_FREE_RUN_MODE_EN_Msk

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_FREE_RUN_MODE_EN_Msk   (0x40UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01)

Definition at line 10932 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_FREE_RUN_MODE_EN_Pos

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_FREE_RUN_MODE_EN_Pos   (6UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_FREE_RUN_MODE_EN (Bit 6)

Definition at line 10931 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN1_EVENT_FALL_EN_Msk

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN1_EVENT_FALL_EN_Msk   (0x8UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01)

Definition at line 10926 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN1_EVENT_FALL_EN_Pos

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN1_EVENT_FALL_EN_Pos   (3UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_IN1_EVENT_FALL_EN (Bit 3)

Definition at line 10925 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN2_EVENT_FALL_EN_Msk

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN2_EVENT_FALL_EN_Msk   (0x10UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01)

Definition at line 10928 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN2_EVENT_FALL_EN_Pos

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IN2_EVENT_FALL_EN_Pos   (4UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_IN2_EVENT_FALL_EN (Bit 4)

Definition at line 10927 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Msk

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Msk   (0x20UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_IRQ_EN (Bitfield-Mask: 0x01)

Definition at line 10930 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Pos

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_IRQ_EN_Pos   (5UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_IRQ_EN (Bit 5)

Definition at line 10929 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_ONESHOT_MODE_EN_Msk

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_ONESHOT_MODE_EN_Msk   (0x2UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01)

Definition at line 10922 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_ONESHOT_MODE_EN_Pos

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_ONESHOT_MODE_EN_Pos   (1UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_ONESHOT_MODE_EN (Bit 1)

Definition at line 10921 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_SYS_CLK_EN_Msk

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_SYS_CLK_EN_Msk   (0x80UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_SYS_CLK_EN (Bitfield-Mask: 0x01)

Definition at line 10934 of file DA14680BA.h.

◆ TIMER1_CAPTIM_CTRL_REG_CAPTIM_SYS_CLK_EN_Pos

#define TIMER1_CAPTIM_CTRL_REG_CAPTIM_SYS_CLK_EN_Pos   (7UL)

TIMER1 CAPTIM_CTRL_REG: CAPTIM_SYS_CLK_EN (Bit 7)

Definition at line 10933 of file DA14680BA.h.

◆ TIMER1_CAPTIM_GPIO1_CONF_REG_CAPTIM_GPIO1_CONF_Msk

#define TIMER1_CAPTIM_GPIO1_CONF_REG_CAPTIM_GPIO1_CONF_Msk   (0x3fUL)

TIMER1 CAPTIM_GPIO1_CONF_REG: CAPTIM_GPIO1_CONF (Bitfield-Mask: 0x3f)

Definition at line 10950 of file DA14680BA.h.

◆ TIMER1_CAPTIM_GPIO1_CONF_REG_CAPTIM_GPIO1_CONF_Pos

#define TIMER1_CAPTIM_GPIO1_CONF_REG_CAPTIM_GPIO1_CONF_Pos   (0UL)

TIMER1 CAPTIM_GPIO1_CONF_REG: CAPTIM_GPIO1_CONF (Bit 0)

Definition at line 10949 of file DA14680BA.h.

◆ TIMER1_CAPTIM_GPIO2_CONF_REG_CAPTIM_GPIO2_CONF_Msk

#define TIMER1_CAPTIM_GPIO2_CONF_REG_CAPTIM_GPIO2_CONF_Msk   (0x3fUL)

TIMER1 CAPTIM_GPIO2_CONF_REG: CAPTIM_GPIO2_CONF (Bitfield-Mask: 0x3f)

Definition at line 10954 of file DA14680BA.h.

◆ TIMER1_CAPTIM_GPIO2_CONF_REG_CAPTIM_GPIO2_CONF_Pos

#define TIMER1_CAPTIM_GPIO2_CONF_REG_CAPTIM_GPIO2_CONF_Pos   (0UL)

TIMER1 CAPTIM_GPIO2_CONF_REG: CAPTIM_GPIO2_CONF (Bit 0)

Definition at line 10953 of file DA14680BA.h.

◆ TIMER1_CAPTIM_PRESCALER_REG_CAPTIM_PRESCALER_Msk

#define TIMER1_CAPTIM_PRESCALER_REG_CAPTIM_PRESCALER_Msk   (0xffffUL)

TIMER1 CAPTIM_PRESCALER_REG: CAPTIM_PRESCALER (Bitfield-Mask: 0xffff)

Definition at line 10966 of file DA14680BA.h.

◆ TIMER1_CAPTIM_PRESCALER_REG_CAPTIM_PRESCALER_Pos

#define TIMER1_CAPTIM_PRESCALER_REG_CAPTIM_PRESCALER_Pos   (0UL)

TIMER1 CAPTIM_PRESCALER_REG: CAPTIM_PRESCALER (Bit 0)

Definition at line 10965 of file DA14680BA.h.

◆ TIMER1_CAPTIM_PRESCALER_VAL_REG_CAPTIM_PRESCALER_VAL_Msk

#define TIMER1_CAPTIM_PRESCALER_VAL_REG_CAPTIM_PRESCALER_VAL_Msk   (0xffffUL)

TIMER1 CAPTIM_PRESCALER_VAL_REG: CAPTIM_PRESCALER_VAL (Bitfield-Mask: 0xffff)

Definition at line 10978 of file DA14680BA.h.

◆ TIMER1_CAPTIM_PRESCALER_VAL_REG_CAPTIM_PRESCALER_VAL_Pos

#define TIMER1_CAPTIM_PRESCALER_VAL_REG_CAPTIM_PRESCALER_VAL_Pos   (0UL)

TIMER1 CAPTIM_PRESCALER_VAL_REG: CAPTIM_PRESCALER_VAL (Bit 0)

Definition at line 10977 of file DA14680BA.h.

◆ TIMER1_CAPTIM_PWM_DC_REG_CAPTIM_PWM_DC_Msk

#define TIMER1_CAPTIM_PWM_DC_REG_CAPTIM_PWM_DC_Msk   (0xffffUL)

TIMER1 CAPTIM_PWM_DC_REG: CAPTIM_PWM_DC (Bitfield-Mask: 0xffff)

Definition at line 10986 of file DA14680BA.h.

◆ TIMER1_CAPTIM_PWM_DC_REG_CAPTIM_PWM_DC_Pos

#define TIMER1_CAPTIM_PWM_DC_REG_CAPTIM_PWM_DC_Pos   (0UL)

TIMER1 CAPTIM_PWM_DC_REG: CAPTIM_PWM_DC (Bit 0)

Definition at line 10985 of file DA14680BA.h.

◆ TIMER1_CAPTIM_PWM_FREQ_REG_CAPTIM_PWM_FREQ_Msk

#define TIMER1_CAPTIM_PWM_FREQ_REG_CAPTIM_PWM_FREQ_Msk   (0xffffUL)

TIMER1 CAPTIM_PWM_FREQ_REG: CAPTIM_PWM_FREQ (Bitfield-Mask: 0xffff)

Definition at line 10982 of file DA14680BA.h.

◆ TIMER1_CAPTIM_PWM_FREQ_REG_CAPTIM_PWM_FREQ_Pos

#define TIMER1_CAPTIM_PWM_FREQ_REG_CAPTIM_PWM_FREQ_Pos   (0UL)

TIMER1 CAPTIM_PWM_FREQ_REG: CAPTIM_PWM_FREQ (Bit 0)

Definition at line 10981 of file DA14680BA.h.

◆ TIMER1_CAPTIM_RELOAD_HIGH_REG_CAPTIM_RELOAD_HIGH_Msk

#define TIMER1_CAPTIM_RELOAD_HIGH_REG_CAPTIM_RELOAD_HIGH_Msk   (0xffffUL)

TIMER1 CAPTIM_RELOAD_HIGH_REG: CAPTIM_RELOAD_HIGH (Bitfield-Mask: 0xffff)

Definition at line 10994 of file DA14680BA.h.

◆ TIMER1_CAPTIM_RELOAD_HIGH_REG_CAPTIM_RELOAD_HIGH_Pos

#define TIMER1_CAPTIM_RELOAD_HIGH_REG_CAPTIM_RELOAD_HIGH_Pos   (0UL)

TIMER1 CAPTIM_RELOAD_HIGH_REG: CAPTIM_RELOAD_HIGH (Bit 0)

Definition at line 10993 of file DA14680BA.h.

◆ TIMER1_CAPTIM_RELOAD_REG_CAPTIM_RELOAD_Msk

#define TIMER1_CAPTIM_RELOAD_REG_CAPTIM_RELOAD_Msk   (0xffffUL)

TIMER1 CAPTIM_RELOAD_REG: CAPTIM_RELOAD (Bitfield-Mask: 0xffff)

Definition at line 10958 of file DA14680BA.h.

◆ TIMER1_CAPTIM_RELOAD_REG_CAPTIM_RELOAD_Pos

#define TIMER1_CAPTIM_RELOAD_REG_CAPTIM_RELOAD_Pos   (0UL)

TIMER1 CAPTIM_RELOAD_REG: CAPTIM_RELOAD (Bit 0)

Definition at line 10957 of file DA14680BA.h.

◆ TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG_CAPTIM_SHOTWIDTH_HIGH_Msk

#define TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG_CAPTIM_SHOTWIDTH_HIGH_Msk   (0xffffUL)

TIMER1 CAPTIM_SHOTWIDTH_HIGH_REG: CAPTIM_SHOTWIDTH_HIGH (Bitfield-Mask: 0xffff)

Definition at line 11006 of file DA14680BA.h.

◆ TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG_CAPTIM_SHOTWIDTH_HIGH_Pos

#define TIMER1_CAPTIM_SHOTWIDTH_HIGH_REG_CAPTIM_SHOTWIDTH_HIGH_Pos   (0UL)

TIMER1 CAPTIM_SHOTWIDTH_HIGH_REG: CAPTIM_SHOTWIDTH_HIGH (Bit 0)

Definition at line 11005 of file DA14680BA.h.

◆ TIMER1_CAPTIM_SHOTWIDTH_REG_CAPTIM_SHOTWIDTH_Msk

#define TIMER1_CAPTIM_SHOTWIDTH_REG_CAPTIM_SHOTWIDTH_Msk   (0xffffUL)

TIMER1 CAPTIM_SHOTWIDTH_REG: CAPTIM_SHOTWIDTH (Bitfield-Mask: 0xffff)

Definition at line 10962 of file DA14680BA.h.

◆ TIMER1_CAPTIM_SHOTWIDTH_REG_CAPTIM_SHOTWIDTH_Pos

#define TIMER1_CAPTIM_SHOTWIDTH_REG_CAPTIM_SHOTWIDTH_Pos   (0UL)

TIMER1 CAPTIM_SHOTWIDTH_REG: CAPTIM_SHOTWIDTH (Bit 0)

Definition at line 10961 of file DA14680BA.h.

◆ TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN1_STATE_Msk

#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN1_STATE_Msk   (0x1UL)

TIMER1 CAPTIM_STATUS_REG: CAPTIM_IN1_STATE (Bitfield-Mask: 0x01)

Definition at line 10942 of file DA14680BA.h.

◆ TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN1_STATE_Pos

#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN1_STATE_Pos   (0UL)

TIMER1 CAPTIM_STATUS_REG: CAPTIM_IN1_STATE (Bit 0)

Definition at line 10941 of file DA14680BA.h.

◆ TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN2_STATE_Msk

#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN2_STATE_Msk   (0x2UL)

TIMER1 CAPTIM_STATUS_REG: CAPTIM_IN2_STATE (Bitfield-Mask: 0x01)

Definition at line 10944 of file DA14680BA.h.

◆ TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN2_STATE_Pos

#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_IN2_STATE_Pos   (1UL)

TIMER1 CAPTIM_STATUS_REG: CAPTIM_IN2_STATE (Bit 1)

Definition at line 10943 of file DA14680BA.h.

◆ TIMER1_CAPTIM_STATUS_REG_CAPTIM_ONESHOT_PHASE_Msk

#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_ONESHOT_PHASE_Msk   (0xcUL)

TIMER1 CAPTIM_STATUS_REG: CAPTIM_ONESHOT_PHASE (Bitfield-Mask: 0x03)

Definition at line 10946 of file DA14680BA.h.

◆ TIMER1_CAPTIM_STATUS_REG_CAPTIM_ONESHOT_PHASE_Pos

#define TIMER1_CAPTIM_STATUS_REG_CAPTIM_ONESHOT_PHASE_Pos   (2UL)

TIMER1 CAPTIM_STATUS_REG: CAPTIM_ONESHOT_PHASE (Bit 2)

Definition at line 10945 of file DA14680BA.h.

◆ TIMER1_CAPTIM_TIMER_HVAL_REG_CAPTIM_TIMER_HVALUE_Msk

#define TIMER1_CAPTIM_TIMER_HVAL_REG_CAPTIM_TIMER_HVALUE_Msk   (0xffffUL)

TIMER1 CAPTIM_TIMER_HVAL_REG: CAPTIM_TIMER_HVALUE (Bitfield-Mask: 0xffff)

Definition at line 10990 of file DA14680BA.h.

◆ TIMER1_CAPTIM_TIMER_HVAL_REG_CAPTIM_TIMER_HVALUE_Pos

#define TIMER1_CAPTIM_TIMER_HVAL_REG_CAPTIM_TIMER_HVALUE_Pos   (0UL)

TIMER1 CAPTIM_TIMER_HVAL_REG: CAPTIM_TIMER_HVALUE (Bit 0)

Definition at line 10989 of file DA14680BA.h.

◆ TIMER1_CAPTIM_TIMER_VAL_REG_CAPTIM_TIMER_VALUE_Msk

#define TIMER1_CAPTIM_TIMER_VAL_REG_CAPTIM_TIMER_VALUE_Msk   (0xffffUL)

TIMER1 CAPTIM_TIMER_VAL_REG: CAPTIM_TIMER_VALUE (Bitfield-Mask: 0xffff)

Definition at line 10938 of file DA14680BA.h.

◆ TIMER1_CAPTIM_TIMER_VAL_REG_CAPTIM_TIMER_VALUE_Pos

#define TIMER1_CAPTIM_TIMER_VAL_REG_CAPTIM_TIMER_VALUE_Pos   (0UL)

TIMER1 CAPTIM_TIMER_VAL_REG: CAPTIM_TIMER_VALUE (Bit 0)

Definition at line 10937 of file DA14680BA.h.

◆ TRNG

#define TRNG   ((TRNG_Type *) TRNG_BASE)

Definition at line 12106 of file DA14680BA.h.

◆ TRNG_BASE

#define TRNG_BASE   0x50005000UL

Definition at line 12061 of file DA14680BA.h.

◆ TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Msk

#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Msk   (0x1UL)

TRNG TRNG_CTRL_REG: TRNG_ENABLE (Bitfield-Mask: 0x01)

Definition at line 11016 of file DA14680BA.h.

◆ TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Pos

#define TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Pos   (0UL)

TRNG TRNG_CTRL_REG: TRNG_ENABLE (Bit 0)

Definition at line 11015 of file DA14680BA.h.

◆ TRNG_TRNG_CTRL_REG_TRNG_MODE_Msk

#define TRNG_TRNG_CTRL_REG_TRNG_MODE_Msk   (0x2UL)

TRNG TRNG_CTRL_REG: TRNG_MODE (Bitfield-Mask: 0x01)

Definition at line 11018 of file DA14680BA.h.

◆ TRNG_TRNG_CTRL_REG_TRNG_MODE_Pos

#define TRNG_TRNG_CTRL_REG_TRNG_MODE_Pos   (1UL)

TRNG TRNG_CTRL_REG: TRNG_MODE (Bit 1)

Definition at line 11017 of file DA14680BA.h.

◆ TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Msk

#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Msk   (0x20UL)

TRNG TRNG_FIFOLVL_REG: TRNG_FIFOFULL (Bitfield-Mask: 0x01)

Definition at line 11024 of file DA14680BA.h.

◆ TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Pos

#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOFULL_Pos   (5UL)

TRNG TRNG_FIFOLVL_REG: TRNG_FIFOFULL (Bit 5)

Definition at line 11023 of file DA14680BA.h.

◆ TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Msk

#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Msk   (0x1fUL)

TRNG TRNG_FIFOLVL_REG: TRNG_FIFOLVL (Bitfield-Mask: 0x1f)

Definition at line 11022 of file DA14680BA.h.

◆ TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Pos

#define TRNG_TRNG_FIFOLVL_REG_TRNG_FIFOLVL_Pos   (0UL)

TRNG TRNG_FIFOLVL_REG: TRNG_FIFOLVL (Bit 0)

Definition at line 11021 of file DA14680BA.h.

◆ TRNG_TRNG_VER_REG_TRNG_MAJ_Msk

#define TRNG_TRNG_VER_REG_TRNG_MAJ_Msk   (0xff000000UL)

TRNG TRNG_VER_REG: TRNG_MAJ (Bitfield-Mask: 0xff)

Definition at line 11032 of file DA14680BA.h.

◆ TRNG_TRNG_VER_REG_TRNG_MAJ_Pos

#define TRNG_TRNG_VER_REG_TRNG_MAJ_Pos   (24UL)

TRNG TRNG_VER_REG: TRNG_MAJ (Bit 24)

Definition at line 11031 of file DA14680BA.h.

◆ TRNG_TRNG_VER_REG_TRNG_MIN_Msk

#define TRNG_TRNG_VER_REG_TRNG_MIN_Msk   (0xff0000UL)

TRNG TRNG_VER_REG: TRNG_MIN (Bitfield-Mask: 0xff)

Definition at line 11030 of file DA14680BA.h.

◆ TRNG_TRNG_VER_REG_TRNG_MIN_Pos

#define TRNG_TRNG_VER_REG_TRNG_MIN_Pos   (16UL)

TRNG TRNG_VER_REG: TRNG_MIN (Bit 16)

Definition at line 11029 of file DA14680BA.h.

◆ TRNG_TRNG_VER_REG_TRNG_SVN_Msk

#define TRNG_TRNG_VER_REG_TRNG_SVN_Msk   (0xffffUL)

TRNG TRNG_VER_REG: TRNG_SVN (Bitfield-Mask: 0xffff)

Definition at line 11028 of file DA14680BA.h.

◆ TRNG_TRNG_VER_REG_TRNG_SVN_Pos

#define TRNG_TRNG_VER_REG_TRNG_SVN_Pos   (0UL)

TRNG TRNG_VER_REG: TRNG_SVN (Bit 0)

Definition at line 11027 of file DA14680BA.h.

◆ UART

#define UART   ((UART_Type *) UART_BASE)

Definition at line 12107 of file DA14680BA.h.

◆ UART2

#define UART2   ((UART2_Type *) UART2_BASE)

Definition at line 12108 of file DA14680BA.h.

◆ UART2_BASE

#define UART2_BASE   0x50001100UL

Definition at line 12063 of file DA14680BA.h.

◆ UART2_UART2_CPR_REG_CPR_Msk

#define UART2_UART2_CPR_REG_CPR_Msk   (0xffffUL)

UART2 UART2_CPR_REG: CPR (Bitfield-Mask: 0xffff)

Definition at line 11348 of file DA14680BA.h.

◆ UART2_UART2_CPR_REG_CPR_Pos

#define UART2_UART2_CPR_REG_CPR_Pos   (0UL)

UART2 UART2_CPR_REG: CPR (Bit 0)

Definition at line 11347 of file DA14680BA.h.

◆ UART2_UART2_CTR_REG_CTR_Msk

#define UART2_UART2_CTR_REG_CTR_Msk   (0xffffUL)

UART2 UART2_CTR_REG: CTR (Bitfield-Mask: 0xffff)

Definition at line 11356 of file DA14680BA.h.

◆ UART2_UART2_CTR_REG_CTR_Pos

#define UART2_UART2_CTR_REG_CTR_Pos   (0UL)

UART2 UART2_CTR_REG: CTR (Bit 0)

Definition at line 11355 of file DA14680BA.h.

◆ UART2_UART2_DLF_REG_UART_DLF_Msk

#define UART2_UART2_DLF_REG_UART_DLF_Msk   (0xfUL)

UART2 UART2_DLF_REG: UART_DLF (Bitfield-Mask: 0x0f)

Definition at line 11344 of file DA14680BA.h.

◆ UART2_UART2_DLF_REG_UART_DLF_Pos

#define UART2_UART2_DLF_REG_UART_DLF_Pos   (0UL)

UART2 UART2_DLF_REG: UART_DLF (Bit 0)

Definition at line 11343 of file DA14680BA.h.

◆ UART2_UART2_DMASA_REG_DMASA_Msk

#define UART2_UART2_DMASA_REG_DMASA_Msk   (0x1UL)

UART2 UART2_DMASA_REG: DMASA (Bitfield-Mask: 0x01)

Definition at line 11340 of file DA14680BA.h.

◆ UART2_UART2_DMASA_REG_DMASA_Pos

#define UART2_UART2_DMASA_REG_DMASA_Pos   (0UL)

UART2 UART2_DMASA_REG: DMASA (Bit 0)

Definition at line 11339 of file DA14680BA.h.

◆ UART2_UART2_FAR_REG_UART_FAR_Msk

#define UART2_UART2_FAR_REG_UART_FAR_Msk   (0x1UL)

UART2 UART2_FAR_REG: UART_FAR (Bitfield-Mask: 0x01)

Definition at line 11280 of file DA14680BA.h.

◆ UART2_UART2_FAR_REG_UART_FAR_Pos

#define UART2_UART2_FAR_REG_UART_FAR_Pos   (0UL)

UART2 UART2_FAR_REG: UART_FAR (Bit 0)

Definition at line 11279 of file DA14680BA.h.

◆ UART2_UART2_HTX_REG_UART_HALT_TX_Msk

#define UART2_UART2_HTX_REG_UART_HALT_TX_Msk   (0x1UL)

UART2 UART2_HTX_REG: UART_HALT_TX (Bitfield-Mask: 0x01)

Definition at line 11336 of file DA14680BA.h.

◆ UART2_UART2_HTX_REG_UART_HALT_TX_Pos

#define UART2_UART2_HTX_REG_UART_HALT_TX_Pos   (0UL)

UART2 UART2_HTX_REG: UART_HALT_TX (Bit 0)

Definition at line 11335 of file DA14680BA.h.

◆ UART2_UART2_IER_DLH_REG_ELSI_dhl2_Msk

#define UART2_UART2_IER_DLH_REG_ELSI_dhl2_Msk   (0x4UL)

UART2 UART2_IER_DLH_REG: ELSI_dhl2 (Bitfield-Mask: 0x01)

Definition at line 11150 of file DA14680BA.h.

◆ UART2_UART2_IER_DLH_REG_ELSI_dhl2_Pos

#define UART2_UART2_IER_DLH_REG_ELSI_dhl2_Pos   (2UL)

UART2 UART2_IER_DLH_REG: ELSI_dhl2 (Bit 2)

Definition at line 11149 of file DA14680BA.h.

◆ UART2_UART2_IER_DLH_REG_ERBFI_dlh0_Msk

#define UART2_UART2_IER_DLH_REG_ERBFI_dlh0_Msk   (0x1UL)

UART2 UART2_IER_DLH_REG: ERBFI_dlh0 (Bitfield-Mask: 0x01)

Definition at line 11146 of file DA14680BA.h.

◆ UART2_UART2_IER_DLH_REG_ERBFI_dlh0_Pos

#define UART2_UART2_IER_DLH_REG_ERBFI_dlh0_Pos   (0UL)

UART2 UART2_IER_DLH_REG: ERBFI_dlh0 (Bit 0)

Definition at line 11145 of file DA14680BA.h.

◆ UART2_UART2_IER_DLH_REG_ETBEI_dlh1_Msk

#define UART2_UART2_IER_DLH_REG_ETBEI_dlh1_Msk   (0x2UL)

UART2 UART2_IER_DLH_REG: ETBEI_dlh1 (Bitfield-Mask: 0x01)

Definition at line 11148 of file DA14680BA.h.

◆ UART2_UART2_IER_DLH_REG_ETBEI_dlh1_Pos

#define UART2_UART2_IER_DLH_REG_ETBEI_dlh1_Pos   (1UL)

UART2 UART2_IER_DLH_REG: ETBEI_dlh1 (Bit 1)

Definition at line 11147 of file DA14680BA.h.

◆ UART2_UART2_IER_DLH_REG_PTIME_dlh7_Msk

#define UART2_UART2_IER_DLH_REG_PTIME_dlh7_Msk   (0x80UL)

UART2 UART2_IER_DLH_REG: PTIME_dlh7 (Bitfield-Mask: 0x01)

Definition at line 11152 of file DA14680BA.h.

◆ UART2_UART2_IER_DLH_REG_PTIME_dlh7_Pos

#define UART2_UART2_IER_DLH_REG_PTIME_dlh7_Pos   (7UL)

UART2 UART2_IER_DLH_REG: PTIME_dlh7 (Bit 7)

Definition at line 11151 of file DA14680BA.h.

◆ UART2_UART2_IIR_FCR_REG_IIR_FCR_Msk

#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Msk   (0xffffUL)

UART2 UART2_IIR_FCR_REG: IIR_FCR (Bitfield-Mask: 0xffff)

Definition at line 11156 of file DA14680BA.h.

◆ UART2_UART2_IIR_FCR_REG_IIR_FCR_Pos

#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Pos   (0UL)

UART2 UART2_IIR_FCR_REG: IIR_FCR (Bit 0)

Definition at line 11155 of file DA14680BA.h.

◆ UART2_UART2_LCR_REG_UART_BC_Msk

#define UART2_UART2_LCR_REG_UART_BC_Msk   (0x40UL)

UART2 UART2_LCR_REG: UART_BC (Bitfield-Mask: 0x01)

Definition at line 11168 of file DA14680BA.h.

◆ UART2_UART2_LCR_REG_UART_BC_Pos

#define UART2_UART2_LCR_REG_UART_BC_Pos   (6UL)

UART2 UART2_LCR_REG: UART_BC (Bit 6)

Definition at line 11167 of file DA14680BA.h.

◆ UART2_UART2_LCR_REG_UART_DLAB_Msk

#define UART2_UART2_LCR_REG_UART_DLAB_Msk   (0x80UL)

UART2 UART2_LCR_REG: UART_DLAB (Bitfield-Mask: 0x01)

Definition at line 11170 of file DA14680BA.h.

◆ UART2_UART2_LCR_REG_UART_DLAB_Pos

#define UART2_UART2_LCR_REG_UART_DLAB_Pos   (7UL)

UART2 UART2_LCR_REG: UART_DLAB (Bit 7)

Definition at line 11169 of file DA14680BA.h.

◆ UART2_UART2_LCR_REG_UART_DLS_Msk

#define UART2_UART2_LCR_REG_UART_DLS_Msk   (0x3UL)

UART2 UART2_LCR_REG: UART_DLS (Bitfield-Mask: 0x03)

Definition at line 11160 of file DA14680BA.h.

◆ UART2_UART2_LCR_REG_UART_DLS_Pos

#define UART2_UART2_LCR_REG_UART_DLS_Pos   (0UL)

UART2 UART2_LCR_REG: UART_DLS (Bit 0)

Definition at line 11159 of file DA14680BA.h.

◆ UART2_UART2_LCR_REG_UART_EPS_Msk

#define UART2_UART2_LCR_REG_UART_EPS_Msk   (0x10UL)

UART2 UART2_LCR_REG: UART_EPS (Bitfield-Mask: 0x01)

Definition at line 11166 of file DA14680BA.h.

◆ UART2_UART2_LCR_REG_UART_EPS_Pos

#define UART2_UART2_LCR_REG_UART_EPS_Pos   (4UL)

UART2 UART2_LCR_REG: UART_EPS (Bit 4)

Definition at line 11165 of file DA14680BA.h.

◆ UART2_UART2_LCR_REG_UART_PEN_Msk

#define UART2_UART2_LCR_REG_UART_PEN_Msk   (0x8UL)

UART2 UART2_LCR_REG: UART_PEN (Bitfield-Mask: 0x01)

Definition at line 11164 of file DA14680BA.h.

◆ UART2_UART2_LCR_REG_UART_PEN_Pos

#define UART2_UART2_LCR_REG_UART_PEN_Pos   (3UL)

UART2 UART2_LCR_REG: UART_PEN (Bit 3)

Definition at line 11163 of file DA14680BA.h.

◆ UART2_UART2_LCR_REG_UART_STOP_Msk

#define UART2_UART2_LCR_REG_UART_STOP_Msk   (0x4UL)

UART2 UART2_LCR_REG: UART_STOP (Bitfield-Mask: 0x01)

Definition at line 11162 of file DA14680BA.h.

◆ UART2_UART2_LCR_REG_UART_STOP_Pos

#define UART2_UART2_LCR_REG_UART_STOP_Pos   (2UL)

UART2 UART2_LCR_REG: UART_STOP (Bit 2)

Definition at line 11161 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_BI_Msk

#define UART2_UART2_LSR_REG_UART_BI_Msk   (0x10UL)

UART2 UART2_LSR_REG: UART_BI (Bitfield-Mask: 0x01)

Definition at line 11196 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_BI_Pos

#define UART2_UART2_LSR_REG_UART_BI_Pos   (4UL)

UART2 UART2_LSR_REG: UART_BI (Bit 4)

Definition at line 11195 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_DR_Msk

#define UART2_UART2_LSR_REG_UART_DR_Msk   (0x1UL)

UART2 UART2_LSR_REG: UART_DR (Bitfield-Mask: 0x01)

Definition at line 11188 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_DR_Pos

#define UART2_UART2_LSR_REG_UART_DR_Pos   (0UL)

UART2 UART2_LSR_REG: UART_DR (Bit 0)

Definition at line 11187 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_FE_Msk

#define UART2_UART2_LSR_REG_UART_FE_Msk   (0x8UL)

UART2 UART2_LSR_REG: UART_FE (Bitfield-Mask: 0x01)

Definition at line 11194 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_FE_Pos

#define UART2_UART2_LSR_REG_UART_FE_Pos   (3UL)

UART2 UART2_LSR_REG: UART_FE (Bit 3)

Definition at line 11193 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_OE_Msk

#define UART2_UART2_LSR_REG_UART_OE_Msk   (0x2UL)

UART2 UART2_LSR_REG: UART_OE (Bitfield-Mask: 0x01)

Definition at line 11190 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_OE_Pos

#define UART2_UART2_LSR_REG_UART_OE_Pos   (1UL)

UART2 UART2_LSR_REG: UART_OE (Bit 1)

Definition at line 11189 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_PE_Msk

#define UART2_UART2_LSR_REG_UART_PE_Msk   (0x4UL)

UART2 UART2_LSR_REG: UART_PE (Bitfield-Mask: 0x01)

Definition at line 11192 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_PE_Pos

#define UART2_UART2_LSR_REG_UART_PE_Pos   (2UL)

UART2 UART2_LSR_REG: UART_PE (Bit 2)

Definition at line 11191 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_RFE_Msk

#define UART2_UART2_LSR_REG_UART_RFE_Msk   (0x80UL)

UART2 UART2_LSR_REG: UART_RFE (Bitfield-Mask: 0x01)

Definition at line 11202 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_RFE_Pos

#define UART2_UART2_LSR_REG_UART_RFE_Pos   (7UL)

UART2 UART2_LSR_REG: UART_RFE (Bit 7)

Definition at line 11201 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_TEMT_Msk

#define UART2_UART2_LSR_REG_UART_TEMT_Msk   (0x40UL)

UART2 UART2_LSR_REG: UART_TEMT (Bitfield-Mask: 0x01)

Definition at line 11200 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_TEMT_Pos

#define UART2_UART2_LSR_REG_UART_TEMT_Pos   (6UL)

UART2 UART2_LSR_REG: UART_TEMT (Bit 6)

Definition at line 11199 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_THRE_Msk

#define UART2_UART2_LSR_REG_UART_THRE_Msk   (0x20UL)

UART2 UART2_LSR_REG: UART_THRE (Bitfield-Mask: 0x01)

Definition at line 11198 of file DA14680BA.h.

◆ UART2_UART2_LSR_REG_UART_THRE_Pos

#define UART2_UART2_LSR_REG_UART_THRE_Pos   (5UL)

UART2 UART2_LSR_REG: UART_THRE (Bit 5)

Definition at line 11197 of file DA14680BA.h.

◆ UART2_UART2_MCR_REG_UART_AFCE_Msk

#define UART2_UART2_MCR_REG_UART_AFCE_Msk   (0x20UL)

UART2 UART2_MCR_REG: UART_AFCE (Bitfield-Mask: 0x01)

Definition at line 11182 of file DA14680BA.h.

◆ UART2_UART2_MCR_REG_UART_AFCE_Pos

#define UART2_UART2_MCR_REG_UART_AFCE_Pos   (5UL)

UART2 UART2_MCR_REG: UART_AFCE (Bit 5)

Definition at line 11181 of file DA14680BA.h.

◆ UART2_UART2_MCR_REG_UART_LB_Msk

#define UART2_UART2_MCR_REG_UART_LB_Msk   (0x10UL)

UART2 UART2_MCR_REG: UART_LB (Bitfield-Mask: 0x01)

Definition at line 11180 of file DA14680BA.h.

◆ UART2_UART2_MCR_REG_UART_LB_Pos

#define UART2_UART2_MCR_REG_UART_LB_Pos   (4UL)

UART2 UART2_MCR_REG: UART_LB (Bit 4)

Definition at line 11179 of file DA14680BA.h.

◆ UART2_UART2_MCR_REG_UART_OUT1_Msk

#define UART2_UART2_MCR_REG_UART_OUT1_Msk   (0x4UL)

UART2 UART2_MCR_REG: UART_OUT1 (Bitfield-Mask: 0x01)

Definition at line 11176 of file DA14680BA.h.

◆ UART2_UART2_MCR_REG_UART_OUT1_Pos

#define UART2_UART2_MCR_REG_UART_OUT1_Pos   (2UL)

UART2 UART2_MCR_REG: UART_OUT1 (Bit 2)

Definition at line 11175 of file DA14680BA.h.

◆ UART2_UART2_MCR_REG_UART_OUT2_Msk

#define UART2_UART2_MCR_REG_UART_OUT2_Msk   (0x8UL)

UART2 UART2_MCR_REG: UART_OUT2 (Bitfield-Mask: 0x01)

Definition at line 11178 of file DA14680BA.h.

◆ UART2_UART2_MCR_REG_UART_OUT2_Pos

#define UART2_UART2_MCR_REG_UART_OUT2_Pos   (3UL)

UART2 UART2_MCR_REG: UART_OUT2 (Bit 3)

Definition at line 11177 of file DA14680BA.h.

◆ UART2_UART2_MCR_REG_UART_RTS_Msk

#define UART2_UART2_MCR_REG_UART_RTS_Msk   (0x2UL)

UART2 UART2_MCR_REG: UART_RTS (Bitfield-Mask: 0x01)

Definition at line 11174 of file DA14680BA.h.

◆ UART2_UART2_MCR_REG_UART_RTS_Pos

#define UART2_UART2_MCR_REG_UART_RTS_Pos   (1UL)

UART2 UART2_MCR_REG: UART_RTS (Bit 1)

Definition at line 11173 of file DA14680BA.h.

◆ UART2_UART2_MCR_REG_UART_SIRE_Msk

#define UART2_UART2_MCR_REG_UART_SIRE_Msk   (0x40UL)

UART2 UART2_MCR_REG: UART_SIRE (Bitfield-Mask: 0x01)

Definition at line 11184 of file DA14680BA.h.

◆ UART2_UART2_MCR_REG_UART_SIRE_Pos

#define UART2_UART2_MCR_REG_UART_SIRE_Pos   (6UL)

UART2 UART2_MCR_REG: UART_SIRE (Bit 6)

Definition at line 11183 of file DA14680BA.h.

◆ UART2_UART2_MSR_REG_UART_CTS_Msk

#define UART2_UART2_MSR_REG_UART_CTS_Msk   (0x10UL)

UART2 UART2_MSR_REG: UART_CTS (Bitfield-Mask: 0x01)

Definition at line 11208 of file DA14680BA.h.

◆ UART2_UART2_MSR_REG_UART_CTS_Pos

#define UART2_UART2_MSR_REG_UART_CTS_Pos   (4UL)

UART2 UART2_MSR_REG: UART_CTS (Bit 4)

Definition at line 11207 of file DA14680BA.h.

◆ UART2_UART2_MSR_REG_UART_DCTS_Msk

#define UART2_UART2_MSR_REG_UART_DCTS_Msk   (0x1UL)

UART2 UART2_MSR_REG: UART_DCTS (Bitfield-Mask: 0x01)

Definition at line 11206 of file DA14680BA.h.

◆ UART2_UART2_MSR_REG_UART_DCTS_Pos

#define UART2_UART2_MSR_REG_UART_DCTS_Pos   (0UL)

UART2 UART2_MSR_REG: UART_DCTS (Bit 0)

Definition at line 11205 of file DA14680BA.h.

◆ UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Msk

#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Msk   (0xffUL)

UART2 UART2_RBR_THR_DLL_REG: RBR_THR_DLL (Bitfield-Mask: 0xff)

Definition at line 11142 of file DA14680BA.h.

◆ UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Pos

#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Pos   (0UL)

UART2 UART2_RBR_THR_DLL_REG: RBR_THR_DLL (Bit 0)

Definition at line 11141 of file DA14680BA.h.

◆ UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk

#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk   (0xffffUL)

UART2 UART2_RFL_REG: UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0xffff)

Definition at line 11300 of file DA14680BA.h.

◆ UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos

#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos   (0UL)

UART2 UART2_RFL_REG: UART_RECEIVE_FIFO_LEVEL (Bit 0)

Definition at line 11299 of file DA14680BA.h.

◆ UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk

#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk   (0x1UL)

UART2 UART2_SBCR_REG: UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01)

Definition at line 11316 of file DA14680BA.h.

◆ UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos

#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos   (0UL)

UART2 UART2_SBCR_REG: UART_SHADOW_BREAK_CONTROL (Bit 0)

Definition at line 11315 of file DA14680BA.h.

◆ UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Msk

#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Msk   (0xffUL)

UART2 UART2_SCR_REG: UART_SCRATCH_PAD (Bitfield-Mask: 0xff)

Definition at line 11212 of file DA14680BA.h.

◆ UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Pos

#define UART2_UART2_SCR_REG_UART_SCRATCH_PAD_Pos   (0UL)

UART2 UART2_SCR_REG: UART_SCRATCH_PAD (Bit 0)

Definition at line 11211 of file DA14680BA.h.

◆ UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk

#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk   (0x1UL)

UART2 UART2_SDMAM_REG: UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01)

Definition at line 11320 of file DA14680BA.h.

◆ UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos

#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos   (0UL)

UART2 UART2_SDMAM_REG: UART_SHADOW_DMA_MODE (Bit 0)

Definition at line 11319 of file DA14680BA.h.

◆ UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk

#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk   (0x1UL)

UART2 UART2_SFE_REG: UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01)

Definition at line 11324 of file DA14680BA.h.

◆ UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos

#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos   (0UL)

UART2 UART2_SFE_REG: UART_SHADOW_FIFO_ENABLE (Bit 0)

Definition at line 11323 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR0_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11216 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR0_REG: SRBR_STHRx (Bit 0)

Definition at line 11215 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR10_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11256 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR10_REG: SRBR_STHRx (Bit 0)

Definition at line 11255 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR11_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11260 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR11_REG: SRBR_STHRx (Bit 0)

Definition at line 11259 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR12_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11264 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR12_REG: SRBR_STHRx (Bit 0)

Definition at line 11263 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR13_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11268 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR13_REG: SRBR_STHRx (Bit 0)

Definition at line 11267 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR14_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11272 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR14_REG: SRBR_STHRx (Bit 0)

Definition at line 11271 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR15_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11276 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR15_REG: SRBR_STHRx (Bit 0)

Definition at line 11275 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR1_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11220 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR1_REG: SRBR_STHRx (Bit 0)

Definition at line 11219 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR2_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11224 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR2_REG: SRBR_STHRx (Bit 0)

Definition at line 11223 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR3_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11228 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR3_REG: SRBR_STHRx (Bit 0)

Definition at line 11227 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR4_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11232 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR4_REG: SRBR_STHRx (Bit 0)

Definition at line 11231 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR5_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11236 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR5_REG: SRBR_STHRx (Bit 0)

Definition at line 11235 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR6_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11240 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR6_REG: SRBR_STHRx (Bit 0)

Definition at line 11239 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR7_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11244 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR7_REG: SRBR_STHRx (Bit 0)

Definition at line 11243 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR8_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11248 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR8_REG: SRBR_STHRx (Bit 0)

Definition at line 11247 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Msk   (0xffUL)

UART2 UART2_SRBR_STHR9_REG: SRBR_STHRx (Bitfield-Mask: 0xff)

Definition at line 11252 of file DA14680BA.h.

◆ UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Pos   (0UL)

UART2 UART2_SRBR_STHR9_REG: SRBR_STHRx (Bit 0)

Definition at line 11251 of file DA14680BA.h.

◆ UART2_UART2_SRR_REG_UART_RFR_Msk

#define UART2_UART2_SRR_REG_UART_RFR_Msk   (0x2UL)

UART2 UART2_SRR_REG: UART_RFR (Bitfield-Mask: 0x01)

Definition at line 11306 of file DA14680BA.h.

◆ UART2_UART2_SRR_REG_UART_RFR_Pos

#define UART2_UART2_SRR_REG_UART_RFR_Pos   (1UL)

UART2 UART2_SRR_REG: UART_RFR (Bit 1)

Definition at line 11305 of file DA14680BA.h.

◆ UART2_UART2_SRR_REG_UART_UR_Msk

#define UART2_UART2_SRR_REG_UART_UR_Msk   (0x1UL)

UART2 UART2_SRR_REG: UART_UR (Bitfield-Mask: 0x01)

Definition at line 11304 of file DA14680BA.h.

◆ UART2_UART2_SRR_REG_UART_UR_Pos

#define UART2_UART2_SRR_REG_UART_UR_Pos   (0UL)

UART2 UART2_SRR_REG: UART_UR (Bit 0)

Definition at line 11303 of file DA14680BA.h.

◆ UART2_UART2_SRR_REG_UART_XFR_Msk

#define UART2_UART2_SRR_REG_UART_XFR_Msk   (0x4UL)

UART2 UART2_SRR_REG: UART_XFR (Bitfield-Mask: 0x01)

Definition at line 11308 of file DA14680BA.h.

◆ UART2_UART2_SRR_REG_UART_XFR_Pos

#define UART2_UART2_SRR_REG_UART_XFR_Pos   (2UL)

UART2 UART2_SRR_REG: UART_XFR (Bit 2)

Definition at line 11307 of file DA14680BA.h.

◆ UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk

#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk   (0x3UL)

UART2 UART2_SRT_REG: UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03)

Definition at line 11328 of file DA14680BA.h.

◆ UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos

#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos   (0UL)

UART2 UART2_SRT_REG: UART_SHADOW_RCVR_TRIGGER (Bit 0)

Definition at line 11327 of file DA14680BA.h.

◆ UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk

#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk   (0x1UL)

UART2 UART2_SRTS_REG: UART_SHADOW_REQUEST_TO_SEND (Bitfield-Mask: 0x01)

Definition at line 11312 of file DA14680BA.h.

◆ UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos

#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos   (0UL)

UART2 UART2_SRTS_REG: UART_SHADOW_REQUEST_TO_SEND (Bit 0)

Definition at line 11311 of file DA14680BA.h.

◆ UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk

#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk   (0x3UL)

UART2 UART2_STET_REG: UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03)

Definition at line 11332 of file DA14680BA.h.

◆ UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos

#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos   (0UL)

UART2 UART2_STET_REG: UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0)

Definition at line 11331 of file DA14680BA.h.

◆ UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk

#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk   (0xffffUL)

UART2 UART2_TFL_REG: UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0xffff)

Definition at line 11296 of file DA14680BA.h.

◆ UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos

#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos   (0UL)

UART2 UART2_TFL_REG: UART_TRANSMIT_FIFO_LEVEL (Bit 0)

Definition at line 11295 of file DA14680BA.h.

◆ UART2_UART2_UCV_REG_UCV_Msk

#define UART2_UART2_UCV_REG_UCV_Msk   (0xffffUL)

UART2 UART2_UCV_REG: UCV (Bitfield-Mask: 0xffff)

Definition at line 11352 of file DA14680BA.h.

◆ UART2_UART2_UCV_REG_UCV_Pos

#define UART2_UART2_UCV_REG_UCV_Pos   (0UL)

UART2 UART2_UCV_REG: UCV (Bit 0)

Definition at line 11351 of file DA14680BA.h.

◆ UART2_UART2_USR_REG_UART_BUSY_Msk

#define UART2_UART2_USR_REG_UART_BUSY_Msk   (0x1UL)

UART2 UART2_USR_REG: UART_BUSY (Bitfield-Mask: 0x01)

Definition at line 11284 of file DA14680BA.h.

◆ UART2_UART2_USR_REG_UART_BUSY_Pos

#define UART2_UART2_USR_REG_UART_BUSY_Pos   (0UL)

UART2 UART2_USR_REG: UART_BUSY (Bit 0)

Definition at line 11283 of file DA14680BA.h.

◆ UART2_UART2_USR_REG_UART_RFF_Msk

#define UART2_UART2_USR_REG_UART_RFF_Msk   (0x10UL)

UART2 UART2_USR_REG: UART_RFF (Bitfield-Mask: 0x01)

Definition at line 11292 of file DA14680BA.h.

◆ UART2_UART2_USR_REG_UART_RFF_Pos

#define UART2_UART2_USR_REG_UART_RFF_Pos   (4UL)

UART2 UART2_USR_REG: UART_RFF (Bit 4)

Definition at line 11291 of file DA14680BA.h.

◆ UART2_UART2_USR_REG_UART_RFNE_Msk

#define UART2_UART2_USR_REG_UART_RFNE_Msk   (0x8UL)

UART2 UART2_USR_REG: UART_RFNE (Bitfield-Mask: 0x01)

Definition at line 11290 of file DA14680BA.h.

◆ UART2_UART2_USR_REG_UART_RFNE_Pos

#define UART2_UART2_USR_REG_UART_RFNE_Pos   (3UL)

UART2 UART2_USR_REG: UART_RFNE (Bit 3)

Definition at line 11289 of file DA14680BA.h.

◆ UART2_UART2_USR_REG_UART_TFE_Msk

#define UART2_UART2_USR_REG_UART_TFE_Msk   (0x4UL)

UART2 UART2_USR_REG: UART_TFE (Bitfield-Mask: 0x01)

Definition at line 11288 of file DA14680BA.h.

◆ UART2_UART2_USR_REG_UART_TFE_Pos

#define UART2_UART2_USR_REG_UART_TFE_Pos   (2UL)

UART2 UART2_USR_REG: UART_TFE (Bit 2)

Definition at line 11287 of file DA14680BA.h.

◆ UART2_UART2_USR_REG_UART_TFNF_Msk

#define UART2_UART2_USR_REG_UART_TFNF_Msk   (0x2UL)

UART2 UART2_USR_REG: UART_TFNF (Bitfield-Mask: 0x01)

Definition at line 11286 of file DA14680BA.h.

◆ UART2_UART2_USR_REG_UART_TFNF_Pos

#define UART2_UART2_USR_REG_UART_TFNF_Pos   (1UL)

UART2 UART2_USR_REG: UART_TFNF (Bit 1)

Definition at line 11285 of file DA14680BA.h.

◆ UART_BASE

#define UART_BASE   0x50001000UL

Definition at line 12062 of file DA14680BA.h.

◆ UART_UART_CPR_REG_CPR_Msk

#define UART_UART_CPR_REG_CPR_Msk   (0xffffUL)

UART UART_CPR_REG: CPR (Bitfield-Mask: 0xffff)

Definition at line 11124 of file DA14680BA.h.

◆ UART_UART_CPR_REG_CPR_Pos

#define UART_UART_CPR_REG_CPR_Pos   (0UL)

UART UART_CPR_REG: CPR (Bit 0)

Definition at line 11123 of file DA14680BA.h.

◆ UART_UART_CTR_REG_CTR_Msk

#define UART_UART_CTR_REG_CTR_Msk   (0xffffUL)

UART UART_CTR_REG: CTR (Bitfield-Mask: 0xffff)

Definition at line 11132 of file DA14680BA.h.

◆ UART_UART_CTR_REG_CTR_Pos

#define UART_UART_CTR_REG_CTR_Pos   (0UL)

UART UART_CTR_REG: CTR (Bit 0)

Definition at line 11131 of file DA14680BA.h.

◆ UART_UART_DLF_REG_UART_DLF_Msk

#define UART_UART_DLF_REG_UART_DLF_Msk   (0xfUL)

UART UART_DLF_REG: UART_DLF (Bitfield-Mask: 0x0f)

Definition at line 11120 of file DA14680BA.h.

◆ UART_UART_DLF_REG_UART_DLF_Pos

#define UART_UART_DLF_REG_UART_DLF_Pos   (0UL)

UART UART_DLF_REG: UART_DLF (Bit 0)

Definition at line 11119 of file DA14680BA.h.

◆ UART_UART_DMASA_REG_DMASA_Msk

#define UART_UART_DMASA_REG_DMASA_Msk   (0x1UL)

UART UART_DMASA_REG: DMASA (Bitfield-Mask: 0x01)

Definition at line 11116 of file DA14680BA.h.

◆ UART_UART_DMASA_REG_DMASA_Pos

#define UART_UART_DMASA_REG_DMASA_Pos   (0UL)

UART UART_DMASA_REG: DMASA (Bit 0)

Definition at line 11115 of file DA14680BA.h.

◆ UART_UART_IER_DLH_REG_ELSI_dhl2_Msk

#define UART_UART_IER_DLH_REG_ELSI_dhl2_Msk   (0x4UL)

UART UART_IER_DLH_REG: ELSI_dhl2 (Bitfield-Mask: 0x01)

Definition at line 11050 of file DA14680BA.h.

◆ UART_UART_IER_DLH_REG_ELSI_dhl2_Pos

#define UART_UART_IER_DLH_REG_ELSI_dhl2_Pos   (2UL)

UART UART_IER_DLH_REG: ELSI_dhl2 (Bit 2)

Definition at line 11049 of file DA14680BA.h.

◆ UART_UART_IER_DLH_REG_ERBFI_dlh0_Msk

#define UART_UART_IER_DLH_REG_ERBFI_dlh0_Msk   (0x1UL)

UART UART_IER_DLH_REG: ERBFI_dlh0 (Bitfield-Mask: 0x01)

Definition at line 11046 of file DA14680BA.h.

◆ UART_UART_IER_DLH_REG_ERBFI_dlh0_Pos

#define UART_UART_IER_DLH_REG_ERBFI_dlh0_Pos   (0UL)

UART UART_IER_DLH_REG: ERBFI_dlh0 (Bit 0)

Definition at line 11045 of file DA14680BA.h.

◆ UART_UART_IER_DLH_REG_ETBEI_dlh1_Msk

#define UART_UART_IER_DLH_REG_ETBEI_dlh1_Msk   (0x2UL)

UART UART_IER_DLH_REG: ETBEI_dlh1 (Bitfield-Mask: 0x01)

Definition at line 11048 of file DA14680BA.h.

◆ UART_UART_IER_DLH_REG_ETBEI_dlh1_Pos

#define UART_UART_IER_DLH_REG_ETBEI_dlh1_Pos   (1UL)

UART UART_IER_DLH_REG: ETBEI_dlh1 (Bit 1)

Definition at line 11047 of file DA14680BA.h.

◆ UART_UART_IER_DLH_REG_PTIME_dlh7_Msk

#define UART_UART_IER_DLH_REG_PTIME_dlh7_Msk   (0x80UL)

UART UART_IER_DLH_REG: PTIME_dlh7 (Bitfield-Mask: 0x01)

Definition at line 11052 of file DA14680BA.h.

◆ UART_UART_IER_DLH_REG_PTIME_dlh7_Pos

#define UART_UART_IER_DLH_REG_PTIME_dlh7_Pos   (7UL)

UART UART_IER_DLH_REG: PTIME_dlh7 (Bit 7)

Definition at line 11051 of file DA14680BA.h.

◆ UART_UART_IIR_FCR_REG_IIR_FCR_Msk

#define UART_UART_IIR_FCR_REG_IIR_FCR_Msk   (0xffffUL)

UART UART_IIR_FCR_REG: IIR_FCR (Bitfield-Mask: 0xffff)

Definition at line 11056 of file DA14680BA.h.

◆ UART_UART_IIR_FCR_REG_IIR_FCR_Pos

#define UART_UART_IIR_FCR_REG_IIR_FCR_Pos   (0UL)

UART UART_IIR_FCR_REG: IIR_FCR (Bit 0)

Definition at line 11055 of file DA14680BA.h.

◆ UART_UART_LCR_REG_UART_BC_Msk

#define UART_UART_LCR_REG_UART_BC_Msk   (0x40UL)

UART UART_LCR_REG: UART_BC (Bitfield-Mask: 0x01)

Definition at line 11068 of file DA14680BA.h.

◆ UART_UART_LCR_REG_UART_BC_Pos

#define UART_UART_LCR_REG_UART_BC_Pos   (6UL)

UART UART_LCR_REG: UART_BC (Bit 6)

Definition at line 11067 of file DA14680BA.h.

◆ UART_UART_LCR_REG_UART_DLAB_Msk

#define UART_UART_LCR_REG_UART_DLAB_Msk   (0x80UL)

UART UART_LCR_REG: UART_DLAB (Bitfield-Mask: 0x01)

Definition at line 11070 of file DA14680BA.h.

◆ UART_UART_LCR_REG_UART_DLAB_Pos

#define UART_UART_LCR_REG_UART_DLAB_Pos   (7UL)

UART UART_LCR_REG: UART_DLAB (Bit 7)

Definition at line 11069 of file DA14680BA.h.

◆ UART_UART_LCR_REG_UART_DLS_Msk

#define UART_UART_LCR_REG_UART_DLS_Msk   (0x3UL)

UART UART_LCR_REG: UART_DLS (Bitfield-Mask: 0x03)

Definition at line 11060 of file DA14680BA.h.

◆ UART_UART_LCR_REG_UART_DLS_Pos

#define UART_UART_LCR_REG_UART_DLS_Pos   (0UL)

UART UART_LCR_REG: UART_DLS (Bit 0)

Definition at line 11059 of file DA14680BA.h.

◆ UART_UART_LCR_REG_UART_EPS_Msk

#define UART_UART_LCR_REG_UART_EPS_Msk   (0x10UL)

UART UART_LCR_REG: UART_EPS (Bitfield-Mask: 0x01)

Definition at line 11066 of file DA14680BA.h.

◆ UART_UART_LCR_REG_UART_EPS_Pos

#define UART_UART_LCR_REG_UART_EPS_Pos   (4UL)

UART UART_LCR_REG: UART_EPS (Bit 4)

Definition at line 11065 of file DA14680BA.h.

◆ UART_UART_LCR_REG_UART_PEN_Msk

#define UART_UART_LCR_REG_UART_PEN_Msk   (0x8UL)

UART UART_LCR_REG: UART_PEN (Bitfield-Mask: 0x01)

Definition at line 11064 of file DA14680BA.h.

◆ UART_UART_LCR_REG_UART_PEN_Pos

#define UART_UART_LCR_REG_UART_PEN_Pos   (3UL)

UART UART_LCR_REG: UART_PEN (Bit 3)

Definition at line 11063 of file DA14680BA.h.

◆ UART_UART_LCR_REG_UART_STOP_Msk

#define UART_UART_LCR_REG_UART_STOP_Msk   (0x4UL)

UART UART_LCR_REG: UART_STOP (Bitfield-Mask: 0x01)

Definition at line 11062 of file DA14680BA.h.

◆ UART_UART_LCR_REG_UART_STOP_Pos

#define UART_UART_LCR_REG_UART_STOP_Pos   (2UL)

UART UART_LCR_REG: UART_STOP (Bit 2)

Definition at line 11061 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_BI_Msk

#define UART_UART_LSR_REG_UART_BI_Msk   (0x10UL)

UART UART_LSR_REG: UART_BI (Bitfield-Mask: 0x01)

Definition at line 11092 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_BI_Pos

#define UART_UART_LSR_REG_UART_BI_Pos   (4UL)

UART UART_LSR_REG: UART_BI (Bit 4)

Definition at line 11091 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_DR_Msk

#define UART_UART_LSR_REG_UART_DR_Msk   (0x1UL)

UART UART_LSR_REG: UART_DR (Bitfield-Mask: 0x01)

Definition at line 11084 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_DR_Pos

#define UART_UART_LSR_REG_UART_DR_Pos   (0UL)

UART UART_LSR_REG: UART_DR (Bit 0)

Definition at line 11083 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_FE_Msk

#define UART_UART_LSR_REG_UART_FE_Msk   (0x8UL)

UART UART_LSR_REG: UART_FE (Bitfield-Mask: 0x01)

Definition at line 11090 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_FE_Pos

#define UART_UART_LSR_REG_UART_FE_Pos   (3UL)

UART UART_LSR_REG: UART_FE (Bit 3)

Definition at line 11089 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_OE_Msk

#define UART_UART_LSR_REG_UART_OE_Msk   (0x2UL)

UART UART_LSR_REG: UART_OE (Bitfield-Mask: 0x01)

Definition at line 11086 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_OE_Pos

#define UART_UART_LSR_REG_UART_OE_Pos   (1UL)

UART UART_LSR_REG: UART_OE (Bit 1)

Definition at line 11085 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_PE_Msk

#define UART_UART_LSR_REG_UART_PE_Msk   (0x4UL)

UART UART_LSR_REG: UART_PE (Bitfield-Mask: 0x01)

Definition at line 11088 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_PE_Pos

#define UART_UART_LSR_REG_UART_PE_Pos   (2UL)

UART UART_LSR_REG: UART_PE (Bit 2)

Definition at line 11087 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_TEMT_Msk

#define UART_UART_LSR_REG_UART_TEMT_Msk   (0x40UL)

UART UART_LSR_REG: UART_TEMT (Bitfield-Mask: 0x01)

Definition at line 11096 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_TEMT_Pos

#define UART_UART_LSR_REG_UART_TEMT_Pos   (6UL)

UART UART_LSR_REG: UART_TEMT (Bit 6)

Definition at line 11095 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_THRE_Msk

#define UART_UART_LSR_REG_UART_THRE_Msk   (0x20UL)

UART UART_LSR_REG: UART_THRE (Bitfield-Mask: 0x01)

Definition at line 11094 of file DA14680BA.h.

◆ UART_UART_LSR_REG_UART_THRE_Pos

#define UART_UART_LSR_REG_UART_THRE_Pos   (5UL)

UART UART_LSR_REG: UART_THRE (Bit 5)

Definition at line 11093 of file DA14680BA.h.

◆ UART_UART_MCR_REG_UART_LB_Msk

#define UART_UART_MCR_REG_UART_LB_Msk   (0x10UL)

UART UART_MCR_REG: UART_LB (Bitfield-Mask: 0x01)

Definition at line 11078 of file DA14680BA.h.

◆ UART_UART_MCR_REG_UART_LB_Pos

#define UART_UART_MCR_REG_UART_LB_Pos   (4UL)

UART UART_MCR_REG: UART_LB (Bit 4)

Definition at line 11077 of file DA14680BA.h.

◆ UART_UART_MCR_REG_UART_OUT1_Msk

#define UART_UART_MCR_REG_UART_OUT1_Msk   (0x4UL)

UART UART_MCR_REG: UART_OUT1 (Bitfield-Mask: 0x01)

Definition at line 11074 of file DA14680BA.h.

◆ UART_UART_MCR_REG_UART_OUT1_Pos

#define UART_UART_MCR_REG_UART_OUT1_Pos   (2UL)

UART UART_MCR_REG: UART_OUT1 (Bit 2)

Definition at line 11073 of file DA14680BA.h.

◆ UART_UART_MCR_REG_UART_OUT2_Msk

#define UART_UART_MCR_REG_UART_OUT2_Msk   (0x8UL)

UART UART_MCR_REG: UART_OUT2 (Bitfield-Mask: 0x01)

Definition at line 11076 of file DA14680BA.h.

◆ UART_UART_MCR_REG_UART_OUT2_Pos

#define UART_UART_MCR_REG_UART_OUT2_Pos   (3UL)

UART UART_MCR_REG: UART_OUT2 (Bit 3)

Definition at line 11075 of file DA14680BA.h.

◆ UART_UART_MCR_REG_UART_SIRE_Msk

#define UART_UART_MCR_REG_UART_SIRE_Msk   (0x40UL)

UART UART_MCR_REG: UART_SIRE (Bitfield-Mask: 0x01)

Definition at line 11080 of file DA14680BA.h.

◆ UART_UART_MCR_REG_UART_SIRE_Pos

#define UART_UART_MCR_REG_UART_SIRE_Pos   (6UL)

UART UART_MCR_REG: UART_SIRE (Bit 6)

Definition at line 11079 of file DA14680BA.h.

◆ UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Msk

#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Msk   (0xffUL)

UART UART_RBR_THR_DLL_REG: RBR_THR_DLL (Bitfield-Mask: 0xff)

Definition at line 11042 of file DA14680BA.h.

◆ UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Pos

#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Pos   (0UL)

UART UART_RBR_THR_DLL_REG: RBR_THR_DLL (Bit 0)

Definition at line 11041 of file DA14680BA.h.

◆ UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk

#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk   (0x1UL)

UART UART_SBCR_REG: UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01)

Definition at line 11112 of file DA14680BA.h.

◆ UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos

#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos   (0UL)

UART UART_SBCR_REG: UART_SHADOW_BREAK_CONTROL (Bit 0)

Definition at line 11111 of file DA14680BA.h.

◆ UART_UART_SCR_REG_UART_SCRATCH_PAD_Msk

#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Msk   (0xffUL)

UART UART_SCR_REG: UART_SCRATCH_PAD (Bitfield-Mask: 0xff)

Definition at line 11100 of file DA14680BA.h.

◆ UART_UART_SCR_REG_UART_SCRATCH_PAD_Pos

#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Pos   (0UL)

UART UART_SCR_REG: UART_SCRATCH_PAD (Bit 0)

Definition at line 11099 of file DA14680BA.h.

◆ UART_UART_SRR_REG_UART_UR_Msk

#define UART_UART_SRR_REG_UART_UR_Msk   (0x1UL)

UART UART_SRR_REG: UART_UR (Bitfield-Mask: 0x01)

Definition at line 11108 of file DA14680BA.h.

◆ UART_UART_SRR_REG_UART_UR_Pos

#define UART_UART_SRR_REG_UART_UR_Pos   (0UL)

UART UART_SRR_REG: UART_UR (Bit 0)

Definition at line 11107 of file DA14680BA.h.

◆ UART_UART_UCV_REG_UCV_Msk

#define UART_UART_UCV_REG_UCV_Msk   (0xffffUL)

UART UART_UCV_REG: UCV (Bitfield-Mask: 0xffff)

Definition at line 11128 of file DA14680BA.h.

◆ UART_UART_UCV_REG_UCV_Pos

#define UART_UART_UCV_REG_UCV_Pos   (0UL)

UART UART_UCV_REG: UCV (Bit 0)

Definition at line 11127 of file DA14680BA.h.

◆ UART_UART_USR_REG_UART_BUSY_Msk

#define UART_UART_USR_REG_UART_BUSY_Msk   (0x1UL)

UART UART_USR_REG: UART_BUSY (Bitfield-Mask: 0x01)

Definition at line 11104 of file DA14680BA.h.

◆ UART_UART_USR_REG_UART_BUSY_Pos

#define UART_UART_USR_REG_UART_BUSY_Pos   (0UL)

UART UART_USR_REG: UART_BUSY (Bit 0)

Definition at line 11103 of file DA14680BA.h.

◆ USB

#define USB   ((USB_Type *) USB_BASE)

Definition at line 12109 of file DA14680BA.h.

◆ USB_BASE

#define USB_BASE   0x50001800UL

Definition at line 12064 of file DA14680BA.h.

◆ USB_USB_ALTEV_REG_USB_EOP_Msk

#define USB_USB_ALTEV_REG_USB_EOP_Msk   (0x8UL)

USB USB_ALTEV_REG: USB_EOP (Bitfield-Mask: 0x01)

Definition at line 11470 of file DA14680BA.h.

◆ USB_USB_ALTEV_REG_USB_EOP_Pos

#define USB_USB_ALTEV_REG_USB_EOP_Pos   (3UL)

USB USB_ALTEV_REG: USB_EOP (Bit 3)

Definition at line 11469 of file DA14680BA.h.

◆ USB_USB_ALTEV_REG_USB_RESET_Msk

#define USB_USB_ALTEV_REG_USB_RESET_Msk   (0x40UL)

USB USB_ALTEV_REG: USB_RESET (Bitfield-Mask: 0x01)

Definition at line 11476 of file DA14680BA.h.

◆ USB_USB_ALTEV_REG_USB_RESET_Pos

#define USB_USB_ALTEV_REG_USB_RESET_Pos   (6UL)

USB USB_ALTEV_REG: USB_RESET (Bit 6)

Definition at line 11475 of file DA14680BA.h.

◆ USB_USB_ALTEV_REG_USB_RESUME_Msk

#define USB_USB_ALTEV_REG_USB_RESUME_Msk   (0x80UL)

USB USB_ALTEV_REG: USB_RESUME (Bitfield-Mask: 0x01)

Definition at line 11478 of file DA14680BA.h.

◆ USB_USB_ALTEV_REG_USB_RESUME_Pos

#define USB_USB_ALTEV_REG_USB_RESUME_Pos   (7UL)

USB USB_ALTEV_REG: USB_RESUME (Bit 7)

Definition at line 11477 of file DA14680BA.h.

◆ USB_USB_ALTEV_REG_USB_SD3_Msk

#define USB_USB_ALTEV_REG_USB_SD3_Msk   (0x10UL)

USB USB_ALTEV_REG: USB_SD3 (Bitfield-Mask: 0x01)

Definition at line 11472 of file DA14680BA.h.

◆ USB_USB_ALTEV_REG_USB_SD3_Pos

#define USB_USB_ALTEV_REG_USB_SD3_Pos   (4UL)

USB USB_ALTEV_REG: USB_SD3 (Bit 4)

Definition at line 11471 of file DA14680BA.h.

◆ USB_USB_ALTEV_REG_USB_SD5_Msk

#define USB_USB_ALTEV_REG_USB_SD5_Msk   (0x20UL)

USB USB_ALTEV_REG: USB_SD5 (Bitfield-Mask: 0x01)

Definition at line 11474 of file DA14680BA.h.

◆ USB_USB_ALTEV_REG_USB_SD5_Pos

#define USB_USB_ALTEV_REG_USB_SD5_Pos   (5UL)

USB USB_ALTEV_REG: USB_SD5 (Bit 5)

Definition at line 11473 of file DA14680BA.h.

◆ USB_USB_ALTMSK_REG_USB_M_EOP_Msk

#define USB_USB_ALTMSK_REG_USB_M_EOP_Msk   (0x8UL)

USB USB_ALTMSK_REG: USB_M_EOP (Bitfield-Mask: 0x01)

Definition at line 11482 of file DA14680BA.h.

◆ USB_USB_ALTMSK_REG_USB_M_EOP_Pos

#define USB_USB_ALTMSK_REG_USB_M_EOP_Pos   (3UL)

USB USB_ALTMSK_REG: USB_M_EOP (Bit 3)

Definition at line 11481 of file DA14680BA.h.

◆ USB_USB_ALTMSK_REG_USB_M_RESET_Msk

#define USB_USB_ALTMSK_REG_USB_M_RESET_Msk   (0x40UL)

USB USB_ALTMSK_REG: USB_M_RESET (Bitfield-Mask: 0x01)

Definition at line 11488 of file DA14680BA.h.

◆ USB_USB_ALTMSK_REG_USB_M_RESET_Pos

#define USB_USB_ALTMSK_REG_USB_M_RESET_Pos   (6UL)

USB USB_ALTMSK_REG: USB_M_RESET (Bit 6)

Definition at line 11487 of file DA14680BA.h.

◆ USB_USB_ALTMSK_REG_USB_M_RESUME_Msk

#define USB_USB_ALTMSK_REG_USB_M_RESUME_Msk   (0x80UL)

USB USB_ALTMSK_REG: USB_M_RESUME (Bitfield-Mask: 0x01)

Definition at line 11490 of file DA14680BA.h.

◆ USB_USB_ALTMSK_REG_USB_M_RESUME_Pos

#define USB_USB_ALTMSK_REG_USB_M_RESUME_Pos   (7UL)

USB USB_ALTMSK_REG: USB_M_RESUME (Bit 7)

Definition at line 11489 of file DA14680BA.h.

◆ USB_USB_ALTMSK_REG_USB_M_SD3_Msk

#define USB_USB_ALTMSK_REG_USB_M_SD3_Msk   (0x10UL)

USB USB_ALTMSK_REG: USB_M_SD3 (Bitfield-Mask: 0x01)

Definition at line 11484 of file DA14680BA.h.

◆ USB_USB_ALTMSK_REG_USB_M_SD3_Pos

#define USB_USB_ALTMSK_REG_USB_M_SD3_Pos   (4UL)

USB USB_ALTMSK_REG: USB_M_SD3 (Bit 4)

Definition at line 11483 of file DA14680BA.h.

◆ USB_USB_ALTMSK_REG_USB_M_SD5_Msk

#define USB_USB_ALTMSK_REG_USB_M_SD5_Msk   (0x20UL)

USB USB_ALTMSK_REG: USB_M_SD5 (Bitfield-Mask: 0x01)

Definition at line 11486 of file DA14680BA.h.

◆ USB_USB_ALTMSK_REG_USB_M_SD5_Pos

#define USB_USB_ALTMSK_REG_USB_M_SD5_Pos   (5UL)

USB USB_ALTMSK_REG: USB_M_SD5 (Bit 5)

Definition at line 11485 of file DA14680BA.h.

◆ USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Msk

#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Msk   (0x20UL)

USB USB_CHARGER_CTRL_REG: IDM_SINK_ON (Bitfield-Mask: 0x01)

Definition at line 11878 of file DA14680BA.h.

◆ USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Pos

#define USB_USB_CHARGER_CTRL_REG_IDM_SINK_ON_Pos   (5UL)

USB USB_CHARGER_CTRL_REG: IDM_SINK_ON (Bit 5)

Definition at line 11877 of file DA14680BA.h.

◆ USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Msk

#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Msk   (0x10UL)

USB USB_CHARGER_CTRL_REG: IDP_SINK_ON (Bitfield-Mask: 0x01)

Definition at line 11876 of file DA14680BA.h.

◆ USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Pos

#define USB_USB_CHARGER_CTRL_REG_IDP_SINK_ON_Pos   (4UL)

USB USB_CHARGER_CTRL_REG: IDP_SINK_ON (Bit 4)

Definition at line 11875 of file DA14680BA.h.

◆ USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Msk

#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Msk   (0x2UL)

USB USB_CHARGER_CTRL_REG: IDP_SRC_ON (Bitfield-Mask: 0x01)

Definition at line 11870 of file DA14680BA.h.

◆ USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Pos

#define USB_USB_CHARGER_CTRL_REG_IDP_SRC_ON_Pos   (1UL)

USB USB_CHARGER_CTRL_REG: IDP_SRC_ON (Bit 1)

Definition at line 11869 of file DA14680BA.h.

◆ USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Msk

#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Msk   (0x1UL)

USB USB_CHARGER_CTRL_REG: USB_CHARGE_ON (Bitfield-Mask: 0x01)

Definition at line 11868 of file DA14680BA.h.

◆ USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Pos

#define USB_USB_CHARGER_CTRL_REG_USB_CHARGE_ON_Pos   (0UL)

USB USB_CHARGER_CTRL_REG: USB_CHARGE_ON (Bit 0)

Definition at line 11867 of file DA14680BA.h.

◆ USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Msk

#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Msk   (0x8UL)

USB USB_CHARGER_CTRL_REG: VDM_SRC_ON (Bitfield-Mask: 0x01)

Definition at line 11874 of file DA14680BA.h.

◆ USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Pos

#define USB_USB_CHARGER_CTRL_REG_VDM_SRC_ON_Pos   (3UL)

USB USB_CHARGER_CTRL_REG: VDM_SRC_ON (Bit 3)

Definition at line 11873 of file DA14680BA.h.

◆ USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Msk

#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Msk   (0x4UL)

USB USB_CHARGER_CTRL_REG: VDP_SRC_ON (Bitfield-Mask: 0x01)

Definition at line 11872 of file DA14680BA.h.

◆ USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Pos

#define USB_USB_CHARGER_CTRL_REG_VDP_SRC_ON_Pos   (2UL)

USB USB_CHARGER_CTRL_REG: VDP_SRC_ON (Bit 2)

Definition at line 11871 of file DA14680BA.h.

◆ USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Msk

#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Msk   (0x2UL)

USB USB_CHARGER_STAT_REG: USB_CHG_DET (Bitfield-Mask: 0x01)

Definition at line 11884 of file DA14680BA.h.

◆ USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Pos

#define USB_USB_CHARGER_STAT_REG_USB_CHG_DET_Pos   (1UL)

USB USB_CHARGER_STAT_REG: USB_CHG_DET (Bit 1)

Definition at line 11883 of file DA14680BA.h.

◆ USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Msk

#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Msk   (0x1UL)

USB USB_CHARGER_STAT_REG: USB_DCP_DET (Bitfield-Mask: 0x01)

Definition at line 11882 of file DA14680BA.h.

◆ USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Pos

#define USB_USB_CHARGER_STAT_REG_USB_DCP_DET_Pos   (0UL)

USB USB_CHARGER_STAT_REG: USB_DCP_DET (Bit 0)

Definition at line 11881 of file DA14680BA.h.

◆ USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Msk

#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Msk   (0x20UL)

USB USB_CHARGER_STAT_REG: USB_DM_VAL2 (Bitfield-Mask: 0x01)

Definition at line 11892 of file DA14680BA.h.

◆ USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Pos

#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL2_Pos   (5UL)

USB USB_CHARGER_STAT_REG: USB_DM_VAL2 (Bit 5)

Definition at line 11891 of file DA14680BA.h.

◆ USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Msk

#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Msk   (0x8UL)

USB USB_CHARGER_STAT_REG: USB_DM_VAL (Bitfield-Mask: 0x01)

Definition at line 11888 of file DA14680BA.h.

◆ USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Pos

#define USB_USB_CHARGER_STAT_REG_USB_DM_VAL_Pos   (3UL)

USB USB_CHARGER_STAT_REG: USB_DM_VAL (Bit 3)

Definition at line 11887 of file DA14680BA.h.

◆ USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Msk

#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Msk   (0x10UL)

USB USB_CHARGER_STAT_REG: USB_DP_VAL2 (Bitfield-Mask: 0x01)

Definition at line 11890 of file DA14680BA.h.

◆ USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Pos

#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL2_Pos   (4UL)

USB USB_CHARGER_STAT_REG: USB_DP_VAL2 (Bit 4)

Definition at line 11889 of file DA14680BA.h.

◆ USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Msk

#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Msk   (0x4UL)

USB USB_CHARGER_STAT_REG: USB_DP_VAL (Bitfield-Mask: 0x01)

Definition at line 11886 of file DA14680BA.h.

◆ USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Pos

#define USB_USB_CHARGER_STAT_REG_USB_DP_VAL_Pos   (2UL)

USB USB_CHARGER_STAT_REG: USB_DP_VAL (Bit 2)

Definition at line 11885 of file DA14680BA.h.

◆ USB_USB_DMA_CTRL_REG_USB_DMA_EN_Msk

#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Msk   (0x40UL)

USB USB_DMA_CTRL_REG: USB_DMA_EN (Bitfield-Mask: 0x01)

Definition at line 11864 of file DA14680BA.h.

◆ USB_USB_DMA_CTRL_REG_USB_DMA_EN_Pos

#define USB_USB_DMA_CTRL_REG_USB_DMA_EN_Pos   (6UL)

USB USB_DMA_CTRL_REG: USB_DMA_EN (Bit 6)

Definition at line 11863 of file DA14680BA.h.

◆ USB_USB_DMA_CTRL_REG_USB_DMA_RX_Msk

#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Msk   (0x7UL)

USB USB_DMA_CTRL_REG: USB_DMA_RX (Bitfield-Mask: 0x07)

Definition at line 11860 of file DA14680BA.h.

◆ USB_USB_DMA_CTRL_REG_USB_DMA_RX_Pos

#define USB_USB_DMA_CTRL_REG_USB_DMA_RX_Pos   (0UL)

USB USB_DMA_CTRL_REG: USB_DMA_RX (Bit 0)

Definition at line 11859 of file DA14680BA.h.

◆ USB_USB_DMA_CTRL_REG_USB_DMA_TX_Msk

#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Msk   (0x38UL)

USB USB_DMA_CTRL_REG: USB_DMA_TX (Bitfield-Mask: 0x07)

Definition at line 11862 of file DA14680BA.h.

◆ USB_USB_DMA_CTRL_REG_USB_DMA_TX_Pos

#define USB_USB_DMA_CTRL_REG_USB_DMA_TX_Pos   (3UL)

USB USB_DMA_CTRL_REG: USB_DMA_TX (Bit 3)

Definition at line 11861 of file DA14680BA.h.

◆ USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Msk

#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Msk   (0x1UL)

USB USB_EP0_NAK_REG: USB_EP0_INNAK (Bitfield-Mask: 0x01)

Definition at line 11602 of file DA14680BA.h.

◆ USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Pos

#define USB_USB_EP0_NAK_REG_USB_EP0_INNAK_Pos   (0UL)

USB USB_EP0_NAK_REG: USB_EP0_INNAK (Bit 0)

Definition at line 11601 of file DA14680BA.h.

◆ USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Msk

#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Msk   (0x2UL)

USB USB_EP0_NAK_REG: USB_EP0_OUTNAK (Bitfield-Mask: 0x01)

Definition at line 11604 of file DA14680BA.h.

◆ USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Pos

#define USB_USB_EP0_NAK_REG_USB_EP0_OUTNAK_Pos   (1UL)

USB USB_EP0_NAK_REG: USB_EP0_OUTNAK (Bit 1)

Definition at line 11603 of file DA14680BA.h.

◆ USB_USB_EPC0_REG_USB_DEF_Msk

#define USB_USB_EPC0_REG_USB_DEF_Msk   (0x40UL)

USB USB_EPC0_REG: USB_DEF (Bitfield-Mask: 0x01)

Definition at line 11574 of file DA14680BA.h.

◆ USB_USB_EPC0_REG_USB_DEF_Pos

#define USB_USB_EPC0_REG_USB_DEF_Pos   (6UL)

USB USB_EPC0_REG: USB_DEF (Bit 6)

Definition at line 11573 of file DA14680BA.h.

◆ USB_USB_EPC0_REG_USB_EP_Msk

#define USB_USB_EPC0_REG_USB_EP_Msk   (0xfUL)

USB USB_EPC0_REG: USB_EP (Bitfield-Mask: 0x0f)

Definition at line 11572 of file DA14680BA.h.

◆ USB_USB_EPC0_REG_USB_EP_Pos

#define USB_USB_EPC0_REG_USB_EP_Pos   (0UL)

USB USB_EPC0_REG: USB_EP (Bit 0)

Definition at line 11571 of file DA14680BA.h.

◆ USB_USB_EPC0_REG_USB_STALL_Msk

#define USB_USB_EPC0_REG_USB_STALL_Msk   (0x80UL)

USB USB_EPC0_REG: USB_STALL (Bitfield-Mask: 0x01)

Definition at line 11576 of file DA14680BA.h.

◆ USB_USB_EPC0_REG_USB_STALL_Pos

#define USB_USB_EPC0_REG_USB_STALL_Pos   (7UL)

USB USB_EPC0_REG: USB_STALL (Bit 7)

Definition at line 11575 of file DA14680BA.h.

◆ USB_USB_EPC1_REG_USB_EP_EN_Msk

#define USB_USB_EPC1_REG_USB_EP_EN_Msk   (0x10UL)

USB USB_EPC1_REG: USB_EP_EN (Bitfield-Mask: 0x01)

Definition at line 11634 of file DA14680BA.h.

◆ USB_USB_EPC1_REG_USB_EP_EN_Pos

#define USB_USB_EPC1_REG_USB_EP_EN_Pos   (4UL)

USB USB_EPC1_REG: USB_EP_EN (Bit 4)

Definition at line 11633 of file DA14680BA.h.

◆ USB_USB_EPC1_REG_USB_EP_Msk

#define USB_USB_EPC1_REG_USB_EP_Msk   (0xfUL)

USB USB_EPC1_REG: USB_EP (Bitfield-Mask: 0x0f)

Definition at line 11632 of file DA14680BA.h.

◆ USB_USB_EPC1_REG_USB_EP_Pos

#define USB_USB_EPC1_REG_USB_EP_Pos   (0UL)

USB USB_EPC1_REG: USB_EP (Bit 0)

Definition at line 11631 of file DA14680BA.h.

◆ USB_USB_EPC1_REG_USB_ISO_Msk

#define USB_USB_EPC1_REG_USB_ISO_Msk   (0x20UL)

USB USB_EPC1_REG: USB_ISO (Bitfield-Mask: 0x01)

Definition at line 11636 of file DA14680BA.h.

◆ USB_USB_EPC1_REG_USB_ISO_Pos

#define USB_USB_EPC1_REG_USB_ISO_Pos   (5UL)

USB USB_EPC1_REG: USB_ISO (Bit 5)

Definition at line 11635 of file DA14680BA.h.

◆ USB_USB_EPC1_REG_USB_STALL_Msk

#define USB_USB_EPC1_REG_USB_STALL_Msk   (0x80UL)

USB USB_EPC1_REG: USB_STALL (Bitfield-Mask: 0x01)

Definition at line 11638 of file DA14680BA.h.

◆ USB_USB_EPC1_REG_USB_STALL_Pos

#define USB_USB_EPC1_REG_USB_STALL_Pos   (7UL)

USB USB_EPC1_REG: USB_STALL (Bit 7)

Definition at line 11637 of file DA14680BA.h.

◆ USB_USB_EPC2_REG_USB_EP_EN_Msk

#define USB_USB_EPC2_REG_USB_EP_EN_Msk   (0x10UL)

USB USB_EPC2_REG: USB_EP_EN (Bitfield-Mask: 0x01)

Definition at line 11674 of file DA14680BA.h.

◆ USB_USB_EPC2_REG_USB_EP_EN_Pos

#define USB_USB_EPC2_REG_USB_EP_EN_Pos   (4UL)

USB USB_EPC2_REG: USB_EP_EN (Bit 4)

Definition at line 11673 of file DA14680BA.h.

◆ USB_USB_EPC2_REG_USB_EP_Msk

#define USB_USB_EPC2_REG_USB_EP_Msk   (0xfUL)

USB USB_EPC2_REG: USB_EP (Bitfield-Mask: 0x0f)

Definition at line 11672 of file DA14680BA.h.

◆ USB_USB_EPC2_REG_USB_EP_Pos

#define USB_USB_EPC2_REG_USB_EP_Pos   (0UL)

USB USB_EPC2_REG: USB_EP (Bit 0)

Definition at line 11671 of file DA14680BA.h.

◆ USB_USB_EPC2_REG_USB_ISO_Msk

#define USB_USB_EPC2_REG_USB_ISO_Msk   (0x20UL)

USB USB_EPC2_REG: USB_ISO (Bitfield-Mask: 0x01)

Definition at line 11676 of file DA14680BA.h.

◆ USB_USB_EPC2_REG_USB_ISO_Pos

#define USB_USB_EPC2_REG_USB_ISO_Pos   (5UL)

USB USB_EPC2_REG: USB_ISO (Bit 5)

Definition at line 11675 of file DA14680BA.h.

◆ USB_USB_EPC2_REG_USB_STALL_Msk

#define USB_USB_EPC2_REG_USB_STALL_Msk   (0x80UL)

USB USB_EPC2_REG: USB_STALL (Bitfield-Mask: 0x01)

Definition at line 11678 of file DA14680BA.h.

◆ USB_USB_EPC2_REG_USB_STALL_Pos

#define USB_USB_EPC2_REG_USB_STALL_Pos   (7UL)

USB USB_EPC2_REG: USB_STALL (Bit 7)

Definition at line 11677 of file DA14680BA.h.

◆ USB_USB_EPC3_REG_USB_EP_EN_Msk

#define USB_USB_EPC3_REG_USB_EP_EN_Msk   (0x10UL)

USB USB_EPC3_REG: USB_EP_EN (Bitfield-Mask: 0x01)

Definition at line 11710 of file DA14680BA.h.

◆ USB_USB_EPC3_REG_USB_EP_EN_Pos

#define USB_USB_EPC3_REG_USB_EP_EN_Pos   (4UL)

USB USB_EPC3_REG: USB_EP_EN (Bit 4)

Definition at line 11709 of file DA14680BA.h.

◆ USB_USB_EPC3_REG_USB_EP_Msk

#define USB_USB_EPC3_REG_USB_EP_Msk   (0xfUL)

USB USB_EPC3_REG: USB_EP (Bitfield-Mask: 0x0f)

Definition at line 11708 of file DA14680BA.h.

◆ USB_USB_EPC3_REG_USB_EP_Pos

#define USB_USB_EPC3_REG_USB_EP_Pos   (0UL)

USB USB_EPC3_REG: USB_EP (Bit 0)

Definition at line 11707 of file DA14680BA.h.

◆ USB_USB_EPC3_REG_USB_ISO_Msk

#define USB_USB_EPC3_REG_USB_ISO_Msk   (0x20UL)

USB USB_EPC3_REG: USB_ISO (Bitfield-Mask: 0x01)

Definition at line 11712 of file DA14680BA.h.

◆ USB_USB_EPC3_REG_USB_ISO_Pos

#define USB_USB_EPC3_REG_USB_ISO_Pos   (5UL)

USB USB_EPC3_REG: USB_ISO (Bit 5)

Definition at line 11711 of file DA14680BA.h.

◆ USB_USB_EPC3_REG_USB_STALL_Msk

#define USB_USB_EPC3_REG_USB_STALL_Msk   (0x80UL)

USB USB_EPC3_REG: USB_STALL (Bitfield-Mask: 0x01)

Definition at line 11714 of file DA14680BA.h.

◆ USB_USB_EPC3_REG_USB_STALL_Pos

#define USB_USB_EPC3_REG_USB_STALL_Pos   (7UL)

USB USB_EPC3_REG: USB_STALL (Bit 7)

Definition at line 11713 of file DA14680BA.h.

◆ USB_USB_EPC4_REG_USB_EP_EN_Msk

#define USB_USB_EPC4_REG_USB_EP_EN_Msk   (0x10UL)

USB USB_EPC4_REG: USB_EP_EN (Bitfield-Mask: 0x01)

Definition at line 11750 of file DA14680BA.h.

◆ USB_USB_EPC4_REG_USB_EP_EN_Pos

#define USB_USB_EPC4_REG_USB_EP_EN_Pos   (4UL)

USB USB_EPC4_REG: USB_EP_EN (Bit 4)

Definition at line 11749 of file DA14680BA.h.

◆ USB_USB_EPC4_REG_USB_EP_Msk

#define USB_USB_EPC4_REG_USB_EP_Msk   (0xfUL)

USB USB_EPC4_REG: USB_EP (Bitfield-Mask: 0x0f)

Definition at line 11748 of file DA14680BA.h.

◆ USB_USB_EPC4_REG_USB_EP_Pos

#define USB_USB_EPC4_REG_USB_EP_Pos   (0UL)

USB USB_EPC4_REG: USB_EP (Bit 0)

Definition at line 11747 of file DA14680BA.h.

◆ USB_USB_EPC4_REG_USB_ISO_Msk

#define USB_USB_EPC4_REG_USB_ISO_Msk   (0x20UL)

USB USB_EPC4_REG: USB_ISO (Bitfield-Mask: 0x01)

Definition at line 11752 of file DA14680BA.h.

◆ USB_USB_EPC4_REG_USB_ISO_Pos

#define USB_USB_EPC4_REG_USB_ISO_Pos   (5UL)

USB USB_EPC4_REG: USB_ISO (Bit 5)

Definition at line 11751 of file DA14680BA.h.

◆ USB_USB_EPC4_REG_USB_STALL_Msk

#define USB_USB_EPC4_REG_USB_STALL_Msk   (0x80UL)

USB USB_EPC4_REG: USB_STALL (Bitfield-Mask: 0x01)

Definition at line 11754 of file DA14680BA.h.

◆ USB_USB_EPC4_REG_USB_STALL_Pos

#define USB_USB_EPC4_REG_USB_STALL_Pos   (7UL)

USB USB_EPC4_REG: USB_STALL (Bit 7)

Definition at line 11753 of file DA14680BA.h.

◆ USB_USB_EPC5_REG_USB_EP_EN_Msk

#define USB_USB_EPC5_REG_USB_EP_EN_Msk   (0x10UL)

USB USB_EPC5_REG: USB_EP_EN (Bitfield-Mask: 0x01)

Definition at line 11786 of file DA14680BA.h.

◆ USB_USB_EPC5_REG_USB_EP_EN_Pos

#define USB_USB_EPC5_REG_USB_EP_EN_Pos   (4UL)

USB USB_EPC5_REG: USB_EP_EN (Bit 4)

Definition at line 11785 of file DA14680BA.h.

◆ USB_USB_EPC5_REG_USB_EP_Msk

#define USB_USB_EPC5_REG_USB_EP_Msk   (0xfUL)

USB USB_EPC5_REG: USB_EP (Bitfield-Mask: 0x0f)

Definition at line 11784 of file DA14680BA.h.

◆ USB_USB_EPC5_REG_USB_EP_Pos

#define USB_USB_EPC5_REG_USB_EP_Pos   (0UL)

USB USB_EPC5_REG: USB_EP (Bit 0)

Definition at line 11783 of file DA14680BA.h.

◆ USB_USB_EPC5_REG_USB_ISO_Msk

#define USB_USB_EPC5_REG_USB_ISO_Msk   (0x20UL)

USB USB_EPC5_REG: USB_ISO (Bitfield-Mask: 0x01)

Definition at line 11788 of file DA14680BA.h.

◆ USB_USB_EPC5_REG_USB_ISO_Pos

#define USB_USB_EPC5_REG_USB_ISO_Pos   (5UL)

USB USB_EPC5_REG: USB_ISO (Bit 5)

Definition at line 11787 of file DA14680BA.h.

◆ USB_USB_EPC5_REG_USB_STALL_Msk

#define USB_USB_EPC5_REG_USB_STALL_Msk   (0x80UL)

USB USB_EPC5_REG: USB_STALL (Bitfield-Mask: 0x01)

Definition at line 11790 of file DA14680BA.h.

◆ USB_USB_EPC5_REG_USB_STALL_Pos

#define USB_USB_EPC5_REG_USB_STALL_Pos   (7UL)

USB USB_EPC5_REG: USB_STALL (Bit 7)

Definition at line 11789 of file DA14680BA.h.

◆ USB_USB_EPC6_REG_USB_EP_EN_Msk

#define USB_USB_EPC6_REG_USB_EP_EN_Msk   (0x10UL)

USB USB_EPC6_REG: USB_EP_EN (Bitfield-Mask: 0x01)

Definition at line 11826 of file DA14680BA.h.

◆ USB_USB_EPC6_REG_USB_EP_EN_Pos

#define USB_USB_EPC6_REG_USB_EP_EN_Pos   (4UL)

USB USB_EPC6_REG: USB_EP_EN (Bit 4)

Definition at line 11825 of file DA14680BA.h.

◆ USB_USB_EPC6_REG_USB_EP_Msk

#define USB_USB_EPC6_REG_USB_EP_Msk   (0xfUL)

USB USB_EPC6_REG: USB_EP (Bitfield-Mask: 0x0f)

Definition at line 11824 of file DA14680BA.h.

◆ USB_USB_EPC6_REG_USB_EP_Pos

#define USB_USB_EPC6_REG_USB_EP_Pos   (0UL)

USB USB_EPC6_REG: USB_EP (Bit 0)

Definition at line 11823 of file DA14680BA.h.

◆ USB_USB_EPC6_REG_USB_ISO_Msk

#define USB_USB_EPC6_REG_USB_ISO_Msk   (0x20UL)

USB USB_EPC6_REG: USB_ISO (Bitfield-Mask: 0x01)

Definition at line 11828 of file DA14680BA.h.

◆ USB_USB_EPC6_REG_USB_ISO_Pos

#define USB_USB_EPC6_REG_USB_ISO_Pos   (5UL)

USB USB_EPC6_REG: USB_ISO (Bit 5)

Definition at line 11827 of file DA14680BA.h.

◆ USB_USB_EPC6_REG_USB_STALL_Msk

#define USB_USB_EPC6_REG_USB_STALL_Msk   (0x80UL)

USB USB_EPC6_REG: USB_STALL (Bitfield-Mask: 0x01)

Definition at line 11830 of file DA14680BA.h.

◆ USB_USB_EPC6_REG_USB_STALL_Pos

#define USB_USB_EPC6_REG_USB_STALL_Pos   (7UL)

USB USB_EPC6_REG: USB_STALL (Bit 7)

Definition at line 11829 of file DA14680BA.h.

◆ USB_USB_FAR_REG_USB_AD_EN_Msk

#define USB_USB_FAR_REG_USB_AD_EN_Msk   (0x80UL)

USB USB_FAR_REG: USB_AD_EN (Bitfield-Mask: 0x01)

Definition at line 11410 of file DA14680BA.h.

◆ USB_USB_FAR_REG_USB_AD_EN_Pos

#define USB_USB_FAR_REG_USB_AD_EN_Pos   (7UL)

USB USB_FAR_REG: USB_AD_EN (Bit 7)

Definition at line 11409 of file DA14680BA.h.

◆ USB_USB_FAR_REG_USB_AD_Msk

#define USB_USB_FAR_REG_USB_AD_Msk   (0x7fUL)

USB USB_FAR_REG: USB_AD (Bitfield-Mask: 0x7f)

Definition at line 11408 of file DA14680BA.h.

◆ USB_USB_FAR_REG_USB_AD_Pos

#define USB_USB_FAR_REG_USB_AD_Pos   (0UL)

USB USB_FAR_REG: USB_AD (Bit 0)

Definition at line 11407 of file DA14680BA.h.

◆ USB_USB_FNH_REG_USB_FN_10_8_Msk

#define USB_USB_FNH_REG_USB_FN_10_8_Msk   (0x7UL)

USB USB_FNH_REG: USB_FN_10_8 (Bitfield-Mask: 0x07)

Definition at line 11542 of file DA14680BA.h.

◆ USB_USB_FNH_REG_USB_FN_10_8_Pos

#define USB_USB_FNH_REG_USB_FN_10_8_Pos   (0UL)

USB USB_FNH_REG: USB_FN_10_8 (Bit 0)

Definition at line 11541 of file DA14680BA.h.

◆ USB_USB_FNH_REG_USB_MF_Msk

#define USB_USB_FNH_REG_USB_MF_Msk   (0x80UL)

USB USB_FNH_REG: USB_MF (Bitfield-Mask: 0x01)

Definition at line 11548 of file DA14680BA.h.

◆ USB_USB_FNH_REG_USB_MF_Pos

#define USB_USB_FNH_REG_USB_MF_Pos   (7UL)

USB USB_FNH_REG: USB_MF (Bit 7)

Definition at line 11547 of file DA14680BA.h.

◆ USB_USB_FNH_REG_USB_RFC_Msk

#define USB_USB_FNH_REG_USB_RFC_Msk   (0x20UL)

USB USB_FNH_REG: USB_RFC (Bitfield-Mask: 0x01)

Definition at line 11544 of file DA14680BA.h.

◆ USB_USB_FNH_REG_USB_RFC_Pos

#define USB_USB_FNH_REG_USB_RFC_Pos   (5UL)

USB USB_FNH_REG: USB_RFC (Bit 5)

Definition at line 11543 of file DA14680BA.h.

◆ USB_USB_FNH_REG_USB_UL_Msk

#define USB_USB_FNH_REG_USB_UL_Msk   (0x40UL)

USB USB_FNH_REG: USB_UL (Bitfield-Mask: 0x01)

Definition at line 11546 of file DA14680BA.h.

◆ USB_USB_FNH_REG_USB_UL_Pos

#define USB_USB_FNH_REG_USB_UL_Pos   (6UL)

USB USB_FNH_REG: USB_UL (Bit 6)

Definition at line 11545 of file DA14680BA.h.

◆ USB_USB_FNL_REG_USB_FN_Msk

#define USB_USB_FNL_REG_USB_FN_Msk   (0xffUL)

USB USB_FNL_REG: USB_FN (Bitfield-Mask: 0xff)

Definition at line 11552 of file DA14680BA.h.

◆ USB_USB_FNL_REG_USB_FN_Pos

#define USB_USB_FNL_REG_USB_FN_Pos   (0UL)

USB USB_FNL_REG: USB_FN (Bit 0)

Definition at line 11551 of file DA14680BA.h.

◆ USB_USB_FWEV_REG_USB_RXWARN31_Msk

#define USB_USB_FWEV_REG_USB_RXWARN31_Msk   (0x70UL)

USB USB_FWEV_REG: USB_RXWARN31 (Bitfield-Mask: 0x07)

Definition at line 11532 of file DA14680BA.h.

◆ USB_USB_FWEV_REG_USB_RXWARN31_Pos

#define USB_USB_FWEV_REG_USB_RXWARN31_Pos   (4UL)

USB USB_FWEV_REG: USB_RXWARN31 (Bit 4)

Definition at line 11531 of file DA14680BA.h.

◆ USB_USB_FWEV_REG_USB_TXWARN31_Msk

#define USB_USB_FWEV_REG_USB_TXWARN31_Msk   (0x7UL)

USB USB_FWEV_REG: USB_TXWARN31 (Bitfield-Mask: 0x07)

Definition at line 11530 of file DA14680BA.h.

◆ USB_USB_FWEV_REG_USB_TXWARN31_Pos

#define USB_USB_FWEV_REG_USB_TXWARN31_Pos   (0UL)

USB USB_FWEV_REG: USB_TXWARN31 (Bit 0)

Definition at line 11529 of file DA14680BA.h.

◆ USB_USB_FWMSK_REG_USB_M_RXWARN31_Msk

#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Msk   (0x70UL)

USB USB_FWMSK_REG: USB_M_RXWARN31 (Bitfield-Mask: 0x07)

Definition at line 11538 of file DA14680BA.h.

◆ USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos

#define USB_USB_FWMSK_REG_USB_M_RXWARN31_Pos   (4UL)

USB USB_FWMSK_REG: USB_M_RXWARN31 (Bit 4)

Definition at line 11537 of file DA14680BA.h.

◆ USB_USB_FWMSK_REG_USB_M_TXWARN31_Msk

#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Msk   (0x7UL)

USB USB_FWMSK_REG: USB_M_TXWARN31 (Bitfield-Mask: 0x07)

Definition at line 11536 of file DA14680BA.h.

◆ USB_USB_FWMSK_REG_USB_M_TXWARN31_Pos

#define USB_USB_FWMSK_REG_USB_M_TXWARN31_Pos   (0UL)

USB USB_FWMSK_REG: USB_M_TXWARN31 (Bit 0)

Definition at line 11535 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_ALT_Msk

#define USB_USB_MAEV_REG_USB_ALT_Msk   (0x2UL)

USB USB_MAEV_REG: USB_ALT (Bitfield-Mask: 0x01)

Definition at line 11420 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_ALT_Pos

#define USB_USB_MAEV_REG_USB_ALT_Pos   (1UL)

USB USB_MAEV_REG: USB_ALT (Bit 1)

Definition at line 11419 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_CH_EV_Msk

#define USB_USB_MAEV_REG_USB_CH_EV_Msk   (0x800UL)

USB USB_MAEV_REG: USB_CH_EV (Bitfield-Mask: 0x01)

Definition at line 11440 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_CH_EV_Pos

#define USB_USB_MAEV_REG_USB_CH_EV_Pos   (11UL)

USB USB_MAEV_REG: USB_CH_EV (Bit 11)

Definition at line 11439 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_EP0_NAK_Msk

#define USB_USB_MAEV_REG_USB_EP0_NAK_Msk   (0x400UL)

USB USB_MAEV_REG: USB_EP0_NAK (Bitfield-Mask: 0x01)

Definition at line 11438 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_EP0_NAK_Pos

#define USB_USB_MAEV_REG_USB_EP0_NAK_Pos   (10UL)

USB USB_MAEV_REG: USB_EP0_NAK (Bit 10)

Definition at line 11437 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_EP0_RX_Msk

#define USB_USB_MAEV_REG_USB_EP0_RX_Msk   (0x200UL)

USB USB_MAEV_REG: USB_EP0_RX (Bitfield-Mask: 0x01)

Definition at line 11436 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_EP0_RX_Pos

#define USB_USB_MAEV_REG_USB_EP0_RX_Pos   (9UL)

USB USB_MAEV_REG: USB_EP0_RX (Bit 9)

Definition at line 11435 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_EP0_TX_Msk

#define USB_USB_MAEV_REG_USB_EP0_TX_Msk   (0x100UL)

USB USB_MAEV_REG: USB_EP0_TX (Bitfield-Mask: 0x01)

Definition at line 11434 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_EP0_TX_Pos

#define USB_USB_MAEV_REG_USB_EP0_TX_Pos   (8UL)

USB USB_MAEV_REG: USB_EP0_TX (Bit 8)

Definition at line 11433 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_FRAME_Msk

#define USB_USB_MAEV_REG_USB_FRAME_Msk   (0x8UL)

USB USB_MAEV_REG: USB_FRAME (Bitfield-Mask: 0x01)

Definition at line 11424 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_FRAME_Pos

#define USB_USB_MAEV_REG_USB_FRAME_Pos   (3UL)

USB USB_MAEV_REG: USB_FRAME (Bit 3)

Definition at line 11423 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_INTR_Msk

#define USB_USB_MAEV_REG_USB_INTR_Msk   (0x80UL)

USB USB_MAEV_REG: USB_INTR (Bitfield-Mask: 0x01)

Definition at line 11432 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_INTR_Pos

#define USB_USB_MAEV_REG_USB_INTR_Pos   (7UL)

USB USB_MAEV_REG: USB_INTR (Bit 7)

Definition at line 11431 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_NAK_Msk

#define USB_USB_MAEV_REG_USB_NAK_Msk   (0x10UL)

USB USB_MAEV_REG: USB_NAK (Bitfield-Mask: 0x01)

Definition at line 11426 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_NAK_Pos

#define USB_USB_MAEV_REG_USB_NAK_Pos   (4UL)

USB USB_MAEV_REG: USB_NAK (Bit 4)

Definition at line 11425 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_RX_EV_Msk

#define USB_USB_MAEV_REG_USB_RX_EV_Msk   (0x40UL)

USB USB_MAEV_REG: USB_RX_EV (Bitfield-Mask: 0x01)

Definition at line 11430 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_RX_EV_Pos

#define USB_USB_MAEV_REG_USB_RX_EV_Pos   (6UL)

USB USB_MAEV_REG: USB_RX_EV (Bit 6)

Definition at line 11429 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_TX_EV_Msk

#define USB_USB_MAEV_REG_USB_TX_EV_Msk   (0x4UL)

USB USB_MAEV_REG: USB_TX_EV (Bitfield-Mask: 0x01)

Definition at line 11422 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_TX_EV_Pos

#define USB_USB_MAEV_REG_USB_TX_EV_Pos   (2UL)

USB USB_MAEV_REG: USB_TX_EV (Bit 2)

Definition at line 11421 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_ULD_Msk

#define USB_USB_MAEV_REG_USB_ULD_Msk   (0x20UL)

USB USB_MAEV_REG: USB_ULD (Bitfield-Mask: 0x01)

Definition at line 11428 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_ULD_Pos

#define USB_USB_MAEV_REG_USB_ULD_Pos   (5UL)

USB USB_MAEV_REG: USB_ULD (Bit 5)

Definition at line 11427 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_WARN_Msk

#define USB_USB_MAEV_REG_USB_WARN_Msk   (0x1UL)

USB USB_MAEV_REG: USB_WARN (Bitfield-Mask: 0x01)

Definition at line 11418 of file DA14680BA.h.

◆ USB_USB_MAEV_REG_USB_WARN_Pos

#define USB_USB_MAEV_REG_USB_WARN_Pos   (0UL)

USB USB_MAEV_REG: USB_WARN (Bit 0)

Definition at line 11417 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_ALT_Msk

#define USB_USB_MAMSK_REG_USB_M_ALT_Msk   (0x2UL)

USB USB_MAMSK_REG: USB_M_ALT (Bitfield-Mask: 0x01)

Definition at line 11446 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_ALT_Pos

#define USB_USB_MAMSK_REG_USB_M_ALT_Pos   (1UL)

USB USB_MAMSK_REG: USB_M_ALT (Bit 1)

Definition at line 11445 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_CH_EV_Msk

#define USB_USB_MAMSK_REG_USB_M_CH_EV_Msk   (0x800UL)

USB USB_MAMSK_REG: USB_M_CH_EV (Bitfield-Mask: 0x01)

Definition at line 11466 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_CH_EV_Pos

#define USB_USB_MAMSK_REG_USB_M_CH_EV_Pos   (11UL)

USB USB_MAMSK_REG: USB_M_CH_EV (Bit 11)

Definition at line 11465 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_EP0_NAK_Msk

#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Msk   (0x400UL)

USB USB_MAMSK_REG: USB_M_EP0_NAK (Bitfield-Mask: 0x01)

Definition at line 11464 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_EP0_NAK_Pos

#define USB_USB_MAMSK_REG_USB_M_EP0_NAK_Pos   (10UL)

USB USB_MAMSK_REG: USB_M_EP0_NAK (Bit 10)

Definition at line 11463 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_EP0_RX_Msk

#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Msk   (0x200UL)

USB USB_MAMSK_REG: USB_M_EP0_RX (Bitfield-Mask: 0x01)

Definition at line 11462 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_EP0_RX_Pos

#define USB_USB_MAMSK_REG_USB_M_EP0_RX_Pos   (9UL)

USB USB_MAMSK_REG: USB_M_EP0_RX (Bit 9)

Definition at line 11461 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_EP0_TX_Msk

#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Msk   (0x100UL)

USB USB_MAMSK_REG: USB_M_EP0_TX (Bitfield-Mask: 0x01)

Definition at line 11460 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_EP0_TX_Pos

#define USB_USB_MAMSK_REG_USB_M_EP0_TX_Pos   (8UL)

USB USB_MAMSK_REG: USB_M_EP0_TX (Bit 8)

Definition at line 11459 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_FRAME_Msk

#define USB_USB_MAMSK_REG_USB_M_FRAME_Msk   (0x8UL)

USB USB_MAMSK_REG: USB_M_FRAME (Bitfield-Mask: 0x01)

Definition at line 11450 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_FRAME_Pos

#define USB_USB_MAMSK_REG_USB_M_FRAME_Pos   (3UL)

USB USB_MAMSK_REG: USB_M_FRAME (Bit 3)

Definition at line 11449 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_INTR_Msk

#define USB_USB_MAMSK_REG_USB_M_INTR_Msk   (0x80UL)

USB USB_MAMSK_REG: USB_M_INTR (Bitfield-Mask: 0x01)

Definition at line 11458 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_INTR_Pos

#define USB_USB_MAMSK_REG_USB_M_INTR_Pos   (7UL)

USB USB_MAMSK_REG: USB_M_INTR (Bit 7)

Definition at line 11457 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_NAK_Msk

#define USB_USB_MAMSK_REG_USB_M_NAK_Msk   (0x10UL)

USB USB_MAMSK_REG: USB_M_NAK (Bitfield-Mask: 0x01)

Definition at line 11452 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_NAK_Pos

#define USB_USB_MAMSK_REG_USB_M_NAK_Pos   (4UL)

USB USB_MAMSK_REG: USB_M_NAK (Bit 4)

Definition at line 11451 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_RX_EV_Msk

#define USB_USB_MAMSK_REG_USB_M_RX_EV_Msk   (0x40UL)

USB USB_MAMSK_REG: USB_M_RX_EV (Bitfield-Mask: 0x01)

Definition at line 11456 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_RX_EV_Pos

#define USB_USB_MAMSK_REG_USB_M_RX_EV_Pos   (6UL)

USB USB_MAMSK_REG: USB_M_RX_EV (Bit 6)

Definition at line 11455 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_TX_EV_Msk

#define USB_USB_MAMSK_REG_USB_M_TX_EV_Msk   (0x4UL)

USB USB_MAMSK_REG: USB_M_TX_EV (Bitfield-Mask: 0x01)

Definition at line 11448 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_TX_EV_Pos

#define USB_USB_MAMSK_REG_USB_M_TX_EV_Pos   (2UL)

USB USB_MAMSK_REG: USB_M_TX_EV (Bit 2)

Definition at line 11447 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_ULD_Msk

#define USB_USB_MAMSK_REG_USB_M_ULD_Msk   (0x20UL)

USB USB_MAMSK_REG: USB_M_ULD (Bitfield-Mask: 0x01)

Definition at line 11454 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_ULD_Pos

#define USB_USB_MAMSK_REG_USB_M_ULD_Pos   (5UL)

USB USB_MAMSK_REG: USB_M_ULD (Bit 5)

Definition at line 11453 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_WARN_Msk

#define USB_USB_MAMSK_REG_USB_M_WARN_Msk   (0x1UL)

USB USB_MAMSK_REG: USB_M_WARN (Bitfield-Mask: 0x01)

Definition at line 11444 of file DA14680BA.h.

◆ USB_USB_MAMSK_REG_USB_M_WARN_Pos

#define USB_USB_MAMSK_REG_USB_M_WARN_Pos   (0UL)

USB USB_MAMSK_REG: USB_M_WARN (Bit 0)

Definition at line 11443 of file DA14680BA.h.

◆ USB_USB_MCTRL_REG_LSMODE_Msk

#define USB_USB_MCTRL_REG_LSMODE_Msk   (0x10UL)

USB USB_MCTRL_REG: LSMODE (Bitfield-Mask: 0x01)

Definition at line 11372 of file DA14680BA.h.

◆ USB_USB_MCTRL_REG_LSMODE_Pos

#define USB_USB_MCTRL_REG_LSMODE_Pos   (4UL)

USB USB_MCTRL_REG: LSMODE (Bit 4)

Definition at line 11371 of file DA14680BA.h.

◆ USB_USB_MCTRL_REG_USB_DBG_Msk

#define USB_USB_MCTRL_REG_USB_DBG_Msk   (0x2UL)

USB USB_MCTRL_REG: USB_DBG (Bitfield-Mask: 0x01)

Definition at line 11368 of file DA14680BA.h.

◆ USB_USB_MCTRL_REG_USB_DBG_Pos

#define USB_USB_MCTRL_REG_USB_DBG_Pos   (1UL)

USB USB_MCTRL_REG: USB_DBG (Bit 1)

Definition at line 11367 of file DA14680BA.h.

◆ USB_USB_MCTRL_REG_USB_NAT_Msk

#define USB_USB_MCTRL_REG_USB_NAT_Msk   (0x8UL)

USB USB_MCTRL_REG: USB_NAT (Bitfield-Mask: 0x01)

Definition at line 11370 of file DA14680BA.h.

◆ USB_USB_MCTRL_REG_USB_NAT_Pos

#define USB_USB_MCTRL_REG_USB_NAT_Pos   (3UL)

USB USB_MCTRL_REG: USB_NAT (Bit 3)

Definition at line 11369 of file DA14680BA.h.

◆ USB_USB_MCTRL_REG_USBEN_Msk

#define USB_USB_MCTRL_REG_USBEN_Msk   (0x1UL)

USB USB_MCTRL_REG: USBEN (Bitfield-Mask: 0x01)

Definition at line 11366 of file DA14680BA.h.

◆ USB_USB_MCTRL_REG_USBEN_Pos

#define USB_USB_MCTRL_REG_USBEN_Pos   (0UL)

USB USB_MCTRL_REG: USBEN (Bit 0)

Definition at line 11365 of file DA14680BA.h.

◆ USB_USB_NAKEV_REG_USB_IN31_Msk

#define USB_USB_NAKEV_REG_USB_IN31_Msk   (0x7UL)

USB USB_NAKEV_REG: USB_IN31 (Bitfield-Mask: 0x07)

Definition at line 11518 of file DA14680BA.h.

◆ USB_USB_NAKEV_REG_USB_IN31_Pos

#define USB_USB_NAKEV_REG_USB_IN31_Pos   (0UL)

USB USB_NAKEV_REG: USB_IN31 (Bit 0)

Definition at line 11517 of file DA14680BA.h.

◆ USB_USB_NAKEV_REG_USB_OUT31_Msk

#define USB_USB_NAKEV_REG_USB_OUT31_Msk   (0x70UL)

USB USB_NAKEV_REG: USB_OUT31 (Bitfield-Mask: 0x07)

Definition at line 11520 of file DA14680BA.h.

◆ USB_USB_NAKEV_REG_USB_OUT31_Pos

#define USB_USB_NAKEV_REG_USB_OUT31_Pos   (4UL)

USB USB_NAKEV_REG: USB_OUT31 (Bit 4)

Definition at line 11519 of file DA14680BA.h.

◆ USB_USB_NAKMSK_REG_USB_M_IN31_Msk

#define USB_USB_NAKMSK_REG_USB_M_IN31_Msk   (0x7UL)

USB USB_NAKMSK_REG: USB_M_IN31 (Bitfield-Mask: 0x07)

Definition at line 11524 of file DA14680BA.h.

◆ USB_USB_NAKMSK_REG_USB_M_IN31_Pos

#define USB_USB_NAKMSK_REG_USB_M_IN31_Pos   (0UL)

USB USB_NAKMSK_REG: USB_M_IN31 (Bit 0)

Definition at line 11523 of file DA14680BA.h.

◆ USB_USB_NAKMSK_REG_USB_M_OUT31_Msk

#define USB_USB_NAKMSK_REG_USB_M_OUT31_Msk   (0x70UL)

USB USB_NAKMSK_REG: USB_M_OUT31 (Bitfield-Mask: 0x07)

Definition at line 11526 of file DA14680BA.h.

◆ USB_USB_NAKMSK_REG_USB_M_OUT31_Pos

#define USB_USB_NAKMSK_REG_USB_M_OUT31_Pos   (4UL)

USB USB_NAKMSK_REG: USB_M_OUT31 (Bit 4)

Definition at line 11525 of file DA14680BA.h.

◆ USB_USB_NFSR_REG_USB_NFS_Msk

#define USB_USB_NFSR_REG_USB_NFS_Msk   (0x3UL)

USB USB_NFSR_REG: USB_NFS (Bitfield-Mask: 0x03)

Definition at line 11414 of file DA14680BA.h.

◆ USB_USB_NFSR_REG_USB_NFS_Pos

#define USB_USB_NFSR_REG_USB_NFS_Pos   (0UL)

USB USB_NFSR_REG: USB_NFS (Bit 0)

Definition at line 11413 of file DA14680BA.h.

◆ USB_USB_RXC0_REG_USB_FLUSH_Msk

#define USB_USB_RXC0_REG_USB_FLUSH_Msk   (0x8UL)

USB USB_RXC0_REG: USB_FLUSH (Bitfield-Mask: 0x01)

Definition at line 11628 of file DA14680BA.h.

◆ USB_USB_RXC0_REG_USB_FLUSH_Pos

#define USB_USB_RXC0_REG_USB_FLUSH_Pos   (3UL)

USB USB_RXC0_REG: USB_FLUSH (Bit 3)

Definition at line 11627 of file DA14680BA.h.

◆ USB_USB_RXC0_REG_USB_IGN_OUT_Msk

#define USB_USB_RXC0_REG_USB_IGN_OUT_Msk   (0x2UL)

USB USB_RXC0_REG: USB_IGN_OUT (Bitfield-Mask: 0x01)

Definition at line 11624 of file DA14680BA.h.

◆ USB_USB_RXC0_REG_USB_IGN_OUT_Pos

#define USB_USB_RXC0_REG_USB_IGN_OUT_Pos   (1UL)

USB USB_RXC0_REG: USB_IGN_OUT (Bit 1)

Definition at line 11623 of file DA14680BA.h.

◆ USB_USB_RXC0_REG_USB_IGN_SETUP_Msk

#define USB_USB_RXC0_REG_USB_IGN_SETUP_Msk   (0x4UL)

USB USB_RXC0_REG: USB_IGN_SETUP (Bitfield-Mask: 0x01)

Definition at line 11626 of file DA14680BA.h.

◆ USB_USB_RXC0_REG_USB_IGN_SETUP_Pos

#define USB_USB_RXC0_REG_USB_IGN_SETUP_Pos   (2UL)

USB USB_RXC0_REG: USB_IGN_SETUP (Bit 2)

Definition at line 11625 of file DA14680BA.h.

◆ USB_USB_RXC0_REG_USB_RX_EN_Msk

#define USB_USB_RXC0_REG_USB_RX_EN_Msk   (0x1UL)

USB USB_RXC0_REG: USB_RX_EN (Bitfield-Mask: 0x01)

Definition at line 11622 of file DA14680BA.h.

◆ USB_USB_RXC0_REG_USB_RX_EN_Pos

#define USB_USB_RXC0_REG_USB_RX_EN_Pos   (0UL)

USB USB_RXC0_REG: USB_RX_EN (Bit 0)

Definition at line 11621 of file DA14680BA.h.

◆ USB_USB_RXC1_REG_USB_FLUSH_Msk

#define USB_USB_RXC1_REG_USB_FLUSH_Msk   (0x8UL)

USB USB_RXC1_REG: USB_FLUSH (Bitfield-Mask: 0x01)

Definition at line 11702 of file DA14680BA.h.

◆ USB_USB_RXC1_REG_USB_FLUSH_Pos

#define USB_USB_RXC1_REG_USB_FLUSH_Pos   (3UL)

USB USB_RXC1_REG: USB_FLUSH (Bit 3)

Definition at line 11701 of file DA14680BA.h.

◆ USB_USB_RXC1_REG_USB_IGN_SETUP_Msk

#define USB_USB_RXC1_REG_USB_IGN_SETUP_Msk   (0x4UL)

USB USB_RXC1_REG: USB_IGN_SETUP (Bitfield-Mask: 0x01)

Definition at line 11700 of file DA14680BA.h.

◆ USB_USB_RXC1_REG_USB_IGN_SETUP_Pos

#define USB_USB_RXC1_REG_USB_IGN_SETUP_Pos   (2UL)

USB USB_RXC1_REG: USB_IGN_SETUP (Bit 2)

Definition at line 11699 of file DA14680BA.h.

◆ USB_USB_RXC1_REG_USB_RFWL_Msk

#define USB_USB_RXC1_REG_USB_RFWL_Msk   (0x60UL)

USB USB_RXC1_REG: USB_RFWL (Bitfield-Mask: 0x03)

Definition at line 11704 of file DA14680BA.h.

◆ USB_USB_RXC1_REG_USB_RFWL_Pos

#define USB_USB_RXC1_REG_USB_RFWL_Pos   (5UL)

USB USB_RXC1_REG: USB_RFWL (Bit 5)

Definition at line 11703 of file DA14680BA.h.

◆ USB_USB_RXC1_REG_USB_RX_EN_Msk

#define USB_USB_RXC1_REG_USB_RX_EN_Msk   (0x1UL)

USB USB_RXC1_REG: USB_RX_EN (Bitfield-Mask: 0x01)

Definition at line 11698 of file DA14680BA.h.

◆ USB_USB_RXC1_REG_USB_RX_EN_Pos

#define USB_USB_RXC1_REG_USB_RX_EN_Pos   (0UL)

USB USB_RXC1_REG: USB_RX_EN (Bit 0)

Definition at line 11697 of file DA14680BA.h.

◆ USB_USB_RXC2_REG_USB_FLUSH_Msk

#define USB_USB_RXC2_REG_USB_FLUSH_Msk   (0x8UL)

USB USB_RXC2_REG: USB_FLUSH (Bitfield-Mask: 0x01)

Definition at line 11778 of file DA14680BA.h.

◆ USB_USB_RXC2_REG_USB_FLUSH_Pos

#define USB_USB_RXC2_REG_USB_FLUSH_Pos   (3UL)

USB USB_RXC2_REG: USB_FLUSH (Bit 3)

Definition at line 11777 of file DA14680BA.h.

◆ USB_USB_RXC2_REG_USB_IGN_SETUP_Msk

#define USB_USB_RXC2_REG_USB_IGN_SETUP_Msk   (0x4UL)

USB USB_RXC2_REG: USB_IGN_SETUP (Bitfield-Mask: 0x01)

Definition at line 11776 of file DA14680BA.h.

◆ USB_USB_RXC2_REG_USB_IGN_SETUP_Pos

#define USB_USB_RXC2_REG_USB_IGN_SETUP_Pos   (2UL)

USB USB_RXC2_REG: USB_IGN_SETUP (Bit 2)

Definition at line 11775 of file DA14680BA.h.

◆ USB_USB_RXC2_REG_USB_RFWL_Msk

#define USB_USB_RXC2_REG_USB_RFWL_Msk   (0x60UL)

USB USB_RXC2_REG: USB_RFWL (Bitfield-Mask: 0x03)

Definition at line 11780 of file DA14680BA.h.

◆ USB_USB_RXC2_REG_USB_RFWL_Pos

#define USB_USB_RXC2_REG_USB_RFWL_Pos   (5UL)

USB USB_RXC2_REG: USB_RFWL (Bit 5)

Definition at line 11779 of file DA14680BA.h.

◆ USB_USB_RXC2_REG_USB_RX_EN_Msk

#define USB_USB_RXC2_REG_USB_RX_EN_Msk   (0x1UL)

USB USB_RXC2_REG: USB_RX_EN (Bitfield-Mask: 0x01)

Definition at line 11774 of file DA14680BA.h.

◆ USB_USB_RXC2_REG_USB_RX_EN_Pos

#define USB_USB_RXC2_REG_USB_RX_EN_Pos   (0UL)

USB USB_RXC2_REG: USB_RX_EN (Bit 0)

Definition at line 11773 of file DA14680BA.h.

◆ USB_USB_RXC3_REG_USB_FLUSH_Msk

#define USB_USB_RXC3_REG_USB_FLUSH_Msk   (0x8UL)

USB USB_RXC3_REG: USB_FLUSH (Bitfield-Mask: 0x01)

Definition at line 11854 of file DA14680BA.h.

◆ USB_USB_RXC3_REG_USB_FLUSH_Pos

#define USB_USB_RXC3_REG_USB_FLUSH_Pos   (3UL)

USB USB_RXC3_REG: USB_FLUSH (Bit 3)

Definition at line 11853 of file DA14680BA.h.

◆ USB_USB_RXC3_REG_USB_IGN_SETUP_Msk

#define USB_USB_RXC3_REG_USB_IGN_SETUP_Msk   (0x4UL)

USB USB_RXC3_REG: USB_IGN_SETUP (Bitfield-Mask: 0x01)

Definition at line 11852 of file DA14680BA.h.

◆ USB_USB_RXC3_REG_USB_IGN_SETUP_Pos

#define USB_USB_RXC3_REG_USB_IGN_SETUP_Pos   (2UL)

USB USB_RXC3_REG: USB_IGN_SETUP (Bit 2)

Definition at line 11851 of file DA14680BA.h.

◆ USB_USB_RXC3_REG_USB_RFWL_Msk

#define USB_USB_RXC3_REG_USB_RFWL_Msk   (0x60UL)

USB USB_RXC3_REG: USB_RFWL (Bitfield-Mask: 0x03)

Definition at line 11856 of file DA14680BA.h.

◆ USB_USB_RXC3_REG_USB_RFWL_Pos

#define USB_USB_RXC3_REG_USB_RFWL_Pos   (5UL)

USB USB_RXC3_REG: USB_RFWL (Bit 5)

Definition at line 11855 of file DA14680BA.h.

◆ USB_USB_RXC3_REG_USB_RX_EN_Msk

#define USB_USB_RXC3_REG_USB_RX_EN_Msk   (0x1UL)

USB USB_RXC3_REG: USB_RX_EN (Bitfield-Mask: 0x01)

Definition at line 11850 of file DA14680BA.h.

◆ USB_USB_RXC3_REG_USB_RX_EN_Pos

#define USB_USB_RXC3_REG_USB_RX_EN_Pos   (0UL)

USB USB_RXC3_REG: USB_RX_EN (Bit 0)

Definition at line 11849 of file DA14680BA.h.

◆ USB_USB_RXD0_REG_USB_RXFD_Msk

#define USB_USB_RXD0_REG_USB_RXFD_Msk   (0xffUL)

USB USB_RXD0_REG: USB_RXFD (Bitfield-Mask: 0xff)

Definition at line 11608 of file DA14680BA.h.

◆ USB_USB_RXD0_REG_USB_RXFD_Pos

#define USB_USB_RXD0_REG_USB_RXFD_Pos   (0UL)

USB USB_RXD0_REG: USB_RXFD (Bit 0)

Definition at line 11607 of file DA14680BA.h.

◆ USB_USB_RXD1_REG_USB_RXFD_Msk

#define USB_USB_RXD1_REG_USB_RXFD_Msk   (0xffUL)

USB USB_RXD1_REG: USB_RXFD (Bitfield-Mask: 0xff)

Definition at line 11682 of file DA14680BA.h.

◆ USB_USB_RXD1_REG_USB_RXFD_Pos

#define USB_USB_RXD1_REG_USB_RXFD_Pos   (0UL)

USB USB_RXD1_REG: USB_RXFD (Bit 0)

Definition at line 11681 of file DA14680BA.h.

◆ USB_USB_RXD2_REG_USB_RXFD_Msk

#define USB_USB_RXD2_REG_USB_RXFD_Msk   (0xffUL)

USB USB_RXD2_REG: USB_RXFD (Bitfield-Mask: 0xff)

Definition at line 11758 of file DA14680BA.h.

◆ USB_USB_RXD2_REG_USB_RXFD_Pos

#define USB_USB_RXD2_REG_USB_RXFD_Pos   (0UL)

USB USB_RXD2_REG: USB_RXFD (Bit 0)

Definition at line 11757 of file DA14680BA.h.

◆ USB_USB_RXD3_REG_USB_RXFD_Msk

#define USB_USB_RXD3_REG_USB_RXFD_Msk   (0xffUL)

USB USB_RXD3_REG: USB_RXFD (Bitfield-Mask: 0xff)

Definition at line 11834 of file DA14680BA.h.

◆ USB_USB_RXD3_REG_USB_RXFD_Pos

#define USB_USB_RXD3_REG_USB_RXFD_Pos   (0UL)

USB USB_RXD3_REG: USB_RXFD (Bit 0)

Definition at line 11833 of file DA14680BA.h.

◆ USB_USB_RXEV_REG_USB_RXFIFO31_Msk

#define USB_USB_RXEV_REG_USB_RXFIFO31_Msk   (0x7UL)

USB USB_RXEV_REG: USB_RXFIFO31 (Bitfield-Mask: 0x07)

Definition at line 11506 of file DA14680BA.h.

◆ USB_USB_RXEV_REG_USB_RXFIFO31_Pos

#define USB_USB_RXEV_REG_USB_RXFIFO31_Pos   (0UL)

USB USB_RXEV_REG: USB_RXFIFO31 (Bit 0)

Definition at line 11505 of file DA14680BA.h.

◆ USB_USB_RXEV_REG_USB_RXOVRRN31_Msk

#define USB_USB_RXEV_REG_USB_RXOVRRN31_Msk   (0x70UL)

USB USB_RXEV_REG: USB_RXOVRRN31 (Bitfield-Mask: 0x07)

Definition at line 11508 of file DA14680BA.h.

◆ USB_USB_RXEV_REG_USB_RXOVRRN31_Pos

#define USB_USB_RXEV_REG_USB_RXOVRRN31_Pos   (4UL)

USB USB_RXEV_REG: USB_RXOVRRN31 (Bit 4)

Definition at line 11507 of file DA14680BA.h.

◆ USB_USB_RXMSK_REG_USB_M_RXFIFO31_Msk

#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Msk   (0x7UL)

USB USB_RXMSK_REG: USB_M_RXFIFO31 (Bitfield-Mask: 0x07)

Definition at line 11512 of file DA14680BA.h.

◆ USB_USB_RXMSK_REG_USB_M_RXFIFO31_Pos

#define USB_USB_RXMSK_REG_USB_M_RXFIFO31_Pos   (0UL)

USB USB_RXMSK_REG: USB_M_RXFIFO31 (Bit 0)

Definition at line 11511 of file DA14680BA.h.

◆ USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Msk

#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Msk   (0x70UL)

USB USB_RXMSK_REG: USB_M_RXOVRRN31 (Bitfield-Mask: 0x07)

Definition at line 11514 of file DA14680BA.h.

◆ USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Pos

#define USB_USB_RXMSK_REG_USB_M_RXOVRRN31_Pos   (4UL)

USB USB_RXMSK_REG: USB_M_RXOVRRN31 (Bit 4)

Definition at line 11513 of file DA14680BA.h.

◆ USB_USB_RXS0_REG_USB_RCOUNT_Msk

#define USB_USB_RXS0_REG_USB_RCOUNT_Msk   (0xfUL)

USB USB_RXS0_REG: USB_RCOUNT (Bitfield-Mask: 0x0f)

Definition at line 11612 of file DA14680BA.h.

◆ USB_USB_RXS0_REG_USB_RCOUNT_Pos

#define USB_USB_RXS0_REG_USB_RCOUNT_Pos   (0UL)

USB USB_RXS0_REG: USB_RCOUNT (Bit 0)

Definition at line 11611 of file DA14680BA.h.

◆ USB_USB_RXS0_REG_USB_RX_LAST_Msk

#define USB_USB_RXS0_REG_USB_RX_LAST_Msk   (0x10UL)

USB USB_RXS0_REG: USB_RX_LAST (Bitfield-Mask: 0x01)

Definition at line 11614 of file DA14680BA.h.

◆ USB_USB_RXS0_REG_USB_RX_LAST_Pos

#define USB_USB_RXS0_REG_USB_RX_LAST_Pos   (4UL)

USB USB_RXS0_REG: USB_RX_LAST (Bit 4)

Definition at line 11613 of file DA14680BA.h.

◆ USB_USB_RXS0_REG_USB_SETUP_Msk

#define USB_USB_RXS0_REG_USB_SETUP_Msk   (0x40UL)

USB USB_RXS0_REG: USB_SETUP (Bitfield-Mask: 0x01)

Definition at line 11618 of file DA14680BA.h.

◆ USB_USB_RXS0_REG_USB_SETUP_Pos

#define USB_USB_RXS0_REG_USB_SETUP_Pos   (6UL)

USB USB_RXS0_REG: USB_SETUP (Bit 6)

Definition at line 11617 of file DA14680BA.h.

◆ USB_USB_RXS0_REG_USB_TOGGLE_RX0_Msk

#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Msk   (0x20UL)

USB USB_RXS0_REG: USB_TOGGLE_RX0 (Bitfield-Mask: 0x01)

Definition at line 11616 of file DA14680BA.h.

◆ USB_USB_RXS0_REG_USB_TOGGLE_RX0_Pos

#define USB_USB_RXS0_REG_USB_TOGGLE_RX0_Pos   (5UL)

USB USB_RXS0_REG: USB_TOGGLE_RX0 (Bit 5)

Definition at line 11615 of file DA14680BA.h.

◆ USB_USB_RXS1_REG_USB_RCOUNT_Msk

#define USB_USB_RXS1_REG_USB_RCOUNT_Msk   (0xfUL)

USB USB_RXS1_REG: USB_RCOUNT (Bitfield-Mask: 0x0f)

Definition at line 11686 of file DA14680BA.h.

◆ USB_USB_RXS1_REG_USB_RCOUNT_Pos

#define USB_USB_RXS1_REG_USB_RCOUNT_Pos   (0UL)

USB USB_RXS1_REG: USB_RCOUNT (Bit 0)

Definition at line 11685 of file DA14680BA.h.

◆ USB_USB_RXS1_REG_USB_RX_ERR_Msk

#define USB_USB_RXS1_REG_USB_RX_ERR_Msk   (0x80UL)

USB USB_RXS1_REG: USB_RX_ERR (Bitfield-Mask: 0x01)

Definition at line 11694 of file DA14680BA.h.

◆ USB_USB_RXS1_REG_USB_RX_ERR_Pos

#define USB_USB_RXS1_REG_USB_RX_ERR_Pos   (7UL)

USB USB_RXS1_REG: USB_RX_ERR (Bit 7)

Definition at line 11693 of file DA14680BA.h.

◆ USB_USB_RXS1_REG_USB_RX_LAST_Msk

#define USB_USB_RXS1_REG_USB_RX_LAST_Msk   (0x10UL)

USB USB_RXS1_REG: USB_RX_LAST (Bitfield-Mask: 0x01)

Definition at line 11688 of file DA14680BA.h.

◆ USB_USB_RXS1_REG_USB_RX_LAST_Pos

#define USB_USB_RXS1_REG_USB_RX_LAST_Pos   (4UL)

USB USB_RXS1_REG: USB_RX_LAST (Bit 4)

Definition at line 11687 of file DA14680BA.h.

◆ USB_USB_RXS1_REG_USB_SETUP_Msk

#define USB_USB_RXS1_REG_USB_SETUP_Msk   (0x40UL)

USB USB_RXS1_REG: USB_SETUP (Bitfield-Mask: 0x01)

Definition at line 11692 of file DA14680BA.h.

◆ USB_USB_RXS1_REG_USB_SETUP_Pos

#define USB_USB_RXS1_REG_USB_SETUP_Pos   (6UL)

USB USB_RXS1_REG: USB_SETUP (Bit 6)

Definition at line 11691 of file DA14680BA.h.

◆ USB_USB_RXS1_REG_USB_TOGGLE_RX_Msk

#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Msk   (0x20UL)

USB USB_RXS1_REG: USB_TOGGLE_RX (Bitfield-Mask: 0x01)

Definition at line 11690 of file DA14680BA.h.

◆ USB_USB_RXS1_REG_USB_TOGGLE_RX_Pos

#define USB_USB_RXS1_REG_USB_TOGGLE_RX_Pos   (5UL)

USB USB_RXS1_REG: USB_TOGGLE_RX (Bit 5)

Definition at line 11689 of file DA14680BA.h.

◆ USB_USB_RXS2_REG_USB_RCOUNT_Msk

#define USB_USB_RXS2_REG_USB_RCOUNT_Msk   (0xfUL)

USB USB_RXS2_REG: USB_RCOUNT (Bitfield-Mask: 0x0f)

Definition at line 11762 of file DA14680BA.h.

◆ USB_USB_RXS2_REG_USB_RCOUNT_Pos

#define USB_USB_RXS2_REG_USB_RCOUNT_Pos   (0UL)

USB USB_RXS2_REG: USB_RCOUNT (Bit 0)

Definition at line 11761 of file DA14680BA.h.

◆ USB_USB_RXS2_REG_USB_RX_ERR_Msk

#define USB_USB_RXS2_REG_USB_RX_ERR_Msk   (0x80UL)

USB USB_RXS2_REG: USB_RX_ERR (Bitfield-Mask: 0x01)

Definition at line 11770 of file DA14680BA.h.

◆ USB_USB_RXS2_REG_USB_RX_ERR_Pos

#define USB_USB_RXS2_REG_USB_RX_ERR_Pos   (7UL)

USB USB_RXS2_REG: USB_RX_ERR (Bit 7)

Definition at line 11769 of file DA14680BA.h.

◆ USB_USB_RXS2_REG_USB_RX_LAST_Msk

#define USB_USB_RXS2_REG_USB_RX_LAST_Msk   (0x10UL)

USB USB_RXS2_REG: USB_RX_LAST (Bitfield-Mask: 0x01)

Definition at line 11764 of file DA14680BA.h.

◆ USB_USB_RXS2_REG_USB_RX_LAST_Pos

#define USB_USB_RXS2_REG_USB_RX_LAST_Pos   (4UL)

USB USB_RXS2_REG: USB_RX_LAST (Bit 4)

Definition at line 11763 of file DA14680BA.h.

◆ USB_USB_RXS2_REG_USB_SETUP_Msk

#define USB_USB_RXS2_REG_USB_SETUP_Msk   (0x40UL)

USB USB_RXS2_REG: USB_SETUP (Bitfield-Mask: 0x01)

Definition at line 11768 of file DA14680BA.h.

◆ USB_USB_RXS2_REG_USB_SETUP_Pos

#define USB_USB_RXS2_REG_USB_SETUP_Pos   (6UL)

USB USB_RXS2_REG: USB_SETUP (Bit 6)

Definition at line 11767 of file DA14680BA.h.

◆ USB_USB_RXS2_REG_USB_TOGGLE_RX_Msk

#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Msk   (0x20UL)

USB USB_RXS2_REG: USB_TOGGLE_RX (Bitfield-Mask: 0x01)

Definition at line 11766 of file DA14680BA.h.

◆ USB_USB_RXS2_REG_USB_TOGGLE_RX_Pos

#define USB_USB_RXS2_REG_USB_TOGGLE_RX_Pos   (5UL)

USB USB_RXS2_REG: USB_TOGGLE_RX (Bit 5)

Definition at line 11765 of file DA14680BA.h.

◆ USB_USB_RXS3_REG_USB_RCOUNT_Msk

#define USB_USB_RXS3_REG_USB_RCOUNT_Msk   (0xfUL)

USB USB_RXS3_REG: USB_RCOUNT (Bitfield-Mask: 0x0f)

Definition at line 11838 of file DA14680BA.h.

◆ USB_USB_RXS3_REG_USB_RCOUNT_Pos

#define USB_USB_RXS3_REG_USB_RCOUNT_Pos   (0UL)

USB USB_RXS3_REG: USB_RCOUNT (Bit 0)

Definition at line 11837 of file DA14680BA.h.

◆ USB_USB_RXS3_REG_USB_RX_ERR_Msk

#define USB_USB_RXS3_REG_USB_RX_ERR_Msk   (0x80UL)

USB USB_RXS3_REG: USB_RX_ERR (Bitfield-Mask: 0x01)

Definition at line 11846 of file DA14680BA.h.

◆ USB_USB_RXS3_REG_USB_RX_ERR_Pos

#define USB_USB_RXS3_REG_USB_RX_ERR_Pos   (7UL)

USB USB_RXS3_REG: USB_RX_ERR (Bit 7)

Definition at line 11845 of file DA14680BA.h.

◆ USB_USB_RXS3_REG_USB_RX_LAST_Msk

#define USB_USB_RXS3_REG_USB_RX_LAST_Msk   (0x10UL)

USB USB_RXS3_REG: USB_RX_LAST (Bitfield-Mask: 0x01)

Definition at line 11840 of file DA14680BA.h.

◆ USB_USB_RXS3_REG_USB_RX_LAST_Pos

#define USB_USB_RXS3_REG_USB_RX_LAST_Pos   (4UL)

USB USB_RXS3_REG: USB_RX_LAST (Bit 4)

Definition at line 11839 of file DA14680BA.h.

◆ USB_USB_RXS3_REG_USB_SETUP_Msk

#define USB_USB_RXS3_REG_USB_SETUP_Msk   (0x40UL)

USB USB_RXS3_REG: USB_SETUP (Bitfield-Mask: 0x01)

Definition at line 11844 of file DA14680BA.h.

◆ USB_USB_RXS3_REG_USB_SETUP_Pos

#define USB_USB_RXS3_REG_USB_SETUP_Pos   (6UL)

USB USB_RXS3_REG: USB_SETUP (Bit 6)

Definition at line 11843 of file DA14680BA.h.

◆ USB_USB_RXS3_REG_USB_TOGGLE_RX_Msk

#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Msk   (0x20UL)

USB USB_RXS3_REG: USB_TOGGLE_RX (Bitfield-Mask: 0x01)

Definition at line 11842 of file DA14680BA.h.

◆ USB_USB_RXS3_REG_USB_TOGGLE_RX_Pos

#define USB_USB_RXS3_REG_USB_TOGGLE_RX_Pos   (5UL)

USB USB_RXS3_REG: USB_TOGGLE_RX (Bit 5)

Definition at line 11841 of file DA14680BA.h.

◆ USB_USB_TCR_REG_USB_CADJ_Msk

#define USB_USB_TCR_REG_USB_CADJ_Msk   (0x1fUL)

USB USB_TCR_REG: USB_CADJ (Bitfield-Mask: 0x1f)

Definition at line 11392 of file DA14680BA.h.

◆ USB_USB_TCR_REG_USB_CADJ_Pos

#define USB_USB_TCR_REG_USB_CADJ_Pos   (0UL)

USB USB_TCR_REG: USB_CADJ (Bit 0)

Definition at line 11391 of file DA14680BA.h.

◆ USB_USB_TCR_REG_USB_VADJ_Msk

#define USB_USB_TCR_REG_USB_VADJ_Msk   (0xe0UL)

USB USB_TCR_REG: USB_VADJ (Bitfield-Mask: 0x07)

Definition at line 11394 of file DA14680BA.h.

◆ USB_USB_TCR_REG_USB_VADJ_Pos

#define USB_USB_TCR_REG_USB_VADJ_Pos   (5UL)

USB USB_TCR_REG: USB_VADJ (Bit 5)

Definition at line 11393 of file DA14680BA.h.

◆ USB_USB_TXC0_REG_USB_FLUSH_Msk

#define USB_USB_TXC0_REG_USB_FLUSH_Msk   (0x8UL)

USB USB_TXC0_REG: USB_FLUSH (Bitfield-Mask: 0x01)

Definition at line 11596 of file DA14680BA.h.

◆ USB_USB_TXC0_REG_USB_FLUSH_Pos

#define USB_USB_TXC0_REG_USB_FLUSH_Pos   (3UL)

USB USB_TXC0_REG: USB_FLUSH (Bit 3)

Definition at line 11595 of file DA14680BA.h.

◆ USB_USB_TXC0_REG_USB_IGN_IN_Msk

#define USB_USB_TXC0_REG_USB_IGN_IN_Msk   (0x10UL)

USB USB_TXC0_REG: USB_IGN_IN (Bitfield-Mask: 0x01)

Definition at line 11598 of file DA14680BA.h.

◆ USB_USB_TXC0_REG_USB_IGN_IN_Pos

#define USB_USB_TXC0_REG_USB_IGN_IN_Pos   (4UL)

USB USB_TXC0_REG: USB_IGN_IN (Bit 4)

Definition at line 11597 of file DA14680BA.h.

◆ USB_USB_TXC0_REG_USB_TOGGLE_TX0_Msk

#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Msk   (0x4UL)

USB USB_TXC0_REG: USB_TOGGLE_TX0 (Bitfield-Mask: 0x01)

Definition at line 11594 of file DA14680BA.h.

◆ USB_USB_TXC0_REG_USB_TOGGLE_TX0_Pos

#define USB_USB_TXC0_REG_USB_TOGGLE_TX0_Pos   (2UL)

USB USB_TXC0_REG: USB_TOGGLE_TX0 (Bit 2)

Definition at line 11593 of file DA14680BA.h.

◆ USB_USB_TXC0_REG_USB_TX_EN_Msk

#define USB_USB_TXC0_REG_USB_TX_EN_Msk   (0x1UL)

USB USB_TXC0_REG: USB_TX_EN (Bitfield-Mask: 0x01)

Definition at line 11592 of file DA14680BA.h.

◆ USB_USB_TXC0_REG_USB_TX_EN_Pos

#define USB_USB_TXC0_REG_USB_TX_EN_Pos   (0UL)

USB USB_TXC0_REG: USB_TX_EN (Bit 0)

Definition at line 11591 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_FLUSH_Msk

#define USB_USB_TXC1_REG_USB_FLUSH_Msk   (0x8UL)

USB USB_TXC1_REG: USB_FLUSH (Bitfield-Mask: 0x01)

Definition at line 11662 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_FLUSH_Pos

#define USB_USB_TXC1_REG_USB_FLUSH_Pos   (3UL)

USB USB_TXC1_REG: USB_FLUSH (Bit 3)

Definition at line 11661 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_IGN_ISOMSK_Msk

#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Msk   (0x80UL)

USB USB_TXC1_REG: USB_IGN_ISOMSK (Bitfield-Mask: 0x01)

Definition at line 11668 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_IGN_ISOMSK_Pos

#define USB_USB_TXC1_REG_USB_IGN_ISOMSK_Pos   (7UL)

USB USB_TXC1_REG: USB_IGN_ISOMSK (Bit 7)

Definition at line 11667 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_LAST_Msk

#define USB_USB_TXC1_REG_USB_LAST_Msk   (0x2UL)

USB USB_TXC1_REG: USB_LAST (Bitfield-Mask: 0x01)

Definition at line 11658 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_LAST_Pos

#define USB_USB_TXC1_REG_USB_LAST_Pos   (1UL)

USB USB_TXC1_REG: USB_LAST (Bit 1)

Definition at line 11657 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_RFF_Msk

#define USB_USB_TXC1_REG_USB_RFF_Msk   (0x10UL)

USB USB_TXC1_REG: USB_RFF (Bitfield-Mask: 0x01)

Definition at line 11664 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_RFF_Pos

#define USB_USB_TXC1_REG_USB_RFF_Pos   (4UL)

USB USB_TXC1_REG: USB_RFF (Bit 4)

Definition at line 11663 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_TFWL_Msk

#define USB_USB_TXC1_REG_USB_TFWL_Msk   (0x60UL)

USB USB_TXC1_REG: USB_TFWL (Bitfield-Mask: 0x03)

Definition at line 11666 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_TFWL_Pos

#define USB_USB_TXC1_REG_USB_TFWL_Pos   (5UL)

USB USB_TXC1_REG: USB_TFWL (Bit 5)

Definition at line 11665 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_TOGGLE_TX_Msk

#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Msk   (0x4UL)

USB USB_TXC1_REG: USB_TOGGLE_TX (Bitfield-Mask: 0x01)

Definition at line 11660 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_TOGGLE_TX_Pos

#define USB_USB_TXC1_REG_USB_TOGGLE_TX_Pos   (2UL)

USB USB_TXC1_REG: USB_TOGGLE_TX (Bit 2)

Definition at line 11659 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_TX_EN_Msk

#define USB_USB_TXC1_REG_USB_TX_EN_Msk   (0x1UL)

USB USB_TXC1_REG: USB_TX_EN (Bitfield-Mask: 0x01)

Definition at line 11656 of file DA14680BA.h.

◆ USB_USB_TXC1_REG_USB_TX_EN_Pos

#define USB_USB_TXC1_REG_USB_TX_EN_Pos   (0UL)

USB USB_TXC1_REG: USB_TX_EN (Bit 0)

Definition at line 11655 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_FLUSH_Msk

#define USB_USB_TXC2_REG_USB_FLUSH_Msk   (0x8UL)

USB USB_TXC2_REG: USB_FLUSH (Bitfield-Mask: 0x01)

Definition at line 11738 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_FLUSH_Pos

#define USB_USB_TXC2_REG_USB_FLUSH_Pos   (3UL)

USB USB_TXC2_REG: USB_FLUSH (Bit 3)

Definition at line 11737 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_IGN_ISOMSK_Msk

#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Msk   (0x80UL)

USB USB_TXC2_REG: USB_IGN_ISOMSK (Bitfield-Mask: 0x01)

Definition at line 11744 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_IGN_ISOMSK_Pos

#define USB_USB_TXC2_REG_USB_IGN_ISOMSK_Pos   (7UL)

USB USB_TXC2_REG: USB_IGN_ISOMSK (Bit 7)

Definition at line 11743 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_LAST_Msk

#define USB_USB_TXC2_REG_USB_LAST_Msk   (0x2UL)

USB USB_TXC2_REG: USB_LAST (Bitfield-Mask: 0x01)

Definition at line 11734 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_LAST_Pos

#define USB_USB_TXC2_REG_USB_LAST_Pos   (1UL)

USB USB_TXC2_REG: USB_LAST (Bit 1)

Definition at line 11733 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_RFF_Msk

#define USB_USB_TXC2_REG_USB_RFF_Msk   (0x10UL)

USB USB_TXC2_REG: USB_RFF (Bitfield-Mask: 0x01)

Definition at line 11740 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_RFF_Pos

#define USB_USB_TXC2_REG_USB_RFF_Pos   (4UL)

USB USB_TXC2_REG: USB_RFF (Bit 4)

Definition at line 11739 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_TFWL_Msk

#define USB_USB_TXC2_REG_USB_TFWL_Msk   (0x60UL)

USB USB_TXC2_REG: USB_TFWL (Bitfield-Mask: 0x03)

Definition at line 11742 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_TFWL_Pos

#define USB_USB_TXC2_REG_USB_TFWL_Pos   (5UL)

USB USB_TXC2_REG: USB_TFWL (Bit 5)

Definition at line 11741 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_TOGGLE_TX_Msk

#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Msk   (0x4UL)

USB USB_TXC2_REG: USB_TOGGLE_TX (Bitfield-Mask: 0x01)

Definition at line 11736 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_TOGGLE_TX_Pos

#define USB_USB_TXC2_REG_USB_TOGGLE_TX_Pos   (2UL)

USB USB_TXC2_REG: USB_TOGGLE_TX (Bit 2)

Definition at line 11735 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_TX_EN_Msk

#define USB_USB_TXC2_REG_USB_TX_EN_Msk   (0x1UL)

USB USB_TXC2_REG: USB_TX_EN (Bitfield-Mask: 0x01)

Definition at line 11732 of file DA14680BA.h.

◆ USB_USB_TXC2_REG_USB_TX_EN_Pos

#define USB_USB_TXC2_REG_USB_TX_EN_Pos   (0UL)

USB USB_TXC2_REG: USB_TX_EN (Bit 0)

Definition at line 11731 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_FLUSH_Msk

#define USB_USB_TXC3_REG_USB_FLUSH_Msk   (0x8UL)

USB USB_TXC3_REG: USB_FLUSH (Bitfield-Mask: 0x01)

Definition at line 11814 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_FLUSH_Pos

#define USB_USB_TXC3_REG_USB_FLUSH_Pos   (3UL)

USB USB_TXC3_REG: USB_FLUSH (Bit 3)

Definition at line 11813 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_IGN_ISOMSK_Msk

#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Msk   (0x80UL)

USB USB_TXC3_REG: USB_IGN_ISOMSK (Bitfield-Mask: 0x01)

Definition at line 11820 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_IGN_ISOMSK_Pos

#define USB_USB_TXC3_REG_USB_IGN_ISOMSK_Pos   (7UL)

USB USB_TXC3_REG: USB_IGN_ISOMSK (Bit 7)

Definition at line 11819 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_LAST_Msk

#define USB_USB_TXC3_REG_USB_LAST_Msk   (0x2UL)

USB USB_TXC3_REG: USB_LAST (Bitfield-Mask: 0x01)

Definition at line 11810 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_LAST_Pos

#define USB_USB_TXC3_REG_USB_LAST_Pos   (1UL)

USB USB_TXC3_REG: USB_LAST (Bit 1)

Definition at line 11809 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_RFF_Msk

#define USB_USB_TXC3_REG_USB_RFF_Msk   (0x10UL)

USB USB_TXC3_REG: USB_RFF (Bitfield-Mask: 0x01)

Definition at line 11816 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_RFF_Pos

#define USB_USB_TXC3_REG_USB_RFF_Pos   (4UL)

USB USB_TXC3_REG: USB_RFF (Bit 4)

Definition at line 11815 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_TFWL_Msk

#define USB_USB_TXC3_REG_USB_TFWL_Msk   (0x60UL)

USB USB_TXC3_REG: USB_TFWL (Bitfield-Mask: 0x03)

Definition at line 11818 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_TFWL_Pos

#define USB_USB_TXC3_REG_USB_TFWL_Pos   (5UL)

USB USB_TXC3_REG: USB_TFWL (Bit 5)

Definition at line 11817 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_TOGGLE_TX_Msk

#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Msk   (0x4UL)

USB USB_TXC3_REG: USB_TOGGLE_TX (Bitfield-Mask: 0x01)

Definition at line 11812 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_TOGGLE_TX_Pos

#define USB_USB_TXC3_REG_USB_TOGGLE_TX_Pos   (2UL)

USB USB_TXC3_REG: USB_TOGGLE_TX (Bit 2)

Definition at line 11811 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_TX_EN_Msk

#define USB_USB_TXC3_REG_USB_TX_EN_Msk   (0x1UL)

USB USB_TXC3_REG: USB_TX_EN (Bitfield-Mask: 0x01)

Definition at line 11808 of file DA14680BA.h.

◆ USB_USB_TXC3_REG_USB_TX_EN_Pos

#define USB_USB_TXC3_REG_USB_TX_EN_Pos   (0UL)

USB USB_TXC3_REG: USB_TX_EN (Bit 0)

Definition at line 11807 of file DA14680BA.h.

◆ USB_USB_TXD0_REG_USB_TXFD_Msk

#define USB_USB_TXD0_REG_USB_TXFD_Msk   (0xffUL)

USB USB_TXD0_REG: USB_TXFD (Bitfield-Mask: 0xff)

Definition at line 11580 of file DA14680BA.h.

◆ USB_USB_TXD0_REG_USB_TXFD_Pos

#define USB_USB_TXD0_REG_USB_TXFD_Pos   (0UL)

USB USB_TXD0_REG: USB_TXFD (Bit 0)

Definition at line 11579 of file DA14680BA.h.

◆ USB_USB_TXD1_REG_USB_TXFD_Msk

#define USB_USB_TXD1_REG_USB_TXFD_Msk   (0xffUL)

USB USB_TXD1_REG: USB_TXFD (Bitfield-Mask: 0xff)

Definition at line 11642 of file DA14680BA.h.

◆ USB_USB_TXD1_REG_USB_TXFD_Pos

#define USB_USB_TXD1_REG_USB_TXFD_Pos   (0UL)

USB USB_TXD1_REG: USB_TXFD (Bit 0)

Definition at line 11641 of file DA14680BA.h.

◆ USB_USB_TXD2_REG_USB_TXFD_Msk

#define USB_USB_TXD2_REG_USB_TXFD_Msk   (0xffUL)

USB USB_TXD2_REG: USB_TXFD (Bitfield-Mask: 0xff)

Definition at line 11718 of file DA14680BA.h.

◆ USB_USB_TXD2_REG_USB_TXFD_Pos

#define USB_USB_TXD2_REG_USB_TXFD_Pos   (0UL)

USB USB_TXD2_REG: USB_TXFD (Bit 0)

Definition at line 11717 of file DA14680BA.h.

◆ USB_USB_TXD3_REG_USB_TXFD_Msk

#define USB_USB_TXD3_REG_USB_TXFD_Msk   (0xffUL)

USB USB_TXD3_REG: USB_TXFD (Bitfield-Mask: 0xff)

Definition at line 11794 of file DA14680BA.h.

◆ USB_USB_TXD3_REG_USB_TXFD_Pos

#define USB_USB_TXD3_REG_USB_TXFD_Pos   (0UL)

USB USB_TXD3_REG: USB_TXFD (Bit 0)

Definition at line 11793 of file DA14680BA.h.

◆ USB_USB_TXEV_REG_USB_TXFIFO31_Msk

#define USB_USB_TXEV_REG_USB_TXFIFO31_Msk   (0x7UL)

USB USB_TXEV_REG: USB_TXFIFO31 (Bitfield-Mask: 0x07)

Definition at line 11494 of file DA14680BA.h.

◆ USB_USB_TXEV_REG_USB_TXFIFO31_Pos

#define USB_USB_TXEV_REG_USB_TXFIFO31_Pos   (0UL)

USB USB_TXEV_REG: USB_TXFIFO31 (Bit 0)

Definition at line 11493 of file DA14680BA.h.

◆ USB_USB_TXEV_REG_USB_TXUDRRN31_Msk

#define USB_USB_TXEV_REG_USB_TXUDRRN31_Msk   (0x70UL)

USB USB_TXEV_REG: USB_TXUDRRN31 (Bitfield-Mask: 0x07)

Definition at line 11496 of file DA14680BA.h.

◆ USB_USB_TXEV_REG_USB_TXUDRRN31_Pos

#define USB_USB_TXEV_REG_USB_TXUDRRN31_Pos   (4UL)

USB USB_TXEV_REG: USB_TXUDRRN31 (Bit 4)

Definition at line 11495 of file DA14680BA.h.

◆ USB_USB_TXMSK_REG_USB_M_TXFIFO31_Msk

#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Msk   (0x7UL)

USB USB_TXMSK_REG: USB_M_TXFIFO31 (Bitfield-Mask: 0x07)

Definition at line 11500 of file DA14680BA.h.

◆ USB_USB_TXMSK_REG_USB_M_TXFIFO31_Pos

#define USB_USB_TXMSK_REG_USB_M_TXFIFO31_Pos   (0UL)

USB USB_TXMSK_REG: USB_M_TXFIFO31 (Bit 0)

Definition at line 11499 of file DA14680BA.h.

◆ USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Msk

#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Msk   (0x70UL)

USB USB_TXMSK_REG: USB_M_TXUDRRN31 (Bitfield-Mask: 0x07)

Definition at line 11502 of file DA14680BA.h.

◆ USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Pos

#define USB_USB_TXMSK_REG_USB_M_TXUDRRN31_Pos   (4UL)

USB USB_TXMSK_REG: USB_M_TXUDRRN31 (Bit 4)

Definition at line 11501 of file DA14680BA.h.

◆ USB_USB_TXS0_REG_USB_ACK_STAT_Msk

#define USB_USB_TXS0_REG_USB_ACK_STAT_Msk   (0x40UL)

USB USB_TXS0_REG: USB_ACK_STAT (Bitfield-Mask: 0x01)

Definition at line 11588 of file DA14680BA.h.

◆ USB_USB_TXS0_REG_USB_ACK_STAT_Pos

#define USB_USB_TXS0_REG_USB_ACK_STAT_Pos   (6UL)

USB USB_TXS0_REG: USB_ACK_STAT (Bit 6)

Definition at line 11587 of file DA14680BA.h.

◆ USB_USB_TXS0_REG_USB_TCOUNT_Msk

#define USB_USB_TXS0_REG_USB_TCOUNT_Msk   (0x1fUL)

USB USB_TXS0_REG: USB_TCOUNT (Bitfield-Mask: 0x1f)

Definition at line 11584 of file DA14680BA.h.

◆ USB_USB_TXS0_REG_USB_TCOUNT_Pos

#define USB_USB_TXS0_REG_USB_TCOUNT_Pos   (0UL)

USB USB_TXS0_REG: USB_TCOUNT (Bit 0)

Definition at line 11583 of file DA14680BA.h.

◆ USB_USB_TXS0_REG_USB_TX_DONE_Msk

#define USB_USB_TXS0_REG_USB_TX_DONE_Msk   (0x20UL)

USB USB_TXS0_REG: USB_TX_DONE (Bitfield-Mask: 0x01)

Definition at line 11586 of file DA14680BA.h.

◆ USB_USB_TXS0_REG_USB_TX_DONE_Pos

#define USB_USB_TXS0_REG_USB_TX_DONE_Pos   (5UL)

USB USB_TXS0_REG: USB_TX_DONE (Bit 5)

Definition at line 11585 of file DA14680BA.h.

◆ USB_USB_TXS1_REG_USB_ACK_STAT_Msk

#define USB_USB_TXS1_REG_USB_ACK_STAT_Msk   (0x40UL)

USB USB_TXS1_REG: USB_ACK_STAT (Bitfield-Mask: 0x01)

Definition at line 11650 of file DA14680BA.h.

◆ USB_USB_TXS1_REG_USB_ACK_STAT_Pos

#define USB_USB_TXS1_REG_USB_ACK_STAT_Pos   (6UL)

USB USB_TXS1_REG: USB_ACK_STAT (Bit 6)

Definition at line 11649 of file DA14680BA.h.

◆ USB_USB_TXS1_REG_USB_TCOUNT_Msk

#define USB_USB_TXS1_REG_USB_TCOUNT_Msk   (0x1fUL)

USB USB_TXS1_REG: USB_TCOUNT (Bitfield-Mask: 0x1f)

Definition at line 11646 of file DA14680BA.h.

◆ USB_USB_TXS1_REG_USB_TCOUNT_Pos

#define USB_USB_TXS1_REG_USB_TCOUNT_Pos   (0UL)

USB USB_TXS1_REG: USB_TCOUNT (Bit 0)

Definition at line 11645 of file DA14680BA.h.

◆ USB_USB_TXS1_REG_USB_TX_DONE_Msk

#define USB_USB_TXS1_REG_USB_TX_DONE_Msk   (0x20UL)

USB USB_TXS1_REG: USB_TX_DONE (Bitfield-Mask: 0x01)

Definition at line 11648 of file DA14680BA.h.

◆ USB_USB_TXS1_REG_USB_TX_DONE_Pos

#define USB_USB_TXS1_REG_USB_TX_DONE_Pos   (5UL)

USB USB_TXS1_REG: USB_TX_DONE (Bit 5)

Definition at line 11647 of file DA14680BA.h.

◆ USB_USB_TXS1_REG_USB_TX_URUN_Msk

#define USB_USB_TXS1_REG_USB_TX_URUN_Msk   (0x80UL)

USB USB_TXS1_REG: USB_TX_URUN (Bitfield-Mask: 0x01)

Definition at line 11652 of file DA14680BA.h.

◆ USB_USB_TXS1_REG_USB_TX_URUN_Pos

#define USB_USB_TXS1_REG_USB_TX_URUN_Pos   (7UL)

USB USB_TXS1_REG: USB_TX_URUN (Bit 7)

Definition at line 11651 of file DA14680BA.h.

◆ USB_USB_TXS2_REG_USB_ACK_STAT_Msk

#define USB_USB_TXS2_REG_USB_ACK_STAT_Msk   (0x40UL)

USB USB_TXS2_REG: USB_ACK_STAT (Bitfield-Mask: 0x01)

Definition at line 11726 of file DA14680BA.h.

◆ USB_USB_TXS2_REG_USB_ACK_STAT_Pos

#define USB_USB_TXS2_REG_USB_ACK_STAT_Pos   (6UL)

USB USB_TXS2_REG: USB_ACK_STAT (Bit 6)

Definition at line 11725 of file DA14680BA.h.

◆ USB_USB_TXS2_REG_USB_TCOUNT_Msk

#define USB_USB_TXS2_REG_USB_TCOUNT_Msk   (0x1fUL)

USB USB_TXS2_REG: USB_TCOUNT (Bitfield-Mask: 0x1f)

Definition at line 11722 of file DA14680BA.h.

◆ USB_USB_TXS2_REG_USB_TCOUNT_Pos

#define USB_USB_TXS2_REG_USB_TCOUNT_Pos   (0UL)

USB USB_TXS2_REG: USB_TCOUNT (Bit 0)

Definition at line 11721 of file DA14680BA.h.

◆ USB_USB_TXS2_REG_USB_TX_DONE_Msk

#define USB_USB_TXS2_REG_USB_TX_DONE_Msk   (0x20UL)

USB USB_TXS2_REG: USB_TX_DONE (Bitfield-Mask: 0x01)

Definition at line 11724 of file DA14680BA.h.

◆ USB_USB_TXS2_REG_USB_TX_DONE_Pos

#define USB_USB_TXS2_REG_USB_TX_DONE_Pos   (5UL)

USB USB_TXS2_REG: USB_TX_DONE (Bit 5)

Definition at line 11723 of file DA14680BA.h.

◆ USB_USB_TXS2_REG_USB_TX_URUN_Msk

#define USB_USB_TXS2_REG_USB_TX_URUN_Msk   (0x80UL)

USB USB_TXS2_REG: USB_TX_URUN (Bitfield-Mask: 0x01)

Definition at line 11728 of file DA14680BA.h.

◆ USB_USB_TXS2_REG_USB_TX_URUN_Pos

#define USB_USB_TXS2_REG_USB_TX_URUN_Pos   (7UL)

USB USB_TXS2_REG: USB_TX_URUN (Bit 7)

Definition at line 11727 of file DA14680BA.h.

◆ USB_USB_TXS3_REG_USB_ACK_STAT_Msk

#define USB_USB_TXS3_REG_USB_ACK_STAT_Msk   (0x40UL)

USB USB_TXS3_REG: USB_ACK_STAT (Bitfield-Mask: 0x01)

Definition at line 11802 of file DA14680BA.h.

◆ USB_USB_TXS3_REG_USB_ACK_STAT_Pos

#define USB_USB_TXS3_REG_USB_ACK_STAT_Pos   (6UL)

USB USB_TXS3_REG: USB_ACK_STAT (Bit 6)

Definition at line 11801 of file DA14680BA.h.

◆ USB_USB_TXS3_REG_USB_TCOUNT_Msk

#define USB_USB_TXS3_REG_USB_TCOUNT_Msk   (0x1fUL)

USB USB_TXS3_REG: USB_TCOUNT (Bitfield-Mask: 0x1f)

Definition at line 11798 of file DA14680BA.h.

◆ USB_USB_TXS3_REG_USB_TCOUNT_Pos

#define USB_USB_TXS3_REG_USB_TCOUNT_Pos   (0UL)

USB USB_TXS3_REG: USB_TCOUNT (Bit 0)

Definition at line 11797 of file DA14680BA.h.

◆ USB_USB_TXS3_REG_USB_TX_DONE_Msk

#define USB_USB_TXS3_REG_USB_TX_DONE_Msk   (0x20UL)

USB USB_TXS3_REG: USB_TX_DONE (Bitfield-Mask: 0x01)

Definition at line 11800 of file DA14680BA.h.

◆ USB_USB_TXS3_REG_USB_TX_DONE_Pos

#define USB_USB_TXS3_REG_USB_TX_DONE_Pos   (5UL)

USB USB_TXS3_REG: USB_TX_DONE (Bit 5)

Definition at line 11799 of file DA14680BA.h.

◆ USB_USB_TXS3_REG_USB_TX_URUN_Msk

#define USB_USB_TXS3_REG_USB_TX_URUN_Msk   (0x80UL)

USB USB_TXS3_REG: USB_TX_URUN (Bitfield-Mask: 0x01)

Definition at line 11804 of file DA14680BA.h.

◆ USB_USB_TXS3_REG_USB_TX_URUN_Pos

#define USB_USB_TXS3_REG_USB_TX_URUN_Pos   (7UL)

USB USB_TXS3_REG: USB_TX_URUN (Bit 7)

Definition at line 11803 of file DA14680BA.h.

◆ USB_USB_UTR_REG_USB_DIAG_Msk

#define USB_USB_UTR_REG_USB_DIAG_Msk   (0x80UL)

USB USB_UTR_REG: USB_DIAG (Bitfield-Mask: 0x01)

Definition at line 11404 of file DA14680BA.h.

◆ USB_USB_UTR_REG_USB_DIAG_Pos

#define USB_USB_UTR_REG_USB_DIAG_Pos   (7UL)

USB USB_UTR_REG: USB_DIAG (Bit 7)

Definition at line 11403 of file DA14680BA.h.

◆ USB_USB_UTR_REG_USB_NCRC_Msk

#define USB_USB_UTR_REG_USB_NCRC_Msk   (0x40UL)

USB USB_UTR_REG: USB_NCRC (Bitfield-Mask: 0x01)

Definition at line 11402 of file DA14680BA.h.

◆ USB_USB_UTR_REG_USB_NCRC_Pos

#define USB_USB_UTR_REG_USB_NCRC_Pos   (6UL)

USB USB_UTR_REG: USB_NCRC (Bit 6)

Definition at line 11401 of file DA14680BA.h.

◆ USB_USB_UTR_REG_USB_SF_Msk

#define USB_USB_UTR_REG_USB_SF_Msk   (0x20UL)

USB USB_UTR_REG: USB_SF (Bitfield-Mask: 0x01)

Definition at line 11400 of file DA14680BA.h.

◆ USB_USB_UTR_REG_USB_SF_Pos

#define USB_USB_UTR_REG_USB_SF_Pos   (5UL)

USB USB_UTR_REG: USB_SF (Bit 5)

Definition at line 11399 of file DA14680BA.h.

◆ USB_USB_UTR_REG_USB_UTR_RES_Msk

#define USB_USB_UTR_REG_USB_UTR_RES_Msk   (0x1fUL)

USB USB_UTR_REG: USB_UTR_RES (Bitfield-Mask: 0x1f)

Definition at line 11398 of file DA14680BA.h.

◆ USB_USB_UTR_REG_USB_UTR_RES_Pos

#define USB_USB_UTR_REG_USB_UTR_RES_Pos   (0UL)

USB USB_UTR_REG: USB_UTR_RES (Bit 0)

Definition at line 11397 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_RCDELAY_Msk

#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Msk   (0x2UL)

USB USB_UX20CDR_REG: RPU_RCDELAY (Bitfield-Mask: 0x01)

Definition at line 11558 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_RCDELAY_Pos

#define USB_USB_UX20CDR_REG_RPU_RCDELAY_Pos   (1UL)

USB USB_UX20CDR_REG: RPU_RCDELAY (Bit 1)

Definition at line 11557 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_SSPROTEN_Msk

#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Msk   (0x1UL)

USB USB_UX20CDR_REG: RPU_SSPROTEN (Bitfield-Mask: 0x01)

Definition at line 11556 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_SSPROTEN_Pos

#define USB_USB_UX20CDR_REG_RPU_SSPROTEN_Pos   (0UL)

USB USB_UX20CDR_REG: RPU_SSPROTEN (Bit 0)

Definition at line 11555 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_TEST7_Msk

#define USB_USB_UX20CDR_REG_RPU_TEST7_Msk   (0x80UL)

USB USB_UX20CDR_REG: RPU_TEST7 (Bitfield-Mask: 0x01)

Definition at line 11568 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_TEST7_Pos

#define USB_USB_UX20CDR_REG_RPU_TEST7_Pos   (7UL)

USB USB_UX20CDR_REG: RPU_TEST7 (Bit 7)

Definition at line 11567 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_TEST_EN_Msk

#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Msk   (0x10UL)

USB USB_UX20CDR_REG: RPU_TEST_EN (Bitfield-Mask: 0x01)

Definition at line 11562 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_TEST_EN_Pos

#define USB_USB_UX20CDR_REG_RPU_TEST_EN_Pos   (4UL)

USB USB_UX20CDR_REG: RPU_TEST_EN (Bit 4)

Definition at line 11561 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_TEST_SW1_Msk

#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Msk   (0x20UL)

USB USB_UX20CDR_REG: RPU_TEST_SW1 (Bitfield-Mask: 0x01)

Definition at line 11564 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_TEST_SW1_Pos

#define USB_USB_UX20CDR_REG_RPU_TEST_SW1_Pos   (5UL)

USB USB_UX20CDR_REG: RPU_TEST_SW1 (Bit 5)

Definition at line 11563 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Msk

#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Msk   (0x4UL)

USB USB_UX20CDR_REG: RPU_TEST_SW1DM (Bitfield-Mask: 0x01)

Definition at line 11560 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Pos

#define USB_USB_UX20CDR_REG_RPU_TEST_SW1DM_Pos   (2UL)

USB USB_UX20CDR_REG: RPU_TEST_SW1DM (Bit 2)

Definition at line 11559 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_TEST_SW2_Msk

#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Msk   (0x40UL)

USB USB_UX20CDR_REG: RPU_TEST_SW2 (Bitfield-Mask: 0x01)

Definition at line 11566 of file DA14680BA.h.

◆ USB_USB_UX20CDR_REG_RPU_TEST_SW2_Pos

#define USB_USB_UX20CDR_REG_RPU_TEST_SW2_Pos   (6UL)

USB USB_UX20CDR_REG: RPU_TEST_SW2 (Bit 6)

Definition at line 11565 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_RCV_Msk

#define USB_USB_XCVDIAG_REG_USB_RCV_Msk   (0x20UL)

USB USB_XCVDIAG_REG: USB_RCV (Bitfield-Mask: 0x01)

Definition at line 11384 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_RCV_Pos

#define USB_USB_XCVDIAG_REG_USB_RCV_Pos   (5UL)

USB USB_XCVDIAG_REG: USB_RCV (Bit 5)

Definition at line 11383 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_VMIN_Msk

#define USB_USB_XCVDIAG_REG_USB_VMIN_Msk   (0x40UL)

USB USB_XCVDIAG_REG: USB_VMIN (Bitfield-Mask: 0x01)

Definition at line 11386 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_VMIN_Pos

#define USB_USB_XCVDIAG_REG_USB_VMIN_Pos   (6UL)

USB USB_XCVDIAG_REG: USB_VMIN (Bit 6)

Definition at line 11385 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_VPIN_Msk

#define USB_USB_XCVDIAG_REG_USB_VPIN_Msk   (0x80UL)

USB USB_XCVDIAG_REG: USB_VPIN (Bitfield-Mask: 0x01)

Definition at line 11388 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_VPIN_Pos

#define USB_USB_XCVDIAG_REG_USB_VPIN_Pos   (7UL)

USB USB_XCVDIAG_REG: USB_VPIN (Bit 7)

Definition at line 11387 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_XCV_TEST_Msk

#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Msk   (0x1UL)

USB USB_XCVDIAG_REG: USB_XCV_TEST (Bitfield-Mask: 0x01)

Definition at line 11376 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_XCV_TEST_Pos

#define USB_USB_XCVDIAG_REG_USB_XCV_TEST_Pos   (0UL)

USB USB_XCVDIAG_REG: USB_XCV_TEST (Bit 0)

Definition at line 11375 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Msk

#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Msk   (0x8UL)

USB USB_XCVDIAG_REG: USB_XCV_TXEN (Bitfield-Mask: 0x01)

Definition at line 11382 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Pos

#define USB_USB_XCVDIAG_REG_USB_XCV_TXEN_Pos   (3UL)

USB USB_XCVDIAG_REG: USB_XCV_TXEN (Bit 3)

Definition at line 11381 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_XCV_TXn_Msk

#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Msk   (0x4UL)

USB USB_XCVDIAG_REG: USB_XCV_TXn (Bitfield-Mask: 0x01)

Definition at line 11380 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_XCV_TXn_Pos

#define USB_USB_XCVDIAG_REG_USB_XCV_TXn_Pos   (2UL)

USB USB_XCVDIAG_REG: USB_XCV_TXn (Bit 2)

Definition at line 11379 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_XCV_TXp_Msk

#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Msk   (0x2UL)

USB USB_XCVDIAG_REG: USB_XCV_TXp (Bitfield-Mask: 0x01)

Definition at line 11378 of file DA14680BA.h.

◆ USB_USB_XCVDIAG_REG_USB_XCV_TXp_Pos

#define USB_USB_XCVDIAG_REG_USB_XCV_TXp_Pos   (1UL)

USB USB_XCVDIAG_REG: USB_XCV_TXp (Bit 1)

Definition at line 11377 of file DA14680BA.h.

◆ WAKEUP

#define WAKEUP   ((WAKEUP_Type *) WAKEUP_BASE)

Definition at line 12110 of file DA14680BA.h.

◆ WAKEUP_BASE

#define WAKEUP_BASE   0x50000100UL

Definition at line 12065 of file DA14680BA.h.

◆ WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P0_Msk

#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P0_Msk   (0xffUL)

WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P0 (Bitfield-Mask: 0xff)

Definition at line 11970 of file DA14680BA.h.

◆ WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P0_Pos

#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P0_Pos   (0UL)

WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P0 (Bit 0)

Definition at line 11969 of file DA14680BA.h.

◆ WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P1_Msk

#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P1_Msk   (0xff00UL)

WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P1 (Bitfield-Mask: 0xff)

Definition at line 11972 of file DA14680BA.h.

◆ WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P1_Pos

#define WAKEUP_WKUP_CLEAR_0_REG_WKUP_CLEAR_P1_Pos   (8UL)

WAKEUP WKUP_CLEAR_0_REG: WKUP_CLEAR_P1 (Bit 8)

Definition at line 11971 of file DA14680BA.h.

◆ WAKEUP_WKUP_CLEAR_1_REG_WKUP_CLEAR_P2_Msk

#define WAKEUP_WKUP_CLEAR_1_REG_WKUP_CLEAR_P2_Msk   (0x1fUL)

WAKEUP WKUP_CLEAR_1_REG: WKUP_CLEAR_P2 (Bitfield-Mask: 0x1f)

Definition at line 11976 of file DA14680BA.h.

◆ WAKEUP_WKUP_CLEAR_1_REG_WKUP_CLEAR_P2_Pos

#define WAKEUP_WKUP_CLEAR_1_REG_WKUP_CLEAR_P2_Pos   (0UL)

WAKEUP WKUP_CLEAR_1_REG: WKUP_CLEAR_P2 (Bit 0)

Definition at line 11975 of file DA14680BA.h.

◆ WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P3_Msk

#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P3_Msk   (0xffUL)

WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P3 (Bitfield-Mask: 0xff)

Definition at line 11980 of file DA14680BA.h.

◆ WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P3_Pos

#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P3_Pos   (0UL)

WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P3 (Bit 0)

Definition at line 11979 of file DA14680BA.h.

◆ WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P4_Msk

#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P4_Msk   (0xff00UL)

WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P4 (Bitfield-Mask: 0xff)

Definition at line 11982 of file DA14680BA.h.

◆ WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P4_Pos

#define WAKEUP_WKUP_CLEAR_2_REG_WKUP_CLEAR_P4_Pos   (8UL)

WAKEUP WKUP_CLEAR_2_REG: WKUP_CLEAR_P4 (Bit 8)

Definition at line 11981 of file DA14680BA.h.

◆ WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Msk

#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Msk   (0x3fUL)

WAKEUP WKUP_CTRL_REG: WKUP_DEB_VALUE (Bitfield-Mask: 0x3f)

Definition at line 11902 of file DA14680BA.h.

◆ WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Pos

#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Pos   (0UL)

WAKEUP WKUP_CTRL_REG: WKUP_DEB_VALUE (Bit 0)

Definition at line 11901 of file DA14680BA.h.

◆ WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk

#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk   (0x80UL)

WAKEUP WKUP_CTRL_REG: WKUP_ENABLE_IRQ (Bitfield-Mask: 0x01)

Definition at line 11906 of file DA14680BA.h.

◆ WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Pos

#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Pos   (7UL)

WAKEUP WKUP_CTRL_REG: WKUP_ENABLE_IRQ (Bit 7)

Definition at line 11905 of file DA14680BA.h.

◆ WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Msk

#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Msk   (0x40UL)

WAKEUP WKUP_CTRL_REG: WKUP_SFT_KEYHIT (Bitfield-Mask: 0x01)

Definition at line 11904 of file DA14680BA.h.

◆ WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Pos

#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Pos   (6UL)

WAKEUP WKUP_CTRL_REG: WKUP_SFT_KEYHIT (Bit 6)

Definition at line 11903 of file DA14680BA.h.

◆ WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Msk

#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Msk   (0xffUL)

WAKEUP WKUP_POL_P0_REG: WKUP_POL_P0 (Bitfield-Mask: 0xff)

Definition at line 11934 of file DA14680BA.h.

◆ WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Pos

#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Pos   (0UL)

WAKEUP WKUP_POL_P0_REG: WKUP_POL_P0 (Bit 0)

Definition at line 11933 of file DA14680BA.h.

◆ WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Msk

#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Msk   (0xffUL)

WAKEUP WKUP_POL_P1_REG: WKUP_POL_P1 (Bitfield-Mask: 0xff)

Definition at line 11938 of file DA14680BA.h.

◆ WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Pos

#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Pos   (0UL)

WAKEUP WKUP_POL_P1_REG: WKUP_POL_P1 (Bit 0)

Definition at line 11937 of file DA14680BA.h.

◆ WAKEUP_WKUP_POL_P2_REG_WKUP_POL_P2_Msk

#define WAKEUP_WKUP_POL_P2_REG_WKUP_POL_P2_Msk   (0x1fUL)

WAKEUP WKUP_POL_P2_REG: WKUP_POL_P2 (Bitfield-Mask: 0x1f)

Definition at line 11942 of file DA14680BA.h.

◆ WAKEUP_WKUP_POL_P2_REG_WKUP_POL_P2_Pos

#define WAKEUP_WKUP_POL_P2_REG_WKUP_POL_P2_Pos   (0UL)

WAKEUP WKUP_POL_P2_REG: WKUP_POL_P2 (Bit 0)

Definition at line 11941 of file DA14680BA.h.

◆ WAKEUP_WKUP_POL_P3_REG_WKUP_POL_P3_Msk

#define WAKEUP_WKUP_POL_P3_REG_WKUP_POL_P3_Msk   (0xffUL)

WAKEUP WKUP_POL_P3_REG: WKUP_POL_P3 (Bitfield-Mask: 0xff)

Definition at line 11946 of file DA14680BA.h.

◆ WAKEUP_WKUP_POL_P3_REG_WKUP_POL_P3_Pos

#define WAKEUP_WKUP_POL_P3_REG_WKUP_POL_P3_Pos   (0UL)

WAKEUP WKUP_POL_P3_REG: WKUP_POL_P3 (Bit 0)

Definition at line 11945 of file DA14680BA.h.

◆ WAKEUP_WKUP_POL_P4_REG_WKUP_POL_P4_Msk

#define WAKEUP_WKUP_POL_P4_REG_WKUP_POL_P4_Msk   (0xffUL)

WAKEUP WKUP_POL_P4_REG: WKUP_POL_P4 (Bitfield-Mask: 0xff)

Definition at line 11950 of file DA14680BA.h.

◆ WAKEUP_WKUP_POL_P4_REG_WKUP_POL_P4_Pos

#define WAKEUP_WKUP_POL_P4_REG_WKUP_POL_P4_Pos   (0UL)

WAKEUP WKUP_POL_P4_REG: WKUP_POL_P4 (Bit 0)

Definition at line 11949 of file DA14680BA.h.

◆ WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk

#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk   (0xffffUL)

WAKEUP WKUP_RESET_IRQ_REG: WKUP_IRQ_RST (Bitfield-Mask: 0xffff)

Definition at line 11910 of file DA14680BA.h.

◆ WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Pos

#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Pos   (0UL)

WAKEUP WKUP_RESET_IRQ_REG: WKUP_IRQ_RST (Bit 0)

Definition at line 11909 of file DA14680BA.h.

◆ WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Msk

#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Msk   (0xffUL)

WAKEUP WKUP_SEL_GPIO_P0_REG: WKUP_SEL_GPIO_P0 (Bitfield-Mask: 0xff)

Definition at line 11986 of file DA14680BA.h.

◆ WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Pos

#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Pos   (0UL)

WAKEUP WKUP_SEL_GPIO_P0_REG: WKUP_SEL_GPIO_P0 (Bit 0)

Definition at line 11985 of file DA14680BA.h.

◆ WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Msk

#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Msk   (0xffUL)

WAKEUP WKUP_SEL_GPIO_P1_REG: WKUP_SEL_GPIO_P1 (Bitfield-Mask: 0xff)

Definition at line 11990 of file DA14680BA.h.

◆ WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Pos

#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Pos   (0UL)

WAKEUP WKUP_SEL_GPIO_P1_REG: WKUP_SEL_GPIO_P1 (Bit 0)

Definition at line 11989 of file DA14680BA.h.

◆ WAKEUP_WKUP_SEL_GPIO_P2_REG_WKUP_SEL_GPIO_P2_Msk

#define WAKEUP_WKUP_SEL_GPIO_P2_REG_WKUP_SEL_GPIO_P2_Msk   (0x1fUL)

WAKEUP WKUP_SEL_GPIO_P2_REG: WKUP_SEL_GPIO_P2 (Bitfield-Mask: 0x1f)

Definition at line 11994 of file DA14680BA.h.

◆ WAKEUP_WKUP_SEL_GPIO_P2_REG_WKUP_SEL_GPIO_P2_Pos

#define WAKEUP_WKUP_SEL_GPIO_P2_REG_WKUP_SEL_GPIO_P2_Pos   (0UL)

WAKEUP WKUP_SEL_GPIO_P2_REG: WKUP_SEL_GPIO_P2 (Bit 0)

Definition at line 11993 of file DA14680BA.h.

◆ WAKEUP_WKUP_SEL_GPIO_P3_REG_WKUP_SEL_GPIO_P3_Msk

#define WAKEUP_WKUP_SEL_GPIO_P3_REG_WKUP_SEL_GPIO_P3_Msk   (0xffUL)

WAKEUP WKUP_SEL_GPIO_P3_REG: WKUP_SEL_GPIO_P3 (Bitfield-Mask: 0xff)

Definition at line 11998 of file DA14680BA.h.

◆ WAKEUP_WKUP_SEL_GPIO_P3_REG_WKUP_SEL_GPIO_P3_Pos

#define WAKEUP_WKUP_SEL_GPIO_P3_REG_WKUP_SEL_GPIO_P3_Pos   (0UL)

WAKEUP WKUP_SEL_GPIO_P3_REG: WKUP_SEL_GPIO_P3 (Bit 0)

Definition at line 11997 of file DA14680BA.h.

◆ WAKEUP_WKUP_SEL_GPIO_P4_REG_WKUP_SEL_GPIO_P4_Msk

#define WAKEUP_WKUP_SEL_GPIO_P4_REG_WKUP_SEL_GPIO_P4_Msk   (0xffUL)

WAKEUP WKUP_SEL_GPIO_P4_REG: WKUP_SEL_GPIO_P4 (Bitfield-Mask: 0xff)

Definition at line 12002 of file DA14680BA.h.

◆ WAKEUP_WKUP_SEL_GPIO_P4_REG_WKUP_SEL_GPIO_P4_Pos

#define WAKEUP_WKUP_SEL_GPIO_P4_REG_WKUP_SEL_GPIO_P4_Pos   (0UL)

WAKEUP WKUP_SEL_GPIO_P4_REG: WKUP_SEL_GPIO_P4 (Bit 0)

Definition at line 12001 of file DA14680BA.h.

◆ WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Msk

#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Msk   (0xffUL)

WAKEUP WKUP_SELECT_P0_REG: WKUP_SELECT_P0 (Bitfield-Mask: 0xff)

Definition at line 11914 of file DA14680BA.h.

◆ WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Pos

#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Pos   (0UL)

WAKEUP WKUP_SELECT_P0_REG: WKUP_SELECT_P0 (Bit 0)

Definition at line 11913 of file DA14680BA.h.

◆ WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Msk

#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Msk   (0xffUL)

WAKEUP WKUP_SELECT_P1_REG: WKUP_SELECT_P1 (Bitfield-Mask: 0xff)

Definition at line 11918 of file DA14680BA.h.

◆ WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Pos

#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Pos   (0UL)

WAKEUP WKUP_SELECT_P1_REG: WKUP_SELECT_P1 (Bit 0)

Definition at line 11917 of file DA14680BA.h.

◆ WAKEUP_WKUP_SELECT_P2_REG_WKUP_SELECT_P2_Msk

#define WAKEUP_WKUP_SELECT_P2_REG_WKUP_SELECT_P2_Msk   (0x1fUL)

WAKEUP WKUP_SELECT_P2_REG: WKUP_SELECT_P2 (Bitfield-Mask: 0x1f)

Definition at line 11922 of file DA14680BA.h.

◆ WAKEUP_WKUP_SELECT_P2_REG_WKUP_SELECT_P2_Pos

#define WAKEUP_WKUP_SELECT_P2_REG_WKUP_SELECT_P2_Pos   (0UL)

WAKEUP WKUP_SELECT_P2_REG: WKUP_SELECT_P2 (Bit 0)

Definition at line 11921 of file DA14680BA.h.

◆ WAKEUP_WKUP_SELECT_P3_REG_WKUP_SELECT_P3_Msk

#define WAKEUP_WKUP_SELECT_P3_REG_WKUP_SELECT_P3_Msk   (0xffUL)

WAKEUP WKUP_SELECT_P3_REG: WKUP_SELECT_P3 (Bitfield-Mask: 0xff)

Definition at line 11926 of file DA14680BA.h.

◆ WAKEUP_WKUP_SELECT_P3_REG_WKUP_SELECT_P3_Pos

#define WAKEUP_WKUP_SELECT_P3_REG_WKUP_SELECT_P3_Pos   (0UL)

WAKEUP WKUP_SELECT_P3_REG: WKUP_SELECT_P3 (Bit 0)

Definition at line 11925 of file DA14680BA.h.

◆ WAKEUP_WKUP_SELECT_P4_REG_WKUP_SELECT_P4_Msk

#define WAKEUP_WKUP_SELECT_P4_REG_WKUP_SELECT_P4_Msk   (0xffUL)

WAKEUP WKUP_SELECT_P4_REG: WKUP_SELECT_P4 (Bitfield-Mask: 0xff)

Definition at line 11930 of file DA14680BA.h.

◆ WAKEUP_WKUP_SELECT_P4_REG_WKUP_SELECT_P4_Pos

#define WAKEUP_WKUP_SELECT_P4_REG_WKUP_SELECT_P4_Pos   (0UL)

WAKEUP WKUP_SELECT_P4_REG: WKUP_SELECT_P4 (Bit 0)

Definition at line 11929 of file DA14680BA.h.

◆ WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P0_Msk

#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P0_Msk   (0xffUL)

WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P0 (Bitfield-Mask: 0xff)

Definition at line 11954 of file DA14680BA.h.

◆ WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P0_Pos

#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P0_Pos   (0UL)

WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P0 (Bit 0)

Definition at line 11953 of file DA14680BA.h.

◆ WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P1_Msk

#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P1_Msk   (0xff00UL)

WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P1 (Bitfield-Mask: 0xff)

Definition at line 11956 of file DA14680BA.h.

◆ WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P1_Pos

#define WAKEUP_WKUP_STATUS_0_REG_WKUP_STAT_P1_Pos   (8UL)

WAKEUP WKUP_STATUS_0_REG: WKUP_STAT_P1 (Bit 8)

Definition at line 11955 of file DA14680BA.h.

◆ WAKEUP_WKUP_STATUS_1_REG_WKUP_STAT_P2_Msk

#define WAKEUP_WKUP_STATUS_1_REG_WKUP_STAT_P2_Msk   (0x1fUL)

WAKEUP WKUP_STATUS_1_REG: WKUP_STAT_P2 (Bitfield-Mask: 0x1f)

Definition at line 11960 of file DA14680BA.h.

◆ WAKEUP_WKUP_STATUS_1_REG_WKUP_STAT_P2_Pos

#define WAKEUP_WKUP_STATUS_1_REG_WKUP_STAT_P2_Pos   (0UL)

WAKEUP WKUP_STATUS_1_REG: WKUP_STAT_P2 (Bit 0)

Definition at line 11959 of file DA14680BA.h.

◆ WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P3_Msk

#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P3_Msk   (0xffUL)

WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P3 (Bitfield-Mask: 0xff)

Definition at line 11964 of file DA14680BA.h.

◆ WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P3_Pos

#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P3_Pos   (0UL)

WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P3 (Bit 0)

Definition at line 11963 of file DA14680BA.h.

◆ WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P4_Msk

#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P4_Msk   (0xff00UL)

WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P4 (Bitfield-Mask: 0xff)

Definition at line 11966 of file DA14680BA.h.

◆ WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P4_Pos

#define WAKEUP_WKUP_STATUS_2_REG_WKUP_STAT_P4_Pos   (8UL)

WAKEUP WKUP_STATUS_2_REG: WKUP_STAT_P4 (Bit 8)

Definition at line 11965 of file DA14680BA.h.

◆ WDOG

#define WDOG   ((WDOG_Type *) WDOG_BASE)

Definition at line 12111 of file DA14680BA.h.

◆ WDOG_BASE

#define WDOG_BASE   0x50003100UL

Definition at line 12066 of file DA14680BA.h.

◆ WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk

#define WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk   (0x1UL)

WDOG WATCHDOG_CTRL_REG: NMI_RST (Bitfield-Mask: 0x01)

Definition at line 12020 of file DA14680BA.h.

◆ WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos

#define WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos   (0UL)

WDOG WATCHDOG_CTRL_REG: NMI_RST (Bit 0)

Definition at line 12019 of file DA14680BA.h.

◆ WDOG_WATCHDOG_REG_WDOG_VAL_Msk

#define WDOG_WATCHDOG_REG_WDOG_VAL_Msk   (0xffUL)

WDOG WATCHDOG_REG: WDOG_VAL (Bitfield-Mask: 0xff)

Definition at line 12012 of file DA14680BA.h.

◆ WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk

#define WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk   (0x100UL)

WDOG WATCHDOG_REG: WDOG_VAL_NEG (Bitfield-Mask: 0x01)

Definition at line 12014 of file DA14680BA.h.

◆ WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Pos

#define WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Pos   (8UL)

WDOG WATCHDOG_REG: WDOG_VAL_NEG (Bit 8)

Definition at line 12013 of file DA14680BA.h.

◆ WDOG_WATCHDOG_REG_WDOG_VAL_Pos

#define WDOG_WATCHDOG_REG_WDOG_VAL_Pos   (0UL)

WDOG WATCHDOG_REG: WDOG_VAL (Bit 0)

Definition at line 12011 of file DA14680BA.h.

◆ WDOG_WATCHDOG_REG_WDOG_WEN_Msk

#define WDOG_WATCHDOG_REG_WDOG_WEN_Msk   (0xfe00UL)

WDOG WATCHDOG_REG: WDOG_WEN (Bitfield-Mask: 0x7f)

Definition at line 12016 of file DA14680BA.h.

◆ WDOG_WATCHDOG_REG_WDOG_WEN_Pos

#define WDOG_WATCHDOG_REG_WDOG_WEN_Pos   (9UL)

WDOG WATCHDOG_REG: WDOG_WEN (Bit 9)

Definition at line 12015 of file DA14680BA.h.

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